./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.11.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 35987657 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.11.cil-2.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash c5f603027c62ff37561a520351662dbe2fd253b52e04e36028cb9a624978ef8e --- Real Ultimate output --- This is Ultimate 0.2.2-?-3598765 [2022-07-22 02:42:40,407 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-07-22 02:42:40,409 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-07-22 02:42:40,441 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-07-22 02:42:40,441 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-07-22 02:42:40,442 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-07-22 02:42:40,445 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-07-22 02:42:40,447 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-07-22 02:42:40,448 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-07-22 02:42:40,456 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-07-22 02:42:40,457 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-07-22 02:42:40,461 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-07-22 02:42:40,461 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-07-22 02:42:40,462 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-07-22 02:42:40,463 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-07-22 02:42:40,466 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-07-22 02:42:40,466 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-07-22 02:42:40,467 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-07-22 02:42:40,468 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-07-22 02:42:40,473 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-07-22 02:42:40,473 INFO L181 SettingsManager]: Resetting HornVerifier preferences to default values [2022-07-22 02:42:40,474 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-07-22 02:42:40,476 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-07-22 02:42:40,476 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-07-22 02:42:40,477 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-07-22 02:42:40,482 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-07-22 02:42:40,483 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-07-22 02:42:40,483 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-07-22 02:42:40,483 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-07-22 02:42:40,484 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-07-22 02:42:40,484 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-07-22 02:42:40,485 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-07-22 02:42:40,486 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-07-22 02:42:40,486 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-07-22 02:42:40,487 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-07-22 02:42:40,488 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-07-22 02:42:40,488 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-07-22 02:42:40,489 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-07-22 02:42:40,489 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-07-22 02:42:40,489 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-07-22 02:42:40,490 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-07-22 02:42:40,491 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-07-22 02:42:40,497 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-07-22 02:42:40,523 INFO L113 SettingsManager]: Loading preferences was successful [2022-07-22 02:42:40,523 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-07-22 02:42:40,524 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-07-22 02:42:40,524 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-07-22 02:42:40,525 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-07-22 02:42:40,525 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-07-22 02:42:40,525 INFO L138 SettingsManager]: * Use SBE=true [2022-07-22 02:42:40,526 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-07-22 02:42:40,526 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-07-22 02:42:40,526 INFO L138 SettingsManager]: * Use old map elimination=false [2022-07-22 02:42:40,527 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-07-22 02:42:40,527 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-07-22 02:42:40,527 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-07-22 02:42:40,527 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-07-22 02:42:40,527 INFO L138 SettingsManager]: * sizeof long=4 [2022-07-22 02:42:40,527 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-07-22 02:42:40,528 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-07-22 02:42:40,528 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-07-22 02:42:40,528 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-07-22 02:42:40,528 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-07-22 02:42:40,528 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-07-22 02:42:40,528 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-07-22 02:42:40,529 INFO L138 SettingsManager]: * sizeof long double=12 [2022-07-22 02:42:40,529 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-07-22 02:42:40,529 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-07-22 02:42:40,529 INFO L138 SettingsManager]: * Use constant arrays=true [2022-07-22 02:42:40,529 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-07-22 02:42:40,529 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-07-22 02:42:40,530 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-07-22 02:42:40,530 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-07-22 02:42:40,530 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-07-22 02:42:40,532 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-07-22 02:42:40,532 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c5f603027c62ff37561a520351662dbe2fd253b52e04e36028cb9a624978ef8e [2022-07-22 02:42:40,815 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-07-22 02:42:40,838 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-07-22 02:42:40,840 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-07-22 02:42:40,841 INFO L271 PluginConnector]: Initializing CDTParser... [2022-07-22 02:42:40,842 INFO L275 PluginConnector]: CDTParser initialized [2022-07-22 02:42:40,843 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.11.cil-2.c [2022-07-22 02:42:40,899 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a80a383d8/9ee08a0dbd8a49afb03fc558cd78e991/FLAG836faec1d [2022-07-22 02:42:41,307 INFO L306 CDTParser]: Found 1 translation units. [2022-07-22 02:42:41,307 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.11.cil-2.c [2022-07-22 02:42:41,316 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a80a383d8/9ee08a0dbd8a49afb03fc558cd78e991/FLAG836faec1d [2022-07-22 02:42:41,719 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a80a383d8/9ee08a0dbd8a49afb03fc558cd78e991 [2022-07-22 02:42:41,722 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-07-22 02:42:41,723 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-07-22 02:42:41,725 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-07-22 02:42:41,725 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-07-22 02:42:41,728 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-07-22 02:42:41,728 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 22.07 02:42:41" (1/1) ... [2022-07-22 02:42:41,729 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1da3cfb5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:42:41, skipping insertion in model container [2022-07-22 02:42:41,737 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 22.07 02:42:41" (1/1) ... [2022-07-22 02:42:41,742 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-07-22 02:42:41,768 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-07-22 02:42:41,853 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.11.cil-2.c[671,684] [2022-07-22 02:42:41,940 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-22 02:42:41,948 INFO L203 MainTranslator]: Completed pre-run [2022-07-22 02:42:41,955 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.11.cil-2.c[671,684] [2022-07-22 02:42:42,017 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-22 02:42:42,030 INFO L208 MainTranslator]: Completed translation [2022-07-22 02:42:42,031 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:42:42 WrapperNode [2022-07-22 02:42:42,032 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-07-22 02:42:42,033 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-07-22 02:42:42,033 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-07-22 02:42:42,033 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-07-22 02:42:42,038 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:42:42" (1/1) ... [2022-07-22 02:42:42,056 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:42:42" (1/1) ... [2022-07-22 02:42:42,133 INFO L137 Inliner]: procedures = 50, calls = 64, calls flagged for inlining = 59, calls inlined = 238, statements flattened = 3645 [2022-07-22 02:42:42,134 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-07-22 02:42:42,134 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-07-22 02:42:42,134 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-07-22 02:42:42,135 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-07-22 02:42:42,140 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:42:42" (1/1) ... [2022-07-22 02:42:42,140 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:42:42" (1/1) ... [2022-07-22 02:42:42,151 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:42:42" (1/1) ... [2022-07-22 02:42:42,151 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:42:42" (1/1) ... [2022-07-22 02:42:42,174 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:42:42" (1/1) ... [2022-07-22 02:42:42,196 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:42:42" (1/1) ... [2022-07-22 02:42:42,205 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:42:42" (1/1) ... [2022-07-22 02:42:42,230 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-07-22 02:42:42,231 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-07-22 02:42:42,231 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-07-22 02:42:42,231 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-07-22 02:42:42,232 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:42:42" (1/1) ... [2022-07-22 02:42:42,247 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-22 02:42:42,254 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-22 02:42:42,293 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-22 02:42:42,341 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-07-22 02:42:42,364 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-07-22 02:42:42,364 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-07-22 02:42:42,364 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-07-22 02:42:42,364 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-07-22 02:42:42,496 INFO L234 CfgBuilder]: Building ICFG [2022-07-22 02:42:42,497 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-07-22 02:42:43,846 INFO L275 CfgBuilder]: Performing block encoding [2022-07-22 02:42:43,858 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-07-22 02:42:43,859 INFO L299 CfgBuilder]: Removed 14 assume(true) statements. [2022-07-22 02:42:43,862 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.07 02:42:43 BoogieIcfgContainer [2022-07-22 02:42:43,862 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-07-22 02:42:43,863 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-07-22 02:42:43,863 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-07-22 02:42:43,878 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-07-22 02:42:43,879 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-22 02:42:43,879 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 22.07 02:42:41" (1/3) ... [2022-07-22 02:42:43,880 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@15788a43 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 22.07 02:42:43, skipping insertion in model container [2022-07-22 02:42:43,880 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-22 02:42:43,881 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:42:42" (2/3) ... [2022-07-22 02:42:43,881 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@15788a43 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 22.07 02:42:43, skipping insertion in model container [2022-07-22 02:42:43,881 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-22 02:42:43,881 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.07 02:42:43" (3/3) ... [2022-07-22 02:42:43,882 INFO L354 chiAutomizerObserver]: Analyzing ICFG token_ring.11.cil-2.c [2022-07-22 02:42:43,933 INFO L255 stractBuchiCegarLoop]: Interprodecural is true [2022-07-22 02:42:43,933 INFO L256 stractBuchiCegarLoop]: Hoare is false [2022-07-22 02:42:43,933 INFO L257 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-07-22 02:42:43,934 INFO L258 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-07-22 02:42:43,934 INFO L259 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-07-22 02:42:43,934 INFO L260 stractBuchiCegarLoop]: Difference is false [2022-07-22 02:42:43,934 INFO L261 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-07-22 02:42:43,934 INFO L265 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-07-22 02:42:43,941 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1572 states, 1571 states have (on average 1.5022278803309994) internal successors, (2360), 1571 states have internal predecessors, (2360), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:43,989 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1417 [2022-07-22 02:42:43,990 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:42:43,990 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:42:44,007 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:44,007 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:44,007 INFO L287 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-07-22 02:42:44,010 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1572 states, 1571 states have (on average 1.5022278803309994) internal successors, (2360), 1571 states have internal predecessors, (2360), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:44,020 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1417 [2022-07-22 02:42:44,021 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:42:44,021 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:42:44,024 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:44,024 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:44,030 INFO L752 eck$LassoCheckResult]: Stem: 394#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 1506#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1130#L1641true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1513#L773true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 113#L780true assume !(1 == ~m_i~0);~m_st~0 := 2; 1151#L780-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 1399#L785-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1083#L790-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1397#L795-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 302#L800-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 571#L805-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1094#L810-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1030#L815-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 254#L820-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 726#L825-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 194#L830-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 927#L835-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1452#L1109true assume !(0 == ~M_E~0); 962#L1109-2true assume !(0 == ~T1_E~0); 198#L1114-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 1522#L1119-1true assume !(0 == ~T3_E~0); 1035#L1124-1true assume !(0 == ~T4_E~0); 26#L1129-1true assume !(0 == ~T5_E~0); 349#L1134-1true assume !(0 == ~T6_E~0); 944#L1139-1true assume !(0 == ~T7_E~0); 1020#L1144-1true assume !(0 == ~T8_E~0); 783#L1149-1true assume !(0 == ~T9_E~0); 74#L1154-1true assume 0 == ~T10_E~0;~T10_E~0 := 1; 919#L1159-1true assume !(0 == ~T11_E~0); 768#L1164-1true assume !(0 == ~E_M~0); 281#L1169-1true assume !(0 == ~E_1~0); 223#L1174-1true assume !(0 == ~E_2~0); 154#L1179-1true assume !(0 == ~E_3~0); 115#L1184-1true assume !(0 == ~E_4~0); 133#L1189-1true assume !(0 == ~E_5~0); 179#L1194-1true assume 0 == ~E_6~0;~E_6~0 := 1; 790#L1199-1true assume !(0 == ~E_7~0); 968#L1204-1true assume !(0 == ~E_8~0); 722#L1209-1true assume !(0 == ~E_9~0); 1176#L1214-1true assume !(0 == ~E_10~0); 1525#L1219-1true assume !(0 == ~E_11~0); 1469#L1224-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 292#L544true assume 1 == ~m_pc~0; 1028#L545true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1187#L555true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 797#L556true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 95#L1379true assume !(0 != activate_threads_~tmp~1#1); 1392#L1379-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 556#L563true assume !(1 == ~t1_pc~0); 1183#L563-2true is_transmit1_triggered_~__retres1~1#1 := 0; 31#L574true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1106#L575true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 664#L1387true assume !(0 != activate_threads_~tmp___0~0#1); 29#L1387-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 404#L582true assume 1 == ~t2_pc~0; 885#L583true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 674#L593true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 782#L594true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 842#L1395true assume !(0 != activate_threads_~tmp___1~0#1); 45#L1395-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 756#L601true assume !(1 == ~t3_pc~0); 462#L601-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1015#L612true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1218#L613true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 705#L1403true assume !(0 != activate_threads_~tmp___2~0#1); 1409#L1403-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 654#L620true assume 1 == ~t4_pc~0; 36#L621true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 363#L631true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 328#L632true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 568#L1411true assume !(0 != activate_threads_~tmp___3~0#1); 758#L1411-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 739#L639true assume 1 == ~t5_pc~0; 629#L640true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 182#L650true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 589#L651true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 583#L1419true assume !(0 != activate_threads_~tmp___4~0#1); 848#L1419-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 528#L658true assume !(1 == ~t6_pc~0); 290#L658-2true is_transmit6_triggered_~__retres1~6#1 := 0; 696#L669true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1135#L670true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1476#L1427true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 709#L1427-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 204#L677true assume 1 == ~t7_pc~0; 1244#L678true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 888#L688true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1340#L689true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1070#L1435true assume !(0 != activate_threads_~tmp___6~0#1); 1229#L1435-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1303#L696true assume !(1 == ~t8_pc~0); 323#L696-2true is_transmit8_triggered_~__retres1~8#1 := 0; 1149#L707true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1195#L708true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1346#L1443true assume !(0 != activate_threads_~tmp___7~0#1); 1520#L1443-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 617#L715true assume 1 == ~t9_pc~0; 1221#L716true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 380#L726true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 322#L727true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 604#L1451true assume !(0 != activate_threads_~tmp___8~0#1); 1390#L1451-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 886#L734true assume !(1 == ~t10_pc~0); 1037#L734-2true is_transmit10_triggered_~__retres1~10#1 := 0; 267#L745true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 276#L746true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 812#L1459true assume !(0 != activate_threads_~tmp___9~0#1); 1256#L1459-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 310#L753true assume 1 == ~t11_pc~0; 715#L754true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1569#L764true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 376#L765true activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 474#L1467true assume !(0 != activate_threads_~tmp___10~0#1); 776#L1467-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 513#L1237true assume !(1 == ~M_E~0); 1298#L1237-2true assume !(1 == ~T1_E~0); 1419#L1242-1true assume !(1 == ~T2_E~0); 360#L1247-1true assume !(1 == ~T3_E~0); 1066#L1252-1true assume !(1 == ~T4_E~0); 234#L1257-1true assume !(1 == ~T5_E~0); 907#L1262-1true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1053#L1267-1true assume !(1 == ~T7_E~0); 1054#L1272-1true assume !(1 == ~T8_E~0); 410#L1277-1true assume !(1 == ~T9_E~0); 822#L1282-1true assume !(1 == ~T10_E~0); 750#L1287-1true assume !(1 == ~T11_E~0); 791#L1292-1true assume !(1 == ~E_M~0); 708#L1297-1true assume !(1 == ~E_1~0); 306#L1302-1true assume 1 == ~E_2~0;~E_2~0 := 2; 1039#L1307-1true assume !(1 == ~E_3~0); 1356#L1312-1true assume !(1 == ~E_4~0); 437#L1317-1true assume !(1 == ~E_5~0); 612#L1322-1true assume !(1 == ~E_6~0); 274#L1327-1true assume !(1 == ~E_7~0); 663#L1332-1true assume !(1 == ~E_8~0); 1335#L1337-1true assume !(1 == ~E_9~0); 608#L1342-1true assume 1 == ~E_10~0;~E_10~0 := 2; 1233#L1347-1true assume !(1 == ~E_11~0); 1038#L1352-1true assume { :end_inline_reset_delta_events } true; 1563#L1678-2true [2022-07-22 02:42:44,033 INFO L754 eck$LassoCheckResult]: Loop: 1563#L1678-2true assume !false; 655#L1679true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 816#L1084true assume !true; 170#L1099true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 104#L773-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1422#L1109-3true assume 0 == ~M_E~0;~M_E~0 := 1; 37#L1109-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1214#L1114-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 710#L1119-3true assume !(0 == ~T3_E~0); 1558#L1124-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 735#L1129-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 953#L1134-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 1114#L1139-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1026#L1144-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 297#L1149-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1550#L1154-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 442#L1159-3true assume !(0 == ~T11_E~0); 1537#L1164-3true assume 0 == ~E_M~0;~E_M~0 := 1; 651#L1169-3true assume 0 == ~E_1~0;~E_1~0 := 1; 985#L1174-3true assume 0 == ~E_2~0;~E_2~0 := 1; 698#L1179-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1305#L1184-3true assume 0 == ~E_4~0;~E_4~0 := 1; 869#L1189-3true assume 0 == ~E_5~0;~E_5~0 := 1; 550#L1194-3true assume 0 == ~E_6~0;~E_6~0 := 1; 167#L1199-3true assume !(0 == ~E_7~0); 793#L1204-3true assume 0 == ~E_8~0;~E_8~0 := 1; 287#L1209-3true assume 0 == ~E_9~0;~E_9~0 := 1; 14#L1214-3true assume 0 == ~E_10~0;~E_10~0 := 1; 601#L1219-3true assume 0 == ~E_11~0;~E_11~0 := 1; 385#L1224-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 643#L544-39true assume 1 == ~m_pc~0; 1009#L545-13true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 737#L555-13true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 123#L556-13true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 208#L1379-39true assume !(0 != activate_threads_~tmp~1#1); 847#L1379-41true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1316#L563-39true assume !(1 == ~t1_pc~0); 72#L563-41true is_transmit1_triggered_~__retres1~1#1 := 0; 1538#L574-13true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 624#L575-13true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1433#L1387-39true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1445#L1387-41true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1002#L582-39true assume !(1 == ~t2_pc~0); 1241#L582-41true is_transmit2_triggered_~__retres1~2#1 := 0; 760#L593-13true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 666#L594-13true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 970#L1395-39true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 119#L1395-41true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19#L601-39true assume !(1 == ~t3_pc~0); 42#L601-41true is_transmit3_triggered_~__retres1~3#1 := 0; 806#L612-13true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 984#L613-13true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1491#L1403-39true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 855#L1403-41true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 526#L620-39true assume !(1 == ~t4_pc~0); 1544#L620-41true is_transmit4_triggered_~__retres1~4#1 := 0; 939#L631-13true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1499#L632-13true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 820#L1411-39true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1545#L1411-41true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1542#L639-39true assume 1 == ~t5_pc~0; 977#L640-13true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 364#L650-13true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 126#L651-13true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32#L1419-39true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1379#L1419-41true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 554#L658-39true assume !(1 == ~t6_pc~0); 1429#L658-41true is_transmit6_triggered_~__retres1~6#1 := 0; 1064#L669-13true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9#L670-13true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 719#L1427-39true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 691#L1427-41true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1237#L677-39true assume !(1 == ~t7_pc~0); 408#L677-41true is_transmit7_triggered_~__retres1~7#1 := 0; 114#L688-13true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 991#L689-13true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 144#L1435-39true assume !(0 != activate_threads_~tmp___6~0#1); 1368#L1435-41true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 476#L696-39true assume 1 == ~t8_pc~0; 449#L697-13true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 374#L707-13true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1494#L708-13true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 577#L1443-39true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 546#L1443-41true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 460#L715-39true assume 1 == ~t9_pc~0; 21#L716-13true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 814#L726-13true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1568#L727-13true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1567#L1451-39true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 741#L1451-41true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1140#L734-39true assume 1 == ~t10_pc~0; 670#L735-13true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 477#L745-13true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 745#L746-13true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 90#L1459-39true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1459#L1459-41true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1090#L753-39true assume 1 == ~t11_pc~0; 433#L754-13true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1018#L764-13true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1146#L765-13true activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 454#L1467-39true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 749#L1467-41true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 524#L1237-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1085#L1237-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 772#L1242-3true assume !(1 == ~T2_E~0); 1510#L1247-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1052#L1252-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 688#L1257-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1021#L1262-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1097#L1267-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1527#L1272-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1333#L1277-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 129#L1282-3true assume !(1 == ~T10_E~0); 665#L1287-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 81#L1292-3true assume 1 == ~E_M~0;~E_M~0 := 2; 1488#L1297-3true assume 1 == ~E_1~0;~E_1~0 := 2; 899#L1302-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1226#L1307-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1508#L1312-3true assume 1 == ~E_4~0;~E_4~0 := 2; 1502#L1317-3true assume 1 == ~E_5~0;~E_5~0 := 2; 794#L1322-3true assume !(1 == ~E_6~0); 1555#L1327-3true assume 1 == ~E_7~0;~E_7~0 := 2; 111#L1332-3true assume 1 == ~E_8~0;~E_8~0 := 2; 98#L1337-3true assume 1 == ~E_9~0;~E_9~0 := 2; 503#L1342-3true assume 1 == ~E_10~0;~E_10~0 := 2; 942#L1347-3true assume 1 == ~E_11~0;~E_11~0 := 2; 603#L1352-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 890#L848-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 213#L910-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 697#L911-1true start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 740#L1697true assume !(0 == start_simulation_~tmp~3#1); 519#L1697-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1308#L848-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 856#L910-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 618#L911-2true stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 1118#L1652true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 573#L1659true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 305#L1660true start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 887#L1710true assume !(0 != start_simulation_~tmp___0~1#1); 1563#L1678-2true [2022-07-22 02:42:44,037 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:44,038 INFO L85 PathProgramCache]: Analyzing trace with hash 430082112, now seen corresponding path program 1 times [2022-07-22 02:42:44,044 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:44,044 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1430710631] [2022-07-22 02:42:44,045 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:44,045 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:44,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:44,214 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:44,215 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:44,215 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1430710631] [2022-07-22 02:42:44,215 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1430710631] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:44,216 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:44,216 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:44,217 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [208335031] [2022-07-22 02:42:44,218 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:44,221 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:42:44,221 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:44,222 INFO L85 PathProgramCache]: Analyzing trace with hash 1645867658, now seen corresponding path program 1 times [2022-07-22 02:42:44,222 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:44,222 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [699415268] [2022-07-22 02:42:44,222 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:44,222 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:44,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:44,261 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:44,268 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:44,269 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [699415268] [2022-07-22 02:42:44,269 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [699415268] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:44,269 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:44,269 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-22 02:42:44,270 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [345503342] [2022-07-22 02:42:44,270 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:44,271 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:42:44,271 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:42:44,294 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-07-22 02:42:44,294 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-07-22 02:42:44,298 INFO L87 Difference]: Start difference. First operand has 1572 states, 1571 states have (on average 1.5022278803309994) internal successors, (2360), 1571 states have internal predecessors, (2360), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 69.5) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:44,349 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:42:44,349 INFO L93 Difference]: Finished difference Result 1571 states and 2330 transitions. [2022-07-22 02:42:44,350 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-07-22 02:42:44,353 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2330 transitions. [2022-07-22 02:42:44,363 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-07-22 02:42:44,375 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1566 states and 2325 transitions. [2022-07-22 02:42:44,376 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2022-07-22 02:42:44,377 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2022-07-22 02:42:44,378 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2325 transitions. [2022-07-22 02:42:44,383 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:42:44,383 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2325 transitions. [2022-07-22 02:42:44,397 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2325 transitions. [2022-07-22 02:42:44,439 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2022-07-22 02:42:44,443 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4846743295019158) internal successors, (2325), 1565 states have internal predecessors, (2325), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:44,447 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2325 transitions. [2022-07-22 02:42:44,448 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2325 transitions. [2022-07-22 02:42:44,448 INFO L374 stractBuchiCegarLoop]: Abstraction has 1566 states and 2325 transitions. [2022-07-22 02:42:44,448 INFO L287 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-07-22 02:42:44,448 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2325 transitions. [2022-07-22 02:42:44,453 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-07-22 02:42:44,453 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:42:44,454 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:42:44,455 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:44,455 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:44,456 INFO L752 eck$LassoCheckResult]: Stem: 3887#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 3888#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 4616#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4617#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3390#L780 assume !(1 == ~m_i~0);~m_st~0 := 2; 3391#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4626#L785-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4591#L790-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4592#L795-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3739#L800-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3740#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4146#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4564#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3651#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3652#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 3537#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 3538#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4490#L1109 assume !(0 == ~M_E~0); 4512#L1109-2 assume !(0 == ~T1_E~0); 3544#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3545#L1119-1 assume !(0 == ~T3_E~0); 4568#L1124-1 assume !(0 == ~T4_E~0); 3205#L1129-1 assume !(0 == ~T5_E~0); 3206#L1134-1 assume !(0 == ~T6_E~0); 3819#L1139-1 assume !(0 == ~T7_E~0); 4496#L1144-1 assume !(0 == ~T8_E~0); 4368#L1149-1 assume !(0 == ~T9_E~0); 3312#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3313#L1159-1 assume !(0 == ~T11_E~0); 4354#L1164-1 assume !(0 == ~E_M~0); 3705#L1169-1 assume !(0 == ~E_1~0); 3594#L1174-1 assume !(0 == ~E_2~0); 3467#L1179-1 assume !(0 == ~E_3~0); 3394#L1184-1 assume !(0 == ~E_4~0); 3395#L1189-1 assume !(0 == ~E_5~0); 3426#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 3513#L1199-1 assume !(0 == ~E_7~0); 4376#L1204-1 assume !(0 == ~E_8~0); 4312#L1209-1 assume !(0 == ~E_9~0); 4313#L1214-1 assume !(0 == ~E_10~0); 4638#L1219-1 assume !(0 == ~E_11~0); 4711#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3722#L544 assume 1 == ~m_pc~0; 3723#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4555#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4383#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3356#L1379 assume !(0 != activate_threads_~tmp~1#1); 3357#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4129#L563 assume !(1 == ~t1_pc~0); 3929#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3215#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3216#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4252#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 3211#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3212#L582 assume 1 == ~t2_pc~0; 3907#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4262#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4263#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4367#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 3244#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3245#L601 assume !(1 == ~t3_pc~0); 3923#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3922#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4556#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4298#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 4299#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4242#L620 assume 1 == ~t4_pc~0; 3225#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3226#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3787#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3788#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 4143#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4330#L639 assume 1 == ~t5_pc~0; 4213#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3517#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3518#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4164#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 4165#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4094#L658 assume !(1 == ~t6_pc~0); 3719#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3720#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4288#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4618#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4302#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3557#L677 assume 1 == ~t7_pc~0; 3558#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3460#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4461#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4585#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 4586#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4657#L696 assume !(1 == ~t8_pc~0); 3777#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3778#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4625#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4646#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 4692#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4196#L715 assume 1 == ~t9_pc~0; 4197#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3867#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3775#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3776#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 4185#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4457#L734 assume !(1 == ~t10_pc~0); 4458#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3677#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3678#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3696#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 4401#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3753#L753 assume 1 == ~t11_pc~0; 3754#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4307#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3862#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3863#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 4012#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4069#L1237 assume !(1 == ~M_E~0); 4070#L1237-2 assume !(1 == ~T1_E~0); 4682#L1242-1 assume !(1 == ~T2_E~0); 3833#L1247-1 assume !(1 == ~T3_E~0); 3834#L1252-1 assume !(1 == ~T4_E~0); 3617#L1257-1 assume !(1 == ~T5_E~0); 3618#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4473#L1267-1 assume !(1 == ~T7_E~0); 4578#L1272-1 assume !(1 == ~T8_E~0); 3916#L1277-1 assume !(1 == ~T9_E~0); 3917#L1282-1 assume !(1 == ~T10_E~0); 4339#L1287-1 assume !(1 == ~T11_E~0); 4340#L1292-1 assume !(1 == ~E_M~0); 4301#L1297-1 assume !(1 == ~E_1~0); 3748#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 3749#L1307-1 assume !(1 == ~E_3~0); 4571#L1312-1 assume !(1 == ~E_4~0); 3959#L1317-1 assume !(1 == ~E_5~0); 3960#L1322-1 assume !(1 == ~E_6~0); 3692#L1327-1 assume !(1 == ~E_7~0); 3693#L1332-1 assume !(1 == ~E_8~0); 4251#L1337-1 assume !(1 == ~E_9~0); 4188#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 4189#L1347-1 assume !(1 == ~E_11~0); 4570#L1352-1 assume { :end_inline_reset_delta_events } true; 4460#L1678-2 [2022-07-22 02:42:44,457 INFO L754 eck$LassoCheckResult]: Loop: 4460#L1678-2 assume !false; 4243#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4244#L1084 assume !false; 4027#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4028#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3331#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 4345#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3257#L925 assume !(0 != eval_~tmp~0#1); 3259#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3373#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3374#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3228#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3229#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4303#L1119-3 assume !(0 == ~T3_E~0); 4304#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4325#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4326#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4504#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4562#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3732#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3733#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3968#L1159-3 assume !(0 == ~T11_E~0); 3969#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4239#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4240#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4290#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4291#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4446#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4123#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3490#L1199-3 assume !(0 == ~E_7~0); 3491#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3714#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3176#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3177#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 3875#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3876#L544-39 assume !(1 == ~m_pc~0); 3157#L544-41 is_master_triggered_~__retres1~0#1 := 0; 3158#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3408#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3409#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 3565#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4433#L563-39 assume 1 == ~t1_pc~0; 4439#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3308#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4207#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4208#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4705#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4548#L582-39 assume !(1 == ~t2_pc~0); 3632#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 3633#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4253#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4254#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3401#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3188#L601-39 assume 1 == ~t3_pc~0; 3189#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3239#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4397#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4533#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4437#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4089#L620-39 assume !(1 == ~t4_pc~0); 4090#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 4287#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4495#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4410#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4411#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4716#L639-39 assume 1 == ~t5_pc~0; 4523#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3837#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3414#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3217#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3218#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4126#L658-39 assume 1 == ~t6_pc~0; 4108#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4109#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3167#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3168#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4283#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4284#L677-39 assume 1 == ~t7_pc~0; 4246#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3392#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3393#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3448#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 3449#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4014#L696-39 assume 1 == ~t8_pc~0; 3979#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3859#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3860#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4155#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4119#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3994#L715-39 assume 1 == ~t9_pc~0; 3193#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3194#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4403#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4717#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4332#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4333#L734-39 assume 1 == ~t10_pc~0; 4258#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 3704#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4015#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3346#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3347#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4595#L753-39 assume !(1 == ~t11_pc~0); 3266#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 3267#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4559#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3984#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3985#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4086#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4087#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4357#L1242-3 assume !(1 == ~T2_E~0); 4358#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4577#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4277#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4278#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4560#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4601#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4689#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3418#L1282-3 assume !(1 == ~T10_E~0); 3419#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 3328#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3329#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4466#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4467#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4655#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4713#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4379#L1322-3 assume !(1 == ~E_6~0); 4380#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3387#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3362#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3363#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4055#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4183#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4184#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3310#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3575#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 4289#L1697 assume !(0 == start_simulation_~tmp~3#1); 4076#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4077#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3434#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 4199#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 4200#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4149#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3746#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 3747#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 4460#L1678-2 [2022-07-22 02:42:44,457 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:44,457 INFO L85 PathProgramCache]: Analyzing trace with hash 430082112, now seen corresponding path program 2 times [2022-07-22 02:42:44,458 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:44,458 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1833661516] [2022-07-22 02:42:44,458 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:44,458 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:44,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:44,510 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:44,510 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:44,511 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1833661516] [2022-07-22 02:42:44,511 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1833661516] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:44,511 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:44,511 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:44,511 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1961336032] [2022-07-22 02:42:44,511 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:44,512 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:42:44,512 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:44,512 INFO L85 PathProgramCache]: Analyzing trace with hash 1065978444, now seen corresponding path program 1 times [2022-07-22 02:42:44,512 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:44,513 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1256145629] [2022-07-22 02:42:44,513 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:44,513 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:44,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:44,574 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:44,575 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:44,575 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1256145629] [2022-07-22 02:42:44,575 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1256145629] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:44,575 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:44,575 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:44,575 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1772473702] [2022-07-22 02:42:44,576 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:44,576 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:42:44,576 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:42:44,577 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:42:44,577 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:42:44,577 INFO L87 Difference]: Start difference. First operand 1566 states and 2325 transitions. cyclomatic complexity: 760 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:44,639 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:42:44,639 INFO L93 Difference]: Finished difference Result 1566 states and 2324 transitions. [2022-07-22 02:42:44,640 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:42:44,640 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2324 transitions. [2022-07-22 02:42:44,647 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-07-22 02:42:44,652 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2324 transitions. [2022-07-22 02:42:44,652 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2022-07-22 02:42:44,653 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2022-07-22 02:42:44,653 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2324 transitions. [2022-07-22 02:42:44,654 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:42:44,655 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2324 transitions. [2022-07-22 02:42:44,656 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2324 transitions. [2022-07-22 02:42:44,666 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2022-07-22 02:42:44,668 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4840357598978289) internal successors, (2324), 1565 states have internal predecessors, (2324), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:44,670 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2324 transitions. [2022-07-22 02:42:44,671 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2324 transitions. [2022-07-22 02:42:44,671 INFO L374 stractBuchiCegarLoop]: Abstraction has 1566 states and 2324 transitions. [2022-07-22 02:42:44,671 INFO L287 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-07-22 02:42:44,671 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2324 transitions. [2022-07-22 02:42:44,676 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-07-22 02:42:44,676 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:42:44,676 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:42:44,678 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:44,678 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:44,678 INFO L752 eck$LassoCheckResult]: Stem: 7026#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 7027#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 7755#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7756#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6529#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 6530#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7765#L785-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 7730#L790-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 7731#L795-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6878#L800-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6879#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7285#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7703#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6790#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 6791#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 6676#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 6677#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7629#L1109 assume !(0 == ~M_E~0); 7651#L1109-2 assume !(0 == ~T1_E~0); 6683#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6684#L1119-1 assume !(0 == ~T3_E~0); 7707#L1124-1 assume !(0 == ~T4_E~0); 6344#L1129-1 assume !(0 == ~T5_E~0); 6345#L1134-1 assume !(0 == ~T6_E~0); 6958#L1139-1 assume !(0 == ~T7_E~0); 7635#L1144-1 assume !(0 == ~T8_E~0); 7507#L1149-1 assume !(0 == ~T9_E~0); 6451#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 6452#L1159-1 assume !(0 == ~T11_E~0); 7493#L1164-1 assume !(0 == ~E_M~0); 6844#L1169-1 assume !(0 == ~E_1~0); 6733#L1174-1 assume !(0 == ~E_2~0); 6606#L1179-1 assume !(0 == ~E_3~0); 6533#L1184-1 assume !(0 == ~E_4~0); 6534#L1189-1 assume !(0 == ~E_5~0); 6565#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 6652#L1199-1 assume !(0 == ~E_7~0); 7515#L1204-1 assume !(0 == ~E_8~0); 7451#L1209-1 assume !(0 == ~E_9~0); 7452#L1214-1 assume !(0 == ~E_10~0); 7777#L1219-1 assume !(0 == ~E_11~0); 7850#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6861#L544 assume 1 == ~m_pc~0; 6862#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7694#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7522#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6495#L1379 assume !(0 != activate_threads_~tmp~1#1); 6496#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7268#L563 assume !(1 == ~t1_pc~0); 7068#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6354#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6355#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7391#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 6350#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6351#L582 assume 1 == ~t2_pc~0; 7046#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7401#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7402#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7506#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 6383#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6384#L601 assume !(1 == ~t3_pc~0); 7062#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7061#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7695#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7437#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 7438#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7381#L620 assume 1 == ~t4_pc~0; 6364#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6365#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6926#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6927#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 7282#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7469#L639 assume 1 == ~t5_pc~0; 7352#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6656#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6657#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7303#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 7304#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7233#L658 assume !(1 == ~t6_pc~0); 6858#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6859#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7427#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7757#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7441#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6696#L677 assume 1 == ~t7_pc~0; 6697#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6599#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7600#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7724#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 7725#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7796#L696 assume !(1 == ~t8_pc~0); 6916#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 6917#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7764#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7785#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 7831#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7335#L715 assume 1 == ~t9_pc~0; 7336#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7006#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6914#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6915#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 7324#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7596#L734 assume !(1 == ~t10_pc~0); 7597#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 6816#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6817#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 6835#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 7540#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6892#L753 assume 1 == ~t11_pc~0; 6893#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7446#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7001#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7002#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 7151#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7208#L1237 assume !(1 == ~M_E~0); 7209#L1237-2 assume !(1 == ~T1_E~0); 7821#L1242-1 assume !(1 == ~T2_E~0); 6972#L1247-1 assume !(1 == ~T3_E~0); 6973#L1252-1 assume !(1 == ~T4_E~0); 6756#L1257-1 assume !(1 == ~T5_E~0); 6757#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7612#L1267-1 assume !(1 == ~T7_E~0); 7717#L1272-1 assume !(1 == ~T8_E~0); 7055#L1277-1 assume !(1 == ~T9_E~0); 7056#L1282-1 assume !(1 == ~T10_E~0); 7478#L1287-1 assume !(1 == ~T11_E~0); 7479#L1292-1 assume !(1 == ~E_M~0); 7440#L1297-1 assume !(1 == ~E_1~0); 6887#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 6888#L1307-1 assume !(1 == ~E_3~0); 7710#L1312-1 assume !(1 == ~E_4~0); 7098#L1317-1 assume !(1 == ~E_5~0); 7099#L1322-1 assume !(1 == ~E_6~0); 6831#L1327-1 assume !(1 == ~E_7~0); 6832#L1332-1 assume !(1 == ~E_8~0); 7390#L1337-1 assume !(1 == ~E_9~0); 7327#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 7328#L1347-1 assume !(1 == ~E_11~0); 7709#L1352-1 assume { :end_inline_reset_delta_events } true; 7599#L1678-2 [2022-07-22 02:42:44,679 INFO L754 eck$LassoCheckResult]: Loop: 7599#L1678-2 assume !false; 7382#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7383#L1084 assume !false; 7166#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 7167#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6470#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 7484#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 6396#L925 assume !(0 != eval_~tmp~0#1); 6398#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6512#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6513#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6367#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6368#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7442#L1119-3 assume !(0 == ~T3_E~0); 7443#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7464#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7465#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7643#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7701#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 6871#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 6872#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 7107#L1159-3 assume !(0 == ~T11_E~0); 7108#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7378#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7379#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7429#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7430#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7585#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7262#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6629#L1199-3 assume !(0 == ~E_7~0); 6630#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6853#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 6315#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 6316#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 7014#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7015#L544-39 assume !(1 == ~m_pc~0); 6296#L544-41 is_master_triggered_~__retres1~0#1 := 0; 6297#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6547#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6548#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 6704#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7572#L563-39 assume 1 == ~t1_pc~0; 7578#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6447#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7346#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7347#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7844#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7687#L582-39 assume 1 == ~t2_pc~0; 6770#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6772#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7392#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7393#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6540#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6327#L601-39 assume 1 == ~t3_pc~0; 6328#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6378#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7536#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7672#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7576#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7228#L620-39 assume !(1 == ~t4_pc~0); 7229#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 7426#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7634#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7549#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7550#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7855#L639-39 assume 1 == ~t5_pc~0; 7662#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6976#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6553#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6356#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6357#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7265#L658-39 assume !(1 == ~t6_pc~0); 7249#L658-41 is_transmit6_triggered_~__retres1~6#1 := 0; 7248#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6306#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6307#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7422#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7423#L677-39 assume 1 == ~t7_pc~0; 7385#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6531#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6532#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6587#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 6588#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7153#L696-39 assume 1 == ~t8_pc~0; 7118#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6998#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6999#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7294#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7258#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7133#L715-39 assume 1 == ~t9_pc~0; 6332#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 6333#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7542#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 7856#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 7471#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7472#L734-39 assume 1 == ~t10_pc~0; 7397#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 6843#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7154#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 6485#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 6486#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 7734#L753-39 assume !(1 == ~t11_pc~0); 6405#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 6406#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7698#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7123#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 7124#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7225#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7226#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7496#L1242-3 assume !(1 == ~T2_E~0); 7497#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7716#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7416#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7417#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7699#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7740#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7828#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 6557#L1282-3 assume !(1 == ~T10_E~0); 6558#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 6467#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6468#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7605#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7606#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7794#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7852#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7518#L1322-3 assume !(1 == ~E_6~0); 7519#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6526#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6501#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 6502#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 7194#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 7322#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 7323#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6449#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 6714#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 7428#L1697 assume !(0 == start_simulation_~tmp~3#1); 7215#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 7216#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6573#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 7338#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 7339#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7288#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6885#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 6886#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 7599#L1678-2 [2022-07-22 02:42:44,679 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:44,679 INFO L85 PathProgramCache]: Analyzing trace with hash -968871490, now seen corresponding path program 1 times [2022-07-22 02:42:44,680 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:44,680 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1250267217] [2022-07-22 02:42:44,680 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:44,680 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:44,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:44,706 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:44,706 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:44,706 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1250267217] [2022-07-22 02:42:44,707 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1250267217] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:44,707 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:44,707 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:44,707 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [476866780] [2022-07-22 02:42:44,707 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:44,708 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:42:44,708 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:44,708 INFO L85 PathProgramCache]: Analyzing trace with hash 764411212, now seen corresponding path program 1 times [2022-07-22 02:42:44,708 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:44,708 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [376148353] [2022-07-22 02:42:44,709 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:44,709 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:44,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:44,774 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:44,774 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:44,774 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [376148353] [2022-07-22 02:42:44,774 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [376148353] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:44,775 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:44,775 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:44,775 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [380181633] [2022-07-22 02:42:44,775 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:44,775 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:42:44,776 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:42:44,776 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:42:44,776 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:42:44,776 INFO L87 Difference]: Start difference. First operand 1566 states and 2324 transitions. cyclomatic complexity: 759 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:44,798 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:42:44,798 INFO L93 Difference]: Finished difference Result 1566 states and 2323 transitions. [2022-07-22 02:42:44,799 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:42:44,799 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2323 transitions. [2022-07-22 02:42:44,806 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-07-22 02:42:44,811 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2323 transitions. [2022-07-22 02:42:44,812 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2022-07-22 02:42:44,812 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2022-07-22 02:42:44,813 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2323 transitions. [2022-07-22 02:42:44,814 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:42:44,814 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2323 transitions. [2022-07-22 02:42:44,816 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2323 transitions. [2022-07-22 02:42:44,826 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2022-07-22 02:42:44,828 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.483397190293742) internal successors, (2323), 1565 states have internal predecessors, (2323), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:44,830 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2323 transitions. [2022-07-22 02:42:44,831 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2323 transitions. [2022-07-22 02:42:44,831 INFO L374 stractBuchiCegarLoop]: Abstraction has 1566 states and 2323 transitions. [2022-07-22 02:42:44,831 INFO L287 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-07-22 02:42:44,831 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2323 transitions. [2022-07-22 02:42:44,839 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-07-22 02:42:44,840 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:42:44,840 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:42:44,841 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:44,841 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:44,842 INFO L752 eck$LassoCheckResult]: Stem: 10165#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 10166#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 10894#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10895#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9668#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 9669#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10904#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10869#L790-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 10870#L795-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 10017#L800-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 10018#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10424#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10842#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9929#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9930#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 9815#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9816#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10770#L1109 assume !(0 == ~M_E~0); 10790#L1109-2 assume !(0 == ~T1_E~0); 9822#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9823#L1119-1 assume !(0 == ~T3_E~0); 10846#L1124-1 assume !(0 == ~T4_E~0); 9485#L1129-1 assume !(0 == ~T5_E~0); 9486#L1134-1 assume !(0 == ~T6_E~0); 10097#L1139-1 assume !(0 == ~T7_E~0); 10774#L1144-1 assume !(0 == ~T8_E~0); 10646#L1149-1 assume !(0 == ~T9_E~0); 9592#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9593#L1159-1 assume !(0 == ~T11_E~0); 10632#L1164-1 assume !(0 == ~E_M~0); 9983#L1169-1 assume !(0 == ~E_1~0); 9872#L1174-1 assume !(0 == ~E_2~0); 9748#L1179-1 assume !(0 == ~E_3~0); 9672#L1184-1 assume !(0 == ~E_4~0); 9673#L1189-1 assume !(0 == ~E_5~0); 9704#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 9793#L1199-1 assume !(0 == ~E_7~0); 10654#L1204-1 assume !(0 == ~E_8~0); 10591#L1209-1 assume !(0 == ~E_9~0); 10592#L1214-1 assume !(0 == ~E_10~0); 10916#L1219-1 assume !(0 == ~E_11~0); 10989#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10002#L544 assume 1 == ~m_pc~0; 10003#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10833#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10663#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9634#L1379 assume !(0 != activate_threads_~tmp~1#1); 9635#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10410#L563 assume !(1 == ~t1_pc~0); 10207#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9493#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9494#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10530#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 9489#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9490#L582 assume 1 == ~t2_pc~0; 10185#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10540#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10541#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10645#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 9522#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9523#L601 assume !(1 == ~t3_pc~0); 10201#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 10200#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10834#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10576#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 10577#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10520#L620 assume 1 == ~t4_pc~0; 9503#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9504#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10065#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10066#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 10421#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10609#L639 assume 1 == ~t5_pc~0; 10494#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9795#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9796#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10442#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 10443#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10374#L658 assume !(1 == ~t6_pc~0); 9997#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 9998#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10567#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10896#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10580#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9837#L677 assume 1 == ~t7_pc~0; 9838#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9741#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10739#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10863#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 10864#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10935#L696 assume !(1 == ~t8_pc~0); 10056#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 10057#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10903#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10924#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 10970#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10474#L715 assume 1 == ~t9_pc~0; 10475#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10145#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10053#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 10054#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 10463#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10736#L734 assume !(1 == ~t10_pc~0); 10737#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 9955#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9956#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9976#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 10679#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10031#L753 assume 1 == ~t11_pc~0; 10032#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 10585#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10140#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 10141#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 10292#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10349#L1237 assume !(1 == ~M_E~0); 10350#L1237-2 assume !(1 == ~T1_E~0); 10961#L1242-1 assume !(1 == ~T2_E~0); 10111#L1247-1 assume !(1 == ~T3_E~0); 10112#L1252-1 assume !(1 == ~T4_E~0); 9895#L1257-1 assume !(1 == ~T5_E~0); 9896#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10752#L1267-1 assume !(1 == ~T7_E~0); 10856#L1272-1 assume !(1 == ~T8_E~0); 10194#L1277-1 assume !(1 == ~T9_E~0); 10195#L1282-1 assume !(1 == ~T10_E~0); 10617#L1287-1 assume !(1 == ~T11_E~0); 10618#L1292-1 assume !(1 == ~E_M~0); 10579#L1297-1 assume !(1 == ~E_1~0); 10026#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 10027#L1307-1 assume !(1 == ~E_3~0); 10849#L1312-1 assume !(1 == ~E_4~0); 10237#L1317-1 assume !(1 == ~E_5~0); 10238#L1322-1 assume !(1 == ~E_6~0); 9970#L1327-1 assume !(1 == ~E_7~0); 9971#L1332-1 assume !(1 == ~E_8~0); 10529#L1337-1 assume !(1 == ~E_9~0); 10466#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 10467#L1347-1 assume !(1 == ~E_11~0); 10848#L1352-1 assume { :end_inline_reset_delta_events } true; 10735#L1678-2 [2022-07-22 02:42:44,842 INFO L754 eck$LassoCheckResult]: Loop: 10735#L1678-2 assume !false; 10522#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10523#L1084 assume !false; 10306#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 10307#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9609#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 10624#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 9535#L925 assume !(0 != eval_~tmp~0#1); 9537#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9651#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9652#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9506#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9507#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10581#L1119-3 assume !(0 == ~T3_E~0); 10582#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10603#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10604#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10782#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10840#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 10010#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10011#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 10248#L1159-3 assume !(0 == ~T11_E~0); 10249#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10517#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10518#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10568#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10569#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10724#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10401#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9768#L1199-3 assume !(0 == ~E_7~0); 9769#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9992#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 9454#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 9455#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 10153#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10154#L544-39 assume !(1 == ~m_pc~0); 9435#L544-41 is_master_triggered_~__retres1~0#1 := 0; 9436#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9684#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9685#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 9843#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10711#L563-39 assume !(1 == ~t1_pc~0); 9585#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 9586#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10485#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10486#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10983#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10826#L582-39 assume 1 == ~t2_pc~0; 9909#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9911#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10531#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10532#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9679#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9466#L601-39 assume 1 == ~t3_pc~0; 9467#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9517#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10675#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10811#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10715#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10367#L620-39 assume !(1 == ~t4_pc~0); 10368#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 10565#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10773#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10688#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10689#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10994#L639-39 assume 1 == ~t5_pc~0; 10801#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10115#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9692#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9495#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9496#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10404#L658-39 assume 1 == ~t6_pc~0; 10386#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10387#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9445#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9446#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10561#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10562#L677-39 assume !(1 == ~t7_pc~0); 10192#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 9670#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9671#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9726#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 9727#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10291#L696-39 assume 1 == ~t8_pc~0; 10257#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 10137#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10138#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10433#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 10397#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10272#L715-39 assume !(1 == ~t9_pc~0); 9473#L715-41 is_transmit9_triggered_~__retres1~9#1 := 0; 9472#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10681#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 10995#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 10610#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10611#L734-39 assume 1 == ~t10_pc~0; 10536#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 9982#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 10293#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9624#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9625#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10873#L753-39 assume !(1 == ~t11_pc~0); 9544#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 9545#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10837#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 10262#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 10263#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10364#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10365#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10635#L1242-3 assume !(1 == ~T2_E~0); 10636#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10855#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10555#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10556#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10838#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10879#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10967#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9696#L1282-3 assume !(1 == ~T10_E~0); 9697#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 9606#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9607#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10744#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10745#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10933#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10991#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10657#L1322-3 assume !(1 == ~E_6~0); 10658#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9665#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9640#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9641#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 10333#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 10461#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 10462#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9588#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 9853#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 10566#L1697 assume !(0 == start_simulation_~tmp~3#1); 10354#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 10355#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9712#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 10477#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 10478#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10427#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10024#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 10025#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 10735#L1678-2 [2022-07-22 02:42:44,843 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:44,843 INFO L85 PathProgramCache]: Analyzing trace with hash -1332337988, now seen corresponding path program 1 times [2022-07-22 02:42:44,843 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:44,844 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2136779728] [2022-07-22 02:42:44,844 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:44,844 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:44,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:44,868 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:44,868 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:44,869 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2136779728] [2022-07-22 02:42:44,869 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2136779728] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:44,869 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:44,869 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:44,869 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1944632962] [2022-07-22 02:42:44,869 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:44,870 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:42:44,870 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:44,870 INFO L85 PathProgramCache]: Analyzing trace with hash 1977169166, now seen corresponding path program 1 times [2022-07-22 02:42:44,871 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:44,871 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [966469134] [2022-07-22 02:42:44,871 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:44,871 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:44,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:44,913 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:44,913 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:44,913 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [966469134] [2022-07-22 02:42:44,913 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [966469134] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:44,914 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:44,914 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:44,914 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1916592732] [2022-07-22 02:42:44,914 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:44,914 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:42:44,915 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:42:44,915 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:42:44,915 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:42:44,915 INFO L87 Difference]: Start difference. First operand 1566 states and 2323 transitions. cyclomatic complexity: 758 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:44,936 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:42:44,936 INFO L93 Difference]: Finished difference Result 1566 states and 2322 transitions. [2022-07-22 02:42:44,936 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:42:44,937 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2322 transitions. [2022-07-22 02:42:44,943 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-07-22 02:42:44,949 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2322 transitions. [2022-07-22 02:42:44,949 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2022-07-22 02:42:44,950 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2022-07-22 02:42:44,950 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2322 transitions. [2022-07-22 02:42:44,951 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:42:44,951 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2322 transitions. [2022-07-22 02:42:44,953 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2322 transitions. [2022-07-22 02:42:44,991 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2022-07-22 02:42:44,993 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4827586206896552) internal successors, (2322), 1565 states have internal predecessors, (2322), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:44,996 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2322 transitions. [2022-07-22 02:42:44,996 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2322 transitions. [2022-07-22 02:42:44,996 INFO L374 stractBuchiCegarLoop]: Abstraction has 1566 states and 2322 transitions. [2022-07-22 02:42:44,997 INFO L287 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-07-22 02:42:44,997 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2322 transitions. [2022-07-22 02:42:45,002 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-07-22 02:42:45,002 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:42:45,002 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:42:45,003 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:45,003 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:45,004 INFO L752 eck$LassoCheckResult]: Stem: 13304#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 13305#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 14033#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14034#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12807#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 12808#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14043#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14008#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14009#L795-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 13156#L800-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13157#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13563#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 13981#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 13068#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 13069#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 12954#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12955#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13907#L1109 assume !(0 == ~M_E~0); 13929#L1109-2 assume !(0 == ~T1_E~0); 12961#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12962#L1119-1 assume !(0 == ~T3_E~0); 13985#L1124-1 assume !(0 == ~T4_E~0); 12624#L1129-1 assume !(0 == ~T5_E~0); 12625#L1134-1 assume !(0 == ~T6_E~0); 13236#L1139-1 assume !(0 == ~T7_E~0); 13913#L1144-1 assume !(0 == ~T8_E~0); 13785#L1149-1 assume !(0 == ~T9_E~0); 12729#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12730#L1159-1 assume !(0 == ~T11_E~0); 13771#L1164-1 assume !(0 == ~E_M~0); 13122#L1169-1 assume !(0 == ~E_1~0); 13011#L1174-1 assume !(0 == ~E_2~0); 12884#L1179-1 assume !(0 == ~E_3~0); 12811#L1184-1 assume !(0 == ~E_4~0); 12812#L1189-1 assume !(0 == ~E_5~0); 12843#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 12930#L1199-1 assume !(0 == ~E_7~0); 13793#L1204-1 assume !(0 == ~E_8~0); 13729#L1209-1 assume !(0 == ~E_9~0); 13730#L1214-1 assume !(0 == ~E_10~0); 14055#L1219-1 assume !(0 == ~E_11~0); 14128#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13139#L544 assume 1 == ~m_pc~0; 13140#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 13972#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13800#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12773#L1379 assume !(0 != activate_threads_~tmp~1#1); 12774#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13546#L563 assume !(1 == ~t1_pc~0); 13346#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12632#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12633#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13669#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 12628#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12629#L582 assume 1 == ~t2_pc~0; 13324#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13679#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13680#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13784#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 12661#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12662#L601 assume !(1 == ~t3_pc~0); 13340#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13339#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13973#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13715#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 13716#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13659#L620 assume 1 == ~t4_pc~0; 12642#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12643#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13204#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13205#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 13560#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13748#L639 assume 1 == ~t5_pc~0; 13631#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12934#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12935#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13581#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 13582#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13511#L658 assume !(1 == ~t6_pc~0); 13136#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 13137#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13706#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14035#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13719#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12974#L677 assume 1 == ~t7_pc~0; 12975#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12877#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13878#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14002#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 14003#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14074#L696 assume !(1 == ~t8_pc~0); 13194#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 13195#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14042#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14063#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 14109#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13613#L715 assume 1 == ~t9_pc~0; 13614#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 13284#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13192#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 13193#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 13602#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13875#L734 assume !(1 == ~t10_pc~0); 13876#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 13094#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13095#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13113#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 13818#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13170#L753 assume 1 == ~t11_pc~0; 13171#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 13724#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 13279#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13280#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 13429#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13486#L1237 assume !(1 == ~M_E~0); 13487#L1237-2 assume !(1 == ~T1_E~0); 14099#L1242-1 assume !(1 == ~T2_E~0); 13250#L1247-1 assume !(1 == ~T3_E~0); 13251#L1252-1 assume !(1 == ~T4_E~0); 13034#L1257-1 assume !(1 == ~T5_E~0); 13035#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13890#L1267-1 assume !(1 == ~T7_E~0); 13995#L1272-1 assume !(1 == ~T8_E~0); 13333#L1277-1 assume !(1 == ~T9_E~0); 13334#L1282-1 assume !(1 == ~T10_E~0); 13756#L1287-1 assume !(1 == ~T11_E~0); 13757#L1292-1 assume !(1 == ~E_M~0); 13718#L1297-1 assume !(1 == ~E_1~0); 13165#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 13166#L1307-1 assume !(1 == ~E_3~0); 13988#L1312-1 assume !(1 == ~E_4~0); 13376#L1317-1 assume !(1 == ~E_5~0); 13377#L1322-1 assume !(1 == ~E_6~0); 13109#L1327-1 assume !(1 == ~E_7~0); 13110#L1332-1 assume !(1 == ~E_8~0); 13668#L1337-1 assume !(1 == ~E_9~0); 13605#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 13606#L1347-1 assume !(1 == ~E_11~0); 13987#L1352-1 assume { :end_inline_reset_delta_events } true; 13874#L1678-2 [2022-07-22 02:42:45,004 INFO L754 eck$LassoCheckResult]: Loop: 13874#L1678-2 assume !false; 13660#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13661#L1084 assume !false; 13444#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 13445#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12748#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 13762#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 12674#L925 assume !(0 != eval_~tmp~0#1); 12676#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12790#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12791#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12645#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12646#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13720#L1119-3 assume !(0 == ~T3_E~0); 13721#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13742#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13743#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13921#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13979#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13149#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13150#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13385#L1159-3 assume !(0 == ~T11_E~0); 13386#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13656#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13657#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13707#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13708#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 13863#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13540#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12907#L1199-3 assume !(0 == ~E_7~0); 12908#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 13133#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12593#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12594#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 13292#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13293#L544-39 assume 1 == ~m_pc~0; 13648#L545-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12575#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12825#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12826#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 12982#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13850#L563-39 assume 1 == ~t1_pc~0; 13856#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12728#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13624#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13625#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14122#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13965#L582-39 assume 1 == ~t2_pc~0; 13048#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13050#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13670#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13671#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12818#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12605#L601-39 assume 1 == ~t3_pc~0; 12606#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12656#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13814#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13950#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13854#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13506#L620-39 assume !(1 == ~t4_pc~0); 13507#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 13704#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13912#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13827#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13828#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14133#L639-39 assume 1 == ~t5_pc~0; 13940#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13254#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12831#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12634#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12635#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13543#L658-39 assume 1 == ~t6_pc~0; 13525#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13526#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12584#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12585#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13700#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13701#L677-39 assume !(1 == ~t7_pc~0); 13331#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 12809#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12810#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12865#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 12866#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13431#L696-39 assume 1 == ~t8_pc~0; 13396#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13276#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13277#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13572#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 13536#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13409#L715-39 assume 1 == ~t9_pc~0; 12608#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12609#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13820#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14134#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13749#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13750#L734-39 assume 1 == ~t10_pc~0; 13675#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 13120#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13432#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12763#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12764#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 14011#L753-39 assume !(1 == ~t11_pc~0); 12683#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 12684#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 13976#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13401#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 13402#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13499#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13500#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13774#L1242-3 assume !(1 == ~T2_E~0); 13775#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13994#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13694#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13695#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13977#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14018#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14106#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 12834#L1282-3 assume !(1 == ~T10_E~0); 12835#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 12745#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12746#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13881#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13882#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14072#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14130#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 13796#L1322-3 assume !(1 == ~E_6~0); 13797#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12804#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12779#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12780#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 13472#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 13600#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 13601#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12722#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 12992#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 13705#L1697 assume !(0 == start_simulation_~tmp~3#1); 13493#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 13494#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12851#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 13616#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 13617#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13566#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13161#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 13162#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 13874#L1678-2 [2022-07-22 02:42:45,005 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:45,005 INFO L85 PathProgramCache]: Analyzing trace with hash -1621157378, now seen corresponding path program 1 times [2022-07-22 02:42:45,005 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:45,005 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [9635372] [2022-07-22 02:42:45,005 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:45,005 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:45,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:45,025 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:45,026 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:45,026 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [9635372] [2022-07-22 02:42:45,026 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [9635372] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:45,026 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:45,026 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:45,027 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [444447549] [2022-07-22 02:42:45,027 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:45,027 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:42:45,027 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:45,028 INFO L85 PathProgramCache]: Analyzing trace with hash 1734525003, now seen corresponding path program 1 times [2022-07-22 02:42:45,028 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:45,028 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [727386082] [2022-07-22 02:42:45,028 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:45,028 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:45,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:45,056 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:45,056 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:45,056 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [727386082] [2022-07-22 02:42:45,056 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [727386082] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:45,057 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:45,057 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:45,057 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1601838085] [2022-07-22 02:42:45,057 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:45,057 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:42:45,057 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:42:45,058 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:42:45,058 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:42:45,058 INFO L87 Difference]: Start difference. First operand 1566 states and 2322 transitions. cyclomatic complexity: 757 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:45,078 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:42:45,078 INFO L93 Difference]: Finished difference Result 1566 states and 2321 transitions. [2022-07-22 02:42:45,078 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:42:45,079 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2321 transitions. [2022-07-22 02:42:45,086 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-07-22 02:42:45,091 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2321 transitions. [2022-07-22 02:42:45,091 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2022-07-22 02:42:45,092 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2022-07-22 02:42:45,092 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2321 transitions. [2022-07-22 02:42:45,093 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:42:45,094 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2321 transitions. [2022-07-22 02:42:45,095 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2321 transitions. [2022-07-22 02:42:45,105 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2022-07-22 02:42:45,107 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4821200510855683) internal successors, (2321), 1565 states have internal predecessors, (2321), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:45,110 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2321 transitions. [2022-07-22 02:42:45,110 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2321 transitions. [2022-07-22 02:42:45,110 INFO L374 stractBuchiCegarLoop]: Abstraction has 1566 states and 2321 transitions. [2022-07-22 02:42:45,110 INFO L287 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-07-22 02:42:45,110 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2321 transitions. [2022-07-22 02:42:45,116 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-07-22 02:42:45,116 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:42:45,116 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:42:45,117 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:45,117 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:45,117 INFO L752 eck$LassoCheckResult]: Stem: 16443#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 16444#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 17172#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17173#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15946#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 15947#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17182#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17147#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17148#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16295#L800-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 16296#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 16702#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17120#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16207#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16208#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 16093#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 16094#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17046#L1109 assume !(0 == ~M_E~0); 17068#L1109-2 assume !(0 == ~T1_E~0); 16100#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16101#L1119-1 assume !(0 == ~T3_E~0); 17124#L1124-1 assume !(0 == ~T4_E~0); 15761#L1129-1 assume !(0 == ~T5_E~0); 15762#L1134-1 assume !(0 == ~T6_E~0); 16375#L1139-1 assume !(0 == ~T7_E~0); 17052#L1144-1 assume !(0 == ~T8_E~0); 16924#L1149-1 assume !(0 == ~T9_E~0); 15868#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 15869#L1159-1 assume !(0 == ~T11_E~0); 16910#L1164-1 assume !(0 == ~E_M~0); 16261#L1169-1 assume !(0 == ~E_1~0); 16150#L1174-1 assume !(0 == ~E_2~0); 16023#L1179-1 assume !(0 == ~E_3~0); 15950#L1184-1 assume !(0 == ~E_4~0); 15951#L1189-1 assume !(0 == ~E_5~0); 15982#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 16069#L1199-1 assume !(0 == ~E_7~0); 16932#L1204-1 assume !(0 == ~E_8~0); 16868#L1209-1 assume !(0 == ~E_9~0); 16869#L1214-1 assume !(0 == ~E_10~0); 17194#L1219-1 assume !(0 == ~E_11~0); 17267#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16278#L544 assume 1 == ~m_pc~0; 16279#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 17111#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16939#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15912#L1379 assume !(0 != activate_threads_~tmp~1#1); 15913#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16685#L563 assume !(1 == ~t1_pc~0); 16485#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 15771#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15772#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16808#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 15767#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15768#L582 assume 1 == ~t2_pc~0; 16463#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16818#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16819#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16923#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 15800#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15801#L601 assume !(1 == ~t3_pc~0); 16479#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 16478#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17112#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16854#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 16855#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16798#L620 assume 1 == ~t4_pc~0; 15781#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15782#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16343#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16344#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 16699#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16886#L639 assume 1 == ~t5_pc~0; 16769#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16073#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16074#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16720#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 16721#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16650#L658 assume !(1 == ~t6_pc~0); 16275#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 16276#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16844#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17174#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16858#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16113#L677 assume 1 == ~t7_pc~0; 16114#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16016#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17017#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17141#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 17142#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17213#L696 assume !(1 == ~t8_pc~0); 16333#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 16334#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17181#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17202#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 17248#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16752#L715 assume 1 == ~t9_pc~0; 16753#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16423#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16331#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16332#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 16741#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17013#L734 assume !(1 == ~t10_pc~0); 17014#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 16233#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16234#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 16252#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 16957#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16309#L753 assume 1 == ~t11_pc~0; 16310#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 16863#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 16418#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16419#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 16568#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16625#L1237 assume !(1 == ~M_E~0); 16626#L1237-2 assume !(1 == ~T1_E~0); 17238#L1242-1 assume !(1 == ~T2_E~0); 16389#L1247-1 assume !(1 == ~T3_E~0); 16390#L1252-1 assume !(1 == ~T4_E~0); 16173#L1257-1 assume !(1 == ~T5_E~0); 16174#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17029#L1267-1 assume !(1 == ~T7_E~0); 17134#L1272-1 assume !(1 == ~T8_E~0); 16472#L1277-1 assume !(1 == ~T9_E~0); 16473#L1282-1 assume !(1 == ~T10_E~0); 16895#L1287-1 assume !(1 == ~T11_E~0); 16896#L1292-1 assume !(1 == ~E_M~0); 16857#L1297-1 assume !(1 == ~E_1~0); 16304#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 16305#L1307-1 assume !(1 == ~E_3~0); 17127#L1312-1 assume !(1 == ~E_4~0); 16515#L1317-1 assume !(1 == ~E_5~0); 16516#L1322-1 assume !(1 == ~E_6~0); 16248#L1327-1 assume !(1 == ~E_7~0); 16249#L1332-1 assume !(1 == ~E_8~0); 16807#L1337-1 assume !(1 == ~E_9~0); 16744#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 16745#L1347-1 assume !(1 == ~E_11~0); 17126#L1352-1 assume { :end_inline_reset_delta_events } true; 17016#L1678-2 [2022-07-22 02:42:45,118 INFO L754 eck$LassoCheckResult]: Loop: 17016#L1678-2 assume !false; 16799#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16800#L1084 assume !false; 16583#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 16584#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15887#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 16901#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 15813#L925 assume !(0 != eval_~tmp~0#1); 15815#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15929#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15930#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15784#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15785#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16859#L1119-3 assume !(0 == ~T3_E~0); 16860#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16881#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16882#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 17060#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 17118#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16288#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16289#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 16524#L1159-3 assume !(0 == ~T11_E~0); 16525#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16795#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16796#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16846#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16847#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17002#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16679#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 16046#L1199-3 assume !(0 == ~E_7~0); 16047#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16270#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15732#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 15733#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16431#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16432#L544-39 assume !(1 == ~m_pc~0); 15713#L544-41 is_master_triggered_~__retres1~0#1 := 0; 15714#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15964#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15965#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 16121#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16989#L563-39 assume 1 == ~t1_pc~0; 16995#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15864#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16763#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16764#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17261#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17104#L582-39 assume 1 == ~t2_pc~0; 16187#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16189#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16809#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16810#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15957#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15744#L601-39 assume 1 == ~t3_pc~0; 15745#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15795#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16953#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17089#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16993#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16645#L620-39 assume !(1 == ~t4_pc~0); 16646#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 16843#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17051#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16966#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16967#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17272#L639-39 assume 1 == ~t5_pc~0; 17079#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16393#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15970#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15773#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15774#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16682#L658-39 assume 1 == ~t6_pc~0; 16664#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 16665#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15723#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15724#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16839#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16840#L677-39 assume 1 == ~t7_pc~0; 16802#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15948#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15949#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16004#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 16005#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16570#L696-39 assume 1 == ~t8_pc~0; 16535#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16415#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16416#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16711#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16675#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16550#L715-39 assume 1 == ~t9_pc~0; 15749#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15750#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16959#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17273#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 16888#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16889#L734-39 assume !(1 == ~t10_pc~0); 16259#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 16260#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16571#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 15902#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 15903#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17151#L753-39 assume !(1 == ~t11_pc~0); 15822#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 15823#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17115#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16540#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 16541#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16642#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16643#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16913#L1242-3 assume !(1 == ~T2_E~0); 16914#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17133#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16833#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16834#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17116#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17157#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17245#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 15974#L1282-3 assume !(1 == ~T10_E~0); 15975#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 15884#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 15885#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17022#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17023#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17211#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17269#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16935#L1322-3 assume !(1 == ~E_6~0); 16936#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15943#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 15918#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 15919#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 16611#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 16739#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 16740#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15866#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 16131#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 16845#L1697 assume !(0 == start_simulation_~tmp~3#1); 16632#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 16633#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15990#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 16755#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 16756#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16705#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16302#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 16303#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 17016#L1678-2 [2022-07-22 02:42:45,118 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:45,118 INFO L85 PathProgramCache]: Analyzing trace with hash -1076284804, now seen corresponding path program 1 times [2022-07-22 02:42:45,119 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:45,119 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [877405866] [2022-07-22 02:42:45,119 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:45,119 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:45,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:45,138 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:45,138 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:45,138 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [877405866] [2022-07-22 02:42:45,138 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [877405866] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:45,138 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:45,138 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:45,139 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1280874664] [2022-07-22 02:42:45,139 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:45,139 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:42:45,139 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:45,140 INFO L85 PathProgramCache]: Analyzing trace with hash 100626508, now seen corresponding path program 1 times [2022-07-22 02:42:45,140 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:45,140 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [445930430] [2022-07-22 02:42:45,140 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:45,140 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:45,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:45,166 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:45,166 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:45,167 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [445930430] [2022-07-22 02:42:45,167 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [445930430] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:45,167 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:45,167 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:45,167 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1827350458] [2022-07-22 02:42:45,167 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:45,168 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:42:45,168 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:42:45,168 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:42:45,168 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:42:45,169 INFO L87 Difference]: Start difference. First operand 1566 states and 2321 transitions. cyclomatic complexity: 756 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:45,187 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:42:45,187 INFO L93 Difference]: Finished difference Result 1566 states and 2320 transitions. [2022-07-22 02:42:45,187 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:42:45,188 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2320 transitions. [2022-07-22 02:42:45,214 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-07-22 02:42:45,220 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2320 transitions. [2022-07-22 02:42:45,220 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2022-07-22 02:42:45,221 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2022-07-22 02:42:45,221 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2320 transitions. [2022-07-22 02:42:45,223 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:42:45,223 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2320 transitions. [2022-07-22 02:42:45,224 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2320 transitions. [2022-07-22 02:42:45,235 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2022-07-22 02:42:45,237 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4814814814814814) internal successors, (2320), 1565 states have internal predecessors, (2320), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:45,240 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2320 transitions. [2022-07-22 02:42:45,240 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2320 transitions. [2022-07-22 02:42:45,240 INFO L374 stractBuchiCegarLoop]: Abstraction has 1566 states and 2320 transitions. [2022-07-22 02:42:45,240 INFO L287 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-07-22 02:42:45,240 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2320 transitions. [2022-07-22 02:42:45,244 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-07-22 02:42:45,244 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:42:45,245 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:42:45,246 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:45,246 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:45,246 INFO L752 eck$LassoCheckResult]: Stem: 19582#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 19583#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 20311#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20312#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19085#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 19086#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20321#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20286#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20287#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19434#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19435#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 19841#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 20259#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19346#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 19347#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 19232#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 19233#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20185#L1109 assume !(0 == ~M_E~0); 20207#L1109-2 assume !(0 == ~T1_E~0); 19239#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19240#L1119-1 assume !(0 == ~T3_E~0); 20263#L1124-1 assume !(0 == ~T4_E~0); 18900#L1129-1 assume !(0 == ~T5_E~0); 18901#L1134-1 assume !(0 == ~T6_E~0); 19514#L1139-1 assume !(0 == ~T7_E~0); 20191#L1144-1 assume !(0 == ~T8_E~0); 20063#L1149-1 assume !(0 == ~T9_E~0); 19007#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19008#L1159-1 assume !(0 == ~T11_E~0); 20049#L1164-1 assume !(0 == ~E_M~0); 19400#L1169-1 assume !(0 == ~E_1~0); 19289#L1174-1 assume !(0 == ~E_2~0); 19162#L1179-1 assume !(0 == ~E_3~0); 19089#L1184-1 assume !(0 == ~E_4~0); 19090#L1189-1 assume !(0 == ~E_5~0); 19121#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 19208#L1199-1 assume !(0 == ~E_7~0); 20071#L1204-1 assume !(0 == ~E_8~0); 20007#L1209-1 assume !(0 == ~E_9~0); 20008#L1214-1 assume !(0 == ~E_10~0); 20333#L1219-1 assume !(0 == ~E_11~0); 20406#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19417#L544 assume 1 == ~m_pc~0; 19418#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 20250#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20078#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19051#L1379 assume !(0 != activate_threads_~tmp~1#1); 19052#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19824#L563 assume !(1 == ~t1_pc~0); 19624#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 18910#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18911#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19947#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 18906#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18907#L582 assume 1 == ~t2_pc~0; 19602#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19957#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19958#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20062#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 18939#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18940#L601 assume !(1 == ~t3_pc~0); 19618#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 19617#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20251#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19993#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 19994#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19937#L620 assume 1 == ~t4_pc~0; 18920#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18921#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19482#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19483#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 19838#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20025#L639 assume 1 == ~t5_pc~0; 19908#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19212#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19213#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19859#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 19860#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19789#L658 assume !(1 == ~t6_pc~0); 19414#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19415#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19983#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20313#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19997#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19252#L677 assume 1 == ~t7_pc~0; 19253#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19155#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20156#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20280#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 20281#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20352#L696 assume !(1 == ~t8_pc~0); 19472#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19473#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20320#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20341#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 20387#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19891#L715 assume 1 == ~t9_pc~0; 19892#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19562#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19470#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19471#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 19880#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20152#L734 assume !(1 == ~t10_pc~0); 20153#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 19372#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19373#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19391#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 20096#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 19448#L753 assume 1 == ~t11_pc~0; 19449#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 20002#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 19557#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 19558#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 19707#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19764#L1237 assume !(1 == ~M_E~0); 19765#L1237-2 assume !(1 == ~T1_E~0); 20377#L1242-1 assume !(1 == ~T2_E~0); 19528#L1247-1 assume !(1 == ~T3_E~0); 19529#L1252-1 assume !(1 == ~T4_E~0); 19312#L1257-1 assume !(1 == ~T5_E~0); 19313#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20168#L1267-1 assume !(1 == ~T7_E~0); 20273#L1272-1 assume !(1 == ~T8_E~0); 19611#L1277-1 assume !(1 == ~T9_E~0); 19612#L1282-1 assume !(1 == ~T10_E~0); 20034#L1287-1 assume !(1 == ~T11_E~0); 20035#L1292-1 assume !(1 == ~E_M~0); 19996#L1297-1 assume !(1 == ~E_1~0); 19443#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 19444#L1307-1 assume !(1 == ~E_3~0); 20266#L1312-1 assume !(1 == ~E_4~0); 19654#L1317-1 assume !(1 == ~E_5~0); 19655#L1322-1 assume !(1 == ~E_6~0); 19387#L1327-1 assume !(1 == ~E_7~0); 19388#L1332-1 assume !(1 == ~E_8~0); 19946#L1337-1 assume !(1 == ~E_9~0); 19883#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 19884#L1347-1 assume !(1 == ~E_11~0); 20265#L1352-1 assume { :end_inline_reset_delta_events } true; 20155#L1678-2 [2022-07-22 02:42:45,247 INFO L754 eck$LassoCheckResult]: Loop: 20155#L1678-2 assume !false; 19938#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19939#L1084 assume !false; 19722#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 19723#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 19026#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 20040#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 18952#L925 assume !(0 != eval_~tmp~0#1); 18954#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19068#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19069#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 18923#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18924#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19998#L1119-3 assume !(0 == ~T3_E~0); 19999#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20020#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20021#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20199#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20257#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19427#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19428#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19663#L1159-3 assume !(0 == ~T11_E~0); 19664#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19934#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19935#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19985#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19986#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20141#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19818#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 19185#L1199-3 assume !(0 == ~E_7~0); 19186#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19409#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 18871#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 18872#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 19570#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19571#L544-39 assume !(1 == ~m_pc~0); 18852#L544-41 is_master_triggered_~__retres1~0#1 := 0; 18853#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19103#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19104#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 19260#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20128#L563-39 assume 1 == ~t1_pc~0; 20134#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19003#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19902#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19903#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20400#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20243#L582-39 assume 1 == ~t2_pc~0; 19326#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19328#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19948#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19949#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19096#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18883#L601-39 assume 1 == ~t3_pc~0; 18884#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18934#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20092#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20228#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20132#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19784#L620-39 assume !(1 == ~t4_pc~0); 19785#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 19982#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20190#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20105#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20106#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20411#L639-39 assume 1 == ~t5_pc~0; 20218#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19532#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19109#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18912#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18913#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19821#L658-39 assume 1 == ~t6_pc~0; 19803#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19804#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18862#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18863#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19978#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19979#L677-39 assume 1 == ~t7_pc~0; 19941#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19087#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19088#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19143#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 19144#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19709#L696-39 assume 1 == ~t8_pc~0; 19674#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19554#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19555#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19850#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19814#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19689#L715-39 assume 1 == ~t9_pc~0; 18888#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18889#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20098#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20412#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 20027#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20028#L734-39 assume 1 == ~t10_pc~0; 19953#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 19399#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19710#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19041#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 19042#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20290#L753-39 assume !(1 == ~t11_pc~0); 18961#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 18962#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20254#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 19679#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 19680#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19781#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19782#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20052#L1242-3 assume !(1 == ~T2_E~0); 20053#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20272#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19972#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19973#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20255#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 20296#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 20384#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19113#L1282-3 assume !(1 == ~T10_E~0); 19114#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 19023#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19024#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 20161#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20162#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20350#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20408#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20074#L1322-3 assume !(1 == ~E_6~0); 20075#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19082#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19057#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 19058#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 19750#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 19878#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 19879#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 19005#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 19270#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 19984#L1697 assume !(0 == start_simulation_~tmp~3#1); 19771#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 19772#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 19129#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 19894#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 19895#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19844#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19441#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 19442#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 20155#L1678-2 [2022-07-22 02:42:45,247 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:45,247 INFO L85 PathProgramCache]: Analyzing trace with hash -1751444930, now seen corresponding path program 1 times [2022-07-22 02:42:45,247 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:45,248 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1075061551] [2022-07-22 02:42:45,248 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:45,248 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:45,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:45,268 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:45,268 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:45,268 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1075061551] [2022-07-22 02:42:45,268 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1075061551] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:45,268 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:45,269 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:45,269 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1037598244] [2022-07-22 02:42:45,269 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:45,269 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:42:45,269 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:45,270 INFO L85 PathProgramCache]: Analyzing trace with hash -1367576821, now seen corresponding path program 1 times [2022-07-22 02:42:45,270 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:45,270 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1272008023] [2022-07-22 02:42:45,270 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:45,270 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:45,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:45,296 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:45,296 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:45,296 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1272008023] [2022-07-22 02:42:45,296 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1272008023] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:45,296 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:45,296 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:45,297 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1827924033] [2022-07-22 02:42:45,297 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:45,297 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:42:45,297 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:42:45,298 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:42:45,298 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:42:45,298 INFO L87 Difference]: Start difference. First operand 1566 states and 2320 transitions. cyclomatic complexity: 755 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:45,317 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:42:45,317 INFO L93 Difference]: Finished difference Result 1566 states and 2319 transitions. [2022-07-22 02:42:45,318 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:42:45,318 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2319 transitions. [2022-07-22 02:42:45,324 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-07-22 02:42:45,329 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2319 transitions. [2022-07-22 02:42:45,330 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2022-07-22 02:42:45,331 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2022-07-22 02:42:45,331 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2319 transitions. [2022-07-22 02:42:45,333 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:42:45,333 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2319 transitions. [2022-07-22 02:42:45,334 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2319 transitions. [2022-07-22 02:42:45,348 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2022-07-22 02:42:45,350 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4808429118773947) internal successors, (2319), 1565 states have internal predecessors, (2319), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:45,354 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2319 transitions. [2022-07-22 02:42:45,354 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2319 transitions. [2022-07-22 02:42:45,355 INFO L374 stractBuchiCegarLoop]: Abstraction has 1566 states and 2319 transitions. [2022-07-22 02:42:45,355 INFO L287 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-07-22 02:42:45,355 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2319 transitions. [2022-07-22 02:42:45,360 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-07-22 02:42:45,361 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:42:45,361 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:42:45,363 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:45,363 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:45,363 INFO L752 eck$LassoCheckResult]: Stem: 22721#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 22722#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 23450#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23451#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22224#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 22225#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23460#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23425#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23426#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22573#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22574#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 22980#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 23398#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 22485#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22486#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 22371#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 22372#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23326#L1109 assume !(0 == ~M_E~0); 23347#L1109-2 assume !(0 == ~T1_E~0); 22378#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22379#L1119-1 assume !(0 == ~T3_E~0); 23402#L1124-1 assume !(0 == ~T4_E~0); 22041#L1129-1 assume !(0 == ~T5_E~0); 22042#L1134-1 assume !(0 == ~T6_E~0); 22653#L1139-1 assume !(0 == ~T7_E~0); 23330#L1144-1 assume !(0 == ~T8_E~0); 23202#L1149-1 assume !(0 == ~T9_E~0); 22148#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 22149#L1159-1 assume !(0 == ~T11_E~0); 23188#L1164-1 assume !(0 == ~E_M~0); 22539#L1169-1 assume !(0 == ~E_1~0); 22428#L1174-1 assume !(0 == ~E_2~0); 22304#L1179-1 assume !(0 == ~E_3~0); 22228#L1184-1 assume !(0 == ~E_4~0); 22229#L1189-1 assume !(0 == ~E_5~0); 22260#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 22349#L1199-1 assume !(0 == ~E_7~0); 23210#L1204-1 assume !(0 == ~E_8~0); 23147#L1209-1 assume !(0 == ~E_9~0); 23148#L1214-1 assume !(0 == ~E_10~0); 23472#L1219-1 assume !(0 == ~E_11~0); 23545#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22558#L544 assume 1 == ~m_pc~0; 22559#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 23389#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23219#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22192#L1379 assume !(0 != activate_threads_~tmp~1#1); 22193#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22966#L563 assume !(1 == ~t1_pc~0); 22763#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22049#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22050#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23086#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 22045#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22046#L582 assume 1 == ~t2_pc~0; 22741#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 23097#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23098#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23201#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 22078#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22079#L601 assume !(1 == ~t3_pc~0); 22757#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 22756#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23390#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23132#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 23133#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23076#L620 assume 1 == ~t4_pc~0; 22059#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22060#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22621#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22622#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 22977#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23164#L639 assume 1 == ~t5_pc~0; 23047#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22351#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22352#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22998#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 22999#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22928#L658 assume !(1 == ~t6_pc~0); 22553#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 22554#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23122#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23452#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23136#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22391#L677 assume 1 == ~t7_pc~0; 22392#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22294#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23295#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23419#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 23420#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23491#L696 assume !(1 == ~t8_pc~0); 22611#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22612#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23459#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23480#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 23526#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 23030#L715 assume 1 == ~t9_pc~0; 23031#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22701#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22609#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22610#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 23019#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23291#L734 assume !(1 == ~t10_pc~0); 23292#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 22511#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22512#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22530#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 23235#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22587#L753 assume 1 == ~t11_pc~0; 22588#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 23141#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 22696#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 22697#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 22846#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22903#L1237 assume !(1 == ~M_E~0); 22904#L1237-2 assume !(1 == ~T1_E~0); 23516#L1242-1 assume !(1 == ~T2_E~0); 22667#L1247-1 assume !(1 == ~T3_E~0); 22668#L1252-1 assume !(1 == ~T4_E~0); 22451#L1257-1 assume !(1 == ~T5_E~0); 22452#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23307#L1267-1 assume !(1 == ~T7_E~0); 23412#L1272-1 assume !(1 == ~T8_E~0); 22750#L1277-1 assume !(1 == ~T9_E~0); 22751#L1282-1 assume !(1 == ~T10_E~0); 23173#L1287-1 assume !(1 == ~T11_E~0); 23174#L1292-1 assume !(1 == ~E_M~0); 23135#L1297-1 assume !(1 == ~E_1~0); 22582#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 22583#L1307-1 assume !(1 == ~E_3~0); 23405#L1312-1 assume !(1 == ~E_4~0); 22793#L1317-1 assume !(1 == ~E_5~0); 22794#L1322-1 assume !(1 == ~E_6~0); 22526#L1327-1 assume !(1 == ~E_7~0); 22527#L1332-1 assume !(1 == ~E_8~0); 23085#L1337-1 assume !(1 == ~E_9~0); 23022#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 23023#L1347-1 assume !(1 == ~E_11~0); 23404#L1352-1 assume { :end_inline_reset_delta_events } true; 23294#L1678-2 [2022-07-22 02:42:45,364 INFO L754 eck$LassoCheckResult]: Loop: 23294#L1678-2 assume !false; 23077#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 23078#L1084 assume !false; 22861#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 22862#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 22165#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 23179#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 22091#L925 assume !(0 != eval_~tmp~0#1); 22093#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22207#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22208#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22062#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22063#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23137#L1119-3 assume !(0 == ~T3_E~0); 23138#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 23159#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 23160#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 23338#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 23396#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 22566#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22567#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 22802#L1159-3 assume !(0 == ~T11_E~0); 22803#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 23073#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23074#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23124#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23125#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23280#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22957#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22324#L1199-3 assume !(0 == ~E_7~0); 22325#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 22548#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 22010#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 22011#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22709#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22710#L544-39 assume !(1 == ~m_pc~0); 21991#L544-41 is_master_triggered_~__retres1~0#1 := 0; 21992#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22242#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22243#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 22399#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23267#L563-39 assume 1 == ~t1_pc~0; 23273#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22142#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23041#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23042#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23539#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23382#L582-39 assume 1 == ~t2_pc~0; 22465#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22467#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23087#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23088#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22235#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22022#L601-39 assume 1 == ~t3_pc~0; 22023#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22073#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23231#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23367#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23271#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22923#L620-39 assume !(1 == ~t4_pc~0); 22924#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 23121#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23329#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23244#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23245#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23550#L639-39 assume 1 == ~t5_pc~0; 23357#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22671#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22248#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22051#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 22052#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22960#L658-39 assume !(1 == ~t6_pc~0); 22944#L658-41 is_transmit6_triggered_~__retres1~6#1 := 0; 22943#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22001#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22002#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23117#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23118#L677-39 assume 1 == ~t7_pc~0; 23080#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22226#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22227#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22282#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 22283#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22848#L696-39 assume 1 == ~t8_pc~0; 22813#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22693#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22694#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22989#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 22953#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22828#L715-39 assume 1 == ~t9_pc~0; 22027#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22028#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23237#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 23551#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 23166#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23167#L734-39 assume 1 == ~t10_pc~0; 23092#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 22538#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22849#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22180#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 22181#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 23429#L753-39 assume !(1 == ~t11_pc~0); 22100#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 22101#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 23393#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 22818#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 22819#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22920#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22921#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23191#L1242-3 assume !(1 == ~T2_E~0); 23192#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23411#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23111#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23112#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23394#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23435#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 23523#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22252#L1282-3 assume !(1 == ~T10_E~0); 22253#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 22162#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22163#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 23300#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23301#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23489#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23547#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 23213#L1322-3 assume !(1 == ~E_6~0); 23214#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22221#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 22196#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 22197#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 22889#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 23017#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 23018#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 22144#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 22409#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 23123#L1697 assume !(0 == start_simulation_~tmp~3#1); 22910#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 22911#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 22268#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 23033#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 23034#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22983#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22580#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 22581#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 23294#L1678-2 [2022-07-22 02:42:45,364 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:45,364 INFO L85 PathProgramCache]: Analyzing trace with hash -803392964, now seen corresponding path program 1 times [2022-07-22 02:42:45,365 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:45,365 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019175038] [2022-07-22 02:42:45,365 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:45,365 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:45,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:45,390 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:45,391 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:45,391 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019175038] [2022-07-22 02:42:45,391 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2019175038] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:45,391 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:45,391 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:45,392 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1329645975] [2022-07-22 02:42:45,392 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:45,392 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:42:45,393 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:45,393 INFO L85 PathProgramCache]: Analyzing trace with hash 764411212, now seen corresponding path program 2 times [2022-07-22 02:42:45,393 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:45,393 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [765261200] [2022-07-22 02:42:45,393 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:45,394 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:45,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:45,430 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:45,430 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:45,430 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [765261200] [2022-07-22 02:42:45,431 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [765261200] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:45,431 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:45,431 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:45,431 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [538093950] [2022-07-22 02:42:45,431 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:45,432 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:42:45,432 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:42:45,432 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:42:45,432 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:42:45,433 INFO L87 Difference]: Start difference. First operand 1566 states and 2319 transitions. cyclomatic complexity: 754 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:45,459 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:42:45,459 INFO L93 Difference]: Finished difference Result 1566 states and 2318 transitions. [2022-07-22 02:42:45,460 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:42:45,460 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2318 transitions. [2022-07-22 02:42:45,468 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-07-22 02:42:45,475 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2318 transitions. [2022-07-22 02:42:45,475 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2022-07-22 02:42:45,476 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2022-07-22 02:42:45,477 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2318 transitions. [2022-07-22 02:42:45,479 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:42:45,479 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2318 transitions. [2022-07-22 02:42:45,511 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2318 transitions. [2022-07-22 02:42:45,526 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2022-07-22 02:42:45,529 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4802043422733078) internal successors, (2318), 1565 states have internal predecessors, (2318), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:45,532 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2318 transitions. [2022-07-22 02:42:45,533 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2318 transitions. [2022-07-22 02:42:45,533 INFO L374 stractBuchiCegarLoop]: Abstraction has 1566 states and 2318 transitions. [2022-07-22 02:42:45,533 INFO L287 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-07-22 02:42:45,533 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2318 transitions. [2022-07-22 02:42:45,538 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-07-22 02:42:45,538 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:42:45,538 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:42:45,540 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:45,540 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:45,541 INFO L752 eck$LassoCheckResult]: Stem: 25860#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 25861#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 26589#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26590#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25363#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 25364#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26599#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26564#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26565#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25712#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25713#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26119#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26537#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 25624#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25625#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 25510#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 25511#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26463#L1109 assume !(0 == ~M_E~0); 26485#L1109-2 assume !(0 == ~T1_E~0); 25517#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25518#L1119-1 assume !(0 == ~T3_E~0); 26541#L1124-1 assume !(0 == ~T4_E~0); 25180#L1129-1 assume !(0 == ~T5_E~0); 25181#L1134-1 assume !(0 == ~T6_E~0); 25792#L1139-1 assume !(0 == ~T7_E~0); 26469#L1144-1 assume !(0 == ~T8_E~0); 26341#L1149-1 assume !(0 == ~T9_E~0); 25287#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25288#L1159-1 assume !(0 == ~T11_E~0); 26327#L1164-1 assume !(0 == ~E_M~0); 25678#L1169-1 assume !(0 == ~E_1~0); 25567#L1174-1 assume !(0 == ~E_2~0); 25440#L1179-1 assume !(0 == ~E_3~0); 25367#L1184-1 assume !(0 == ~E_4~0); 25368#L1189-1 assume !(0 == ~E_5~0); 25399#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 25486#L1199-1 assume !(0 == ~E_7~0); 26349#L1204-1 assume !(0 == ~E_8~0); 26285#L1209-1 assume !(0 == ~E_9~0); 26286#L1214-1 assume !(0 == ~E_10~0); 26611#L1219-1 assume !(0 == ~E_11~0); 26684#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25695#L544 assume 1 == ~m_pc~0; 25696#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 26528#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26356#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25329#L1379 assume !(0 != activate_threads_~tmp~1#1); 25330#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26102#L563 assume !(1 == ~t1_pc~0); 25902#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25188#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25189#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26225#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 25184#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25185#L582 assume 1 == ~t2_pc~0; 25880#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 26235#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26236#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26340#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 25217#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25218#L601 assume !(1 == ~t3_pc~0); 25896#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 25895#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26529#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26271#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 26272#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26215#L620 assume 1 == ~t4_pc~0; 25198#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25199#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25760#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25761#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 26116#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26304#L639 assume 1 == ~t5_pc~0; 26187#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25490#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25491#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26137#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 26138#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26067#L658 assume !(1 == ~t6_pc~0); 25692#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 25693#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26262#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26591#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26275#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25530#L677 assume 1 == ~t7_pc~0; 25531#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25433#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26434#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26558#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 26559#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26630#L696 assume !(1 == ~t8_pc~0); 25751#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 25752#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26598#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26619#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 26665#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26169#L715 assume 1 == ~t9_pc~0; 26170#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25840#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25748#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25749#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 26158#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 26431#L734 assume !(1 == ~t10_pc~0); 26432#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25650#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25651#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25669#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 26374#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 25726#L753 assume 1 == ~t11_pc~0; 25727#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 26280#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25835#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25836#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 25987#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26042#L1237 assume !(1 == ~M_E~0); 26043#L1237-2 assume !(1 == ~T1_E~0); 26656#L1242-1 assume !(1 == ~T2_E~0); 25806#L1247-1 assume !(1 == ~T3_E~0); 25807#L1252-1 assume !(1 == ~T4_E~0); 25590#L1257-1 assume !(1 == ~T5_E~0); 25591#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26446#L1267-1 assume !(1 == ~T7_E~0); 26551#L1272-1 assume !(1 == ~T8_E~0); 25889#L1277-1 assume !(1 == ~T9_E~0); 25890#L1282-1 assume !(1 == ~T10_E~0); 26312#L1287-1 assume !(1 == ~T11_E~0); 26313#L1292-1 assume !(1 == ~E_M~0); 26274#L1297-1 assume !(1 == ~E_1~0); 25721#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 25722#L1307-1 assume !(1 == ~E_3~0); 26544#L1312-1 assume !(1 == ~E_4~0); 25932#L1317-1 assume !(1 == ~E_5~0); 25933#L1322-1 assume !(1 == ~E_6~0); 25665#L1327-1 assume !(1 == ~E_7~0); 25666#L1332-1 assume !(1 == ~E_8~0); 26224#L1337-1 assume !(1 == ~E_9~0); 26161#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 26162#L1347-1 assume !(1 == ~E_11~0); 26543#L1352-1 assume { :end_inline_reset_delta_events } true; 26430#L1678-2 [2022-07-22 02:42:45,541 INFO L754 eck$LassoCheckResult]: Loop: 26430#L1678-2 assume !false; 26216#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 26217#L1084 assume !false; 26001#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 26002#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 25304#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 26319#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 25230#L925 assume !(0 != eval_~tmp~0#1); 25232#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25346#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25347#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25201#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25202#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26276#L1119-3 assume !(0 == ~T3_E~0); 26277#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26298#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 26299#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 26477#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 26535#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25705#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25706#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25942#L1159-3 assume !(0 == ~T11_E~0); 25943#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 26212#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26213#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 26263#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26264#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26419#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26096#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25466#L1199-3 assume !(0 == ~E_7~0); 25467#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 25691#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 25152#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 25153#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 25848#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25849#L544-39 assume !(1 == ~m_pc~0); 25130#L544-41 is_master_triggered_~__retres1~0#1 := 0; 25131#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25381#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25382#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 25538#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26406#L563-39 assume !(1 == ~t1_pc~0); 25283#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 25284#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26180#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26181#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26678#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26521#L582-39 assume 1 == ~t2_pc~0; 25604#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25606#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26226#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26227#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25376#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25161#L601-39 assume 1 == ~t3_pc~0; 25162#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25212#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26370#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26506#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26410#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26064#L620-39 assume !(1 == ~t4_pc~0); 26065#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 26260#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26468#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26383#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26384#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26689#L639-39 assume 1 == ~t5_pc~0; 26496#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25810#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25387#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25190#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25191#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26099#L658-39 assume 1 == ~t6_pc~0; 26081#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26082#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25138#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25139#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26256#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26257#L677-39 assume 1 == ~t7_pc~0; 26219#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25365#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25366#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25421#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 25422#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25986#L696-39 assume 1 == ~t8_pc~0; 25952#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 25832#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25833#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26128#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 26092#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25967#L715-39 assume 1 == ~t9_pc~0; 25164#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25165#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26376#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26690#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 26305#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 26306#L734-39 assume 1 == ~t10_pc~0; 26231#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 25677#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25988#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25319#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 25320#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26568#L753-39 assume !(1 == ~t11_pc~0); 25239#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 25240#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 26532#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25957#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 25958#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26055#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 26056#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26330#L1242-3 assume !(1 == ~T2_E~0); 26331#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26550#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26250#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 26251#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26533#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26574#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 26662#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25390#L1282-3 assume !(1 == ~T10_E~0); 25391#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25301#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25302#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 26438#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26439#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26628#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 26686#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 26352#L1322-3 assume !(1 == ~E_6~0); 26353#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25360#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25335#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 25336#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 26028#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 26156#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 26157#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 25278#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 25548#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 26261#L1697 assume !(0 == start_simulation_~tmp~3#1); 26049#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 26050#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 25407#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 26172#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 26173#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26122#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25717#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 25718#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 26430#L1678-2 [2022-07-22 02:42:45,542 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:45,542 INFO L85 PathProgramCache]: Analyzing trace with hash -218621314, now seen corresponding path program 1 times [2022-07-22 02:42:45,542 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:45,542 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1804853538] [2022-07-22 02:42:45,543 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:45,543 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:45,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:45,569 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:45,569 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:45,569 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1804853538] [2022-07-22 02:42:45,569 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1804853538] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:45,570 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:45,570 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:45,570 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1203119824] [2022-07-22 02:42:45,570 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:45,570 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:42:45,571 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:45,571 INFO L85 PathProgramCache]: Analyzing trace with hash 947803532, now seen corresponding path program 1 times [2022-07-22 02:42:45,571 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:45,571 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [95565528] [2022-07-22 02:42:45,572 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:45,572 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:45,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:45,606 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:45,607 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:45,607 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [95565528] [2022-07-22 02:42:45,607 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [95565528] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:45,607 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:45,607 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:45,608 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1240913018] [2022-07-22 02:42:45,608 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:45,608 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:42:45,608 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:42:45,609 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:42:45,609 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:42:45,609 INFO L87 Difference]: Start difference. First operand 1566 states and 2318 transitions. cyclomatic complexity: 753 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:45,635 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:42:45,636 INFO L93 Difference]: Finished difference Result 1566 states and 2317 transitions. [2022-07-22 02:42:45,636 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:42:45,637 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2317 transitions. [2022-07-22 02:42:45,644 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-07-22 02:42:45,652 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2317 transitions. [2022-07-22 02:42:45,652 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2022-07-22 02:42:45,653 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2022-07-22 02:42:45,653 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2317 transitions. [2022-07-22 02:42:45,655 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:42:45,655 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2317 transitions. [2022-07-22 02:42:45,657 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2317 transitions. [2022-07-22 02:42:45,674 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2022-07-22 02:42:45,677 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4795657726692208) internal successors, (2317), 1565 states have internal predecessors, (2317), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:45,681 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2317 transitions. [2022-07-22 02:42:45,681 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2317 transitions. [2022-07-22 02:42:45,681 INFO L374 stractBuchiCegarLoop]: Abstraction has 1566 states and 2317 transitions. [2022-07-22 02:42:45,681 INFO L287 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-07-22 02:42:45,681 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2317 transitions. [2022-07-22 02:42:45,687 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-07-22 02:42:45,687 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:42:45,687 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:42:45,689 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:45,689 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:45,689 INFO L752 eck$LassoCheckResult]: Stem: 28999#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 29000#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 29728#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29729#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28502#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 28503#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29738#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29703#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29704#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28851#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 28852#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29258#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29676#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 28763#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 28764#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 28649#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 28650#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29602#L1109 assume !(0 == ~M_E~0); 29624#L1109-2 assume !(0 == ~T1_E~0); 28656#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28657#L1119-1 assume !(0 == ~T3_E~0); 29680#L1124-1 assume !(0 == ~T4_E~0); 28317#L1129-1 assume !(0 == ~T5_E~0); 28318#L1134-1 assume !(0 == ~T6_E~0); 28931#L1139-1 assume !(0 == ~T7_E~0); 29608#L1144-1 assume !(0 == ~T8_E~0); 29480#L1149-1 assume !(0 == ~T9_E~0); 28424#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 28425#L1159-1 assume !(0 == ~T11_E~0); 29466#L1164-1 assume !(0 == ~E_M~0); 28817#L1169-1 assume !(0 == ~E_1~0); 28706#L1174-1 assume !(0 == ~E_2~0); 28579#L1179-1 assume !(0 == ~E_3~0); 28506#L1184-1 assume !(0 == ~E_4~0); 28507#L1189-1 assume !(0 == ~E_5~0); 28538#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 28625#L1199-1 assume !(0 == ~E_7~0); 29488#L1204-1 assume !(0 == ~E_8~0); 29424#L1209-1 assume !(0 == ~E_9~0); 29425#L1214-1 assume !(0 == ~E_10~0); 29750#L1219-1 assume !(0 == ~E_11~0); 29823#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28834#L544 assume 1 == ~m_pc~0; 28835#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29667#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29495#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28468#L1379 assume !(0 != activate_threads_~tmp~1#1); 28469#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29241#L563 assume !(1 == ~t1_pc~0); 29041#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 28327#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28328#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29364#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 28323#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28324#L582 assume 1 == ~t2_pc~0; 29019#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29374#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29375#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29479#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 28356#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28357#L601 assume !(1 == ~t3_pc~0); 29035#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29034#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29668#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29410#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 29411#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29354#L620 assume 1 == ~t4_pc~0; 28337#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 28338#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28899#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28900#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 29255#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29442#L639 assume 1 == ~t5_pc~0; 29325#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28629#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28630#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29276#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 29277#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29206#L658 assume !(1 == ~t6_pc~0); 28831#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 28832#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29400#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29730#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29414#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28669#L677 assume 1 == ~t7_pc~0; 28670#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28572#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29573#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29697#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 29698#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29769#L696 assume !(1 == ~t8_pc~0); 28889#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 28890#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29737#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29758#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 29804#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29308#L715 assume 1 == ~t9_pc~0; 29309#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28979#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28887#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28888#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 29297#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29569#L734 assume !(1 == ~t10_pc~0); 29570#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 28789#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28790#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28808#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 29513#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28865#L753 assume 1 == ~t11_pc~0; 28866#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29419#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28974#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 28975#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 29124#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29181#L1237 assume !(1 == ~M_E~0); 29182#L1237-2 assume !(1 == ~T1_E~0); 29794#L1242-1 assume !(1 == ~T2_E~0); 28945#L1247-1 assume !(1 == ~T3_E~0); 28946#L1252-1 assume !(1 == ~T4_E~0); 28729#L1257-1 assume !(1 == ~T5_E~0); 28730#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 29585#L1267-1 assume !(1 == ~T7_E~0); 29690#L1272-1 assume !(1 == ~T8_E~0); 29028#L1277-1 assume !(1 == ~T9_E~0); 29029#L1282-1 assume !(1 == ~T10_E~0); 29451#L1287-1 assume !(1 == ~T11_E~0); 29452#L1292-1 assume !(1 == ~E_M~0); 29413#L1297-1 assume !(1 == ~E_1~0); 28860#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 28861#L1307-1 assume !(1 == ~E_3~0); 29683#L1312-1 assume !(1 == ~E_4~0); 29071#L1317-1 assume !(1 == ~E_5~0); 29072#L1322-1 assume !(1 == ~E_6~0); 28804#L1327-1 assume !(1 == ~E_7~0); 28805#L1332-1 assume !(1 == ~E_8~0); 29363#L1337-1 assume !(1 == ~E_9~0); 29300#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 29301#L1347-1 assume !(1 == ~E_11~0); 29682#L1352-1 assume { :end_inline_reset_delta_events } true; 29572#L1678-2 [2022-07-22 02:42:45,690 INFO L754 eck$LassoCheckResult]: Loop: 29572#L1678-2 assume !false; 29355#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29356#L1084 assume !false; 29139#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 29140#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 28443#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 29457#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 28369#L925 assume !(0 != eval_~tmp~0#1); 28371#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28485#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28486#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28340#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28341#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29415#L1119-3 assume !(0 == ~T3_E~0); 29416#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29437#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29438#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 29616#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29674#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28844#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28845#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 29080#L1159-3 assume !(0 == ~T11_E~0); 29081#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29351#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29352#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29402#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29403#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 29558#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 29235#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28602#L1199-3 assume !(0 == ~E_7~0); 28603#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 28826#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 28288#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 28289#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28987#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28988#L544-39 assume !(1 == ~m_pc~0); 28269#L544-41 is_master_triggered_~__retres1~0#1 := 0; 28270#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28520#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28521#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 28677#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29545#L563-39 assume !(1 == ~t1_pc~0); 28419#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 28420#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29319#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29320#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29817#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29660#L582-39 assume 1 == ~t2_pc~0; 28743#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28745#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29365#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29366#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28513#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28300#L601-39 assume 1 == ~t3_pc~0; 28301#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 28351#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29509#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29645#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29549#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29201#L620-39 assume !(1 == ~t4_pc~0); 29202#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 29399#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29607#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29522#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29523#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29828#L639-39 assume 1 == ~t5_pc~0; 29635#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28949#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28526#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28329#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 28330#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29238#L658-39 assume 1 == ~t6_pc~0; 29220#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29221#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28279#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28280#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29395#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29396#L677-39 assume !(1 == ~t7_pc~0); 29026#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 28504#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28505#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28560#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 28561#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29126#L696-39 assume 1 == ~t8_pc~0; 29091#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 28971#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28972#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29267#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29231#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29106#L715-39 assume 1 == ~t9_pc~0; 28305#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28306#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29515#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29829#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 29444#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29445#L734-39 assume 1 == ~t10_pc~0; 29370#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 28816#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29127#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28458#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28459#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29707#L753-39 assume !(1 == ~t11_pc~0); 28378#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 28379#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29671#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29096#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 29097#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29198#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 29199#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29469#L1242-3 assume !(1 == ~T2_E~0); 29470#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29689#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29389#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 29390#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 29672#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 29713#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 29801#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28530#L1282-3 assume !(1 == ~T10_E~0); 28531#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 28440#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 28441#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 29578#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 29579#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 29767#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29825#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29491#L1322-3 assume !(1 == ~E_6~0); 29492#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28499#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28474#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 28475#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 29167#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 29295#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 29296#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 28422#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 28687#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 29401#L1697 assume !(0 == start_simulation_~tmp~3#1); 29188#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 29189#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 28546#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 29311#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 29312#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 29261#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28858#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 28859#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 29572#L1678-2 [2022-07-22 02:42:45,691 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:45,691 INFO L85 PathProgramCache]: Analyzing trace with hash 215884284, now seen corresponding path program 1 times [2022-07-22 02:42:45,691 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:45,691 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [309363188] [2022-07-22 02:42:45,692 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:45,692 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:45,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:45,718 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:45,718 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:45,718 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [309363188] [2022-07-22 02:42:45,719 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [309363188] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:45,719 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:45,719 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:45,719 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1826261002] [2022-07-22 02:42:45,719 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:45,720 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:42:45,720 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:45,720 INFO L85 PathProgramCache]: Analyzing trace with hash -1209669491, now seen corresponding path program 1 times [2022-07-22 02:42:45,721 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:45,721 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [324935817] [2022-07-22 02:42:45,721 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:45,721 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:45,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:45,758 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:45,759 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:45,759 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [324935817] [2022-07-22 02:42:45,759 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [324935817] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:45,759 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:45,760 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:45,760 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [437278293] [2022-07-22 02:42:45,760 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:45,760 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:42:45,760 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:42:45,761 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:42:45,761 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:42:45,761 INFO L87 Difference]: Start difference. First operand 1566 states and 2317 transitions. cyclomatic complexity: 752 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:45,791 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:42:45,792 INFO L93 Difference]: Finished difference Result 1566 states and 2316 transitions. [2022-07-22 02:42:45,792 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:42:45,793 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2316 transitions. [2022-07-22 02:42:45,800 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-07-22 02:42:45,807 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2316 transitions. [2022-07-22 02:42:45,807 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2022-07-22 02:42:45,809 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2022-07-22 02:42:45,809 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2316 transitions. [2022-07-22 02:42:45,811 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:42:45,811 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2316 transitions. [2022-07-22 02:42:45,845 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2316 transitions. [2022-07-22 02:42:45,862 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2022-07-22 02:42:45,865 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4789272030651341) internal successors, (2316), 1565 states have internal predecessors, (2316), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:45,868 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2316 transitions. [2022-07-22 02:42:45,869 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2316 transitions. [2022-07-22 02:42:45,869 INFO L374 stractBuchiCegarLoop]: Abstraction has 1566 states and 2316 transitions. [2022-07-22 02:42:45,869 INFO L287 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-07-22 02:42:45,869 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2316 transitions. [2022-07-22 02:42:45,875 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-07-22 02:42:45,875 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:42:45,875 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:42:45,877 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:45,877 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:45,878 INFO L752 eck$LassoCheckResult]: Stem: 32138#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 32139#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 32867#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 32868#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31641#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 31642#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32877#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32842#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32843#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31990#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 31991#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 32397#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 32815#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 31902#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 31903#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 31788#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 31789#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32741#L1109 assume !(0 == ~M_E~0); 32763#L1109-2 assume !(0 == ~T1_E~0); 31795#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31796#L1119-1 assume !(0 == ~T3_E~0); 32819#L1124-1 assume !(0 == ~T4_E~0); 31456#L1129-1 assume !(0 == ~T5_E~0); 31457#L1134-1 assume !(0 == ~T6_E~0); 32070#L1139-1 assume !(0 == ~T7_E~0); 32747#L1144-1 assume !(0 == ~T8_E~0); 32619#L1149-1 assume !(0 == ~T9_E~0); 31563#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 31564#L1159-1 assume !(0 == ~T11_E~0); 32605#L1164-1 assume !(0 == ~E_M~0); 31956#L1169-1 assume !(0 == ~E_1~0); 31845#L1174-1 assume !(0 == ~E_2~0); 31718#L1179-1 assume !(0 == ~E_3~0); 31645#L1184-1 assume !(0 == ~E_4~0); 31646#L1189-1 assume !(0 == ~E_5~0); 31677#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 31764#L1199-1 assume !(0 == ~E_7~0); 32627#L1204-1 assume !(0 == ~E_8~0); 32563#L1209-1 assume !(0 == ~E_9~0); 32564#L1214-1 assume !(0 == ~E_10~0); 32889#L1219-1 assume !(0 == ~E_11~0); 32962#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31973#L544 assume 1 == ~m_pc~0; 31974#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 32806#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32634#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31607#L1379 assume !(0 != activate_threads_~tmp~1#1); 31608#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32380#L563 assume !(1 == ~t1_pc~0); 32180#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 31466#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31467#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 32503#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 31462#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31463#L582 assume 1 == ~t2_pc~0; 32158#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32513#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32514#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32618#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 31495#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31496#L601 assume !(1 == ~t3_pc~0); 32174#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 32173#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32807#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32549#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 32550#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32493#L620 assume 1 == ~t4_pc~0; 31476#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 31477#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32038#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32039#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 32394#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32581#L639 assume 1 == ~t5_pc~0; 32464#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31768#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31769#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32415#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 32416#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32345#L658 assume !(1 == ~t6_pc~0); 31970#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 31971#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32539#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32869#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 32553#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 31808#L677 assume 1 == ~t7_pc~0; 31809#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 31711#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32712#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32836#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 32837#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32908#L696 assume !(1 == ~t8_pc~0); 32028#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 32029#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32876#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32897#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 32943#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32447#L715 assume 1 == ~t9_pc~0; 32448#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32118#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32026#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32027#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 32436#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32708#L734 assume !(1 == ~t10_pc~0); 32709#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 31928#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 31929#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 31947#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 32652#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32004#L753 assume 1 == ~t11_pc~0; 32005#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32558#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32113#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32114#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 32263#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32320#L1237 assume !(1 == ~M_E~0); 32321#L1237-2 assume !(1 == ~T1_E~0); 32933#L1242-1 assume !(1 == ~T2_E~0); 32084#L1247-1 assume !(1 == ~T3_E~0); 32085#L1252-1 assume !(1 == ~T4_E~0); 31868#L1257-1 assume !(1 == ~T5_E~0); 31869#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 32724#L1267-1 assume !(1 == ~T7_E~0); 32829#L1272-1 assume !(1 == ~T8_E~0); 32167#L1277-1 assume !(1 == ~T9_E~0); 32168#L1282-1 assume !(1 == ~T10_E~0); 32590#L1287-1 assume !(1 == ~T11_E~0); 32591#L1292-1 assume !(1 == ~E_M~0); 32552#L1297-1 assume !(1 == ~E_1~0); 31999#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 32000#L1307-1 assume !(1 == ~E_3~0); 32822#L1312-1 assume !(1 == ~E_4~0); 32210#L1317-1 assume !(1 == ~E_5~0); 32211#L1322-1 assume !(1 == ~E_6~0); 31943#L1327-1 assume !(1 == ~E_7~0); 31944#L1332-1 assume !(1 == ~E_8~0); 32502#L1337-1 assume !(1 == ~E_9~0); 32439#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 32440#L1347-1 assume !(1 == ~E_11~0); 32821#L1352-1 assume { :end_inline_reset_delta_events } true; 32711#L1678-2 [2022-07-22 02:42:45,878 INFO L754 eck$LassoCheckResult]: Loop: 32711#L1678-2 assume !false; 32494#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32495#L1084 assume !false; 32278#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 32279#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 31582#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 32596#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 31508#L925 assume !(0 != eval_~tmp~0#1); 31510#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 31624#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 31625#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 31479#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 31480#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 32554#L1119-3 assume !(0 == ~T3_E~0); 32555#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32576#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 32577#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32755#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 32813#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 31983#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 31984#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 32219#L1159-3 assume !(0 == ~T11_E~0); 32220#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 32490#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32491#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 32541#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32542#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 32697#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32374#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 31741#L1199-3 assume !(0 == ~E_7~0); 31742#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 31965#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 31427#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 31428#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32126#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32127#L544-39 assume !(1 == ~m_pc~0); 31408#L544-41 is_master_triggered_~__retres1~0#1 := 0; 31409#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31659#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31660#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 31816#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32684#L563-39 assume 1 == ~t1_pc~0; 32690#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 31559#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32458#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 32459#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32956#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32799#L582-39 assume 1 == ~t2_pc~0; 31882#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 31884#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32504#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32505#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 31652#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31439#L601-39 assume 1 == ~t3_pc~0; 31440#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 31490#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32648#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32784#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 32688#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32340#L620-39 assume !(1 == ~t4_pc~0); 32341#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 32538#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32746#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32661#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32662#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32967#L639-39 assume 1 == ~t5_pc~0; 32774#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 32088#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31665#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 31468#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 31469#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32377#L658-39 assume 1 == ~t6_pc~0; 32359#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 32360#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31418#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 31419#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 32534#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32535#L677-39 assume 1 == ~t7_pc~0; 32497#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 31643#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31644#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 31699#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 31700#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32265#L696-39 assume 1 == ~t8_pc~0; 32230#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 32110#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32111#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32406#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32370#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32245#L715-39 assume 1 == ~t9_pc~0; 31444#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31445#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32654#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32968#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 32583#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32584#L734-39 assume !(1 == ~t10_pc~0); 31954#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 31955#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32266#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 31597#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 31598#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32846#L753-39 assume !(1 == ~t11_pc~0); 31517#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 31518#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32810#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32235#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 32236#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32337#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 32338#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32608#L1242-3 assume !(1 == ~T2_E~0); 32609#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32828#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 32528#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 32529#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 32811#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 32852#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 32940#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 31669#L1282-3 assume !(1 == ~T10_E~0); 31670#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 31579#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 31580#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32717#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 32718#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 32906#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 32964#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32630#L1322-3 assume !(1 == ~E_6~0); 32631#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 31638#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 31613#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 31614#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 32306#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 32434#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 32435#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 31561#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 31826#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 32540#L1697 assume !(0 == start_simulation_~tmp~3#1); 32327#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 32328#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 31685#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 32450#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 32451#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 32400#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 31997#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 31998#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 32711#L1678-2 [2022-07-22 02:42:45,879 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:45,879 INFO L85 PathProgramCache]: Analyzing trace with hash 922480890, now seen corresponding path program 1 times [2022-07-22 02:42:45,879 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:45,879 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [150011590] [2022-07-22 02:42:45,880 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:45,880 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:45,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:45,907 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:45,908 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:45,908 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [150011590] [2022-07-22 02:42:45,908 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [150011590] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:45,908 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:45,909 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:45,909 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1082161226] [2022-07-22 02:42:45,909 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:45,909 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:42:45,910 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:45,910 INFO L85 PathProgramCache]: Analyzing trace with hash 100626508, now seen corresponding path program 2 times [2022-07-22 02:42:45,910 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:45,910 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [611974052] [2022-07-22 02:42:45,910 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:45,911 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:45,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:45,947 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:45,947 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:45,948 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [611974052] [2022-07-22 02:42:45,948 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [611974052] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:45,948 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:45,948 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:45,948 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1028032659] [2022-07-22 02:42:45,948 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:45,949 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:42:45,949 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:42:45,949 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:42:45,950 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:42:45,950 INFO L87 Difference]: Start difference. First operand 1566 states and 2316 transitions. cyclomatic complexity: 751 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:45,977 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:42:45,978 INFO L93 Difference]: Finished difference Result 1566 states and 2315 transitions. [2022-07-22 02:42:45,978 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:42:45,979 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2315 transitions. [2022-07-22 02:42:45,987 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-07-22 02:42:45,996 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2315 transitions. [2022-07-22 02:42:45,996 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2022-07-22 02:42:45,998 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2022-07-22 02:42:45,998 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2315 transitions. [2022-07-22 02:42:46,000 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:42:46,001 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2315 transitions. [2022-07-22 02:42:46,003 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2315 transitions. [2022-07-22 02:42:46,022 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2022-07-22 02:42:46,025 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4782886334610472) internal successors, (2315), 1565 states have internal predecessors, (2315), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:46,029 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2315 transitions. [2022-07-22 02:42:46,029 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1566 states and 2315 transitions. [2022-07-22 02:42:46,029 INFO L374 stractBuchiCegarLoop]: Abstraction has 1566 states and 2315 transitions. [2022-07-22 02:42:46,029 INFO L287 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-07-22 02:42:46,030 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2315 transitions. [2022-07-22 02:42:46,036 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2022-07-22 02:42:46,036 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:42:46,036 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:42:46,038 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:46,038 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:46,039 INFO L752 eck$LassoCheckResult]: Stem: 35277#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 35278#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 36006#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 36007#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34780#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 34781#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36016#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35981#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35982#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35129#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 35130#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 35536#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35954#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 35041#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 35042#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 34927#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 34928#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 35880#L1109 assume !(0 == ~M_E~0); 35902#L1109-2 assume !(0 == ~T1_E~0); 34934#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34935#L1119-1 assume !(0 == ~T3_E~0); 35958#L1124-1 assume !(0 == ~T4_E~0); 34595#L1129-1 assume !(0 == ~T5_E~0); 34596#L1134-1 assume !(0 == ~T6_E~0); 35209#L1139-1 assume !(0 == ~T7_E~0); 35886#L1144-1 assume !(0 == ~T8_E~0); 35758#L1149-1 assume !(0 == ~T9_E~0); 34702#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 34703#L1159-1 assume !(0 == ~T11_E~0); 35744#L1164-1 assume !(0 == ~E_M~0); 35095#L1169-1 assume !(0 == ~E_1~0); 34984#L1174-1 assume !(0 == ~E_2~0); 34857#L1179-1 assume !(0 == ~E_3~0); 34784#L1184-1 assume !(0 == ~E_4~0); 34785#L1189-1 assume !(0 == ~E_5~0); 34816#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 34903#L1199-1 assume !(0 == ~E_7~0); 35766#L1204-1 assume !(0 == ~E_8~0); 35702#L1209-1 assume !(0 == ~E_9~0); 35703#L1214-1 assume !(0 == ~E_10~0); 36028#L1219-1 assume !(0 == ~E_11~0); 36101#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35112#L544 assume 1 == ~m_pc~0; 35113#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 35945#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35773#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 34746#L1379 assume !(0 != activate_threads_~tmp~1#1); 34747#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35519#L563 assume !(1 == ~t1_pc~0); 35319#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 34605#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34606#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35642#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 34601#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34602#L582 assume 1 == ~t2_pc~0; 35297#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35652#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35653#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35757#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 34634#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34635#L601 assume !(1 == ~t3_pc~0); 35313#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 35312#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35946#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35688#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 35689#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35632#L620 assume 1 == ~t4_pc~0; 34615#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 34616#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35177#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35178#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 35533#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35720#L639 assume 1 == ~t5_pc~0; 35603#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 34907#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34908#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35554#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 35555#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35484#L658 assume !(1 == ~t6_pc~0); 35109#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 35110#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35678#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36008#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35692#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 34947#L677 assume 1 == ~t7_pc~0; 34948#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34850#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35851#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35975#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 35976#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36047#L696 assume !(1 == ~t8_pc~0); 35167#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 35168#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36015#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36036#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 36082#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35586#L715 assume 1 == ~t9_pc~0; 35587#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 35257#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35165#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35166#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 35575#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35847#L734 assume !(1 == ~t10_pc~0); 35848#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 35067#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35068#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35086#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 35791#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35143#L753 assume 1 == ~t11_pc~0; 35144#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 35697#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35252#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35253#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 35402#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35459#L1237 assume !(1 == ~M_E~0); 35460#L1237-2 assume !(1 == ~T1_E~0); 36072#L1242-1 assume !(1 == ~T2_E~0); 35223#L1247-1 assume !(1 == ~T3_E~0); 35224#L1252-1 assume !(1 == ~T4_E~0); 35007#L1257-1 assume !(1 == ~T5_E~0); 35008#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 35863#L1267-1 assume !(1 == ~T7_E~0); 35968#L1272-1 assume !(1 == ~T8_E~0); 35306#L1277-1 assume !(1 == ~T9_E~0); 35307#L1282-1 assume !(1 == ~T10_E~0); 35729#L1287-1 assume !(1 == ~T11_E~0); 35730#L1292-1 assume !(1 == ~E_M~0); 35691#L1297-1 assume !(1 == ~E_1~0); 35138#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 35139#L1307-1 assume !(1 == ~E_3~0); 35961#L1312-1 assume !(1 == ~E_4~0); 35349#L1317-1 assume !(1 == ~E_5~0); 35350#L1322-1 assume !(1 == ~E_6~0); 35082#L1327-1 assume !(1 == ~E_7~0); 35083#L1332-1 assume !(1 == ~E_8~0); 35641#L1337-1 assume !(1 == ~E_9~0); 35578#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 35579#L1347-1 assume !(1 == ~E_11~0); 35960#L1352-1 assume { :end_inline_reset_delta_events } true; 35850#L1678-2 [2022-07-22 02:42:46,039 INFO L754 eck$LassoCheckResult]: Loop: 35850#L1678-2 assume !false; 35633#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 35634#L1084 assume !false; 35417#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 35418#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 34721#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 35735#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 34647#L925 assume !(0 != eval_~tmp~0#1); 34649#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 34763#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 34764#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 34618#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 34619#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35693#L1119-3 assume !(0 == ~T3_E~0); 35694#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 35715#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 35716#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 35894#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 35952#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 35122#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 35123#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 35358#L1159-3 assume !(0 == ~T11_E~0); 35359#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 35629#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 35630#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 35680#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 35681#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 35836#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 35513#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 34880#L1199-3 assume !(0 == ~E_7~0); 34881#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 35104#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 34566#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 34567#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 35265#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35266#L544-39 assume !(1 == ~m_pc~0); 34547#L544-41 is_master_triggered_~__retres1~0#1 := 0; 34548#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34798#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 34799#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 34955#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35823#L563-39 assume 1 == ~t1_pc~0; 35829#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 34698#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35597#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35598#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36095#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35938#L582-39 assume 1 == ~t2_pc~0; 35021#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35023#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35643#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35644#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34791#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34578#L601-39 assume 1 == ~t3_pc~0; 34579#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34629#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35787#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35923#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 35827#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35479#L620-39 assume !(1 == ~t4_pc~0); 35480#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 35677#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35885#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35800#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 35801#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36106#L639-39 assume 1 == ~t5_pc~0; 35913#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35227#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34804#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34607#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 34608#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35516#L658-39 assume 1 == ~t6_pc~0; 35498#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 35499#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34557#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34558#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35673#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35674#L677-39 assume 1 == ~t7_pc~0; 35636#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34782#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34783#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34838#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 34839#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35404#L696-39 assume 1 == ~t8_pc~0; 35369#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 35249#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35250#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 35545#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 35509#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35384#L715-39 assume 1 == ~t9_pc~0; 34583#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34584#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35793#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36107#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 35722#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35723#L734-39 assume 1 == ~t10_pc~0; 35648#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 35094#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35405#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34736#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 34737#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35985#L753-39 assume !(1 == ~t11_pc~0); 34656#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 34657#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35949#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35374#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35375#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35476#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 35477#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35747#L1242-3 assume !(1 == ~T2_E~0); 35748#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 35967#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35667#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 35668#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 35950#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 35991#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 36079#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34808#L1282-3 assume !(1 == ~T10_E~0); 34809#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 34718#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 34719#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 35856#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 35857#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 36045#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36103#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 35769#L1322-3 assume !(1 == ~E_6~0); 35770#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 34777#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 34752#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 34753#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 35445#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 35573#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 35574#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 34700#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 34965#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 35679#L1697 assume !(0 == start_simulation_~tmp~3#1); 35466#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 35467#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 34824#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 35589#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 35590#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 35539#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 35136#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 35137#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 35850#L1678-2 [2022-07-22 02:42:46,040 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:46,040 INFO L85 PathProgramCache]: Analyzing trace with hash -24556996, now seen corresponding path program 1 times [2022-07-22 02:42:46,040 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:46,041 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [618561873] [2022-07-22 02:42:46,041 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:46,041 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:46,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:46,080 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:46,080 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:46,080 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [618561873] [2022-07-22 02:42:46,081 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [618561873] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:46,081 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:46,081 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:46,081 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [737830379] [2022-07-22 02:42:46,081 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:46,082 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:42:46,082 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:46,082 INFO L85 PathProgramCache]: Analyzing trace with hash -1367576821, now seen corresponding path program 2 times [2022-07-22 02:42:46,083 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:46,083 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1138121680] [2022-07-22 02:42:46,083 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:46,083 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:46,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:46,119 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:46,120 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:46,120 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1138121680] [2022-07-22 02:42:46,120 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1138121680] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:46,120 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:46,120 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:46,120 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [448678747] [2022-07-22 02:42:46,121 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:46,121 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:42:46,121 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:42:46,122 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-22 02:42:46,122 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-22 02:42:46,122 INFO L87 Difference]: Start difference. First operand 1566 states and 2315 transitions. cyclomatic complexity: 750 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:46,245 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:42:46,245 INFO L93 Difference]: Finished difference Result 2895 states and 4265 transitions. [2022-07-22 02:42:46,245 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-22 02:42:46,246 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2895 states and 4265 transitions. [2022-07-22 02:42:46,261 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2720 [2022-07-22 02:42:46,276 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2895 states to 2895 states and 4265 transitions. [2022-07-22 02:42:46,276 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2895 [2022-07-22 02:42:46,278 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2895 [2022-07-22 02:42:46,278 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2895 states and 4265 transitions. [2022-07-22 02:42:46,282 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:42:46,283 INFO L369 hiAutomatonCegarLoop]: Abstraction has 2895 states and 4265 transitions. [2022-07-22 02:42:46,285 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2895 states and 4265 transitions. [2022-07-22 02:42:46,326 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2895 to 2895. [2022-07-22 02:42:46,331 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2895 states, 2895 states have (on average 1.4732297063903281) internal successors, (4265), 2894 states have internal predecessors, (4265), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:46,337 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2895 states to 2895 states and 4265 transitions. [2022-07-22 02:42:46,338 INFO L392 hiAutomatonCegarLoop]: Abstraction has 2895 states and 4265 transitions. [2022-07-22 02:42:46,338 INFO L374 stractBuchiCegarLoop]: Abstraction has 2895 states and 4265 transitions. [2022-07-22 02:42:46,338 INFO L287 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-07-22 02:42:46,338 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2895 states and 4265 transitions. [2022-07-22 02:42:46,349 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2720 [2022-07-22 02:42:46,350 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:42:46,350 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:42:46,352 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:46,352 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:46,352 INFO L752 eck$LassoCheckResult]: Stem: 39748#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 39749#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 40512#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 40513#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39251#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 39252#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40525#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40484#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 40485#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39600#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 39601#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 40013#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 40455#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 39512#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 39513#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 39398#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 39399#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40378#L1109 assume !(0 == ~M_E~0); 40400#L1109-2 assume !(0 == ~T1_E~0); 39405#L1114-1 assume !(0 == ~T2_E~0); 39406#L1119-1 assume !(0 == ~T3_E~0); 40459#L1124-1 assume !(0 == ~T4_E~0); 39068#L1129-1 assume !(0 == ~T5_E~0); 39069#L1134-1 assume !(0 == ~T6_E~0); 39680#L1139-1 assume !(0 == ~T7_E~0); 40383#L1144-1 assume !(0 == ~T8_E~0); 40243#L1149-1 assume !(0 == ~T9_E~0); 39175#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 39176#L1159-1 assume !(0 == ~T11_E~0); 40227#L1164-1 assume !(0 == ~E_M~0); 39566#L1169-1 assume !(0 == ~E_1~0); 39455#L1174-1 assume !(0 == ~E_2~0); 39328#L1179-1 assume !(0 == ~E_3~0); 39255#L1184-1 assume !(0 == ~E_4~0); 39256#L1189-1 assume !(0 == ~E_5~0); 39287#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 39376#L1199-1 assume !(0 == ~E_7~0); 40251#L1204-1 assume !(0 == ~E_8~0); 40185#L1209-1 assume !(0 == ~E_9~0); 40186#L1214-1 assume !(0 == ~E_10~0); 40539#L1219-1 assume !(0 == ~E_11~0); 40626#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39585#L544 assume 1 == ~m_pc~0; 39586#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 40446#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40260#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 39217#L1379 assume !(0 != activate_threads_~tmp~1#1); 39218#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39999#L563 assume !(1 == ~t1_pc~0); 39791#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 39076#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39077#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 40121#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 39072#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39073#L582 assume 1 == ~t2_pc~0; 39769#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 40131#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40132#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40242#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 39105#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39106#L601 assume !(1 == ~t3_pc~0); 39785#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 39784#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40447#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 40167#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 40168#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40111#L620 assume 1 == ~t4_pc~0; 39086#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 39087#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39648#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39649#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 40010#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40203#L639 assume 1 == ~t5_pc~0; 40082#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39378#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39379#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40032#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 40033#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39961#L658 assume !(1 == ~t6_pc~0); 39580#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 39581#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40158#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40515#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 40174#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39420#L677 assume 1 == ~t7_pc~0; 39421#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 39324#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40344#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40477#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 40478#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40562#L696 assume !(1 == ~t8_pc~0); 39639#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 39640#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40524#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40547#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 40601#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40064#L715 assume 1 == ~t9_pc~0; 40065#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 39728#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39636#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 39637#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 40053#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 40341#L734 assume !(1 == ~t10_pc~0); 40342#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 39538#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 39539#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 39557#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 40277#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39614#L753 assume 1 == ~t11_pc~0; 39615#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 40179#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39723#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 39724#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 39878#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39936#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 39937#L1237-2 assume !(1 == ~T1_E~0); 40591#L1242-1 assume !(1 == ~T2_E~0); 39694#L1247-1 assume !(1 == ~T3_E~0); 39695#L1252-1 assume !(1 == ~T4_E~0); 39478#L1257-1 assume !(1 == ~T5_E~0); 39479#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 40359#L1267-1 assume !(1 == ~T7_E~0); 40470#L1272-1 assume !(1 == ~T8_E~0); 39778#L1277-1 assume !(1 == ~T9_E~0); 39779#L1282-1 assume !(1 == ~T10_E~0); 40211#L1287-1 assume !(1 == ~T11_E~0); 40212#L1292-1 assume !(1 == ~E_M~0); 40172#L1297-1 assume !(1 == ~E_1~0); 40173#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 40462#L1307-1 assume !(1 == ~E_3~0); 40463#L1312-1 assume !(1 == ~E_4~0); 39821#L1317-1 assume !(1 == ~E_5~0); 39822#L1322-1 assume !(1 == ~E_6~0); 39553#L1327-1 assume !(1 == ~E_7~0); 39554#L1332-1 assume !(1 == ~E_8~0); 40120#L1337-1 assume !(1 == ~E_9~0); 40056#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 40057#L1347-1 assume !(1 == ~E_11~0); 40566#L1352-1 assume { :end_inline_reset_delta_events } true; 40658#L1678-2 [2022-07-22 02:42:46,353 INFO L754 eck$LassoCheckResult]: Loop: 40658#L1678-2 assume !false; 40656#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40653#L1084 assume !false; 40652#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 40558#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 39192#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 40614#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 40638#L925 assume !(0 != eval_~tmp~0#1); 40637#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 40636#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 40635#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 39089#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 39090#L1114-3 assume !(0 == ~T2_E~0); 40175#L1119-3 assume !(0 == ~T3_E~0); 40176#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 40197#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40198#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 40392#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 40453#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 39593#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 39594#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 39832#L1159-3 assume !(0 == ~T11_E~0); 39833#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 40108#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 40109#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40159#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 40160#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 40328#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 39990#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 39351#L1199-3 assume !(0 == ~E_7~0); 39352#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 39575#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 39037#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 39038#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 39736#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39737#L544-39 assume 1 == ~m_pc~0; 40097#L545-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 39016#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39267#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 39268#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 39426#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40309#L563-39 assume !(1 == ~t1_pc~0); 39168#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 39169#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40075#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 40076#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 40619#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40439#L582-39 assume 1 == ~t2_pc~0; 39492#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 39494#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40122#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40123#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 39262#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39049#L601-39 assume 1 == ~t3_pc~0; 39050#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 39100#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40273#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 40422#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 40314#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 39956#L620-39 assume !(1 == ~t4_pc~0); 39957#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 40156#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40381#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40286#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 40287#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40631#L639-39 assume 1 == ~t5_pc~0; 40411#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39698#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39275#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39078#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 39079#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39993#L658-39 assume 1 == ~t6_pc~0; 39975#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 39976#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39028#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39029#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 40152#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40153#L677-39 assume !(1 == ~t7_pc~0); 39776#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 39253#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 39254#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41232#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 41230#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41228#L696-39 assume 1 == ~t8_pc~0; 41225#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 41223#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41220#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 41218#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 41217#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41216#L715-39 assume !(1 == ~t9_pc~0); 39056#L715-41 is_transmit9_triggered_~__retres1~9#1 := 0; 39055#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40279#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 40634#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 40204#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 40205#L734-39 assume 1 == ~t10_pc~0; 41201#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 41199#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41196#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 41194#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41192#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41190#L753-39 assume !(1 == ~t11_pc~0); 41187#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 41185#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41182#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41180#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 41178#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41176#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 39953#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 41173#L1242-3 assume !(1 == ~T2_E~0); 40232#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41169#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41167#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 41165#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 41163#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41162#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 41161#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 41160#L1282-3 assume !(1 == ~T10_E~0); 41159#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 41158#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41157#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 41156#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 41155#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 41154#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 41153#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 41152#L1322-3 assume !(1 == ~E_6~0); 41151#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 41150#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 41149#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 41148#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 41147#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 41146#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 41136#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 41133#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 41132#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 41131#L1697 assume !(0 == start_simulation_~tmp~3#1); 40431#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 41127#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 41118#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 40067#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 40068#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 40723#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 39607#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 39608#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 40658#L1678-2 [2022-07-22 02:42:46,354 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:46,354 INFO L85 PathProgramCache]: Analyzing trace with hash -1257740808, now seen corresponding path program 1 times [2022-07-22 02:42:46,354 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:46,354 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2120165035] [2022-07-22 02:42:46,354 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:46,355 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:46,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:46,385 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:46,386 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:46,386 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2120165035] [2022-07-22 02:42:46,386 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2120165035] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:46,386 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:46,386 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:46,386 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [391146435] [2022-07-22 02:42:46,387 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:46,387 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:42:46,387 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:46,388 INFO L85 PathProgramCache]: Analyzing trace with hash -1064371189, now seen corresponding path program 1 times [2022-07-22 02:42:46,388 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:46,388 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [590051287] [2022-07-22 02:42:46,388 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:46,388 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:46,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:46,423 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:46,424 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:46,424 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [590051287] [2022-07-22 02:42:46,424 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [590051287] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:46,424 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:46,424 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:46,424 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1992639886] [2022-07-22 02:42:46,425 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:46,425 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:42:46,425 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:42:46,426 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-22 02:42:46,426 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-22 02:42:46,426 INFO L87 Difference]: Start difference. First operand 2895 states and 4265 transitions. cyclomatic complexity: 1372 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:46,516 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:42:46,517 INFO L93 Difference]: Finished difference Result 5541 states and 8142 transitions. [2022-07-22 02:42:46,517 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-22 02:42:46,517 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5541 states and 8142 transitions. [2022-07-22 02:42:46,539 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5330 [2022-07-22 02:42:46,558 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5541 states to 5541 states and 8142 transitions. [2022-07-22 02:42:46,559 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5541 [2022-07-22 02:42:46,562 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5541 [2022-07-22 02:42:46,562 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5541 states and 8142 transitions. [2022-07-22 02:42:46,567 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:42:46,567 INFO L369 hiAutomatonCegarLoop]: Abstraction has 5541 states and 8142 transitions. [2022-07-22 02:42:46,570 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5541 states and 8142 transitions. [2022-07-22 02:42:46,667 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5541 to 5541. [2022-07-22 02:42:46,674 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5541 states, 5541 states have (on average 1.4694098538170006) internal successors, (8142), 5540 states have internal predecessors, (8142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:46,683 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5541 states to 5541 states and 8142 transitions. [2022-07-22 02:42:46,683 INFO L392 hiAutomatonCegarLoop]: Abstraction has 5541 states and 8142 transitions. [2022-07-22 02:42:46,683 INFO L374 stractBuchiCegarLoop]: Abstraction has 5541 states and 8142 transitions. [2022-07-22 02:42:46,683 INFO L287 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-07-22 02:42:46,683 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5541 states and 8142 transitions. [2022-07-22 02:42:46,699 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5330 [2022-07-22 02:42:46,699 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:42:46,699 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:42:46,701 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:46,701 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:46,701 INFO L752 eck$LassoCheckResult]: Stem: 48203#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 48204#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 49012#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 49013#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 47697#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 47698#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49024#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 48977#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 48978#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 48052#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 48053#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 48470#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 48941#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 47962#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 47963#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 47848#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 47849#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 48849#L1109 assume !(0 == ~M_E~0); 48875#L1109-2 assume !(0 == ~T1_E~0); 47855#L1114-1 assume !(0 == ~T2_E~0); 47856#L1119-1 assume !(0 == ~T3_E~0); 48947#L1124-1 assume !(0 == ~T4_E~0); 47512#L1129-1 assume !(0 == ~T5_E~0); 47513#L1134-1 assume !(0 == ~T6_E~0); 48135#L1139-1 assume !(0 == ~T7_E~0); 48857#L1144-1 assume !(0 == ~T8_E~0); 48714#L1149-1 assume !(0 == ~T9_E~0); 47619#L1154-1 assume !(0 == ~T10_E~0); 47620#L1159-1 assume !(0 == ~T11_E~0); 48699#L1164-1 assume !(0 == ~E_M~0); 48016#L1169-1 assume !(0 == ~E_1~0); 47905#L1174-1 assume !(0 == ~E_2~0); 47776#L1179-1 assume !(0 == ~E_3~0); 47701#L1184-1 assume !(0 == ~E_4~0); 47702#L1189-1 assume !(0 == ~E_5~0); 47734#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 47823#L1199-1 assume !(0 == ~E_7~0); 48722#L1204-1 assume !(0 == ~E_8~0); 48655#L1209-1 assume !(0 == ~E_9~0); 48656#L1214-1 assume !(0 == ~E_10~0); 49039#L1219-1 assume !(0 == ~E_11~0); 49149#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48033#L544 assume 1 == ~m_pc~0; 48034#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 48931#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48730#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 47663#L1379 assume !(0 != activate_threads_~tmp~1#1); 47664#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48452#L563 assume !(1 == ~t1_pc~0); 48245#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 47522#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47523#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 48586#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 47518#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47519#L582 assume 1 == ~t2_pc~0; 48223#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 48598#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48599#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 48713#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 47551#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47552#L601 assume !(1 == ~t3_pc~0); 48239#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 48238#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48932#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 48636#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 48637#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48576#L620 assume 1 == ~t4_pc~0; 47532#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 47533#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48100#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 48101#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 48467#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 48673#L639 assume 1 == ~t5_pc~0; 48545#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47827#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47828#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 48489#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 48490#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 48415#L658 assume !(1 == ~t6_pc~0); 48030#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 48031#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 48626#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49014#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 48640#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47868#L677 assume 1 == ~t7_pc~0; 47869#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 47768#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48816#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 48969#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 48970#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49061#L696 assume !(1 == ~t8_pc~0); 48090#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 48091#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49023#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49048#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 49118#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48524#L715 assume 1 == ~t9_pc~0; 48525#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 48183#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 48088#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 48089#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 48510#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 48811#L734 assume !(1 == ~t10_pc~0); 48812#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 47988#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47989#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 48007#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 48748#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48066#L753 assume 1 == ~t11_pc~0; 48067#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 48648#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 48178#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 48179#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 48328#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48388#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 48389#L1237-2 assume !(1 == ~T1_E~0); 49098#L1242-1 assume !(1 == ~T2_E~0); 49139#L1247-1 assume !(1 == ~T3_E~0); 48966#L1252-1 assume !(1 == ~T4_E~0); 48967#L1257-1 assume !(1 == ~T5_E~0); 49490#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 49488#L1267-1 assume !(1 == ~T7_E~0); 49486#L1272-1 assume !(1 == ~T8_E~0); 49451#L1277-1 assume !(1 == ~T9_E~0); 49449#L1282-1 assume !(1 == ~T10_E~0); 49445#L1287-1 assume !(1 == ~T11_E~0); 49443#L1292-1 assume !(1 == ~E_M~0); 49408#L1297-1 assume !(1 == ~E_1~0); 49365#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 49326#L1307-1 assume !(1 == ~E_3~0); 49321#L1312-1 assume !(1 == ~E_4~0); 49303#L1317-1 assume !(1 == ~E_5~0); 49286#L1322-1 assume !(1 == ~E_6~0); 49273#L1327-1 assume !(1 == ~E_7~0); 49253#L1332-1 assume !(1 == ~E_8~0); 49232#L1337-1 assume !(1 == ~E_9~0); 49230#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 49216#L1347-1 assume !(1 == ~E_11~0); 49207#L1352-1 assume { :end_inline_reset_delta_events } true; 49199#L1678-2 [2022-07-22 02:42:46,702 INFO L754 eck$LassoCheckResult]: Loop: 49199#L1678-2 assume !false; 49192#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49189#L1084 assume !false; 49188#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 49178#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 49175#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 49174#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 49172#L925 assume !(0 != eval_~tmp~0#1); 49171#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 49170#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 49168#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 49169#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 50494#L1114-3 assume !(0 == ~T2_E~0); 50493#L1119-3 assume !(0 == ~T3_E~0); 50492#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 50491#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 50490#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 50489#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 50488#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 50487#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 50486#L1154-3 assume !(0 == ~T10_E~0); 50485#L1159-3 assume !(0 == ~T11_E~0); 50484#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 50483#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 50482#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 50480#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50478#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 50477#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 50473#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 50474#L1199-3 assume !(0 == ~E_7~0); 52124#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 52122#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 50464#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 50463#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 50462#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48564#L544-39 assume 1 == ~m_pc~0; 48565#L545-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 47465#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47715#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 47716#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 47876#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48784#L563-39 assume 1 == ~t1_pc~0; 49107#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 51761#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48538#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 48539#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 49140#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49143#L582-39 assume 1 == ~t2_pc~0; 47942#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 47944#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48693#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 48882#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 48883#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50255#L601-39 assume 1 == ~t3_pc~0; 50252#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 50250#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50248#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50246#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 50244#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48410#L620-39 assume !(1 == ~t4_pc~0); 48411#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 48625#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50048#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50045#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50043#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50001#L639-39 assume 1 == ~t5_pc~0; 49997#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49995#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49993#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49949#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 49947#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49945#L658-39 assume !(1 == ~t6_pc~0); 49942#L658-41 is_transmit6_triggered_~__retres1~6#1 := 0; 49900#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49897#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49895#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 49893#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49854#L677-39 assume 1 == ~t7_pc~0; 49809#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49807#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49773#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49771#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 49770#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49710#L696-39 assume 1 == ~t8_pc~0; 49707#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 49705#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49702#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49700#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 49698#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49697#L715-39 assume !(1 == ~t9_pc~0); 49696#L715-41 is_transmit9_triggered_~__retres1~9#1 := 0; 49694#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49693#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49692#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 49691#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49690#L734-39 assume 1 == ~t10_pc~0; 49688#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 49687#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 49684#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 49682#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 49680#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 49678#L753-39 assume !(1 == ~t11_pc~0); 47573#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 47574#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 48935#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 49584#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 49582#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49580#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 48407#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 49578#L1242-3 assume !(1 == ~T2_E~0); 48704#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 49575#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 49537#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 49535#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 49533#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 49502#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 49499#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 49461#L1282-3 assume !(1 == ~T10_E~0); 49423#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 49391#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 49388#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 49386#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 49385#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 49384#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49383#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 49382#L1322-3 assume !(1 == ~E_6~0); 49381#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 49380#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 49379#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 49378#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 49377#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 49375#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 49338#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 49335#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 49333#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 49331#L1697 assume !(0 == start_simulation_~tmp~3#1); 48910#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 49282#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 49272#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 49252#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 49231#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 49229#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 49215#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 49206#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 49199#L1678-2 [2022-07-22 02:42:46,702 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:46,702 INFO L85 PathProgramCache]: Analyzing trace with hash -786384458, now seen corresponding path program 1 times [2022-07-22 02:42:46,703 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:46,703 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [126104513] [2022-07-22 02:42:46,703 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:46,703 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:46,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:46,726 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:46,726 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:46,726 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [126104513] [2022-07-22 02:42:46,726 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [126104513] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:46,727 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:46,727 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:46,727 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1901198678] [2022-07-22 02:42:46,727 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:46,727 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:42:46,727 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:46,728 INFO L85 PathProgramCache]: Analyzing trace with hash 1856747400, now seen corresponding path program 1 times [2022-07-22 02:42:46,728 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:46,728 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [519431330] [2022-07-22 02:42:46,728 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:46,728 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:46,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:46,753 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:46,753 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:46,753 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [519431330] [2022-07-22 02:42:46,753 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [519431330] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:46,753 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:46,754 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:46,754 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [234380692] [2022-07-22 02:42:46,754 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:46,754 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:42:46,754 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:42:46,755 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-22 02:42:46,755 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-22 02:42:46,755 INFO L87 Difference]: Start difference. First operand 5541 states and 8142 transitions. cyclomatic complexity: 2605 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:46,885 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:42:46,885 INFO L93 Difference]: Finished difference Result 10453 states and 15329 transitions. [2022-07-22 02:42:46,885 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-22 02:42:46,886 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10453 states and 15329 transitions. [2022-07-22 02:42:46,927 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10206 [2022-07-22 02:42:46,953 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10453 states to 10453 states and 15329 transitions. [2022-07-22 02:42:46,953 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10453 [2022-07-22 02:42:46,960 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10453 [2022-07-22 02:42:46,961 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10453 states and 15329 transitions. [2022-07-22 02:42:46,971 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:42:46,971 INFO L369 hiAutomatonCegarLoop]: Abstraction has 10453 states and 15329 transitions. [2022-07-22 02:42:46,977 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10453 states and 15329 transitions. [2022-07-22 02:42:47,063 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10453 to 10449. [2022-07-22 02:42:47,074 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10449 states, 10449 states have (on average 1.4666475260790506) internal successors, (15325), 10448 states have internal predecessors, (15325), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:47,090 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10449 states to 10449 states and 15325 transitions. [2022-07-22 02:42:47,090 INFO L392 hiAutomatonCegarLoop]: Abstraction has 10449 states and 15325 transitions. [2022-07-22 02:42:47,090 INFO L374 stractBuchiCegarLoop]: Abstraction has 10449 states and 15325 transitions. [2022-07-22 02:42:47,090 INFO L287 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-07-22 02:42:47,091 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10449 states and 15325 transitions. [2022-07-22 02:42:47,151 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10206 [2022-07-22 02:42:47,152 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:42:47,152 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:42:47,153 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:47,153 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:47,153 INFO L752 eck$LassoCheckResult]: Stem: 64200#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 64201#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 64959#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 64960#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 63701#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 63702#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 64969#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 64933#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 64934#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 64052#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 64053#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 64465#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 64897#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 63963#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 63964#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 63849#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 63850#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 64820#L1109 assume !(0 == ~M_E~0); 64843#L1109-2 assume !(0 == ~T1_E~0); 63856#L1114-1 assume !(0 == ~T2_E~0); 63857#L1119-1 assume !(0 == ~T3_E~0); 64901#L1124-1 assume !(0 == ~T4_E~0); 63516#L1129-1 assume !(0 == ~T5_E~0); 63517#L1134-1 assume !(0 == ~T6_E~0); 64132#L1139-1 assume !(0 == ~T7_E~0); 64826#L1144-1 assume !(0 == ~T8_E~0); 64694#L1149-1 assume !(0 == ~T9_E~0); 63623#L1154-1 assume !(0 == ~T10_E~0); 63624#L1159-1 assume !(0 == ~T11_E~0); 64679#L1164-1 assume !(0 == ~E_M~0); 64017#L1169-1 assume !(0 == ~E_1~0); 63906#L1174-1 assume !(0 == ~E_2~0); 63779#L1179-1 assume !(0 == ~E_3~0); 63705#L1184-1 assume !(0 == ~E_4~0); 63706#L1189-1 assume !(0 == ~E_5~0); 63738#L1194-1 assume !(0 == ~E_6~0); 63825#L1199-1 assume !(0 == ~E_7~0); 64702#L1204-1 assume !(0 == ~E_8~0); 64636#L1209-1 assume !(0 == ~E_9~0); 64637#L1214-1 assume !(0 == ~E_10~0); 64982#L1219-1 assume !(0 == ~E_11~0); 65076#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 64035#L544 assume 1 == ~m_pc~0; 64036#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 64888#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 64710#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 63667#L1379 assume !(0 != activate_threads_~tmp~1#1); 63668#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 64448#L563 assume !(1 == ~t1_pc~0); 64243#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 63526#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 63527#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 64575#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 63522#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 63523#L582 assume 1 == ~t2_pc~0; 64221#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 64586#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 64587#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 64693#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 63555#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 63556#L601 assume !(1 == ~t3_pc~0); 64237#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 64236#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 64889#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 64622#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 64623#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 64565#L620 assume 1 == ~t4_pc~0; 63536#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 63537#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64100#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 64101#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 64462#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 64654#L639 assume 1 == ~t5_pc~0; 64535#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 63829#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 63830#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 64483#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 64484#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 64413#L658 assume !(1 == ~t6_pc~0); 64032#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 64033#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 64612#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 64961#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 64626#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 63869#L677 assume 1 == ~t7_pc~0; 63870#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 63772#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 64790#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 64926#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 64927#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 65004#L696 assume !(1 == ~t8_pc~0); 64090#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 64091#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 64968#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 64990#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 65045#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 64518#L715 assume 1 == ~t9_pc~0; 64519#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 64180#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 64088#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 64089#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 64504#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 64786#L734 assume !(1 == ~t10_pc~0); 64787#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 63989#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 63990#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 64008#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 64728#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 64066#L753 assume 1 == ~t11_pc~0; 64067#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 64631#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 64175#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 64176#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 64327#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64386#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 64387#L1237-2 assume !(1 == ~T1_E~0); 65058#L1242-1 assume !(1 == ~T2_E~0); 64146#L1247-1 assume !(1 == ~T3_E~0); 64147#L1252-1 assume !(1 == ~T4_E~0); 65493#L1257-1 assume !(1 == ~T5_E~0); 65491#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 65489#L1267-1 assume !(1 == ~T7_E~0); 65442#L1272-1 assume !(1 == ~T8_E~0); 65439#L1277-1 assume !(1 == ~T9_E~0); 65384#L1282-1 assume !(1 == ~T10_E~0); 65332#L1287-1 assume !(1 == ~T11_E~0); 65293#L1292-1 assume !(1 == ~E_M~0); 65291#L1297-1 assume !(1 == ~E_1~0); 65251#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 65249#L1307-1 assume !(1 == ~E_3~0); 65213#L1312-1 assume !(1 == ~E_4~0); 65211#L1317-1 assume !(1 == ~E_5~0); 65210#L1322-1 assume !(1 == ~E_6~0); 65181#L1327-1 assume !(1 == ~E_7~0); 65177#L1332-1 assume !(1 == ~E_8~0); 65176#L1337-1 assume !(1 == ~E_9~0); 65155#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 65137#L1347-1 assume !(1 == ~E_11~0); 65128#L1352-1 assume { :end_inline_reset_delta_events } true; 65120#L1678-2 [2022-07-22 02:42:47,154 INFO L754 eck$LassoCheckResult]: Loop: 65120#L1678-2 assume !false; 65113#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 65110#L1084 assume !false; 65109#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 65099#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 65096#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 65095#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 65093#L925 assume !(0 != eval_~tmp~0#1); 65092#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 65091#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 65089#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 65090#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 67577#L1114-3 assume !(0 == ~T2_E~0); 67576#L1119-3 assume !(0 == ~T3_E~0); 67574#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 67572#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 67570#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 67221#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 67219#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 67217#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 67215#L1154-3 assume !(0 == ~T10_E~0); 67213#L1159-3 assume !(0 == ~T11_E~0); 67211#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 67209#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 67207#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 67205#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 67203#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 67201#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 67198#L1194-3 assume !(0 == ~E_6~0); 67196#L1199-3 assume !(0 == ~E_7~0); 67194#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 67192#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 67190#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 67188#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 67185#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67183#L544-39 assume !(1 == ~m_pc~0); 67181#L544-41 is_master_triggered_~__retres1~0#1 := 0; 67179#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 67177#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 67174#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 66609#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 66607#L563-39 assume !(1 == ~t1_pc~0); 66605#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 66603#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 66602#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 66599#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 66597#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 66595#L582-39 assume 1 == ~t2_pc~0; 66593#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 66590#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 66588#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 66585#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 66583#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 66581#L601-39 assume !(1 == ~t3_pc~0); 66579#L601-41 is_transmit3_triggered_~__retres1~3#1 := 0; 66577#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 66576#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 66575#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 66573#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 66571#L620-39 assume 1 == ~t4_pc~0; 66569#L621-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 66566#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66564#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 64737#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 64738#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 65087#L639-39 assume 1 == ~t5_pc~0; 64854#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 64150#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 63725#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 63528#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 63529#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 64445#L658-39 assume 1 == ~t6_pc~0; 64427#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 64428#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 63478#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 63479#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 64607#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 64608#L677-39 assume !(1 == ~t7_pc~0); 64228#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 63703#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 63704#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 63760#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 63761#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 64331#L696-39 assume 1 == ~t8_pc~0; 64293#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 64172#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 64173#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 64474#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 64438#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 64309#L715-39 assume 1 == ~t9_pc~0; 63504#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 63505#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 64730#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 65088#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 64656#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 64657#L734-39 assume 1 == ~t10_pc~0; 64582#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 64016#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 64332#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 63657#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 63658#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 64937#L753-39 assume !(1 == ~t11_pc~0); 63577#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 63578#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 64892#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 64299#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 64300#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 65767#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 64405#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 65672#L1242-3 assume !(1 == ~T2_E~0); 64684#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 65616#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 65549#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 65547#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 65545#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 65495#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 65494#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 65448#L1282-3 assume !(1 == ~T10_E~0); 65397#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 65395#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 65393#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 65353#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 65351#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 65349#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 65347#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 65342#L1322-3 assume !(1 == ~E_6~0); 65341#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 65340#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 65339#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 65338#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 65337#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 65336#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 65301#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 65297#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 65273#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 65272#L1697 assume !(0 == start_simulation_~tmp~3#1); 64872#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 65240#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 65200#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 65198#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 65175#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 65154#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 65136#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 65127#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 65120#L1678-2 [2022-07-22 02:42:47,154 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:47,154 INFO L85 PathProgramCache]: Analyzing trace with hash 602909556, now seen corresponding path program 1 times [2022-07-22 02:42:47,154 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:47,154 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [946966967] [2022-07-22 02:42:47,155 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:47,155 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:47,163 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:47,174 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:47,175 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:47,175 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [946966967] [2022-07-22 02:42:47,175 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [946966967] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:47,175 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:47,175 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-22 02:42:47,175 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [444235774] [2022-07-22 02:42:47,175 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:47,176 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:42:47,176 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:47,176 INFO L85 PathProgramCache]: Analyzing trace with hash -250116089, now seen corresponding path program 1 times [2022-07-22 02:42:47,176 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:47,176 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [495835366] [2022-07-22 02:42:47,177 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:47,177 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:47,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:47,196 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:47,197 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:47,197 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [495835366] [2022-07-22 02:42:47,197 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [495835366] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:47,197 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:47,197 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:47,197 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1125878112] [2022-07-22 02:42:47,197 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:47,198 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:42:47,198 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:42:47,198 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:42:47,198 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:42:47,199 INFO L87 Difference]: Start difference. First operand 10449 states and 15325 transitions. cyclomatic complexity: 4884 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:47,319 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:42:47,319 INFO L93 Difference]: Finished difference Result 20529 states and 29894 transitions. [2022-07-22 02:42:47,319 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:42:47,320 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20529 states and 29894 transitions. [2022-07-22 02:42:47,403 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 20279 [2022-07-22 02:42:47,459 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20529 states to 20529 states and 29894 transitions. [2022-07-22 02:42:47,460 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20529 [2022-07-22 02:42:47,478 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20529 [2022-07-22 02:42:47,478 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20529 states and 29894 transitions. [2022-07-22 02:42:47,499 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:42:47,500 INFO L369 hiAutomatonCegarLoop]: Abstraction has 20529 states and 29894 transitions. [2022-07-22 02:42:47,514 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20529 states and 29894 transitions. [2022-07-22 02:42:47,859 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20529 to 19865. [2022-07-22 02:42:47,887 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19865 states, 19865 states have (on average 1.4577397432670527) internal successors, (28958), 19864 states have internal predecessors, (28958), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:47,919 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19865 states to 19865 states and 28958 transitions. [2022-07-22 02:42:47,919 INFO L392 hiAutomatonCegarLoop]: Abstraction has 19865 states and 28958 transitions. [2022-07-22 02:42:47,919 INFO L374 stractBuchiCegarLoop]: Abstraction has 19865 states and 28958 transitions. [2022-07-22 02:42:47,919 INFO L287 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-07-22 02:42:47,919 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19865 states and 28958 transitions. [2022-07-22 02:42:48,104 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 19615 [2022-07-22 02:42:48,105 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:42:48,105 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:42:48,107 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:48,107 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:48,107 INFO L752 eck$LassoCheckResult]: Stem: 95200#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 95201#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 96074#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 96075#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 94687#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 94688#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 96089#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 96039#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 96040#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 95044#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 95045#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 95479#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 95992#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 94954#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 94955#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 94837#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 94838#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 95893#L1109 assume !(0 == ~M_E~0); 95923#L1109-2 assume !(0 == ~T1_E~0); 94844#L1114-1 assume !(0 == ~T2_E~0); 94845#L1119-1 assume !(0 == ~T3_E~0); 95996#L1124-1 assume !(0 == ~T4_E~0); 94502#L1129-1 assume !(0 == ~T5_E~0); 94503#L1134-1 assume !(0 == ~T6_E~0); 95129#L1139-1 assume !(0 == ~T7_E~0); 95902#L1144-1 assume !(0 == ~T8_E~0); 95735#L1149-1 assume !(0 == ~T9_E~0); 94609#L1154-1 assume !(0 == ~T10_E~0); 94610#L1159-1 assume !(0 == ~T11_E~0); 95720#L1164-1 assume !(0 == ~E_M~0); 95010#L1169-1 assume !(0 == ~E_1~0); 94894#L1174-1 assume !(0 == ~E_2~0); 94767#L1179-1 assume !(0 == ~E_3~0); 94691#L1184-1 assume !(0 == ~E_4~0); 94692#L1189-1 assume !(0 == ~E_5~0); 94725#L1194-1 assume !(0 == ~E_6~0); 94813#L1199-1 assume !(0 == ~E_7~0); 95743#L1204-1 assume !(0 == ~E_8~0); 95668#L1209-1 assume !(0 == ~E_9~0); 95669#L1214-1 assume !(0 == ~E_10~0); 96113#L1219-1 assume !(0 == ~E_11~0); 96274#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 95027#L544 assume !(1 == ~m_pc~0); 95028#L544-2 is_master_triggered_~__retres1~0#1 := 0; 95979#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 95753#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 94652#L1379 assume !(0 != activate_threads_~tmp~1#1); 94653#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 95459#L563 assume !(1 == ~t1_pc~0); 95244#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 94512#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 94513#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 95606#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 94508#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 94509#L582 assume 1 == ~t2_pc~0; 95221#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 95616#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 95617#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 95734#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 94541#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 94542#L601 assume !(1 == ~t3_pc~0); 95238#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 95237#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 95980#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 95653#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 95654#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 95596#L620 assume 1 == ~t4_pc~0; 94522#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 94523#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 95097#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 95098#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 95473#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 95692#L639 assume 1 == ~t5_pc~0; 95563#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 94817#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 94818#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 95498#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 95499#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 95424#L658 assume !(1 == ~t6_pc~0); 95024#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 95025#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 95643#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 96077#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 95658#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 94857#L677 assume 1 == ~t7_pc~0; 94858#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 94759#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 95856#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 96026#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 96027#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 96143#L696 assume !(1 == ~t8_pc~0); 95087#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 95088#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 96088#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 96124#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 96214#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 95544#L715 assume 1 == ~t9_pc~0; 95545#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 95179#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 95085#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 95086#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 95526#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 95852#L734 assume !(1 == ~t10_pc~0); 95853#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 94982#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 94983#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 95001#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 95774#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 95060#L753 assume 1 == ~t11_pc~0; 95061#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 95663#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 95174#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 95175#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 95336#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 95394#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 95395#L1237-2 assume !(1 == ~T1_E~0); 96243#L1242-1 assume !(1 == ~T2_E~0); 95143#L1247-1 assume !(1 == ~T3_E~0); 95144#L1252-1 assume !(1 == ~T4_E~0); 94917#L1257-1 assume !(1 == ~T5_E~0); 94918#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 96015#L1267-1 assume !(1 == ~T7_E~0); 96016#L1272-1 assume !(1 == ~T8_E~0); 95231#L1277-1 assume !(1 == ~T9_E~0); 95232#L1282-1 assume !(1 == ~T10_E~0); 95789#L1287-1 assume !(1 == ~T11_E~0); 95744#L1292-1 assume !(1 == ~E_M~0); 95745#L1297-1 assume !(1 == ~E_1~0); 95053#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 95054#L1307-1 assume !(1 == ~E_3~0); 95999#L1312-1 assume !(1 == ~E_4~0); 95278#L1317-1 assume !(1 == ~E_5~0); 95279#L1322-1 assume !(1 == ~E_6~0); 94997#L1327-1 assume !(1 == ~E_7~0); 94998#L1332-1 assume !(1 == ~E_8~0); 95605#L1337-1 assume !(1 == ~E_9~0); 95532#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 95533#L1347-1 assume !(1 == ~E_11~0); 95998#L1352-1 assume { :end_inline_reset_delta_events } true; 95855#L1678-2 [2022-07-22 02:42:48,107 INFO L754 eck$LassoCheckResult]: Loop: 95855#L1678-2 assume !false; 95597#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 95598#L1084 assume !false; 95351#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 95352#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 94628#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 95711#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 94554#L925 assume !(0 != eval_~tmp~0#1); 94556#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 94670#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 94671#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 94525#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 94526#L1114-3 assume !(0 == ~T2_E~0); 95659#L1119-3 assume !(0 == ~T3_E~0); 95660#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 95686#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 95687#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 95910#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 95990#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 95036#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 95037#L1154-3 assume !(0 == ~T10_E~0); 95288#L1159-3 assume !(0 == ~T11_E~0); 95289#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 95590#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 95591#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 95645#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 95646#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 95838#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 95453#L1194-3 assume !(0 == ~E_6~0); 94790#L1199-3 assume !(0 == ~E_7~0); 94791#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 95019#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 94473#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 94474#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 95187#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 95188#L544-39 assume !(1 == ~m_pc~0); 94450#L544-41 is_master_triggered_~__retres1~0#1 := 0; 94451#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 94706#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 94707#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 94865#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 95820#L563-39 assume 1 == ~t1_pc~0; 95827#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 94605#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 95556#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 95557#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 96254#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 95966#L582-39 assume 1 == ~t2_pc~0; 94933#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 94935#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 95607#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 95608#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 94698#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 94699#L601-39 assume !(1 == ~t3_pc~0); 113793#L601-41 is_transmit3_triggered_~__retres1~3#1 := 0; 113791#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 113788#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 113786#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 113784#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 113782#L620-39 assume !(1 == ~t4_pc~0); 113779#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 113777#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 113774#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 113772#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 113770#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 113768#L639-39 assume 1 == ~t5_pc~0; 113765#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 113764#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 113763#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 113762#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 113761#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 113760#L658-39 assume 1 == ~t6_pc~0; 113759#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 113757#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 113756#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 113755#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 113754#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 113753#L677-39 assume 1 == ~t7_pc~0; 113751#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 113750#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 113749#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 113748#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 113747#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 113746#L696-39 assume !(1 == ~t8_pc~0); 113745#L696-41 is_transmit8_triggered_~__retres1~8#1 := 0; 113743#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 113742#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 113741#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 113740#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 113739#L715-39 assume 1 == ~t9_pc~0; 113737#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 95776#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 95777#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 113736#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 113735#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 113734#L734-39 assume !(1 == ~t10_pc~0); 113733#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 113731#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 95699#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 94642#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 94643#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 96043#L753-39 assume !(1 == ~t11_pc~0); 94563#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 94564#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 95985#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 95305#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 95306#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 95416#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 95417#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 95723#L1242-3 assume !(1 == ~T2_E~0); 95724#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 96014#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 95632#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 95633#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 95987#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 96050#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 96208#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 94717#L1282-3 assume !(1 == ~T10_E~0); 94718#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 94625#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 94626#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 95861#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 95862#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 96140#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 96292#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 95748#L1322-3 assume !(1 == ~E_6~0); 95749#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 94684#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 94658#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 94659#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 95379#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 95524#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 95525#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 94607#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 94875#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 95644#L1697 assume !(0 == start_simulation_~tmp~3#1); 95406#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 95407#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 94733#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 95547#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 95548#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 95482#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 95051#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 95052#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 95855#L1678-2 [2022-07-22 02:42:48,108 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:48,108 INFO L85 PathProgramCache]: Analyzing trace with hash -1258502475, now seen corresponding path program 1 times [2022-07-22 02:42:48,108 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:48,108 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1303185780] [2022-07-22 02:42:48,108 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:48,108 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:48,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:48,137 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:48,138 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:48,138 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1303185780] [2022-07-22 02:42:48,138 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1303185780] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:48,138 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:48,138 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:48,139 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1550649301] [2022-07-22 02:42:48,139 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:48,139 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:42:48,139 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:48,139 INFO L85 PathProgramCache]: Analyzing trace with hash 871525448, now seen corresponding path program 1 times [2022-07-22 02:42:48,140 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:48,140 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [942360082] [2022-07-22 02:42:48,140 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:48,140 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:48,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:48,169 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:48,169 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:48,169 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [942360082] [2022-07-22 02:42:48,169 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [942360082] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:48,170 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:48,170 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:48,170 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [666554289] [2022-07-22 02:42:48,170 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:48,170 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:42:48,170 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:42:48,171 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-22 02:42:48,171 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-22 02:42:48,171 INFO L87 Difference]: Start difference. First operand 19865 states and 28958 transitions. cyclomatic complexity: 9109 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:48,500 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:42:48,500 INFO L93 Difference]: Finished difference Result 48329 states and 69889 transitions. [2022-07-22 02:42:48,500 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-22 02:42:48,502 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 48329 states and 69889 transitions. [2022-07-22 02:42:48,942 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 47352 [2022-07-22 02:42:49,097 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 48329 states to 48329 states and 69889 transitions. [2022-07-22 02:42:49,097 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 48329 [2022-07-22 02:42:49,133 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 48329 [2022-07-22 02:42:49,133 INFO L73 IsDeterministic]: Start isDeterministic. Operand 48329 states and 69889 transitions. [2022-07-22 02:42:49,172 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:42:49,172 INFO L369 hiAutomatonCegarLoop]: Abstraction has 48329 states and 69889 transitions. [2022-07-22 02:42:49,198 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48329 states and 69889 transitions. [2022-07-22 02:42:49,629 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48329 to 37893. [2022-07-22 02:42:49,670 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37893 states, 37893 states have (on average 1.4509276119599925) internal successors, (54980), 37892 states have internal predecessors, (54980), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:49,900 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37893 states to 37893 states and 54980 transitions. [2022-07-22 02:42:49,900 INFO L392 hiAutomatonCegarLoop]: Abstraction has 37893 states and 54980 transitions. [2022-07-22 02:42:49,900 INFO L374 stractBuchiCegarLoop]: Abstraction has 37893 states and 54980 transitions. [2022-07-22 02:42:49,900 INFO L287 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-07-22 02:42:49,900 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37893 states and 54980 transitions. [2022-07-22 02:42:50,012 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 37636 [2022-07-22 02:42:50,013 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:42:50,013 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:42:50,017 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:50,017 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:50,017 INFO L752 eck$LassoCheckResult]: Stem: 163392#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 163393#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 164196#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 164197#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 162890#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 162891#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 164207#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 164167#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 164168#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 163243#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 163244#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 163662#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 164135#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 163156#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 163157#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 163039#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 163040#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 164037#L1109 assume !(0 == ~M_E~0); 164066#L1109-2 assume !(0 == ~T1_E~0); 163046#L1114-1 assume !(0 == ~T2_E~0); 163047#L1119-1 assume !(0 == ~T3_E~0); 164140#L1124-1 assume !(0 == ~T4_E~0); 162707#L1129-1 assume !(0 == ~T5_E~0); 162708#L1134-1 assume !(0 == ~T6_E~0); 163325#L1139-1 assume !(0 == ~T7_E~0); 164044#L1144-1 assume !(0 == ~T8_E~0); 163902#L1149-1 assume !(0 == ~T9_E~0); 162814#L1154-1 assume !(0 == ~T10_E~0); 162815#L1159-1 assume !(0 == ~T11_E~0); 163887#L1164-1 assume !(0 == ~E_M~0); 163210#L1169-1 assume !(0 == ~E_1~0); 163096#L1174-1 assume !(0 == ~E_2~0); 162970#L1179-1 assume !(0 == ~E_3~0); 162894#L1184-1 assume !(0 == ~E_4~0); 162895#L1189-1 assume !(0 == ~E_5~0); 162927#L1194-1 assume !(0 == ~E_6~0); 163017#L1199-1 assume !(0 == ~E_7~0); 163910#L1204-1 assume !(0 == ~E_8~0); 163842#L1209-1 assume !(0 == ~E_9~0); 163843#L1214-1 assume !(0 == ~E_10~0); 164220#L1219-1 assume !(0 == ~E_11~0); 164326#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 163229#L544 assume !(1 == ~m_pc~0); 163230#L544-2 is_master_triggered_~__retres1~0#1 := 0; 164125#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 163920#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 162857#L1379 assume !(0 != activate_threads_~tmp~1#1); 162858#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 163647#L563 assume !(1 == ~t1_pc~0); 163433#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 162715#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 162716#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 163776#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 162711#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 162712#L582 assume !(1 == ~t2_pc~0); 163412#L582-2 is_transmit2_triggered_~__retres1~2#1 := 0; 163788#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 163789#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 163901#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 162744#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 162745#L601 assume !(1 == ~t3_pc~0); 163427#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 163426#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 164128#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 163826#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 163827#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 163765#L620 assume 1 == ~t4_pc~0; 162727#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 162728#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 163291#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 163292#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 163658#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 163860#L639 assume 1 == ~t5_pc~0; 163737#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 163019#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 163020#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 163681#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 163682#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 163609#L658 assume !(1 == ~t6_pc~0); 163224#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 163225#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 163817#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 164199#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 163830#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 163061#L677 assume 1 == ~t7_pc~0; 163062#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 162964#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 164003#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 164160#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 164161#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 164244#L696 assume !(1 == ~t8_pc~0); 163282#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 163283#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 164206#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 164230#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 164292#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 163717#L715 assume 1 == ~t9_pc~0; 163718#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 163372#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 163279#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 163280#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 163703#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 164000#L734 assume !(1 == ~t10_pc~0); 164001#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 163182#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 163183#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 163203#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 163937#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 163258#L753 assume 1 == ~t11_pc~0; 163259#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 163835#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 163367#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 163368#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 163521#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 163578#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 163579#L1237-2 assume !(1 == ~T1_E~0); 164307#L1242-1 assume !(1 == ~T2_E~0); 164308#L1247-1 assume !(1 == ~T3_E~0); 174396#L1252-1 assume !(1 == ~T4_E~0); 174394#L1257-1 assume !(1 == ~T5_E~0); 174392#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 174390#L1267-1 assume !(1 == ~T7_E~0); 174388#L1272-1 assume !(1 == ~T8_E~0); 174386#L1277-1 assume !(1 == ~T9_E~0); 174384#L1282-1 assume !(1 == ~T10_E~0); 174381#L1287-1 assume !(1 == ~T11_E~0); 174379#L1292-1 assume !(1 == ~E_M~0); 174377#L1297-1 assume !(1 == ~E_1~0); 174375#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 174373#L1307-1 assume !(1 == ~E_3~0); 174371#L1312-1 assume !(1 == ~E_4~0); 174369#L1317-1 assume !(1 == ~E_5~0); 174297#L1322-1 assume !(1 == ~E_6~0); 174294#L1327-1 assume !(1 == ~E_7~0); 174293#L1332-1 assume !(1 == ~E_8~0); 174292#L1337-1 assume !(1 == ~E_9~0); 174291#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 174290#L1347-1 assume !(1 == ~E_11~0); 174289#L1352-1 assume { :end_inline_reset_delta_events } true; 174286#L1678-2 [2022-07-22 02:42:50,018 INFO L754 eck$LassoCheckResult]: Loop: 174286#L1678-2 assume !false; 174281#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 174277#L1084 assume !false; 174274#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 174260#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 174254#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 174251#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 174245#L925 assume !(0 != eval_~tmp~0#1); 174246#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 181353#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 181140#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 181130#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 180528#L1114-3 assume !(0 == ~T2_E~0); 180525#L1119-3 assume !(0 == ~T3_E~0); 180522#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 180518#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 180515#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 180512#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 180507#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 180503#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 180499#L1154-3 assume !(0 == ~T10_E~0); 180494#L1159-3 assume !(0 == ~T11_E~0); 180490#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 180486#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 180483#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 180478#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 180474#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 180469#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 180465#L1194-3 assume !(0 == ~E_6~0); 180461#L1199-3 assume !(0 == ~E_7~0); 180456#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 180453#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 180449#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 180444#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 180440#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 180436#L544-39 assume !(1 == ~m_pc~0); 180431#L544-41 is_master_triggered_~__retres1~0#1 := 0; 180426#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 180422#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 180417#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 180414#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 180411#L563-39 assume 1 == ~t1_pc~0; 180406#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 180402#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 180399#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 180396#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 180392#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 180388#L582-39 assume !(1 == ~t2_pc~0); 167508#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 180379#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 180375#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 180371#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 180367#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 180362#L601-39 assume 1 == ~t3_pc~0; 180356#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 180351#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 180347#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 180343#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 180339#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 180336#L620-39 assume !(1 == ~t4_pc~0); 180330#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 180325#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 180321#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 180317#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 180313#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 180308#L639-39 assume 1 == ~t5_pc~0; 180302#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 180297#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 180293#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 180289#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 180285#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 180280#L658-39 assume !(1 == ~t6_pc~0); 180274#L658-41 is_transmit6_triggered_~__retres1~6#1 := 0; 180269#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 180265#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 180261#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 180257#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 180252#L677-39 assume 1 == ~t7_pc~0; 180246#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 180241#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 180237#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 180233#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 180229#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 176014#L696-39 assume 1 == ~t8_pc~0; 176010#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 176008#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 176006#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 176004#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 176002#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 176000#L715-39 assume 1 == ~t9_pc~0; 175995#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 175993#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 175991#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 175989#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 175987#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 175984#L734-39 assume !(1 == ~t10_pc~0); 175982#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 175979#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 175977#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 175975#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 175973#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 175972#L753-39 assume !(1 == ~t11_pc~0); 175970#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 175969#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 175968#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 175966#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 175964#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 175962#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 163594#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 175959#L1242-3 assume !(1 == ~T2_E~0); 163892#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 175956#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 175953#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 175951#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 175949#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 175947#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 175945#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 175482#L1282-3 assume !(1 == ~T10_E~0); 175480#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 175478#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 175476#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 175473#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 175471#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 175469#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 175467#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 175334#L1322-3 assume !(1 == ~E_6~0); 175331#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 175329#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 175327#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 175325#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 175323#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 175321#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 175259#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 175249#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 175241#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 174778#L1697 assume !(0 == start_simulation_~tmp~3#1); 174776#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 174341#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 174330#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 174329#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 174318#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 174310#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 174303#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 174288#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 174286#L1678-2 [2022-07-22 02:42:50,018 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:50,018 INFO L85 PathProgramCache]: Analyzing trace with hash 1819278198, now seen corresponding path program 1 times [2022-07-22 02:42:50,019 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:50,019 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1725212662] [2022-07-22 02:42:50,019 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:50,019 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:50,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:50,053 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:50,054 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:50,054 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1725212662] [2022-07-22 02:42:50,054 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1725212662] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:50,054 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:50,054 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-22 02:42:50,055 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [44513032] [2022-07-22 02:42:50,055 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:50,055 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:42:50,055 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:50,055 INFO L85 PathProgramCache]: Analyzing trace with hash 1274416648, now seen corresponding path program 1 times [2022-07-22 02:42:50,056 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:50,056 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2146845055] [2022-07-22 02:42:50,056 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:50,056 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:50,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:50,089 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:50,089 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:50,089 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2146845055] [2022-07-22 02:42:50,089 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2146845055] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:50,090 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:50,090 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-22 02:42:50,090 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1336475610] [2022-07-22 02:42:50,090 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:50,090 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:42:50,091 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:42:50,091 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:42:50,091 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:42:50,091 INFO L87 Difference]: Start difference. First operand 37893 states and 54980 transitions. cyclomatic complexity: 17103 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:50,545 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:42:50,545 INFO L93 Difference]: Finished difference Result 72452 states and 104661 transitions. [2022-07-22 02:42:50,545 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:42:50,546 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 72452 states and 104661 transitions. [2022-07-22 02:42:50,959 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 72116 [2022-07-22 02:42:51,310 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 72452 states to 72452 states and 104661 transitions. [2022-07-22 02:42:51,310 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 72452 [2022-07-22 02:42:51,339 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 72452 [2022-07-22 02:42:51,339 INFO L73 IsDeterministic]: Start isDeterministic. Operand 72452 states and 104661 transitions. [2022-07-22 02:42:51,404 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:42:51,405 INFO L369 hiAutomatonCegarLoop]: Abstraction has 72452 states and 104661 transitions. [2022-07-22 02:42:51,446 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72452 states and 104661 transitions. [2022-07-22 02:42:52,113 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72452 to 72388. [2022-07-22 02:42:52,186 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 72388 states, 72388 states have (on average 1.444949439133558) internal successors, (104597), 72387 states have internal predecessors, (104597), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:52,351 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72388 states to 72388 states and 104597 transitions. [2022-07-22 02:42:52,351 INFO L392 hiAutomatonCegarLoop]: Abstraction has 72388 states and 104597 transitions. [2022-07-22 02:42:52,352 INFO L374 stractBuchiCegarLoop]: Abstraction has 72388 states and 104597 transitions. [2022-07-22 02:42:52,352 INFO L287 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-07-22 02:42:52,352 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 72388 states and 104597 transitions. [2022-07-22 02:42:52,791 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 72052 [2022-07-22 02:42:52,792 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:42:52,792 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:42:52,793 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:52,794 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:52,794 INFO L752 eck$LassoCheckResult]: Stem: 273749#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 273750#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 274631#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 274632#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 273239#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 273240#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 274645#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 274600#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 274601#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 273595#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 273596#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 274026#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 274553#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 273506#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 273507#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 273388#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 273389#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 274438#L1109 assume !(0 == ~M_E~0); 274479#L1109-2 assume !(0 == ~T1_E~0); 273395#L1114-1 assume !(0 == ~T2_E~0); 273396#L1119-1 assume !(0 == ~T3_E~0); 274558#L1124-1 assume !(0 == ~T4_E~0); 273060#L1129-1 assume !(0 == ~T5_E~0); 273061#L1134-1 assume !(0 == ~T6_E~0); 273680#L1139-1 assume !(0 == ~T7_E~0); 274453#L1144-1 assume !(0 == ~T8_E~0); 274290#L1149-1 assume !(0 == ~T9_E~0); 273162#L1154-1 assume !(0 == ~T10_E~0); 273163#L1159-1 assume !(0 == ~T11_E~0); 274276#L1164-1 assume !(0 == ~E_M~0); 273561#L1169-1 assume !(0 == ~E_1~0); 273447#L1174-1 assume !(0 == ~E_2~0); 273317#L1179-1 assume !(0 == ~E_3~0); 273243#L1184-1 assume !(0 == ~E_4~0); 273244#L1189-1 assume !(0 == ~E_5~0); 273276#L1194-1 assume !(0 == ~E_6~0); 273363#L1199-1 assume !(0 == ~E_7~0); 274299#L1204-1 assume !(0 == ~E_8~0); 274225#L1209-1 assume !(0 == ~E_9~0); 274226#L1214-1 assume !(0 == ~E_10~0); 274662#L1219-1 assume !(0 == ~E_11~0); 274799#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 273579#L544 assume !(1 == ~m_pc~0); 273580#L544-2 is_master_triggered_~__retres1~0#1 := 0; 274540#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 274306#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 273205#L1379 assume !(0 != activate_threads_~tmp~1#1); 273206#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 274007#L563 assume !(1 == ~t1_pc~0); 273791#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 273068#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 273069#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 274152#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 273064#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 273065#L582 assume !(1 == ~t2_pc~0); 273769#L582-2 is_transmit2_triggered_~__retres1~2#1 := 0; 274162#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 274163#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 274289#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 273094#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 273095#L601 assume !(1 == ~t3_pc~0); 273785#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 273784#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 274541#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 274203#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 274204#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 274138#L620 assume !(1 == ~t4_pc~0); 274139#L620-2 is_transmit4_triggered_~__retres1~4#1 := 0; 273699#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 273642#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 273643#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 274021#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 274250#L639 assume 1 == ~t5_pc~0; 274103#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 273367#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 273368#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 274044#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 274045#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 273967#L658 assume !(1 == ~t6_pc~0); 273575#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 273576#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 274194#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 274634#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 274210#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 273408#L677 assume 1 == ~t7_pc~0; 273409#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 273310#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 274403#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 274586#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 274587#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 274693#L696 assume !(1 == ~t8_pc~0); 273634#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 273635#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 274644#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 274676#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 274757#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 274084#L715 assume 1 == ~t9_pc~0; 274085#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 273729#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 273631#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 273632#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 274066#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 274400#L734 assume !(1 == ~t10_pc~0); 274401#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 273533#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 273534#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 273552#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 274323#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 273608#L753 assume 1 == ~t11_pc~0; 273609#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 274216#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 273724#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 273725#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 273882#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 273941#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 273942#L1237-2 assume !(1 == ~T1_E~0); 274736#L1242-1 assume !(1 == ~T2_E~0); 274785#L1247-1 assume !(1 == ~T3_E~0); 279069#L1252-1 assume !(1 == ~T4_E~0); 279067#L1257-1 assume !(1 == ~T5_E~0); 279065#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 279062#L1267-1 assume !(1 == ~T7_E~0); 279060#L1272-1 assume !(1 == ~T8_E~0); 279058#L1277-1 assume !(1 == ~T9_E~0); 279056#L1282-1 assume !(1 == ~T10_E~0); 279055#L1287-1 assume !(1 == ~T11_E~0); 279054#L1292-1 assume !(1 == ~E_M~0); 279053#L1297-1 assume !(1 == ~E_1~0); 278162#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 278149#L1307-1 assume !(1 == ~E_3~0); 278147#L1312-1 assume !(1 == ~E_4~0); 278145#L1317-1 assume !(1 == ~E_5~0); 278143#L1322-1 assume !(1 == ~E_6~0); 276694#L1327-1 assume !(1 == ~E_7~0); 278140#L1332-1 assume !(1 == ~E_8~0); 278139#L1337-1 assume !(1 == ~E_9~0); 278138#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 278137#L1347-1 assume !(1 == ~E_11~0); 278133#L1352-1 assume { :end_inline_reset_delta_events } true; 278130#L1678-2 [2022-07-22 02:42:52,794 INFO L754 eck$LassoCheckResult]: Loop: 278130#L1678-2 assume !false; 278125#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 278121#L1084 assume !false; 278119#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 277750#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 277745#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 277743#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 277740#L925 assume !(0 != eval_~tmp~0#1); 277741#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 283957#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 283955#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 283953#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 283951#L1114-3 assume !(0 == ~T2_E~0); 283950#L1119-3 assume !(0 == ~T3_E~0); 283949#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 283947#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 283945#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 283943#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 283941#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 283939#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 283937#L1154-3 assume !(0 == ~T10_E~0); 283935#L1159-3 assume !(0 == ~T11_E~0); 283933#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 283931#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 283929#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 283927#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 283925#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 283923#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 283921#L1194-3 assume !(0 == ~E_6~0); 283919#L1199-3 assume !(0 == ~E_7~0); 283917#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 283915#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 283913#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 283911#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 283909#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 283907#L544-39 assume !(1 == ~m_pc~0); 283905#L544-41 is_master_triggered_~__retres1~0#1 := 0; 283903#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 283901#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 281805#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 281803#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 281801#L563-39 assume 1 == ~t1_pc~0; 281798#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 281796#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 281794#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 281793#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 281792#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 281788#L582-39 assume !(1 == ~t2_pc~0); 278693#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 281785#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 281784#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 281783#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 281782#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 281779#L601-39 assume 1 == ~t3_pc~0; 281773#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 281768#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 281763#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 281759#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 281754#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 281749#L620-39 assume !(1 == ~t4_pc~0); 281744#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 281743#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 281742#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 281741#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 281740#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 281739#L639-39 assume 1 == ~t5_pc~0; 281737#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 281736#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 281735#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 281734#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 281733#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 281732#L658-39 assume !(1 == ~t6_pc~0); 281730#L658-41 is_transmit6_triggered_~__retres1~6#1 := 0; 281729#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 280989#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 280976#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 280974#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 280972#L677-39 assume 1 == ~t7_pc~0; 280969#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 280967#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 280965#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 280963#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 280961#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 280960#L696-39 assume 1 == ~t8_pc~0; 280958#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 280957#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 280956#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 280955#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 280954#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 280953#L715-39 assume 1 == ~t9_pc~0; 280951#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 280950#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 280949#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 280947#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 280945#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 280943#L734-39 assume 1 == ~t10_pc~0; 275076#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 275072#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 275069#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 275067#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 275065#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 275061#L753-39 assume !(1 == ~t11_pc~0); 275062#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 280687#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 280685#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 280683#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 280681#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 280679#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 275044#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 280371#L1242-3 assume !(1 == ~T2_E~0); 280368#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 280366#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 280364#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 280362#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 280360#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 280358#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 280356#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 280353#L1282-3 assume !(1 == ~T10_E~0); 280352#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 280351#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 280350#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 280349#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 280348#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 280347#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 280346#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 279111#L1322-3 assume !(1 == ~E_6~0); 279109#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 279107#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 279105#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 279102#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 279100#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 279098#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 279042#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 279038#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 279037#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 279034#L1697 assume !(0 == start_simulation_~tmp~3#1); 279031#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 278158#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 278148#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 278146#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 278144#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 278142#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 278141#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 278132#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 278130#L1678-2 [2022-07-22 02:42:52,795 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:52,795 INFO L85 PathProgramCache]: Analyzing trace with hash -343701065, now seen corresponding path program 1 times [2022-07-22 02:42:52,795 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:52,795 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [82278706] [2022-07-22 02:42:52,795 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:52,795 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:52,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:52,817 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:52,817 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:52,817 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [82278706] [2022-07-22 02:42:52,817 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [82278706] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:52,817 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:52,817 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-22 02:42:52,818 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [726903946] [2022-07-22 02:42:52,818 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:52,818 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:42:52,818 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:52,819 INFO L85 PathProgramCache]: Analyzing trace with hash -193786681, now seen corresponding path program 1 times [2022-07-22 02:42:52,819 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:52,819 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [410393747] [2022-07-22 02:42:52,819 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:52,819 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:52,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:52,842 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:52,842 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:52,842 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [410393747] [2022-07-22 02:42:52,842 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [410393747] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:52,843 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:52,843 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-22 02:42:52,843 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1667496301] [2022-07-22 02:42:52,843 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:52,843 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:42:52,843 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:42:52,844 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:42:52,844 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:42:52,844 INFO L87 Difference]: Start difference. First operand 72388 states and 104597 transitions. cyclomatic complexity: 32241 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:53,659 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:42:53,660 INFO L93 Difference]: Finished difference Result 141087 states and 202862 transitions. [2022-07-22 02:42:53,660 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:42:53,661 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 141087 states and 202862 transitions. [2022-07-22 02:42:54,190 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 140528 [2022-07-22 02:42:54,718 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 141087 states to 141087 states and 202862 transitions. [2022-07-22 02:42:54,718 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 141087 [2022-07-22 02:42:54,797 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 141087 [2022-07-22 02:42:54,797 INFO L73 IsDeterministic]: Start isDeterministic. Operand 141087 states and 202862 transitions. [2022-07-22 02:42:54,865 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:42:54,865 INFO L369 hiAutomatonCegarLoop]: Abstraction has 141087 states and 202862 transitions. [2022-07-22 02:42:54,954 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 141087 states and 202862 transitions. [2022-07-22 02:42:56,508 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 141087 to 140959. [2022-07-22 02:42:56,642 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 140959 states, 140959 states have (on average 1.438248001191836) internal successors, (202734), 140958 states have internal predecessors, (202734), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:57,004 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 140959 states to 140959 states and 202734 transitions. [2022-07-22 02:42:57,004 INFO L392 hiAutomatonCegarLoop]: Abstraction has 140959 states and 202734 transitions. [2022-07-22 02:42:57,004 INFO L374 stractBuchiCegarLoop]: Abstraction has 140959 states and 202734 transitions. [2022-07-22 02:42:57,004 INFO L287 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-07-22 02:42:57,004 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 140959 states and 202734 transitions. [2022-07-22 02:42:57,361 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 140400 [2022-07-22 02:42:57,361 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:42:57,361 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:42:57,364 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:57,364 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:42:57,364 INFO L752 eck$LassoCheckResult]: Stem: 487237#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 487238#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 488062#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 488063#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 486726#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 486727#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 488075#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 488031#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 488032#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 487080#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 487081#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 487510#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 487995#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 486991#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 486992#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 486873#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 486874#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 487903#L1109 assume !(0 == ~M_E~0); 487932#L1109-2 assume !(0 == ~T1_E~0); 486880#L1114-1 assume !(0 == ~T2_E~0); 486881#L1119-1 assume !(0 == ~T3_E~0); 487999#L1124-1 assume !(0 == ~T4_E~0); 486542#L1129-1 assume !(0 == ~T5_E~0); 486543#L1134-1 assume !(0 == ~T6_E~0); 487168#L1139-1 assume !(0 == ~T7_E~0); 487911#L1144-1 assume !(0 == ~T8_E~0); 487756#L1149-1 assume !(0 == ~T9_E~0); 486646#L1154-1 assume !(0 == ~T10_E~0); 486647#L1159-1 assume !(0 == ~T11_E~0); 487741#L1164-1 assume !(0 == ~E_M~0); 487045#L1169-1 assume !(0 == ~E_1~0); 486931#L1174-1 assume !(0 == ~E_2~0); 486803#L1179-1 assume !(0 == ~E_3~0); 486730#L1184-1 assume !(0 == ~E_4~0); 486731#L1189-1 assume !(0 == ~E_5~0); 486762#L1194-1 assume !(0 == ~E_6~0); 486848#L1199-1 assume !(0 == ~E_7~0); 487764#L1204-1 assume !(0 == ~E_8~0); 487692#L1209-1 assume !(0 == ~E_9~0); 487693#L1214-1 assume !(0 == ~E_10~0); 488090#L1219-1 assume !(0 == ~E_11~0); 488202#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 487064#L544 assume !(1 == ~m_pc~0); 487065#L544-2 is_master_triggered_~__retres1~0#1 := 0; 487984#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 487775#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 486690#L1379 assume !(0 != activate_threads_~tmp~1#1); 486691#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 487494#L563 assume !(1 == ~t1_pc~0); 487279#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 486552#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 486553#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 487626#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 486548#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 486549#L582 assume !(1 == ~t2_pc~0); 487257#L582-2 is_transmit2_triggered_~__retres1~2#1 := 0; 487636#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 487637#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 487755#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 486578#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 486579#L601 assume !(1 == ~t3_pc~0); 487273#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 487272#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 487985#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 487674#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 487675#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 487615#L620 assume !(1 == ~t4_pc~0); 487616#L620-2 is_transmit4_triggered_~__retres1~4#1 := 0; 487186#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 487131#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 487132#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 487507#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 487710#L639 assume !(1 == ~t5_pc~0); 487711#L639-2 is_transmit5_triggered_~__retres1~5#1 := 0; 486852#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 486853#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 487529#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 487530#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 487453#L658 assume !(1 == ~t6_pc~0); 487061#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 487062#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 487664#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 488064#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 487681#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 486893#L677 assume 1 == ~t7_pc~0; 486894#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 486796#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 487871#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 488022#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 488023#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 488117#L696 assume !(1 == ~t8_pc~0); 487120#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 487121#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 488074#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 488100#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 488168#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 487567#L715 assume 1 == ~t9_pc~0; 487568#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 487217#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 487118#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 487119#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 487550#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 487867#L734 assume !(1 == ~t10_pc~0); 487868#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 487017#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 487018#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 487036#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 487793#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 487095#L753 assume 1 == ~t11_pc~0; 487096#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 487686#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 487211#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 487212#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 487366#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 487425#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 487426#L1237-2 assume !(1 == ~T1_E~0); 488155#L1242-1 assume !(1 == ~T2_E~0); 487182#L1247-1 assume !(1 == ~T3_E~0); 487183#L1252-1 assume !(1 == ~T4_E~0); 486954#L1257-1 assume !(1 == ~T5_E~0); 486955#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 487886#L1267-1 assume !(1 == ~T7_E~0); 488013#L1272-1 assume !(1 == ~T8_E~0); 487266#L1277-1 assume !(1 == ~T9_E~0); 487267#L1282-1 assume !(1 == ~T10_E~0); 487724#L1287-1 assume !(1 == ~T11_E~0); 487725#L1292-1 assume !(1 == ~E_M~0); 487680#L1297-1 assume !(1 == ~E_1~0); 487089#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 487090#L1307-1 assume !(1 == ~E_3~0); 488003#L1312-1 assume !(1 == ~E_4~0); 487310#L1317-1 assume !(1 == ~E_5~0); 487311#L1322-1 assume !(1 == ~E_6~0); 487032#L1327-1 assume !(1 == ~E_7~0); 487033#L1332-1 assume !(1 == ~E_8~0); 487625#L1337-1 assume !(1 == ~E_9~0); 487556#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 487557#L1347-1 assume !(1 == ~E_11~0); 488001#L1352-1 assume { :end_inline_reset_delta_events } true; 488002#L1678-2 [2022-07-22 02:42:57,365 INFO L754 eck$LassoCheckResult]: Loop: 488002#L1678-2 assume !false; 519843#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 519840#L1084 assume !false; 519839#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 519823#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 519819#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 519817#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 519814#L925 assume !(0 != eval_~tmp~0#1); 519815#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 521126#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 521124#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 521122#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 521120#L1114-3 assume !(0 == ~T2_E~0); 521118#L1119-3 assume !(0 == ~T3_E~0); 521116#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 521114#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 521111#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 521108#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 521105#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 521102#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 521099#L1154-3 assume !(0 == ~T10_E~0); 521096#L1159-3 assume !(0 == ~T11_E~0); 521093#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 521089#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 521086#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 521083#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 521079#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 521076#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 521067#L1194-3 assume !(0 == ~E_6~0); 521065#L1199-3 assume !(0 == ~E_7~0); 521062#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 521058#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 521053#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 521049#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 521045#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 521040#L544-39 assume !(1 == ~m_pc~0); 521036#L544-41 is_master_triggered_~__retres1~0#1 := 0; 521032#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 521026#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 521022#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 521018#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 521014#L563-39 assume !(1 == ~t1_pc~0); 521010#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 521005#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 521001#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 520997#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 520993#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 520989#L582-39 assume !(1 == ~t2_pc~0); 511526#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 520982#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 520976#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 520972#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 520967#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 520961#L601-39 assume !(1 == ~t3_pc~0); 520956#L601-41 is_transmit3_triggered_~__retres1~3#1 := 0; 520950#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 520944#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 520939#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 520934#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 520927#L620-39 assume !(1 == ~t4_pc~0); 520921#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 520913#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 520821#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 520818#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 520816#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 520814#L639-39 assume !(1 == ~t5_pc~0); 520812#L639-41 is_transmit5_triggered_~__retres1~5#1 := 0; 520810#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 520808#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 520805#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 520803#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 520801#L658-39 assume 1 == ~t6_pc~0; 520799#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 520796#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 520794#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 520791#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 520789#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 520787#L677-39 assume !(1 == ~t7_pc~0); 520785#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 520782#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 520780#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 520779#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 520778#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 520777#L696-39 assume !(1 == ~t8_pc~0); 520683#L696-41 is_transmit8_triggered_~__retres1~8#1 := 0; 520673#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 520654#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 520653#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 520652#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 520651#L715-39 assume !(1 == ~t9_pc~0); 520650#L715-41 is_transmit9_triggered_~__retres1~9#1 := 0; 520648#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 520647#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 520646#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 520645#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 520644#L734-39 assume !(1 == ~t10_pc~0); 520643#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 520641#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 520640#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 520639#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 520638#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 520637#L753-39 assume 1 == ~t11_pc~0; 520636#L754-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 520633#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 520631#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 520629#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 520627#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 520625#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 500683#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 520621#L1242-3 assume !(1 == ~T2_E~0); 516551#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 520618#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 520616#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 520614#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 520612#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 520610#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 520608#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 520606#L1282-3 assume !(1 == ~T10_E~0); 501563#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 520603#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 520601#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 520599#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 520597#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 520595#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 520593#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 520591#L1322-3 assume !(1 == ~E_6~0); 511714#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 520587#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 520585#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 520583#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 520581#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 520579#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 520444#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 520440#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 520430#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 487712#L1697 assume !(0 == start_simulation_~tmp~3#1); 487713#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 519897#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 519887#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 519885#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 519883#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 519880#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 519878#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 519876#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 488002#L1678-2 [2022-07-22 02:42:57,365 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:57,365 INFO L85 PathProgramCache]: Analyzing trace with hash 1793793208, now seen corresponding path program 1 times [2022-07-22 02:42:57,365 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:57,365 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1618213260] [2022-07-22 02:42:57,365 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:57,365 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:57,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:57,392 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:57,392 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:57,392 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1618213260] [2022-07-22 02:42:57,392 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1618213260] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:57,392 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:57,392 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-22 02:42:57,392 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [576706019] [2022-07-22 02:42:57,392 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:57,393 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:42:57,394 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:42:57,394 INFO L85 PathProgramCache]: Analyzing trace with hash -480698100, now seen corresponding path program 1 times [2022-07-22 02:42:57,394 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:42:57,394 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [824743517] [2022-07-22 02:42:57,394 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:42:57,394 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:42:57,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:42:57,415 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:42:57,415 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:42:57,415 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [824743517] [2022-07-22 02:42:57,416 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [824743517] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:42:57,417 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:42:57,417 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:42:57,417 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1098435830] [2022-07-22 02:42:57,417 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:42:57,417 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:42:57,418 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:42:57,418 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-07-22 02:42:57,418 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-07-22 02:42:57,418 INFO L87 Difference]: Start difference. First operand 140959 states and 202734 transitions. cyclomatic complexity: 61839 Second operand has 5 states, 5 states have (on average 27.8) internal successors, (139), 5 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:42:58,804 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:42:58,804 INFO L93 Difference]: Finished difference Result 354324 states and 511515 transitions. [2022-07-22 02:42:58,804 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-07-22 02:42:58,804 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 354324 states and 511515 transitions. [2022-07-22 02:43:00,796 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 352816 [2022-07-22 02:43:01,694 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 354324 states to 354324 states and 511515 transitions. [2022-07-22 02:43:01,695 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 354324 [2022-07-22 02:43:01,887 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 354324 [2022-07-22 02:43:01,887 INFO L73 IsDeterministic]: Start isDeterministic. Operand 354324 states and 511515 transitions. [2022-07-22 02:43:02,075 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:43:02,075 INFO L369 hiAutomatonCegarLoop]: Abstraction has 354324 states and 511515 transitions. [2022-07-22 02:43:02,577 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 354324 states and 511515 transitions. [2022-07-22 02:43:04,603 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 354324 to 145138. [2022-07-22 02:43:04,737 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 145138 states, 145138 states have (on average 1.4256294009838912) internal successors, (206913), 145137 states have internal predecessors, (206913), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:05,026 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 145138 states to 145138 states and 206913 transitions. [2022-07-22 02:43:05,026 INFO L392 hiAutomatonCegarLoop]: Abstraction has 145138 states and 206913 transitions. [2022-07-22 02:43:05,026 INFO L374 stractBuchiCegarLoop]: Abstraction has 145138 states and 206913 transitions. [2022-07-22 02:43:05,026 INFO L287 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-07-22 02:43:05,026 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 145138 states and 206913 transitions. [2022-07-22 02:43:05,410 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 144576 [2022-07-22 02:43:05,411 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:43:05,411 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:43:05,412 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:05,412 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:05,413 INFO L752 eck$LassoCheckResult]: Stem: 982526#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 982527#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 983340#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 983341#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 982022#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 982023#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 983356#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 983310#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 983311#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 982374#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 982375#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 982791#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 983268#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 982286#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 982287#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 982168#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 982169#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 983172#L1109 assume !(0 == ~M_E~0); 983206#L1109-2 assume !(0 == ~T1_E~0); 982175#L1114-1 assume !(0 == ~T2_E~0); 982176#L1119-1 assume !(0 == ~T3_E~0); 983272#L1124-1 assume !(0 == ~T4_E~0); 981838#L1129-1 assume !(0 == ~T5_E~0); 981839#L1134-1 assume !(0 == ~T6_E~0); 982456#L1139-1 assume !(0 == ~T7_E~0); 983185#L1144-1 assume !(0 == ~T8_E~0); 983037#L1149-1 assume !(0 == ~T9_E~0); 981943#L1154-1 assume !(0 == ~T10_E~0); 981944#L1159-1 assume !(0 == ~T11_E~0); 983022#L1164-1 assume !(0 == ~E_M~0); 982340#L1169-1 assume !(0 == ~E_1~0); 982226#L1174-1 assume !(0 == ~E_2~0); 982099#L1179-1 assume !(0 == ~E_3~0); 982026#L1184-1 assume !(0 == ~E_4~0); 982027#L1189-1 assume !(0 == ~E_5~0); 982058#L1194-1 assume !(0 == ~E_6~0); 982144#L1199-1 assume !(0 == ~E_7~0); 983045#L1204-1 assume !(0 == ~E_8~0); 982975#L1209-1 assume !(0 == ~E_9~0); 982976#L1214-1 assume !(0 == ~E_10~0); 983372#L1219-1 assume !(0 == ~E_11~0); 983491#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 982358#L544 assume !(1 == ~m_pc~0); 982359#L544-2 is_master_triggered_~__retres1~0#1 := 0; 983258#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 983052#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 981987#L1379 assume !(0 != activate_threads_~tmp~1#1); 981988#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 982774#L563 assume !(1 == ~t1_pc~0); 982567#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 981848#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 981849#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 982908#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 981844#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 981845#L582 assume !(1 == ~t2_pc~0); 982546#L582-2 is_transmit2_triggered_~__retres1~2#1 := 0; 982918#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 982919#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 983036#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 981875#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 981876#L601 assume !(1 == ~t3_pc~0); 982561#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 982560#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 983259#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 982957#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 982958#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 982897#L620 assume !(1 == ~t4_pc~0); 982898#L620-2 is_transmit4_triggered_~__retres1~4#1 := 0; 982476#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 982420#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 982421#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 982788#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 982994#L639 assume !(1 == ~t5_pc~0); 982995#L639-2 is_transmit5_triggered_~__retres1~5#1 := 0; 982148#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 982149#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 982809#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 982810#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 982731#L658 assume !(1 == ~t6_pc~0); 982355#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 982356#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 982948#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 983492#L1427 assume !(0 != activate_threads_~tmp___5~0#1); 982964#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 982188#L677 assume 1 == ~t7_pc~0; 982189#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 982092#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 983143#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 983300#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 983301#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 983394#L696 assume !(1 == ~t8_pc~0); 982410#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 982411#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 983355#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 983381#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 983452#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 982848#L715 assume 1 == ~t9_pc~0; 982849#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 982506#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 982408#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 982409#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 982831#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 983139#L734 assume !(1 == ~t10_pc~0); 983140#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 982312#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 982313#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 982331#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 983070#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 982387#L753 assume 1 == ~t11_pc~0; 982388#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 982969#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 982501#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 982502#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 982651#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 982707#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 982708#L1237-2 assume !(1 == ~T1_E~0); 983437#L1242-1 assume !(1 == ~T2_E~0); 982472#L1247-1 assume !(1 == ~T3_E~0); 982473#L1252-1 assume !(1 == ~T4_E~0); 982249#L1257-1 assume !(1 == ~T5_E~0); 982250#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 983155#L1267-1 assume !(1 == ~T7_E~0); 983290#L1272-1 assume !(1 == ~T8_E~0); 982554#L1277-1 assume !(1 == ~T9_E~0); 982555#L1282-1 assume !(1 == ~T10_E~0); 983006#L1287-1 assume !(1 == ~T11_E~0); 983007#L1292-1 assume !(1 == ~E_M~0); 982963#L1297-1 assume !(1 == ~E_1~0); 982382#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 982383#L1307-1 assume !(1 == ~E_3~0); 983276#L1312-1 assume !(1 == ~E_4~0); 982598#L1317-1 assume !(1 == ~E_5~0); 982599#L1322-1 assume !(1 == ~E_6~0); 982843#L1327-1 assume !(1 == ~E_7~0); 1088426#L1332-1 assume !(1 == ~E_8~0); 1088424#L1337-1 assume !(1 == ~E_9~0); 1088422#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 1088420#L1347-1 assume !(1 == ~E_11~0); 1088419#L1352-1 assume { :end_inline_reset_delta_events } true; 1088413#L1678-2 [2022-07-22 02:43:05,413 INFO L754 eck$LassoCheckResult]: Loop: 1088413#L1678-2 assume !false; 1086924#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1086920#L1084 assume !false; 1086917#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1086901#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1085726#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1085561#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1085555#L925 assume !(0 != eval_~tmp~0#1); 1085556#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1088826#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1088824#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1088822#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1088819#L1114-3 assume !(0 == ~T2_E~0); 1088817#L1119-3 assume !(0 == ~T3_E~0); 1088815#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1088813#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1088811#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1088810#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1088806#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1088804#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1088802#L1154-3 assume !(0 == ~T10_E~0); 1088797#L1159-3 assume !(0 == ~T11_E~0); 1088796#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1088795#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1088794#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1088793#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1088792#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1088791#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1088790#L1194-3 assume !(0 == ~E_6~0); 1088789#L1199-3 assume !(0 == ~E_7~0); 1088788#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1088787#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1088786#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1088785#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1088784#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1088783#L544-39 assume !(1 == ~m_pc~0); 1088782#L544-41 is_master_triggered_~__retres1~0#1 := 0; 1088781#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1088780#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1088779#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 1088778#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1088777#L563-39 assume 1 == ~t1_pc~0; 1088775#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1088774#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1088773#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1088772#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1088771#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1088770#L582-39 assume !(1 == ~t2_pc~0); 1062321#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 1088769#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1088768#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1088767#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1088766#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1088765#L601-39 assume 1 == ~t3_pc~0; 1088763#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1088762#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1088761#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1088760#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1088759#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1088758#L620-39 assume !(1 == ~t4_pc~0); 1088757#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 1088756#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1088755#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1088754#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1088753#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1088752#L639-39 assume !(1 == ~t5_pc~0); 1088751#L639-41 is_transmit5_triggered_~__retres1~5#1 := 0; 1088750#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1088749#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1088748#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1088747#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1088746#L658-39 assume 1 == ~t6_pc~0; 1088744#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1088742#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1088740#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1088738#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1088736#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1088734#L677-39 assume 1 == ~t7_pc~0; 1088731#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1088729#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1088727#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1088724#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 1088722#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1088720#L696-39 assume 1 == ~t8_pc~0; 1088717#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1088715#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1088713#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1088710#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1088708#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1088706#L715-39 assume 1 == ~t9_pc~0; 1088656#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1088654#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1088652#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1088649#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1088647#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1088645#L734-39 assume 1 == ~t10_pc~0; 1088642#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1088640#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1088638#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1088635#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1088633#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1088631#L753-39 assume !(1 == ~t11_pc~0); 1088628#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 1088626#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1088624#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1088621#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1088619#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1088617#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 984179#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1088614#L1242-3 assume !(1 == ~T2_E~0); 1070003#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1088610#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1088608#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1088606#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1088604#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1088602#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1088600#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1088597#L1282-3 assume !(1 == ~T10_E~0); 983985#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1088594#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1088592#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1088590#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1088589#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1088585#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1088583#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1088581#L1322-3 assume !(1 == ~E_6~0); 1064981#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1088576#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1088575#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1088574#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1088573#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1088572#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1088562#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1088559#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1088558#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1088451#L1697 assume !(0 == start_simulation_~tmp~3#1); 1088449#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1088437#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1088428#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1088427#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 1088425#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1088423#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1088421#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 1088418#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 1088413#L1678-2 [2022-07-22 02:43:05,413 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:05,414 INFO L85 PathProgramCache]: Analyzing trace with hash -1240256838, now seen corresponding path program 1 times [2022-07-22 02:43:05,414 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:05,414 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [746282433] [2022-07-22 02:43:05,414 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:05,414 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:05,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:05,436 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:05,437 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:05,437 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [746282433] [2022-07-22 02:43:05,437 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [746282433] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:05,437 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:05,437 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:05,437 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [288539310] [2022-07-22 02:43:05,438 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:05,438 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:43:05,438 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:05,438 INFO L85 PathProgramCache]: Analyzing trace with hash 1032165383, now seen corresponding path program 1 times [2022-07-22 02:43:05,438 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:05,439 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1183718098] [2022-07-22 02:43:05,439 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:05,439 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:05,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:05,456 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:05,456 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:05,457 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1183718098] [2022-07-22 02:43:05,457 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1183718098] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:05,457 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:05,457 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:05,457 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1927047550] [2022-07-22 02:43:05,457 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:05,457 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:43:05,458 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:43:05,458 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-22 02:43:05,458 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-22 02:43:05,458 INFO L87 Difference]: Start difference. First operand 145138 states and 206913 transitions. cyclomatic complexity: 61839 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:07,056 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:43:07,057 INFO L93 Difference]: Finished difference Result 350285 states and 496218 transitions. [2022-07-22 02:43:07,057 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-22 02:43:07,058 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 350285 states and 496218 transitions. [2022-07-22 02:43:09,236 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 343420 [2022-07-22 02:43:10,676 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 350285 states to 350285 states and 496218 transitions. [2022-07-22 02:43:10,677 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 350285 [2022-07-22 02:43:10,816 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 350285 [2022-07-22 02:43:10,816 INFO L73 IsDeterministic]: Start isDeterministic. Operand 350285 states and 496218 transitions. [2022-07-22 02:43:10,954 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:43:10,954 INFO L369 hiAutomatonCegarLoop]: Abstraction has 350285 states and 496218 transitions. [2022-07-22 02:43:11,126 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 350285 states and 496218 transitions. [2022-07-22 02:43:13,826 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 350285 to 277249. [2022-07-22 02:43:14,105 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 277249 states, 277249 states have (on average 1.4206940331615263) internal successors, (393886), 277248 states have internal predecessors, (393886), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:14,866 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 277249 states to 277249 states and 393886 transitions. [2022-07-22 02:43:14,867 INFO L392 hiAutomatonCegarLoop]: Abstraction has 277249 states and 393886 transitions. [2022-07-22 02:43:14,867 INFO L374 stractBuchiCegarLoop]: Abstraction has 277249 states and 393886 transitions. [2022-07-22 02:43:14,867 INFO L287 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-07-22 02:43:14,867 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 277249 states and 393886 transitions. [2022-07-22 02:43:16,272 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 276368 [2022-07-22 02:43:16,272 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:43:16,272 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:43:16,282 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:16,282 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:16,283 INFO L752 eck$LassoCheckResult]: Stem: 1477959#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 1477960#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1478794#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1478795#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1477455#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 1477456#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1478808#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1478762#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1478763#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1477807#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1477808#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1478233#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1478721#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1477718#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1477719#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1477604#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1477605#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1478616#L1109 assume !(0 == ~M_E~0); 1478648#L1109-2 assume !(0 == ~T1_E~0); 1477611#L1114-1 assume !(0 == ~T2_E~0); 1477612#L1119-1 assume !(0 == ~T3_E~0); 1478725#L1124-1 assume !(0 == ~T4_E~0); 1477272#L1129-1 assume !(0 == ~T5_E~0); 1477273#L1134-1 assume !(0 == ~T6_E~0); 1477890#L1139-1 assume !(0 == ~T7_E~0); 1478624#L1144-1 assume !(0 == ~T8_E~0); 1478480#L1149-1 assume !(0 == ~T9_E~0); 1477376#L1154-1 assume !(0 == ~T10_E~0); 1477377#L1159-1 assume !(0 == ~T11_E~0); 1478466#L1164-1 assume !(0 == ~E_M~0); 1477772#L1169-1 assume !(0 == ~E_1~0); 1477658#L1174-1 assume !(0 == ~E_2~0); 1477533#L1179-1 assume !(0 == ~E_3~0); 1477459#L1184-1 assume !(0 == ~E_4~0); 1477460#L1189-1 assume !(0 == ~E_5~0); 1477491#L1194-1 assume !(0 == ~E_6~0); 1477579#L1199-1 assume !(0 == ~E_7~0); 1478488#L1204-1 assume !(0 == ~E_8~0); 1478417#L1209-1 assume !(0 == ~E_9~0); 1478418#L1214-1 assume !(0 == ~E_10~0); 1478824#L1219-1 assume !(0 == ~E_11~0); 1478955#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1477789#L544 assume !(1 == ~m_pc~0); 1477790#L544-2 is_master_triggered_~__retres1~0#1 := 0; 1478711#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1478497#L556 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1477419#L1379 assume !(0 != activate_threads_~tmp~1#1); 1477420#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1478216#L563 assume !(1 == ~t1_pc~0); 1478003#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1477282#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1477283#L575 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1478353#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 1477278#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1477279#L582 assume !(1 == ~t2_pc~0); 1477979#L582-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1478363#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1478364#L594 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1478479#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 1477308#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1477309#L601 assume !(1 == ~t3_pc~0); 1477997#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1477996#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1478712#L613 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1478398#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 1478399#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1478337#L620 assume !(1 == ~t4_pc~0); 1478338#L620-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1477909#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1477854#L632 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1477855#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 1478230#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1478437#L639 assume !(1 == ~t5_pc~0); 1478438#L639-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1477583#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1477584#L651 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1478251#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 1478252#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1478177#L658 assume !(1 == ~t6_pc~0); 1477786#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1477787#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1478389#L670 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1478957#L1427 assume !(0 != activate_threads_~tmp___5~0#1); 1478404#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1477624#L677 assume !(1 == ~t7_pc~0); 1477525#L677-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1477526#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1478582#L689 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1478757#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 1478758#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1478850#L696 assume !(1 == ~t8_pc~0); 1477844#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1477845#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1478807#L708 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1478833#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 1478910#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1478290#L715 assume 1 == ~t9_pc~0; 1478291#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1477939#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1477842#L727 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1477843#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 1478275#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1478578#L734 assume !(1 == ~t10_pc~0); 1478579#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1477744#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1477745#L746 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1477763#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 1478516#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1477821#L753 assume 1 == ~t11_pc~0; 1477822#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1478410#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1477934#L765 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1477935#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 1478091#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1478148#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 1478149#L1237-2 assume !(1 == ~T1_E~0); 1478936#L1242-1 assume !(1 == ~T2_E~0); 1478937#L1247-1 assume !(1 == ~T3_E~0); 1478753#L1252-1 assume !(1 == ~T4_E~0); 1478754#L1257-1 assume !(1 == ~T5_E~0); 1478596#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1478597#L1267-1 assume !(1 == ~T7_E~0); 1478743#L1272-1 assume !(1 == ~T8_E~0); 1478744#L1277-1 assume !(1 == ~T9_E~0); 1478527#L1282-1 assume !(1 == ~T10_E~0); 1478528#L1287-1 assume !(1 == ~T11_E~0); 1478489#L1292-1 assume !(1 == ~E_M~0); 1478490#L1297-1 assume !(1 == ~E_1~0); 1477816#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1477817#L1307-1 assume !(1 == ~E_3~0); 1478914#L1312-1 assume !(1 == ~E_4~0); 1478915#L1317-1 assume !(1 == ~E_5~0); 1478285#L1322-1 assume !(1 == ~E_6~0); 1478286#L1327-1 assume !(1 == ~E_7~0); 1478351#L1332-1 assume !(1 == ~E_8~0); 1478352#L1337-1 assume !(1 == ~E_9~0); 1478280#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 1478281#L1347-1 assume !(1 == ~E_11~0); 1478727#L1352-1 assume { :end_inline_reset_delta_events } true; 1478728#L1678-2 [2022-07-22 02:43:16,284 INFO L754 eck$LassoCheckResult]: Loop: 1478728#L1678-2 assume !false; 1606202#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1606198#L1084 assume !false; 1606196#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1606121#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1606112#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1606105#L911 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1606087#L925 assume !(0 != eval_~tmp~0#1); 1606088#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1611417#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1611415#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1611413#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1611411#L1114-3 assume !(0 == ~T2_E~0); 1611409#L1119-3 assume !(0 == ~T3_E~0); 1611407#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1611404#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1611402#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1611400#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1611398#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1611396#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1611394#L1154-3 assume !(0 == ~T10_E~0); 1611392#L1159-3 assume !(0 == ~T11_E~0); 1611390#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1611388#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1611386#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1611384#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1611382#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1611380#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1611378#L1194-3 assume !(0 == ~E_6~0); 1611376#L1199-3 assume !(0 == ~E_7~0); 1611374#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1611371#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1611368#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1611364#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1611360#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1611356#L544-39 assume !(1 == ~m_pc~0); 1611352#L544-41 is_master_triggered_~__retres1~0#1 := 0; 1611349#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1611345#L556-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1611343#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 1611340#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1611337#L563-39 assume 1 == ~t1_pc~0; 1611333#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1611330#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1611326#L575-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1611322#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1611319#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1611316#L582-39 assume !(1 == ~t2_pc~0); 1608266#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 1611311#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1611307#L594-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1611303#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1611300#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1611297#L601-39 assume 1 == ~t3_pc~0; 1611293#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1611290#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1611287#L613-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1611283#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1611280#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1611277#L620-39 assume !(1 == ~t4_pc~0); 1611274#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 1611271#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1611267#L632-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1611263#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1611260#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1611257#L639-39 assume !(1 == ~t5_pc~0); 1611254#L639-41 is_transmit5_triggered_~__retres1~5#1 := 0; 1611251#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1611247#L651-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1611243#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1611239#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1611235#L658-39 assume 1 == ~t6_pc~0; 1611231#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1611227#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1611224#L670-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1611220#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1611217#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1611214#L677-39 assume !(1 == ~t7_pc~0); 1529995#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 1611209#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1611205#L689-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1611202#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 1611199#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1611196#L696-39 assume 1 == ~t8_pc~0; 1611192#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1611189#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1611184#L708-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1611180#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1611176#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1611172#L715-39 assume 1 == ~t9_pc~0; 1611167#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1611165#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1611162#L727-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1611158#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1611154#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1611150#L734-39 assume 1 == ~t10_pc~0; 1611144#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1611139#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1611134#L746-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1611130#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1611125#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1611118#L753-39 assume !(1 == ~t11_pc~0); 1611112#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 1611106#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1611101#L765-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1611095#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1611090#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1611083#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1571883#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1611073#L1242-3 assume !(1 == ~T2_E~0); 1573044#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1611064#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1611059#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1611052#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1611047#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1611041#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1611036#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1611031#L1282-3 assume !(1 == ~T10_E~0); 1583119#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1611022#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1610977#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1610972#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1610965#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1610959#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1610953#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1610947#L1322-3 assume !(1 == ~E_6~0); 1601670#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1610936#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1610930#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1610925#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1610920#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1610915#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1610840#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1610835#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1610833#L911-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1610768#L1697 assume !(0 == start_simulation_~tmp~3#1); 1610725#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1606231#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1606221#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1606219#L911-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 1606217#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1606215#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1606213#L1660 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 1606211#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 1478728#L1678-2 [2022-07-22 02:43:16,284 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:16,284 INFO L85 PathProgramCache]: Analyzing trace with hash 1946581819, now seen corresponding path program 1 times [2022-07-22 02:43:16,285 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:16,299 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1828513836] [2022-07-22 02:43:16,299 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:16,300 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:16,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:16,355 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:16,355 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:16,355 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1828513836] [2022-07-22 02:43:16,355 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1828513836] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:16,356 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:16,356 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:16,356 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [761784123] [2022-07-22 02:43:16,357 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:16,357 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:43:16,357 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:16,358 INFO L85 PathProgramCache]: Analyzing trace with hash -1125307640, now seen corresponding path program 1 times [2022-07-22 02:43:16,358 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:16,358 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [60839972] [2022-07-22 02:43:16,358 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:16,358 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:16,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:16,383 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:16,384 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:16,384 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [60839972] [2022-07-22 02:43:16,384 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [60839972] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:16,384 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:16,384 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:16,384 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [102586963] [2022-07-22 02:43:16,384 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:16,385 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:43:16,385 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:43:16,385 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-22 02:43:16,385 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-22 02:43:16,386 INFO L87 Difference]: Start difference. First operand 277249 states and 393886 transitions. cyclomatic complexity: 116701 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:19,137 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:43:19,137 INFO L93 Difference]: Finished difference Result 665168 states and 939227 transitions. [2022-07-22 02:43:19,138 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-22 02:43:19,142 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 665168 states and 939227 transitions. [2022-07-22 02:43:23,222 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 651744 [2022-07-22 02:43:25,439 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 665168 states to 665168 states and 939227 transitions. [2022-07-22 02:43:25,439 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 665168