./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.14.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 35987657 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.14.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 78a96934dff25285973ef889167a345947d7e73ab8a2ec405d96bd61e690530f --- Real Ultimate output --- This is Ultimate 0.2.2-?-3598765 [2022-07-22 02:42:58,596 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-07-22 02:42:58,599 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-07-22 02:42:58,631 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-07-22 02:42:58,632 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-07-22 02:42:58,633 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-07-22 02:42:58,636 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-07-22 02:42:58,638 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-07-22 02:42:58,640 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-07-22 02:42:58,643 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-07-22 02:42:58,644 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-07-22 02:42:58,646 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-07-22 02:42:58,646 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-07-22 02:42:58,648 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-07-22 02:42:58,648 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-07-22 02:42:58,653 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-07-22 02:42:58,653 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-07-22 02:42:58,654 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-07-22 02:42:58,656 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-07-22 02:42:58,660 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-07-22 02:42:58,661 INFO L181 SettingsManager]: Resetting HornVerifier preferences to default values [2022-07-22 02:42:58,662 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-07-22 02:42:58,663 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-07-22 02:42:58,664 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-07-22 02:42:58,665 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-07-22 02:42:58,669 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-07-22 02:42:58,669 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-07-22 02:42:58,669 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-07-22 02:42:58,670 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-07-22 02:42:58,670 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-07-22 02:42:58,671 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-07-22 02:42:58,671 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-07-22 02:42:58,673 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-07-22 02:42:58,673 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-07-22 02:42:58,674 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-07-22 02:42:58,675 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-07-22 02:42:58,675 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-07-22 02:42:58,675 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-07-22 02:42:58,675 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-07-22 02:42:58,676 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-07-22 02:42:58,676 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-07-22 02:42:58,677 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-07-22 02:42:58,684 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-07-22 02:42:58,708 INFO L113 SettingsManager]: Loading preferences was successful [2022-07-22 02:42:58,709 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-07-22 02:42:58,709 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-07-22 02:42:58,709 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-07-22 02:42:58,712 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-07-22 02:42:58,712 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-07-22 02:42:58,712 INFO L138 SettingsManager]: * Use SBE=true [2022-07-22 02:42:58,712 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-07-22 02:42:58,712 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-07-22 02:42:58,713 INFO L138 SettingsManager]: * Use old map elimination=false [2022-07-22 02:42:58,713 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-07-22 02:42:58,713 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-07-22 02:42:58,718 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-07-22 02:42:58,718 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-07-22 02:42:58,718 INFO L138 SettingsManager]: * sizeof long=4 [2022-07-22 02:42:58,719 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-07-22 02:42:58,719 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-07-22 02:42:58,719 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-07-22 02:42:58,719 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-07-22 02:42:58,719 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-07-22 02:42:58,719 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-07-22 02:42:58,720 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-07-22 02:42:58,720 INFO L138 SettingsManager]: * sizeof long double=12 [2022-07-22 02:42:58,720 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-07-22 02:42:58,720 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-07-22 02:42:58,720 INFO L138 SettingsManager]: * Use constant arrays=true [2022-07-22 02:42:58,720 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-07-22 02:42:58,720 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-07-22 02:42:58,721 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-07-22 02:42:58,721 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-07-22 02:42:58,721 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-07-22 02:42:58,723 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-07-22 02:42:58,723 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 78a96934dff25285973ef889167a345947d7e73ab8a2ec405d96bd61e690530f [2022-07-22 02:42:58,990 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-07-22 02:42:59,008 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-07-22 02:42:59,010 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-07-22 02:42:59,011 INFO L271 PluginConnector]: Initializing CDTParser... [2022-07-22 02:42:59,012 INFO L275 PluginConnector]: CDTParser initialized [2022-07-22 02:42:59,013 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.14.cil.c [2022-07-22 02:42:59,076 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/50580c54e/e6f6da7f7e994b59b29206724dd14566/FLAG466557d80 [2022-07-22 02:42:59,488 INFO L306 CDTParser]: Found 1 translation units. [2022-07-22 02:42:59,488 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.14.cil.c [2022-07-22 02:42:59,500 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/50580c54e/e6f6da7f7e994b59b29206724dd14566/FLAG466557d80 [2022-07-22 02:42:59,512 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/50580c54e/e6f6da7f7e994b59b29206724dd14566 [2022-07-22 02:42:59,514 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-07-22 02:42:59,515 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-07-22 02:42:59,517 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-07-22 02:42:59,517 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-07-22 02:42:59,520 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-07-22 02:42:59,520 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 22.07 02:42:59" (1/1) ... [2022-07-22 02:42:59,521 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@71c8218a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:42:59, skipping insertion in model container [2022-07-22 02:42:59,521 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 22.07 02:42:59" (1/1) ... [2022-07-22 02:42:59,526 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-07-22 02:42:59,569 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-07-22 02:42:59,686 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.14.cil.c[669,682] [2022-07-22 02:42:59,851 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-22 02:42:59,867 INFO L203 MainTranslator]: Completed pre-run [2022-07-22 02:42:59,878 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.14.cil.c[669,682] [2022-07-22 02:42:59,938 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-22 02:42:59,965 INFO L208 MainTranslator]: Completed translation [2022-07-22 02:42:59,974 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:42:59 WrapperNode [2022-07-22 02:42:59,975 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-07-22 02:42:59,976 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-07-22 02:42:59,976 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-07-22 02:42:59,976 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-07-22 02:42:59,983 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:42:59" (1/1) ... [2022-07-22 02:43:00,002 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:42:59" (1/1) ... [2022-07-22 02:43:00,118 INFO L137 Inliner]: procedures = 52, calls = 68, calls flagged for inlining = 63, calls inlined = 270, statements flattened = 4144 [2022-07-22 02:43:00,119 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-07-22 02:43:00,120 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-07-22 02:43:00,121 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-07-22 02:43:00,121 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-07-22 02:43:00,127 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:42:59" (1/1) ... [2022-07-22 02:43:00,127 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:42:59" (1/1) ... [2022-07-22 02:43:00,139 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:42:59" (1/1) ... [2022-07-22 02:43:00,141 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:42:59" (1/1) ... [2022-07-22 02:43:00,190 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:42:59" (1/1) ... [2022-07-22 02:43:00,224 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:42:59" (1/1) ... [2022-07-22 02:43:00,233 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:42:59" (1/1) ... [2022-07-22 02:43:00,246 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-07-22 02:43:00,247 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-07-22 02:43:00,247 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-07-22 02:43:00,248 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-07-22 02:43:00,249 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:42:59" (1/1) ... [2022-07-22 02:43:00,253 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-22 02:43:00,261 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-22 02:43:00,309 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-22 02:43:00,318 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-07-22 02:43:00,350 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-07-22 02:43:00,351 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-07-22 02:43:00,351 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-07-22 02:43:00,351 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-07-22 02:43:00,527 INFO L234 CfgBuilder]: Building ICFG [2022-07-22 02:43:00,529 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-07-22 02:43:02,141 INFO L275 CfgBuilder]: Performing block encoding [2022-07-22 02:43:02,153 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-07-22 02:43:02,153 INFO L299 CfgBuilder]: Removed 15 assume(true) statements. [2022-07-22 02:43:02,156 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.07 02:43:02 BoogieIcfgContainer [2022-07-22 02:43:02,156 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-07-22 02:43:02,157 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-07-22 02:43:02,157 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-07-22 02:43:02,160 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-07-22 02:43:02,160 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-22 02:43:02,160 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 22.07 02:42:59" (1/3) ... [2022-07-22 02:43:02,161 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@13d693d0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 22.07 02:43:02, skipping insertion in model container [2022-07-22 02:43:02,161 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-22 02:43:02,161 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:42:59" (2/3) ... [2022-07-22 02:43:02,162 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@13d693d0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 22.07 02:43:02, skipping insertion in model container [2022-07-22 02:43:02,162 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-22 02:43:02,162 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.07 02:43:02" (3/3) ... [2022-07-22 02:43:02,163 INFO L354 chiAutomizerObserver]: Analyzing ICFG token_ring.14.cil.c [2022-07-22 02:43:02,220 INFO L255 stractBuchiCegarLoop]: Interprodecural is true [2022-07-22 02:43:02,220 INFO L256 stractBuchiCegarLoop]: Hoare is false [2022-07-22 02:43:02,221 INFO L257 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-07-22 02:43:02,221 INFO L258 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-07-22 02:43:02,221 INFO L259 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-07-22 02:43:02,221 INFO L260 stractBuchiCegarLoop]: Difference is false [2022-07-22 02:43:02,221 INFO L261 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-07-22 02:43:02,221 INFO L265 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-07-22 02:43:02,228 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1796 states, 1795 states have (on average 1.4991643454038996) internal successors, (2691), 1795 states have internal predecessors, (2691), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:02,306 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1629 [2022-07-22 02:43:02,307 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:43:02,307 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:43:02,323 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:02,323 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:02,324 INFO L287 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-07-22 02:43:02,326 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1796 states, 1795 states have (on average 1.4991643454038996) internal successors, (2691), 1795 states have internal predecessors, (2691), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:02,338 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1629 [2022-07-22 02:43:02,338 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:43:02,338 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:43:02,342 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:02,342 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:02,348 INFO L752 eck$LassoCheckResult]: Stem: 424#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 1702#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 147#L1773true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 173#L841true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1362#L848true assume !(1 == ~m_i~0);~m_st~0 := 2; 1468#L848-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 430#L853-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 307#L858-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2#L863-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 748#L868-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 842#L873-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1598#L878-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1564#L883-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 1649#L888-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 383#L893-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 772#L898-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 1773#L903-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 695#L908-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 407#L1201true assume !(0 == ~M_E~0); 1176#L1201-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1595#L1206-1true assume !(0 == ~T2_E~0); 1155#L1211-1true assume !(0 == ~T3_E~0); 1302#L1216-1true assume !(0 == ~T4_E~0); 297#L1221-1true assume !(0 == ~T5_E~0); 1243#L1226-1true assume !(0 == ~T6_E~0); 104#L1231-1true assume !(0 == ~T7_E~0); 1387#L1236-1true assume !(0 == ~T8_E~0); 1224#L1241-1true assume 0 == ~T9_E~0;~T9_E~0 := 1; 320#L1246-1true assume !(0 == ~T10_E~0); 405#L1251-1true assume !(0 == ~T11_E~0); 875#L1256-1true assume !(0 == ~T12_E~0); 8#L1261-1true assume !(0 == ~E_M~0); 1567#L1266-1true assume !(0 == ~E_1~0); 1507#L1271-1true assume !(0 == ~E_2~0); 830#L1276-1true assume !(0 == ~E_3~0); 1502#L1281-1true assume 0 == ~E_4~0;~E_4~0 := 1; 785#L1286-1true assume !(0 == ~E_5~0); 237#L1291-1true assume !(0 == ~E_6~0); 1593#L1296-1true assume !(0 == ~E_7~0); 609#L1301-1true assume !(0 == ~E_8~0); 1098#L1306-1true assume !(0 == ~E_9~0); 1071#L1311-1true assume !(0 == ~E_10~0); 212#L1316-1true assume !(0 == ~E_11~0); 1456#L1321-1true assume 0 == ~E_12~0;~E_12~0 := 1; 622#L1326-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 738#L593true assume 1 == ~m_pc~0; 862#L594true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1467#L604true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1723#L605true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 793#L1492true assume !(0 != activate_threads_~tmp~1#1); 1226#L1492-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1124#L612true assume !(1 == ~t1_pc~0); 1657#L612-2true is_transmit1_triggered_~__retres1~1#1 := 0; 1533#L623true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 363#L624true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 153#L1500true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 436#L1500-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 389#L631true assume 1 == ~t2_pc~0; 350#L632true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46#L642true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 916#L643true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 524#L1508true assume !(0 != activate_threads_~tmp___1~0#1); 1306#L1508-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 191#L650true assume !(1 == ~t3_pc~0); 959#L650-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1216#L661true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 151#L662true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25#L1516true assume !(0 != activate_threads_~tmp___2~0#1); 969#L1516-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 766#L669true assume 1 == ~t4_pc~0; 1268#L670true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1781#L680true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 382#L681true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 121#L1524true assume !(0 != activate_threads_~tmp___3~0#1); 243#L1524-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 983#L688true assume !(1 == ~t5_pc~0); 129#L688-2true is_transmit5_triggered_~__retres1~5#1 := 0; 1466#L699true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 718#L700true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 663#L1532true assume !(0 != activate_threads_~tmp___4~0#1); 778#L1532-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1292#L707true assume 1 == ~t6_pc~0; 1338#L708true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 503#L718true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1288#L719true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1368#L1540true assume !(0 != activate_threads_~tmp___5~0#1); 725#L1540-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 406#L726true assume 1 == ~t7_pc~0; 342#L727true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 910#L737true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1577#L738true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1303#L1548true assume !(0 != activate_threads_~tmp___6~0#1); 62#L1548-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 294#L745true assume !(1 == ~t8_pc~0); 1108#L745-2true is_transmit8_triggered_~__retres1~8#1 := 0; 1190#L756true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 947#L757true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 552#L1556true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1024#L1556-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1786#L764true assume 1 == ~t9_pc~0; 403#L765true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 796#L775true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1556#L776true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1433#L1564true assume !(0 != activate_threads_~tmp___8~0#1); 71#L1564-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1389#L783true assume !(1 == ~t10_pc~0); 98#L783-2true is_transmit10_triggered_~__retres1~10#1 := 0; 193#L794true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 118#L795true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 376#L1572true assume !(0 != activate_threads_~tmp___9~0#1); 1167#L1572-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1272#L802true assume 1 == ~t11_pc~0; 1141#L803true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 44#L813true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 750#L814true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 298#L1580true assume !(0 != activate_threads_~tmp___10~0#1); 362#L1580-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 533#L821true assume !(1 == ~t12_pc~0); 601#L821-2true is_transmit12_triggered_~__retres1~12#1 := 0; 1328#L832true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 47#L833true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1242#L1588true assume !(0 != activate_threads_~tmp___11~0#1); 1249#L1588-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 803#L1339true assume !(1 == ~M_E~0); 1454#L1339-2true assume !(1 == ~T1_E~0); 1310#L1344-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1721#L1349-1true assume !(1 == ~T3_E~0); 618#L1354-1true assume !(1 == ~T4_E~0); 991#L1359-1true assume !(1 == ~T5_E~0); 1540#L1364-1true assume !(1 == ~T6_E~0); 267#L1369-1true assume !(1 == ~T7_E~0); 962#L1374-1true assume !(1 == ~T8_E~0); 620#L1379-1true assume !(1 == ~T9_E~0); 690#L1384-1true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1759#L1389-1true assume !(1 == ~T11_E~0); 1231#L1394-1true assume !(1 == ~T12_E~0); 1627#L1399-1true assume !(1 == ~E_M~0); 1436#L1404-1true assume !(1 == ~E_1~0); 322#L1409-1true assume !(1 == ~E_2~0); 1405#L1414-1true assume !(1 == ~E_3~0); 863#L1419-1true assume !(1 == ~E_4~0); 125#L1424-1true assume 1 == ~E_5~0;~E_5~0 := 2; 626#L1429-1true assume !(1 == ~E_6~0); 1263#L1434-1true assume !(1 == ~E_7~0); 1601#L1439-1true assume !(1 == ~E_8~0); 145#L1444-1true assume !(1 == ~E_9~0); 815#L1449-1true assume !(1 == ~E_10~0); 353#L1454-1true assume !(1 == ~E_11~0); 1301#L1459-1true assume !(1 == ~E_12~0); 723#L1464-1true assume { :end_inline_reset_delta_events } true; 489#L1810-2true [2022-07-22 02:43:02,350 INFO L754 eck$LassoCheckResult]: Loop: 489#L1810-2true assume !false; 1334#L1811true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1769#L1176true assume false; 157#L1191true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1413#L841-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1053#L1201-3true assume 0 == ~M_E~0;~M_E~0 := 1; 820#L1201-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1597#L1206-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 721#L1211-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 189#L1216-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 466#L1221-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 1022#L1226-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 229#L1231-3true assume !(0 == ~T7_E~0); 369#L1236-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1771#L1241-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1333#L1246-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1144#L1251-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 806#L1256-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 198#L1261-3true assume 0 == ~E_M~0;~E_M~0 := 1; 517#L1266-3true assume 0 == ~E_1~0;~E_1~0 := 1; 225#L1271-3true assume !(0 == ~E_2~0); 487#L1276-3true assume 0 == ~E_3~0;~E_3~0 := 1; 450#L1281-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1200#L1286-3true assume 0 == ~E_5~0;~E_5~0 := 1; 860#L1291-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1609#L1296-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1534#L1301-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1424#L1306-3true assume 0 == ~E_9~0;~E_9~0 := 1; 529#L1311-3true assume !(0 == ~E_10~0); 158#L1316-3true assume 0 == ~E_11~0;~E_11~0 := 1; 199#L1321-3true assume 0 == ~E_12~0;~E_12~0 := 1; 600#L1326-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1209#L593-42true assume !(1 == ~m_pc~0); 727#L593-44true is_master_triggered_~__retres1~0#1 := 0; 1756#L604-14true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1500#L605-14true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1719#L1492-42true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 107#L1492-44true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 680#L612-42true assume !(1 == ~t1_pc~0); 1093#L612-44true is_transmit1_triggered_~__retres1~1#1 := 0; 1581#L623-14true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1290#L624-14true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 152#L1500-42true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1753#L1500-44true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 576#L631-42true assume 1 == ~t2_pc~0; 40#L632-14true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 567#L642-14true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1747#L643-14true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 485#L1508-42true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1634#L1508-44true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 239#L650-42true assume 1 == ~t3_pc~0; 22#L651-14true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1715#L661-14true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1347#L662-14true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 349#L1516-42true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1374#L1516-44true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1267#L669-42true assume 1 == ~t4_pc~0; 536#L670-14true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 997#L680-14true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1495#L681-14true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 870#L1524-42true assume !(0 != activate_threads_~tmp___3~0#1); 777#L1524-44true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 859#L688-42true assume !(1 == ~t5_pc~0); 1100#L688-44true is_transmit5_triggered_~__retres1~5#1 := 0; 1350#L699-14true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 85#L700-14true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 120#L1532-42true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1430#L1532-44true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35#L707-42true assume !(1 == ~t6_pc~0); 1678#L707-44true is_transmit6_triggered_~__retres1~6#1 := 0; 1694#L718-14true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1003#L719-14true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1291#L1540-42true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 752#L1540-44true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1032#L726-42true assume !(1 == ~t7_pc~0); 1785#L726-44true is_transmit7_triggered_~__retres1~7#1 := 0; 1069#L737-14true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1599#L738-14true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 531#L1548-42true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 604#L1548-44true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1185#L745-42true assume !(1 == ~t8_pc~0); 818#L745-44true is_transmit8_triggered_~__retres1~8#1 := 0; 1428#L756-14true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 205#L757-14true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29#L1556-42true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 421#L1556-44true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 514#L764-42true assume 1 == ~t9_pc~0; 1658#L765-14true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 791#L775-14true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 995#L776-14true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 165#L1564-42true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 194#L1564-44true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 242#L783-42true assume !(1 == ~t10_pc~0); 1743#L783-44true is_transmit10_triggered_~__retres1~10#1 := 0; 314#L794-14true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 391#L795-14true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1536#L1572-42true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1516#L1572-44true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 958#L802-42true assume !(1 == ~t11_pc~0); 1074#L802-44true is_transmit11_triggered_~__retres1~11#1 := 0; 74#L813-14true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1187#L814-14true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 51#L1580-42true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1549#L1580-44true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 801#L821-42true assume !(1 == ~t12_pc~0); 336#L821-44true is_transmit12_triggered_~__retres1~12#1 := 0; 1006#L832-14true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 9#L833-14true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1158#L1588-42true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 559#L1588-44true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 551#L1339-3true assume !(1 == ~M_E~0); 665#L1339-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 807#L1344-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 765#L1349-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 341#L1354-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 774#L1359-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1606#L1364-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1498#L1369-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1262#L1374-3true assume !(1 == ~T8_E~0); 240#L1379-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1148#L1384-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 340#L1389-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 478#L1394-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1706#L1399-3true assume 1 == ~E_M~0;~E_M~0 := 2; 1278#L1404-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1223#L1409-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1332#L1414-3true assume !(1 == ~E_3~0); 1355#L1419-3true assume 1 == ~E_4~0;~E_4~0 := 2; 961#L1424-3true assume 1 == ~E_5~0;~E_5~0 := 2; 175#L1429-3true assume 1 == ~E_6~0;~E_6~0 := 2; 773#L1434-3true assume 1 == ~E_7~0;~E_7~0 := 2; 924#L1439-3true assume 1 == ~E_8~0;~E_8~0 := 2; 139#L1444-3true assume 1 == ~E_9~0;~E_9~0 := 2; 203#L1449-3true assume 1 == ~E_10~0;~E_10~0 := 2; 1423#L1454-3true assume !(1 == ~E_11~0); 769#L1459-3true assume 1 == ~E_12~0;~E_12~0 := 2; 1768#L1464-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 504#L921-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1726#L988-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 231#L989-1true start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1455#L1829true assume !(0 == start_simulation_~tmp~3#1); 87#L1829-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1039#L921-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 555#L988-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 930#L989-2true stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 786#L1784true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1542#L1791true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 492#L1792true start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 218#L1842true assume !(0 != start_simulation_~tmp___0~1#1); 489#L1810-2true [2022-07-22 02:43:02,366 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:02,366 INFO L85 PathProgramCache]: Analyzing trace with hash -1818030166, now seen corresponding path program 1 times [2022-07-22 02:43:02,372 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:02,372 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1987934984] [2022-07-22 02:43:02,372 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:02,373 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:02,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:02,507 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:02,507 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:02,508 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1987934984] [2022-07-22 02:43:02,508 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1987934984] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:02,508 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:02,508 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:02,509 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [187962614] [2022-07-22 02:43:02,511 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:02,514 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:43:02,514 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:02,514 INFO L85 PathProgramCache]: Analyzing trace with hash 1962033275, now seen corresponding path program 1 times [2022-07-22 02:43:02,514 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:02,515 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2009476545] [2022-07-22 02:43:02,515 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:02,515 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:02,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:02,545 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:02,546 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:02,546 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2009476545] [2022-07-22 02:43:02,546 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2009476545] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:02,546 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:02,546 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-22 02:43:02,546 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1008892935] [2022-07-22 02:43:02,547 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:02,548 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:43:02,548 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:43:02,566 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-07-22 02:43:02,567 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-07-22 02:43:02,571 INFO L87 Difference]: Start difference. First operand has 1796 states, 1795 states have (on average 1.4991643454038996) internal successors, (2691), 1795 states have internal predecessors, (2691), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 74.5) internal successors, (149), 2 states have internal predecessors, (149), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:02,620 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:43:02,620 INFO L93 Difference]: Finished difference Result 1794 states and 2657 transitions. [2022-07-22 02:43:02,621 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-07-22 02:43:02,624 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1794 states and 2657 transitions. [2022-07-22 02:43:02,637 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-07-22 02:43:02,647 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1794 states to 1788 states and 2651 transitions. [2022-07-22 02:43:02,648 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2022-07-22 02:43:02,649 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2022-07-22 02:43:02,650 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2651 transitions. [2022-07-22 02:43:02,654 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:43:02,654 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2651 transitions. [2022-07-22 02:43:02,667 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2651 transitions. [2022-07-22 02:43:02,703 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2022-07-22 02:43:02,706 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.482662192393736) internal successors, (2651), 1787 states have internal predecessors, (2651), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:02,711 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2651 transitions. [2022-07-22 02:43:02,712 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2651 transitions. [2022-07-22 02:43:02,712 INFO L374 stractBuchiCegarLoop]: Abstraction has 1788 states and 2651 transitions. [2022-07-22 02:43:02,712 INFO L287 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-07-22 02:43:02,712 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2651 transitions. [2022-07-22 02:43:02,719 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-07-22 02:43:02,719 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:43:02,719 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:43:02,721 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:02,721 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:02,722 INFO L752 eck$LassoCheckResult]: Stem: 4388#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 4389#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 3909#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3910#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3964#L848 assume !(1 == ~m_i~0);~m_st~0 := 2; 5303#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4397#L853-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4200#L858-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3599#L863-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3600#L868-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4822#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4933#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5369#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 5370#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4328#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4329#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4851#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 4770#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4363#L1201 assume !(0 == ~M_E~0); 4364#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5210#L1206-1 assume !(0 == ~T2_E~0); 5196#L1211-1 assume !(0 == ~T3_E~0); 5197#L1216-1 assume !(0 == ~T4_E~0); 4184#L1221-1 assume !(0 == ~T5_E~0); 4185#L1226-1 assume !(0 == ~T6_E~0); 3824#L1231-1 assume !(0 == ~T7_E~0); 3825#L1236-1 assume !(0 == ~T8_E~0); 5233#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4221#L1246-1 assume !(0 == ~T10_E~0); 4222#L1251-1 assume !(0 == ~T11_E~0); 4361#L1256-1 assume !(0 == ~T12_E~0); 3610#L1261-1 assume !(0 == ~E_M~0); 3611#L1266-1 assume !(0 == ~E_1~0); 5355#L1271-1 assume !(0 == ~E_2~0); 4917#L1276-1 assume !(0 == ~E_3~0); 4918#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 4865#L1286-1 assume !(0 == ~E_5~0); 4075#L1291-1 assume !(0 == ~E_6~0); 4076#L1296-1 assume !(0 == ~E_7~0); 4651#L1301-1 assume !(0 == ~E_8~0); 4652#L1306-1 assume !(0 == ~E_9~0); 5132#L1311-1 assume !(0 == ~E_10~0); 4026#L1316-1 assume !(0 == ~E_11~0); 4027#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 4669#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4670#L593 assume 1 == ~m_pc~0; 4814#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3916#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5342#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4876#L1492 assume !(0 != activate_threads_~tmp~1#1); 4877#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5168#L612 assume !(1 == ~t1_pc~0); 5169#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5298#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4298#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3920#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3921#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4340#L631 assume 1 == ~t2_pc~0; 4275#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3697#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3698#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4534#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 4535#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3993#L650 assume !(1 == ~t3_pc~0); 3994#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4694#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3917#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3650#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 3651#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4843#L669 assume 1 == ~t4_pc~0; 4844#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5202#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4327#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3859#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 3860#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4084#L688 assume !(1 == ~t5_pc~0); 3875#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3876#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4794#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4728#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 4729#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4858#L707 assume 1 == ~t6_pc~0; 5267#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4504#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4505#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5265#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 4800#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4362#L726 assume 1 == ~t7_pc~0; 4261#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3960#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5001#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5275#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 3729#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3730#L745 assume !(1 == ~t8_pc~0); 4177#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4196#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5034#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4582#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4583#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5093#L764 assume 1 == ~t9_pc~0; 4360#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4202#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4879#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5326#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 3749#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3750#L783 assume !(1 == ~t10_pc~0); 3811#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3812#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3853#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 3854#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 4316#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5204#L802 assume 1 == ~t11_pc~0; 5186#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3694#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3695#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4186#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 4187#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4297#L821 assume !(1 == ~t12_pc~0); 4548#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 4644#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3699#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 3700#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 5242#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4888#L1339 assume !(1 == ~M_E~0); 4889#L1339-2 assume !(1 == ~T1_E~0); 5277#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5278#L1349-1 assume !(1 == ~T3_E~0); 4662#L1354-1 assume !(1 == ~T4_E~0); 4663#L1359-1 assume !(1 == ~T5_E~0); 5064#L1364-1 assume !(1 == ~T6_E~0); 4127#L1369-1 assume !(1 == ~T7_E~0); 4128#L1374-1 assume !(1 == ~T8_E~0); 4665#L1379-1 assume !(1 == ~T9_E~0); 4666#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4765#L1389-1 assume !(1 == ~T11_E~0); 5236#L1394-1 assume !(1 == ~T12_E~0); 5237#L1399-1 assume !(1 == ~E_M~0); 5327#L1404-1 assume !(1 == ~E_1~0); 4226#L1409-1 assume !(1 == ~E_2~0); 4227#L1414-1 assume !(1 == ~E_3~0); 4953#L1419-1 assume !(1 == ~E_4~0); 3867#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 3868#L1429-1 assume !(1 == ~E_6~0); 4678#L1434-1 assume !(1 == ~E_7~0); 5257#L1439-1 assume !(1 == ~E_8~0); 3905#L1444-1 assume !(1 == ~E_9~0); 3906#L1449-1 assume !(1 == ~E_10~0); 4280#L1454-1 assume !(1 == ~E_11~0); 4281#L1459-1 assume !(1 == ~E_12~0); 4799#L1464-1 assume { :end_inline_reset_delta_events } true; 4039#L1810-2 [2022-07-22 02:43:02,723 INFO L754 eck$LassoCheckResult]: Loop: 4039#L1810-2 assume !false; 4483#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4399#L1176 assume !false; 4961#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4531#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3737#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4287#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4288#L1003 assume !(0 != eval_~tmp~0#1); 3929#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3930#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5120#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4903#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4904#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4797#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3988#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3989#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4455#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4059#L1231-3 assume !(0 == ~T7_E~0); 4060#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4306#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5288#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5189#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4894#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4005#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4006#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4051#L1271-3 assume !(0 == ~E_2~0); 4052#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4428#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4429#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4950#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4951#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5366#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5323#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4540#L1311-3 assume !(0 == ~E_10~0); 3931#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 3932#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 4007#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4643#L593-42 assume !(1 == ~m_pc~0); 4801#L593-44 is_master_triggered_~__retres1~0#1 := 0; 4802#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5351#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5352#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3830#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3831#L612-42 assume !(1 == ~t1_pc~0); 4752#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 5145#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5266#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3918#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3919#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4614#L631-42 assume 1 == ~t2_pc~0; 3683#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3684#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4603#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4479#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4480#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4080#L650-42 assume 1 == ~t3_pc~0; 3642#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3643#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5294#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4273#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4274#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5258#L669-42 assume !(1 == ~t4_pc~0); 3640#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 3641#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5069#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4959#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 4856#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4857#L688-42 assume 1 == ~t5_pc~0; 4948#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5149#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3781#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3782#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3858#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3672#L707-42 assume !(1 == ~t6_pc~0); 3673#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 5330#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5074#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5075#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4824#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4825#L726-42 assume 1 == ~t7_pc~0; 5102#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5128#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5129#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4543#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4544#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4647#L745-42 assume 1 == ~t8_pc~0; 4684#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4686#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4013#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3658#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3659#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4384#L764-42 assume 1 == ~t9_pc~0; 4520#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4873#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4874#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3944#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3945#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3998#L783-42 assume !(1 == ~t10_pc~0); 3616#L783-44 is_transmit10_triggered_~__retres1~10#1 := 0; 3615#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4210#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4343#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5360#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5044#L802-42 assume 1 == ~t11_pc~0; 4145#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3756#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3757#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3707#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3708#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4884#L821-42 assume 1 == ~t12_pc~0; 4885#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4250#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3612#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 3613#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 4590#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4580#L1339-3 assume !(1 == ~M_E~0); 4581#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4732#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4842#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4259#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4260#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4853#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5349#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5256#L1374-3 assume !(1 == ~T8_E~0); 4081#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4082#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4257#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4258#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4467#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5263#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5231#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5232#L1414-3 assume !(1 == ~E_3~0); 5287#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5046#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3965#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3966#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4852#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3893#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3894#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4010#L1454-3 assume !(1 == ~E_11~0); 4847#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4848#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4506#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3803#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4063#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 4064#L1829 assume !(0 == start_simulation_~tmp~3#1); 3785#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 3786#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 4586#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4587#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 4866#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4867#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4487#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 4038#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 4039#L1810-2 [2022-07-22 02:43:02,723 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:02,724 INFO L85 PathProgramCache]: Analyzing trace with hash -1818030166, now seen corresponding path program 2 times [2022-07-22 02:43:02,724 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:02,724 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1403246706] [2022-07-22 02:43:02,724 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:02,724 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:02,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:02,782 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:02,782 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:02,783 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1403246706] [2022-07-22 02:43:02,783 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1403246706] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:02,783 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:02,783 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:02,783 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1858147697] [2022-07-22 02:43:02,784 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:02,784 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:43:02,784 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:02,785 INFO L85 PathProgramCache]: Analyzing trace with hash -830311852, now seen corresponding path program 1 times [2022-07-22 02:43:02,785 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:02,785 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1390020564] [2022-07-22 02:43:02,785 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:02,785 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:02,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:02,852 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:02,852 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:02,852 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1390020564] [2022-07-22 02:43:02,853 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1390020564] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:02,853 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:02,853 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:02,853 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [968530273] [2022-07-22 02:43:02,853 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:02,854 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:43:02,854 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:43:02,854 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:43:02,855 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:43:02,855 INFO L87 Difference]: Start difference. First operand 1788 states and 2651 transitions. cyclomatic complexity: 864 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:02,923 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:43:02,923 INFO L93 Difference]: Finished difference Result 1788 states and 2650 transitions. [2022-07-22 02:43:02,923 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:43:02,924 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2650 transitions. [2022-07-22 02:43:02,932 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-07-22 02:43:02,955 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2650 transitions. [2022-07-22 02:43:02,956 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2022-07-22 02:43:02,971 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2022-07-22 02:43:02,972 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2650 transitions. [2022-07-22 02:43:02,974 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:43:02,974 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2650 transitions. [2022-07-22 02:43:02,976 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2650 transitions. [2022-07-22 02:43:02,989 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2022-07-22 02:43:02,992 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4821029082774049) internal successors, (2650), 1787 states have internal predecessors, (2650), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:02,996 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2650 transitions. [2022-07-22 02:43:02,996 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2650 transitions. [2022-07-22 02:43:02,996 INFO L374 stractBuchiCegarLoop]: Abstraction has 1788 states and 2650 transitions. [2022-07-22 02:43:02,996 INFO L287 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-07-22 02:43:02,996 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2650 transitions. [2022-07-22 02:43:03,002 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-07-22 02:43:03,003 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:43:03,003 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:43:03,004 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:03,004 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:03,005 INFO L752 eck$LassoCheckResult]: Stem: 7971#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 7972#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 7492#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7493#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7547#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 8886#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7980#L853-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 7783#L858-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 7182#L863-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 7183#L868-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8405#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8516#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8952#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8953#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7911#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 7912#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 8434#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 8353#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7946#L1201 assume !(0 == ~M_E~0); 7947#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8793#L1206-1 assume !(0 == ~T2_E~0); 8779#L1211-1 assume !(0 == ~T3_E~0); 8780#L1216-1 assume !(0 == ~T4_E~0); 7767#L1221-1 assume !(0 == ~T5_E~0); 7768#L1226-1 assume !(0 == ~T6_E~0); 7407#L1231-1 assume !(0 == ~T7_E~0); 7408#L1236-1 assume !(0 == ~T8_E~0); 8816#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7804#L1246-1 assume !(0 == ~T10_E~0); 7805#L1251-1 assume !(0 == ~T11_E~0); 7944#L1256-1 assume !(0 == ~T12_E~0); 7193#L1261-1 assume !(0 == ~E_M~0); 7194#L1266-1 assume !(0 == ~E_1~0); 8938#L1271-1 assume !(0 == ~E_2~0); 8500#L1276-1 assume !(0 == ~E_3~0); 8501#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 8448#L1286-1 assume !(0 == ~E_5~0); 7658#L1291-1 assume !(0 == ~E_6~0); 7659#L1296-1 assume !(0 == ~E_7~0); 8234#L1301-1 assume !(0 == ~E_8~0); 8235#L1306-1 assume !(0 == ~E_9~0); 8715#L1311-1 assume !(0 == ~E_10~0); 7609#L1316-1 assume !(0 == ~E_11~0); 7610#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 8252#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8253#L593 assume 1 == ~m_pc~0; 8397#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7499#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8925#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8459#L1492 assume !(0 != activate_threads_~tmp~1#1); 8460#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8751#L612 assume !(1 == ~t1_pc~0); 8752#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8881#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7881#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7503#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7504#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7923#L631 assume 1 == ~t2_pc~0; 7858#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7280#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7281#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8117#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 8118#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7576#L650 assume !(1 == ~t3_pc~0); 7577#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8277#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7500#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7233#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 7234#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8426#L669 assume 1 == ~t4_pc~0; 8427#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8785#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7910#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7442#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 7443#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7667#L688 assume !(1 == ~t5_pc~0); 7458#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7459#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8377#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8311#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 8312#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8441#L707 assume 1 == ~t6_pc~0; 8850#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8087#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8088#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8848#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 8383#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7945#L726 assume 1 == ~t7_pc~0; 7844#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7543#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8584#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8858#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 7312#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7313#L745 assume !(1 == ~t8_pc~0); 7760#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 7779#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8617#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8165#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8166#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8676#L764 assume 1 == ~t9_pc~0; 7943#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7785#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8462#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8909#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 7332#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7333#L783 assume !(1 == ~t10_pc~0); 7394#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 7395#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7436#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 7437#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 7899#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8787#L802 assume 1 == ~t11_pc~0; 8769#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7277#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7278#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 7769#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 7770#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 7880#L821 assume !(1 == ~t12_pc~0); 8131#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 8227#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 7282#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 7283#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 8825#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8471#L1339 assume !(1 == ~M_E~0); 8472#L1339-2 assume !(1 == ~T1_E~0); 8860#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8861#L1349-1 assume !(1 == ~T3_E~0); 8245#L1354-1 assume !(1 == ~T4_E~0); 8246#L1359-1 assume !(1 == ~T5_E~0); 8647#L1364-1 assume !(1 == ~T6_E~0); 7710#L1369-1 assume !(1 == ~T7_E~0); 7711#L1374-1 assume !(1 == ~T8_E~0); 8248#L1379-1 assume !(1 == ~T9_E~0); 8249#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8348#L1389-1 assume !(1 == ~T11_E~0); 8819#L1394-1 assume !(1 == ~T12_E~0); 8820#L1399-1 assume !(1 == ~E_M~0); 8910#L1404-1 assume !(1 == ~E_1~0); 7809#L1409-1 assume !(1 == ~E_2~0); 7810#L1414-1 assume !(1 == ~E_3~0); 8536#L1419-1 assume !(1 == ~E_4~0); 7450#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 7451#L1429-1 assume !(1 == ~E_6~0); 8261#L1434-1 assume !(1 == ~E_7~0); 8840#L1439-1 assume !(1 == ~E_8~0); 7488#L1444-1 assume !(1 == ~E_9~0); 7489#L1449-1 assume !(1 == ~E_10~0); 7863#L1454-1 assume !(1 == ~E_11~0); 7864#L1459-1 assume !(1 == ~E_12~0); 8382#L1464-1 assume { :end_inline_reset_delta_events } true; 7622#L1810-2 [2022-07-22 02:43:03,005 INFO L754 eck$LassoCheckResult]: Loop: 7622#L1810-2 assume !false; 8066#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7982#L1176 assume !false; 8544#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8114#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7320#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7870#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 7871#L1003 assume !(0 != eval_~tmp~0#1); 7512#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7513#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8703#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8486#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8487#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8380#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7571#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7572#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8038#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7642#L1231-3 assume !(0 == ~T7_E~0); 7643#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7889#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8871#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 8772#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 8477#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 7588#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7589#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7634#L1271-3 assume !(0 == ~E_2~0); 7635#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8011#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8012#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8533#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8534#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8949#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8906#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8123#L1311-3 assume !(0 == ~E_10~0); 7514#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 7515#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 7590#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8226#L593-42 assume !(1 == ~m_pc~0); 8384#L593-44 is_master_triggered_~__retres1~0#1 := 0; 8385#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8934#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8935#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7413#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7414#L612-42 assume 1 == ~t1_pc~0; 8336#L613-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8728#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8849#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7501#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7502#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8197#L631-42 assume 1 == ~t2_pc~0; 7266#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7267#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8186#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8062#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8063#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7663#L650-42 assume 1 == ~t3_pc~0; 7225#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7226#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8877#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7856#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7857#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8841#L669-42 assume !(1 == ~t4_pc~0); 7223#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 7224#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8652#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8542#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 8439#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8440#L688-42 assume 1 == ~t5_pc~0; 8531#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8732#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7364#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7365#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7441#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7255#L707-42 assume !(1 == ~t6_pc~0); 7256#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 8913#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8657#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8658#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8407#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8408#L726-42 assume 1 == ~t7_pc~0; 8685#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8711#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8712#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8126#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8127#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8230#L745-42 assume 1 == ~t8_pc~0; 8267#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8269#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7596#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7241#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7242#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7967#L764-42 assume 1 == ~t9_pc~0; 8103#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8456#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8457#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7527#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 7528#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7581#L783-42 assume 1 == ~t10_pc~0; 7197#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 7198#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7793#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 7926#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8943#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8627#L802-42 assume 1 == ~t11_pc~0; 7728#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7339#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7340#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 7290#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 7291#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8467#L821-42 assume 1 == ~t12_pc~0; 8468#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 7833#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 7195#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 7196#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 8173#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8163#L1339-3 assume !(1 == ~M_E~0); 8164#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8315#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8425#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7842#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7843#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8436#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8932#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8839#L1374-3 assume !(1 == ~T8_E~0); 7664#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7665#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 7840#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 7841#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8050#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8846#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8814#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8815#L1414-3 assume !(1 == ~E_3~0); 8870#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8629#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7548#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7549#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8435#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7476#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 7477#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 7593#L1454-3 assume !(1 == ~E_11~0); 8430#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 8431#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8089#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7386#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7646#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 7647#L1829 assume !(0 == start_simulation_~tmp~3#1); 7368#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 7369#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 8169#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 8170#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 8449#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8450#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8070#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 7621#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 7622#L1810-2 [2022-07-22 02:43:03,006 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:03,006 INFO L85 PathProgramCache]: Analyzing trace with hash -494851220, now seen corresponding path program 1 times [2022-07-22 02:43:03,006 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:03,006 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [981459522] [2022-07-22 02:43:03,006 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:03,006 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:03,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:03,035 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:03,035 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:03,036 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [981459522] [2022-07-22 02:43:03,036 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [981459522] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:03,036 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:03,036 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:03,036 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1137441295] [2022-07-22 02:43:03,036 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:03,037 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:43:03,037 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:03,037 INFO L85 PathProgramCache]: Analyzing trace with hash -1795658606, now seen corresponding path program 1 times [2022-07-22 02:43:03,038 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:03,038 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [401631930] [2022-07-22 02:43:03,038 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:03,038 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:03,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:03,134 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:03,134 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:03,135 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [401631930] [2022-07-22 02:43:03,135 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [401631930] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:03,135 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:03,135 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:03,137 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2035140312] [2022-07-22 02:43:03,137 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:03,137 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:43:03,138 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:43:03,138 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:43:03,138 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:43:03,138 INFO L87 Difference]: Start difference. First operand 1788 states and 2650 transitions. cyclomatic complexity: 863 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:03,162 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:43:03,163 INFO L93 Difference]: Finished difference Result 1788 states and 2649 transitions. [2022-07-22 02:43:03,163 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:43:03,165 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2649 transitions. [2022-07-22 02:43:03,175 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-07-22 02:43:03,182 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2649 transitions. [2022-07-22 02:43:03,183 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2022-07-22 02:43:03,184 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2022-07-22 02:43:03,184 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2649 transitions. [2022-07-22 02:43:03,186 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:43:03,186 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2649 transitions. [2022-07-22 02:43:03,188 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2649 transitions. [2022-07-22 02:43:03,201 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2022-07-22 02:43:03,204 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4815436241610738) internal successors, (2649), 1787 states have internal predecessors, (2649), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:03,208 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2649 transitions. [2022-07-22 02:43:03,209 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2649 transitions. [2022-07-22 02:43:03,209 INFO L374 stractBuchiCegarLoop]: Abstraction has 1788 states and 2649 transitions. [2022-07-22 02:43:03,209 INFO L287 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-07-22 02:43:03,209 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2649 transitions. [2022-07-22 02:43:03,231 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-07-22 02:43:03,233 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:43:03,233 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:43:03,234 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:03,234 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:03,235 INFO L752 eck$LassoCheckResult]: Stem: 11554#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 11555#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 11075#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11076#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11130#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 12469#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11563#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11366#L858-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 10765#L863-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 10766#L868-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11988#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12099#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12535#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12536#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11494#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 11495#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12017#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 11936#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11529#L1201 assume !(0 == ~M_E~0); 11530#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12376#L1206-1 assume !(0 == ~T2_E~0); 12362#L1211-1 assume !(0 == ~T3_E~0); 12363#L1216-1 assume !(0 == ~T4_E~0); 11350#L1221-1 assume !(0 == ~T5_E~0); 11351#L1226-1 assume !(0 == ~T6_E~0); 10990#L1231-1 assume !(0 == ~T7_E~0); 10991#L1236-1 assume !(0 == ~T8_E~0); 12399#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11387#L1246-1 assume !(0 == ~T10_E~0); 11388#L1251-1 assume !(0 == ~T11_E~0); 11527#L1256-1 assume !(0 == ~T12_E~0); 10776#L1261-1 assume !(0 == ~E_M~0); 10777#L1266-1 assume !(0 == ~E_1~0); 12521#L1271-1 assume !(0 == ~E_2~0); 12083#L1276-1 assume !(0 == ~E_3~0); 12084#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 12031#L1286-1 assume !(0 == ~E_5~0); 11241#L1291-1 assume !(0 == ~E_6~0); 11242#L1296-1 assume !(0 == ~E_7~0); 11817#L1301-1 assume !(0 == ~E_8~0); 11818#L1306-1 assume !(0 == ~E_9~0); 12298#L1311-1 assume !(0 == ~E_10~0); 11192#L1316-1 assume !(0 == ~E_11~0); 11193#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 11835#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11836#L593 assume 1 == ~m_pc~0; 11980#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11082#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12508#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12042#L1492 assume !(0 != activate_threads_~tmp~1#1); 12043#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12334#L612 assume !(1 == ~t1_pc~0); 12335#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12464#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11464#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11086#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11087#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11506#L631 assume 1 == ~t2_pc~0; 11441#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10863#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10864#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11700#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 11701#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11159#L650 assume !(1 == ~t3_pc~0); 11160#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 11860#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11083#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10816#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 10817#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12009#L669 assume 1 == ~t4_pc~0; 12010#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12368#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11493#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11025#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 11026#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11250#L688 assume !(1 == ~t5_pc~0); 11041#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 11042#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11960#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11894#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 11895#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12024#L707 assume 1 == ~t6_pc~0; 12433#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11670#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11671#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12431#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 11966#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11528#L726 assume 1 == ~t7_pc~0; 11427#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11126#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12167#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12441#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 10895#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10896#L745 assume !(1 == ~t8_pc~0); 11343#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 11362#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12200#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11748#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11749#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12259#L764 assume 1 == ~t9_pc~0; 11526#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11368#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12045#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12492#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 10915#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10916#L783 assume !(1 == ~t10_pc~0); 10977#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 10978#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11019#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 11020#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 11482#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12370#L802 assume 1 == ~t11_pc~0; 12352#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 10860#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10861#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 11352#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 11353#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 11463#L821 assume !(1 == ~t12_pc~0); 11714#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 11810#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 10865#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 10866#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 12408#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12054#L1339 assume !(1 == ~M_E~0); 12055#L1339-2 assume !(1 == ~T1_E~0); 12443#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12444#L1349-1 assume !(1 == ~T3_E~0); 11828#L1354-1 assume !(1 == ~T4_E~0); 11829#L1359-1 assume !(1 == ~T5_E~0); 12230#L1364-1 assume !(1 == ~T6_E~0); 11293#L1369-1 assume !(1 == ~T7_E~0); 11294#L1374-1 assume !(1 == ~T8_E~0); 11831#L1379-1 assume !(1 == ~T9_E~0); 11832#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11931#L1389-1 assume !(1 == ~T11_E~0); 12402#L1394-1 assume !(1 == ~T12_E~0); 12403#L1399-1 assume !(1 == ~E_M~0); 12493#L1404-1 assume !(1 == ~E_1~0); 11392#L1409-1 assume !(1 == ~E_2~0); 11393#L1414-1 assume !(1 == ~E_3~0); 12119#L1419-1 assume !(1 == ~E_4~0); 11033#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 11034#L1429-1 assume !(1 == ~E_6~0); 11844#L1434-1 assume !(1 == ~E_7~0); 12423#L1439-1 assume !(1 == ~E_8~0); 11071#L1444-1 assume !(1 == ~E_9~0); 11072#L1449-1 assume !(1 == ~E_10~0); 11446#L1454-1 assume !(1 == ~E_11~0); 11447#L1459-1 assume !(1 == ~E_12~0); 11965#L1464-1 assume { :end_inline_reset_delta_events } true; 11205#L1810-2 [2022-07-22 02:43:03,235 INFO L754 eck$LassoCheckResult]: Loop: 11205#L1810-2 assume !false; 11649#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11565#L1176 assume !false; 12127#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11697#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10903#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11453#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 11454#L1003 assume !(0 != eval_~tmp~0#1); 11095#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11096#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12286#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12069#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12070#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11963#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11154#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11155#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11621#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11225#L1231-3 assume !(0 == ~T7_E~0); 11226#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 11472#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 12454#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12355#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 12060#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 11171#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 11172#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11217#L1271-3 assume !(0 == ~E_2~0); 11218#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11594#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11595#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12116#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12117#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12532#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12489#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11706#L1311-3 assume !(0 == ~E_10~0); 11097#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 11098#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 11173#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11809#L593-42 assume 1 == ~m_pc~0; 12202#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11968#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12517#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12518#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10996#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10997#L612-42 assume !(1 == ~t1_pc~0); 11918#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 12311#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12432#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11084#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11085#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11780#L631-42 assume 1 == ~t2_pc~0; 10849#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10850#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11769#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11645#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11646#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11246#L650-42 assume 1 == ~t3_pc~0; 10808#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10809#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12460#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11439#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11440#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12424#L669-42 assume !(1 == ~t4_pc~0); 10806#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 10807#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12235#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12125#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 12022#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12023#L688-42 assume 1 == ~t5_pc~0; 12114#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12315#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10947#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10948#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11024#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10838#L707-42 assume !(1 == ~t6_pc~0); 10839#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 12496#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12240#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12241#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11990#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11991#L726-42 assume 1 == ~t7_pc~0; 12268#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12294#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12295#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11709#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11710#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11813#L745-42 assume 1 == ~t8_pc~0; 11850#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11852#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11179#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 10824#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 10825#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11550#L764-42 assume 1 == ~t9_pc~0; 11686#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12039#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12040#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 11110#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11111#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11164#L783-42 assume 1 == ~t10_pc~0; 10780#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 10781#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11376#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 11509#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12526#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12210#L802-42 assume !(1 == ~t11_pc~0); 11312#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 10922#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10923#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 10873#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 10874#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12050#L821-42 assume 1 == ~t12_pc~0; 12051#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 11416#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 10778#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 10779#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 11756#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11746#L1339-3 assume !(1 == ~M_E~0); 11747#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11898#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12008#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11425#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11426#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12019#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12515#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12422#L1374-3 assume !(1 == ~T8_E~0); 11247#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11248#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11423#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 11424#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 11633#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12429#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12397#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12398#L1414-3 assume !(1 == ~E_3~0); 12453#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12212#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11131#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11132#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12018#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11059#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 11060#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 11176#L1454-3 assume !(1 == ~E_11~0); 12013#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 12014#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11672#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10969#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11229#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 11230#L1829 assume !(0 == start_simulation_~tmp~3#1); 10951#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 10952#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 11752#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11753#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 12032#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12033#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11653#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 11204#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 11205#L1810-2 [2022-07-22 02:43:03,236 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:03,236 INFO L85 PathProgramCache]: Analyzing trace with hash -833138770, now seen corresponding path program 1 times [2022-07-22 02:43:03,236 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:03,236 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [128529341] [2022-07-22 02:43:03,236 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:03,237 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:03,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:03,259 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:03,259 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:03,259 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [128529341] [2022-07-22 02:43:03,259 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [128529341] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:03,259 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:03,259 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:03,260 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [119165545] [2022-07-22 02:43:03,260 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:03,260 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:43:03,260 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:03,260 INFO L85 PathProgramCache]: Analyzing trace with hash 1706034771, now seen corresponding path program 1 times [2022-07-22 02:43:03,261 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:03,261 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1466838598] [2022-07-22 02:43:03,261 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:03,261 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:03,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:03,306 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:03,306 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:03,306 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1466838598] [2022-07-22 02:43:03,306 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1466838598] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:03,306 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:03,306 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:03,306 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [785103487] [2022-07-22 02:43:03,307 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:03,307 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:43:03,307 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:43:03,307 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:43:03,307 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:43:03,308 INFO L87 Difference]: Start difference. First operand 1788 states and 2649 transitions. cyclomatic complexity: 862 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:03,330 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:43:03,332 INFO L93 Difference]: Finished difference Result 1788 states and 2648 transitions. [2022-07-22 02:43:03,332 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:43:03,333 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2648 transitions. [2022-07-22 02:43:03,342 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-07-22 02:43:03,349 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2648 transitions. [2022-07-22 02:43:03,350 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2022-07-22 02:43:03,351 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2022-07-22 02:43:03,351 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2648 transitions. [2022-07-22 02:43:03,354 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:43:03,354 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2648 transitions. [2022-07-22 02:43:03,357 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2648 transitions. [2022-07-22 02:43:03,372 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2022-07-22 02:43:03,375 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4809843400447427) internal successors, (2648), 1787 states have internal predecessors, (2648), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:03,380 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2648 transitions. [2022-07-22 02:43:03,380 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2648 transitions. [2022-07-22 02:43:03,380 INFO L374 stractBuchiCegarLoop]: Abstraction has 1788 states and 2648 transitions. [2022-07-22 02:43:03,381 INFO L287 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-07-22 02:43:03,381 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2648 transitions. [2022-07-22 02:43:03,387 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-07-22 02:43:03,388 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:43:03,388 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:43:03,389 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:03,390 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:03,390 INFO L752 eck$LassoCheckResult]: Stem: 15137#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 15138#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 14658#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14659#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14713#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 16052#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15146#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14949#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14348#L863-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 14349#L868-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 15571#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 15682#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 16118#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16119#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 15077#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 15078#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 15600#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 15519#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15112#L1201 assume !(0 == ~M_E~0); 15113#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15959#L1206-1 assume !(0 == ~T2_E~0); 15945#L1211-1 assume !(0 == ~T3_E~0); 15946#L1216-1 assume !(0 == ~T4_E~0); 14933#L1221-1 assume !(0 == ~T5_E~0); 14934#L1226-1 assume !(0 == ~T6_E~0); 14573#L1231-1 assume !(0 == ~T7_E~0); 14574#L1236-1 assume !(0 == ~T8_E~0); 15982#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14970#L1246-1 assume !(0 == ~T10_E~0); 14971#L1251-1 assume !(0 == ~T11_E~0); 15110#L1256-1 assume !(0 == ~T12_E~0); 14359#L1261-1 assume !(0 == ~E_M~0); 14360#L1266-1 assume !(0 == ~E_1~0); 16104#L1271-1 assume !(0 == ~E_2~0); 15666#L1276-1 assume !(0 == ~E_3~0); 15667#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 15614#L1286-1 assume !(0 == ~E_5~0); 14824#L1291-1 assume !(0 == ~E_6~0); 14825#L1296-1 assume !(0 == ~E_7~0); 15400#L1301-1 assume !(0 == ~E_8~0); 15401#L1306-1 assume !(0 == ~E_9~0); 15881#L1311-1 assume !(0 == ~E_10~0); 14775#L1316-1 assume !(0 == ~E_11~0); 14776#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 15418#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15419#L593 assume 1 == ~m_pc~0; 15563#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14665#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16091#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15625#L1492 assume !(0 != activate_threads_~tmp~1#1); 15626#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15917#L612 assume !(1 == ~t1_pc~0); 15918#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16047#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15047#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14669#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14670#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15089#L631 assume 1 == ~t2_pc~0; 15024#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14446#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14447#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15283#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 15284#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14742#L650 assume !(1 == ~t3_pc~0); 14743#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 15443#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14666#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14399#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 14400#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15592#L669 assume 1 == ~t4_pc~0; 15593#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15951#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15076#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14608#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 14609#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14833#L688 assume !(1 == ~t5_pc~0); 14624#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 14625#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15543#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15477#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 15478#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15607#L707 assume 1 == ~t6_pc~0; 16016#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15253#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15254#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16014#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 15549#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15111#L726 assume 1 == ~t7_pc~0; 15010#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14709#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15750#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16024#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 14478#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14479#L745 assume !(1 == ~t8_pc~0); 14926#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 14945#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15783#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 15331#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 15332#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15842#L764 assume 1 == ~t9_pc~0; 15109#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14951#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15628#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16075#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 14498#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14499#L783 assume !(1 == ~t10_pc~0); 14560#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 14561#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14602#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 14603#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 15065#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 15953#L802 assume 1 == ~t11_pc~0; 15935#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 14443#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14444#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 14935#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 14936#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 15046#L821 assume !(1 == ~t12_pc~0); 15297#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 15393#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 14448#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 14449#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 15991#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15637#L1339 assume !(1 == ~M_E~0); 15638#L1339-2 assume !(1 == ~T1_E~0); 16026#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16027#L1349-1 assume !(1 == ~T3_E~0); 15411#L1354-1 assume !(1 == ~T4_E~0); 15412#L1359-1 assume !(1 == ~T5_E~0); 15813#L1364-1 assume !(1 == ~T6_E~0); 14876#L1369-1 assume !(1 == ~T7_E~0); 14877#L1374-1 assume !(1 == ~T8_E~0); 15414#L1379-1 assume !(1 == ~T9_E~0); 15415#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 15514#L1389-1 assume !(1 == ~T11_E~0); 15985#L1394-1 assume !(1 == ~T12_E~0); 15986#L1399-1 assume !(1 == ~E_M~0); 16076#L1404-1 assume !(1 == ~E_1~0); 14975#L1409-1 assume !(1 == ~E_2~0); 14976#L1414-1 assume !(1 == ~E_3~0); 15702#L1419-1 assume !(1 == ~E_4~0); 14616#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 14617#L1429-1 assume !(1 == ~E_6~0); 15427#L1434-1 assume !(1 == ~E_7~0); 16006#L1439-1 assume !(1 == ~E_8~0); 14654#L1444-1 assume !(1 == ~E_9~0); 14655#L1449-1 assume !(1 == ~E_10~0); 15029#L1454-1 assume !(1 == ~E_11~0); 15030#L1459-1 assume !(1 == ~E_12~0); 15548#L1464-1 assume { :end_inline_reset_delta_events } true; 14788#L1810-2 [2022-07-22 02:43:03,390 INFO L754 eck$LassoCheckResult]: Loop: 14788#L1810-2 assume !false; 15232#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15148#L1176 assume !false; 15710#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15280#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14486#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 15036#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 15037#L1003 assume !(0 != eval_~tmp~0#1); 14678#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14679#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15869#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15652#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15653#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15546#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14737#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14738#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15204#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14808#L1231-3 assume !(0 == ~T7_E~0); 14809#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 15055#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16037#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 15938#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 15643#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 14754#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14755#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14800#L1271-3 assume !(0 == ~E_2~0); 14801#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15177#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15178#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15699#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15700#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 16115#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16072#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15289#L1311-3 assume !(0 == ~E_10~0); 14680#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 14681#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 14756#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15392#L593-42 assume 1 == ~m_pc~0; 15785#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 15551#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16100#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16101#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14579#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14580#L612-42 assume !(1 == ~t1_pc~0); 15501#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 15894#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16015#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14667#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14668#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15363#L631-42 assume 1 == ~t2_pc~0; 14432#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14433#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15352#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15228#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15229#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14829#L650-42 assume 1 == ~t3_pc~0; 14391#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14392#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16043#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15022#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15023#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16007#L669-42 assume !(1 == ~t4_pc~0); 14389#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 14390#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15818#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15708#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 15605#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15606#L688-42 assume 1 == ~t5_pc~0; 15697#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15898#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14530#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14531#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14607#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14421#L707-42 assume !(1 == ~t6_pc~0); 14422#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 16079#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15823#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15824#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15573#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15574#L726-42 assume 1 == ~t7_pc~0; 15851#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15877#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15878#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 15292#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15293#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15396#L745-42 assume 1 == ~t8_pc~0; 15433#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15435#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14762#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14407#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14408#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15133#L764-42 assume 1 == ~t9_pc~0; 15269#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15622#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15623#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 14693#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 14694#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14747#L783-42 assume 1 == ~t10_pc~0; 14363#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 14364#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14959#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 15092#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16109#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 15793#L802-42 assume 1 == ~t11_pc~0; 14894#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 14505#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14506#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 14456#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 14457#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 15633#L821-42 assume 1 == ~t12_pc~0; 15634#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 14999#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 14361#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 14362#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 15339#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15329#L1339-3 assume !(1 == ~M_E~0); 15330#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15481#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15591#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15008#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15009#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15602#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16098#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16005#L1374-3 assume !(1 == ~T8_E~0); 14830#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14831#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 15006#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 15007#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 15216#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16012#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15980#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15981#L1414-3 assume !(1 == ~E_3~0); 16036#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15795#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14714#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14715#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15601#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14642#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 14643#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 14759#L1454-3 assume !(1 == ~E_11~0); 15596#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 15597#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15255#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14552#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14812#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 14813#L1829 assume !(0 == start_simulation_~tmp~3#1); 14534#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 14535#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 15335#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 15336#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 15615#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15616#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15236#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 14787#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 14788#L1810-2 [2022-07-22 02:43:03,392 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:03,392 INFO L85 PathProgramCache]: Analyzing trace with hash -1259693268, now seen corresponding path program 1 times [2022-07-22 02:43:03,392 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:03,392 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1019473921] [2022-07-22 02:43:03,393 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:03,393 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:03,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:03,420 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:03,420 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:03,420 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1019473921] [2022-07-22 02:43:03,420 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1019473921] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:03,421 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:03,421 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:03,421 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [632890675] [2022-07-22 02:43:03,421 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:03,421 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:43:03,422 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:03,422 INFO L85 PathProgramCache]: Analyzing trace with hash -488091310, now seen corresponding path program 1 times [2022-07-22 02:43:03,422 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:03,422 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [973655901] [2022-07-22 02:43:03,422 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:03,422 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:03,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:03,453 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:03,453 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:03,453 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [973655901] [2022-07-22 02:43:03,454 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [973655901] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:03,454 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:03,454 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:03,454 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [708972968] [2022-07-22 02:43:03,454 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:03,454 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:43:03,455 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:43:03,455 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:43:03,455 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:43:03,455 INFO L87 Difference]: Start difference. First operand 1788 states and 2648 transitions. cyclomatic complexity: 861 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:03,488 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:43:03,488 INFO L93 Difference]: Finished difference Result 1788 states and 2647 transitions. [2022-07-22 02:43:03,488 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:43:03,489 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2647 transitions. [2022-07-22 02:43:03,497 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-07-22 02:43:03,504 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2647 transitions. [2022-07-22 02:43:03,504 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2022-07-22 02:43:03,505 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2022-07-22 02:43:03,505 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2647 transitions. [2022-07-22 02:43:03,507 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:43:03,507 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2647 transitions. [2022-07-22 02:43:03,509 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2647 transitions. [2022-07-22 02:43:03,523 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2022-07-22 02:43:03,526 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4804250559284116) internal successors, (2647), 1787 states have internal predecessors, (2647), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:03,530 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2647 transitions. [2022-07-22 02:43:03,531 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2647 transitions. [2022-07-22 02:43:03,531 INFO L374 stractBuchiCegarLoop]: Abstraction has 1788 states and 2647 transitions. [2022-07-22 02:43:03,531 INFO L287 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-07-22 02:43:03,531 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2647 transitions. [2022-07-22 02:43:03,536 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-07-22 02:43:03,536 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:43:03,536 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:43:03,538 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:03,538 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:03,538 INFO L752 eck$LassoCheckResult]: Stem: 18720#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 18721#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 18241#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18242#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18296#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 19635#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18729#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18532#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17931#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17932#L868-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 19154#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 19267#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 19701#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19702#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 18660#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 18661#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 19183#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 19102#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18695#L1201 assume !(0 == ~M_E~0); 18696#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19542#L1206-1 assume !(0 == ~T2_E~0); 19528#L1211-1 assume !(0 == ~T3_E~0); 19529#L1216-1 assume !(0 == ~T4_E~0); 18517#L1221-1 assume !(0 == ~T5_E~0); 18518#L1226-1 assume !(0 == ~T6_E~0); 18156#L1231-1 assume !(0 == ~T7_E~0); 18157#L1236-1 assume !(0 == ~T8_E~0); 19565#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18556#L1246-1 assume !(0 == ~T10_E~0); 18557#L1251-1 assume !(0 == ~T11_E~0); 18693#L1256-1 assume !(0 == ~T12_E~0); 17944#L1261-1 assume !(0 == ~E_M~0); 17945#L1266-1 assume !(0 == ~E_1~0); 19687#L1271-1 assume !(0 == ~E_2~0); 19249#L1276-1 assume !(0 == ~E_3~0); 19250#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 19197#L1286-1 assume !(0 == ~E_5~0); 18407#L1291-1 assume !(0 == ~E_6~0); 18408#L1296-1 assume !(0 == ~E_7~0); 18983#L1301-1 assume !(0 == ~E_8~0); 18984#L1306-1 assume !(0 == ~E_9~0); 19464#L1311-1 assume !(0 == ~E_10~0); 18358#L1316-1 assume !(0 == ~E_11~0); 18359#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 19001#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19002#L593 assume 1 == ~m_pc~0; 19146#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 18248#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19674#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19208#L1492 assume !(0 != activate_threads_~tmp~1#1); 19209#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19500#L612 assume !(1 == ~t1_pc~0); 19501#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19630#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18630#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18252#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18253#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18672#L631 assume 1 == ~t2_pc~0; 18607#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18029#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18030#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18866#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 18867#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18325#L650 assume !(1 == ~t3_pc~0); 18326#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 19026#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18249#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17982#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 17983#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19175#L669 assume 1 == ~t4_pc~0; 19176#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19534#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18659#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18191#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 18192#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18416#L688 assume !(1 == ~t5_pc~0); 18207#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 18208#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19126#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19062#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 19063#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19193#L707 assume 1 == ~t6_pc~0; 19599#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18836#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18837#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19597#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 19134#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18694#L726 assume 1 == ~t7_pc~0; 18595#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18292#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19333#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19608#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 18061#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18062#L745 assume !(1 == ~t8_pc~0); 18509#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 18528#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19366#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 18914#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18915#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19425#L764 assume 1 == ~t9_pc~0; 18692#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18534#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19211#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 19658#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 18081#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18082#L783 assume !(1 == ~t10_pc~0); 18143#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 18144#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18185#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 18186#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 18653#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 19536#L802 assume 1 == ~t11_pc~0; 19518#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 18026#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18027#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 18519#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 18520#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 18629#L821 assume !(1 == ~t12_pc~0); 18880#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 18976#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 18033#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 18034#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 19574#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19220#L1339 assume !(1 == ~M_E~0); 19221#L1339-2 assume !(1 == ~T1_E~0); 19609#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19610#L1349-1 assume !(1 == ~T3_E~0); 18995#L1354-1 assume !(1 == ~T4_E~0); 18996#L1359-1 assume !(1 == ~T5_E~0); 19398#L1364-1 assume !(1 == ~T6_E~0); 18459#L1369-1 assume !(1 == ~T7_E~0); 18460#L1374-1 assume !(1 == ~T8_E~0); 18999#L1379-1 assume !(1 == ~T9_E~0); 19000#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19097#L1389-1 assume !(1 == ~T11_E~0); 19568#L1394-1 assume !(1 == ~T12_E~0); 19569#L1399-1 assume !(1 == ~E_M~0); 19659#L1404-1 assume !(1 == ~E_1~0); 18560#L1409-1 assume !(1 == ~E_2~0); 18561#L1414-1 assume !(1 == ~E_3~0); 19285#L1419-1 assume !(1 == ~E_4~0); 18199#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 18200#L1429-1 assume !(1 == ~E_6~0); 19010#L1434-1 assume !(1 == ~E_7~0); 19589#L1439-1 assume !(1 == ~E_8~0); 18237#L1444-1 assume !(1 == ~E_9~0); 18238#L1449-1 assume !(1 == ~E_10~0); 18612#L1454-1 assume !(1 == ~E_11~0); 18613#L1459-1 assume !(1 == ~E_12~0); 19131#L1464-1 assume { :end_inline_reset_delta_events } true; 18371#L1810-2 [2022-07-22 02:43:03,539 INFO L754 eck$LassoCheckResult]: Loop: 18371#L1810-2 assume !false; 18815#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18731#L1176 assume !false; 19293#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18865#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18069#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18619#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 18620#L1003 assume !(0 != eval_~tmp~0#1); 18263#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18264#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19452#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19235#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19236#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19130#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18320#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18321#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18787#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18391#L1231-3 assume !(0 == ~T7_E~0); 18392#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 18638#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19620#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19521#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 19226#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 18337#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 18338#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18383#L1271-3 assume !(0 == ~E_2~0); 18384#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18760#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18761#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19282#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 19283#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 19698#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19655#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 18872#L1311-3 assume !(0 == ~E_10~0); 18261#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 18262#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 18339#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18975#L593-42 assume 1 == ~m_pc~0; 19368#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19133#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19682#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19683#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18162#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18163#L612-42 assume !(1 == ~t1_pc~0); 19084#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 19477#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19598#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18250#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18251#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18946#L631-42 assume !(1 == ~t2_pc~0); 18017#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 18016#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18935#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18811#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18812#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18412#L650-42 assume 1 == ~t3_pc~0; 17974#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17975#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19626#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18605#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18606#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19590#L669-42 assume !(1 == ~t4_pc~0); 17972#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 17973#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19401#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19291#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 19188#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19189#L688-42 assume 1 == ~t5_pc~0; 19280#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19481#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18113#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18114#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18187#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18004#L707-42 assume !(1 == ~t6_pc~0); 18005#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 19662#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19406#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19407#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19156#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19157#L726-42 assume 1 == ~t7_pc~0; 19434#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19460#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19461#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 18875#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18876#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18979#L745-42 assume 1 == ~t8_pc~0; 19016#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19018#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18345#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17990#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 17991#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18716#L764-42 assume 1 == ~t9_pc~0; 18852#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19205#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19206#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 18276#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 18277#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18330#L783-42 assume 1 == ~t10_pc~0; 17946#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 17947#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18542#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 18675#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 19692#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 19376#L802-42 assume 1 == ~t11_pc~0; 18477#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 18088#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18089#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 18039#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 18040#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 19216#L821-42 assume 1 == ~t12_pc~0; 19217#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 18582#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 17942#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 17943#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 18922#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18912#L1339-3 assume !(1 == ~M_E~0); 18913#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19064#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19174#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18591#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18592#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19185#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19681#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19588#L1374-3 assume !(1 == ~T8_E~0); 18413#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18414#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 18589#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 18590#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 18799#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19595#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19563#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19564#L1414-3 assume !(1 == ~E_3~0); 19619#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19378#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18297#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18298#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19184#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 18225#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 18226#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 18342#L1454-3 assume !(1 == ~E_11~0); 19179#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 19180#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18838#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18135#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18395#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 18396#L1829 assume !(0 == start_simulation_~tmp~3#1); 18117#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18118#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18918#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18919#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 19198#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19199#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18819#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 18370#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 18371#L1810-2 [2022-07-22 02:43:03,539 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:03,539 INFO L85 PathProgramCache]: Analyzing trace with hash -719263762, now seen corresponding path program 1 times [2022-07-22 02:43:03,540 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:03,540 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [585035119] [2022-07-22 02:43:03,540 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:03,540 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:03,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:03,561 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:03,561 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:03,561 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [585035119] [2022-07-22 02:43:03,562 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [585035119] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:03,562 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:03,562 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:03,562 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2075060844] [2022-07-22 02:43:03,562 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:03,563 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:43:03,563 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:03,563 INFO L85 PathProgramCache]: Analyzing trace with hash -200631405, now seen corresponding path program 1 times [2022-07-22 02:43:03,563 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:03,564 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2059368769] [2022-07-22 02:43:03,564 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:03,564 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:03,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:03,592 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:03,592 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:03,592 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2059368769] [2022-07-22 02:43:03,592 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2059368769] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:03,592 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:03,593 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:03,593 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1104775681] [2022-07-22 02:43:03,593 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:03,593 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:43:03,593 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:43:03,594 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:43:03,594 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:43:03,594 INFO L87 Difference]: Start difference. First operand 1788 states and 2647 transitions. cyclomatic complexity: 860 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:03,616 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:43:03,616 INFO L93 Difference]: Finished difference Result 1788 states and 2646 transitions. [2022-07-22 02:43:03,617 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:43:03,617 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2646 transitions. [2022-07-22 02:43:03,625 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-07-22 02:43:03,631 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2646 transitions. [2022-07-22 02:43:03,632 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2022-07-22 02:43:03,633 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2022-07-22 02:43:03,633 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2646 transitions. [2022-07-22 02:43:03,634 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:43:03,635 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2646 transitions. [2022-07-22 02:43:03,636 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2646 transitions. [2022-07-22 02:43:03,650 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2022-07-22 02:43:03,653 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4798657718120805) internal successors, (2646), 1787 states have internal predecessors, (2646), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:03,657 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2646 transitions. [2022-07-22 02:43:03,657 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2646 transitions. [2022-07-22 02:43:03,658 INFO L374 stractBuchiCegarLoop]: Abstraction has 1788 states and 2646 transitions. [2022-07-22 02:43:03,658 INFO L287 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-07-22 02:43:03,658 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2646 transitions. [2022-07-22 02:43:03,672 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-07-22 02:43:03,673 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:43:03,673 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:43:03,675 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:03,675 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:03,675 INFO L752 eck$LassoCheckResult]: Stem: 22303#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 22304#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 21824#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21825#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21879#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 23218#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22312#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22115#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21514#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21515#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22737#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 22850#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 23284#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 23285#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22243#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 22244#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 22766#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 22685#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22278#L1201 assume !(0 == ~M_E~0); 22279#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 23125#L1206-1 assume !(0 == ~T2_E~0); 23111#L1211-1 assume !(0 == ~T3_E~0); 23112#L1216-1 assume !(0 == ~T4_E~0); 22100#L1221-1 assume !(0 == ~T5_E~0); 22101#L1226-1 assume !(0 == ~T6_E~0); 21739#L1231-1 assume !(0 == ~T7_E~0); 21740#L1236-1 assume !(0 == ~T8_E~0); 23148#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22139#L1246-1 assume !(0 == ~T10_E~0); 22140#L1251-1 assume !(0 == ~T11_E~0); 22276#L1256-1 assume !(0 == ~T12_E~0); 21527#L1261-1 assume !(0 == ~E_M~0); 21528#L1266-1 assume !(0 == ~E_1~0); 23270#L1271-1 assume !(0 == ~E_2~0); 22832#L1276-1 assume !(0 == ~E_3~0); 22833#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 22780#L1286-1 assume !(0 == ~E_5~0); 21990#L1291-1 assume !(0 == ~E_6~0); 21991#L1296-1 assume !(0 == ~E_7~0); 22566#L1301-1 assume !(0 == ~E_8~0); 22567#L1306-1 assume !(0 == ~E_9~0); 23047#L1311-1 assume !(0 == ~E_10~0); 21941#L1316-1 assume !(0 == ~E_11~0); 21942#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 22584#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22585#L593 assume 1 == ~m_pc~0; 22729#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 21831#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23257#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22791#L1492 assume !(0 != activate_threads_~tmp~1#1); 22792#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23083#L612 assume !(1 == ~t1_pc~0); 23084#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 23213#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22213#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21835#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21836#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22255#L631 assume 1 == ~t2_pc~0; 22190#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21612#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21613#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22449#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 22450#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21908#L650 assume !(1 == ~t3_pc~0); 21909#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 22609#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21832#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21565#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 21566#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22758#L669 assume 1 == ~t4_pc~0; 22759#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 23117#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22242#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21774#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 21775#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21999#L688 assume !(1 == ~t5_pc~0); 21790#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 21791#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22709#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22643#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 22644#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22776#L707 assume 1 == ~t6_pc~0; 23182#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 22419#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22420#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23180#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 22715#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22277#L726 assume 1 == ~t7_pc~0; 22178#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21875#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22916#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 23190#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 21644#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21645#L745 assume !(1 == ~t8_pc~0); 22092#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22111#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22949#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22497#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 22498#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 23008#L764 assume 1 == ~t9_pc~0; 22275#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22117#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22794#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 23241#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 21664#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21665#L783 assume !(1 == ~t10_pc~0); 21726#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 21727#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21768#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21769#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 22236#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 23119#L802 assume 1 == ~t11_pc~0; 23101#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 21609#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21610#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 22102#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 22103#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 22212#L821 assume !(1 == ~t12_pc~0); 22463#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 22559#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21616#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 21617#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 23157#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22803#L1339 assume !(1 == ~M_E~0); 22804#L1339-2 assume !(1 == ~T1_E~0); 23192#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23193#L1349-1 assume !(1 == ~T3_E~0); 22578#L1354-1 assume !(1 == ~T4_E~0); 22579#L1359-1 assume !(1 == ~T5_E~0); 22979#L1364-1 assume !(1 == ~T6_E~0); 22042#L1369-1 assume !(1 == ~T7_E~0); 22043#L1374-1 assume !(1 == ~T8_E~0); 22580#L1379-1 assume !(1 == ~T9_E~0); 22581#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22680#L1389-1 assume !(1 == ~T11_E~0); 23151#L1394-1 assume !(1 == ~T12_E~0); 23152#L1399-1 assume !(1 == ~E_M~0); 23242#L1404-1 assume !(1 == ~E_1~0); 22141#L1409-1 assume !(1 == ~E_2~0); 22142#L1414-1 assume !(1 == ~E_3~0); 22868#L1419-1 assume !(1 == ~E_4~0); 21782#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 21783#L1429-1 assume !(1 == ~E_6~0); 22593#L1434-1 assume !(1 == ~E_7~0); 23172#L1439-1 assume !(1 == ~E_8~0); 21820#L1444-1 assume !(1 == ~E_9~0); 21821#L1449-1 assume !(1 == ~E_10~0); 22195#L1454-1 assume !(1 == ~E_11~0); 22196#L1459-1 assume !(1 == ~E_12~0); 22714#L1464-1 assume { :end_inline_reset_delta_events } true; 21954#L1810-2 [2022-07-22 02:43:03,676 INFO L754 eck$LassoCheckResult]: Loop: 21954#L1810-2 assume !false; 22398#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22314#L1176 assume !false; 22876#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22448#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 21652#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 22202#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 22203#L1003 assume !(0 != eval_~tmp~0#1); 21844#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21845#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 23035#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22818#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22819#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22712#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21903#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21904#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22370#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 21976#L1231-3 assume !(0 == ~T7_E~0); 21977#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 22223#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 23203#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 23105#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 22809#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 21920#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 21921#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21966#L1271-3 assume !(0 == ~E_2~0); 21967#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22343#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22344#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22866#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22867#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 23281#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23238#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 22455#L1311-3 assume !(0 == ~E_10~0); 21846#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 21847#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 21922#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22558#L593-42 assume 1 == ~m_pc~0; 22952#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22717#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23266#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23267#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21748#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21749#L612-42 assume !(1 == ~t1_pc~0); 22667#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 23060#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23181#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21833#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21834#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22528#L631-42 assume !(1 == ~t2_pc~0); 21600#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 21599#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22516#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22394#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22395#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21992#L650-42 assume 1 == ~t3_pc~0; 21557#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21558#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23209#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22188#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22189#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23173#L669-42 assume !(1 == ~t4_pc~0); 21553#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 21554#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22984#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22874#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 22771#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22772#L688-42 assume !(1 == ~t5_pc~0); 22864#L688-44 is_transmit5_triggered_~__retres1~5#1 := 0; 23064#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21696#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21697#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21770#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21585#L707-42 assume !(1 == ~t6_pc~0); 21586#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 23245#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22989#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22990#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22739#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22740#L726-42 assume 1 == ~t7_pc~0; 23017#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23043#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23044#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22458#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22459#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22562#L745-42 assume 1 == ~t8_pc~0; 22598#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22600#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21928#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21573#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21574#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22299#L764-42 assume 1 == ~t9_pc~0; 22435#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22788#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22789#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21859#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21860#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21913#L783-42 assume 1 == ~t10_pc~0; 21529#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21530#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22125#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 22258#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 23275#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22959#L802-42 assume 1 == ~t11_pc~0; 22060#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 21671#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21672#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 21622#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 21623#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 22799#L821-42 assume 1 == ~t12_pc~0; 22800#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 22165#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21525#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 21526#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 22505#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22495#L1339-3 assume !(1 == ~M_E~0); 22496#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22647#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22757#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22174#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22175#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22768#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23264#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23171#L1374-3 assume !(1 == ~T8_E~0); 21996#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21997#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22172#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 22173#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 22382#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 23178#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 23146#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23147#L1414-3 assume !(1 == ~E_3~0); 23202#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22961#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21880#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21881#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22767#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21808#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 21809#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 21925#L1454-3 assume !(1 == ~E_11~0); 22762#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 22763#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22421#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 21718#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 21978#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 21979#L1829 assume !(0 == start_simulation_~tmp~3#1); 21700#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 21701#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 22501#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 22502#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 22781#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22782#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22402#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 21953#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 21954#L1810-2 [2022-07-22 02:43:03,676 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:03,676 INFO L85 PathProgramCache]: Analyzing trace with hash -563283220, now seen corresponding path program 1 times [2022-07-22 02:43:03,676 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:03,677 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [617208745] [2022-07-22 02:43:03,677 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:03,677 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:03,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:03,699 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:03,700 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:03,700 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [617208745] [2022-07-22 02:43:03,700 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [617208745] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:03,700 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:03,700 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:03,701 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [549575082] [2022-07-22 02:43:03,701 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:03,701 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:43:03,701 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:03,702 INFO L85 PathProgramCache]: Analyzing trace with hash -1685871596, now seen corresponding path program 1 times [2022-07-22 02:43:03,702 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:03,702 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1914411469] [2022-07-22 02:43:03,702 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:03,702 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:03,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:03,732 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:03,732 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:03,732 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1914411469] [2022-07-22 02:43:03,733 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1914411469] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:03,733 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:03,733 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:03,733 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [246326825] [2022-07-22 02:43:03,733 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:03,734 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:43:03,734 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:43:03,734 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:43:03,734 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:43:03,734 INFO L87 Difference]: Start difference. First operand 1788 states and 2646 transitions. cyclomatic complexity: 859 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:03,756 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:43:03,757 INFO L93 Difference]: Finished difference Result 1788 states and 2645 transitions. [2022-07-22 02:43:03,757 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:43:03,758 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2645 transitions. [2022-07-22 02:43:03,765 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-07-22 02:43:03,771 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2645 transitions. [2022-07-22 02:43:03,772 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2022-07-22 02:43:03,773 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2022-07-22 02:43:03,773 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2645 transitions. [2022-07-22 02:43:03,775 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:43:03,775 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2645 transitions. [2022-07-22 02:43:03,776 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2645 transitions. [2022-07-22 02:43:03,791 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2022-07-22 02:43:03,793 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4793064876957494) internal successors, (2645), 1787 states have internal predecessors, (2645), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:03,797 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2645 transitions. [2022-07-22 02:43:03,798 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2645 transitions. [2022-07-22 02:43:03,798 INFO L374 stractBuchiCegarLoop]: Abstraction has 1788 states and 2645 transitions. [2022-07-22 02:43:03,798 INFO L287 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-07-22 02:43:03,798 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2645 transitions. [2022-07-22 02:43:03,803 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-07-22 02:43:03,803 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:43:03,803 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:43:03,805 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:03,805 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:03,805 INFO L752 eck$LassoCheckResult]: Stem: 25886#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 25887#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 25407#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25408#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25462#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 26801#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25895#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25698#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25097#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25098#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26320#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26431#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 26867#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 26868#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25826#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 25827#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 26349#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 26268#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 25861#L1201 assume !(0 == ~M_E~0); 25862#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26708#L1206-1 assume !(0 == ~T2_E~0); 26694#L1211-1 assume !(0 == ~T3_E~0); 26695#L1216-1 assume !(0 == ~T4_E~0); 25683#L1221-1 assume !(0 == ~T5_E~0); 25684#L1226-1 assume !(0 == ~T6_E~0); 25322#L1231-1 assume !(0 == ~T7_E~0); 25323#L1236-1 assume !(0 == ~T8_E~0); 26731#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25719#L1246-1 assume !(0 == ~T10_E~0); 25720#L1251-1 assume !(0 == ~T11_E~0); 25859#L1256-1 assume !(0 == ~T12_E~0); 25110#L1261-1 assume !(0 == ~E_M~0); 25111#L1266-1 assume !(0 == ~E_1~0); 26853#L1271-1 assume !(0 == ~E_2~0); 26415#L1276-1 assume !(0 == ~E_3~0); 26416#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 26363#L1286-1 assume !(0 == ~E_5~0); 25573#L1291-1 assume !(0 == ~E_6~0); 25574#L1296-1 assume !(0 == ~E_7~0); 26149#L1301-1 assume !(0 == ~E_8~0); 26150#L1306-1 assume !(0 == ~E_9~0); 26630#L1311-1 assume !(0 == ~E_10~0); 25524#L1316-1 assume !(0 == ~E_11~0); 25525#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 26167#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26168#L593 assume 1 == ~m_pc~0; 26312#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25414#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26840#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26374#L1492 assume !(0 != activate_threads_~tmp~1#1); 26375#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26666#L612 assume !(1 == ~t1_pc~0); 26667#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 26796#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25796#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25418#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25419#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25838#L631 assume 1 == ~t2_pc~0; 25773#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25195#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25196#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26032#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 26033#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25491#L650 assume !(1 == ~t3_pc~0); 25492#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 26192#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25415#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25148#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 25149#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26341#L669 assume 1 == ~t4_pc~0; 26342#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 26700#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25825#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25357#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 25358#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25582#L688 assume !(1 == ~t5_pc~0); 25373#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 25374#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26292#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26226#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 26227#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26359#L707 assume 1 == ~t6_pc~0; 26765#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26002#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26003#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26763#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 26298#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25860#L726 assume 1 == ~t7_pc~0; 25761#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25458#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26499#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26773#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 25227#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25228#L745 assume !(1 == ~t8_pc~0); 25675#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 25694#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26532#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26080#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 26081#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26591#L764 assume 1 == ~t9_pc~0; 25858#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25700#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26377#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26824#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 25247#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25248#L783 assume !(1 == ~t10_pc~0); 25309#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25310#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25351#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25352#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 25816#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26702#L802 assume 1 == ~t11_pc~0; 26684#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25192#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25193#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25685#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 25686#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25795#L821 assume !(1 == ~t12_pc~0); 26046#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 26142#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 25199#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 25200#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 26740#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26386#L1339 assume !(1 == ~M_E~0); 26387#L1339-2 assume !(1 == ~T1_E~0); 26775#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26776#L1349-1 assume !(1 == ~T3_E~0); 26161#L1354-1 assume !(1 == ~T4_E~0); 26162#L1359-1 assume !(1 == ~T5_E~0); 26562#L1364-1 assume !(1 == ~T6_E~0); 25625#L1369-1 assume !(1 == ~T7_E~0); 25626#L1374-1 assume !(1 == ~T8_E~0); 26163#L1379-1 assume !(1 == ~T9_E~0); 26164#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 26263#L1389-1 assume !(1 == ~T11_E~0); 26734#L1394-1 assume !(1 == ~T12_E~0); 26735#L1399-1 assume !(1 == ~E_M~0); 26825#L1404-1 assume !(1 == ~E_1~0); 25724#L1409-1 assume !(1 == ~E_2~0); 25725#L1414-1 assume !(1 == ~E_3~0); 26451#L1419-1 assume !(1 == ~E_4~0); 25365#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 25366#L1429-1 assume !(1 == ~E_6~0); 26176#L1434-1 assume !(1 == ~E_7~0); 26755#L1439-1 assume !(1 == ~E_8~0); 25403#L1444-1 assume !(1 == ~E_9~0); 25404#L1449-1 assume !(1 == ~E_10~0); 25778#L1454-1 assume !(1 == ~E_11~0); 25779#L1459-1 assume !(1 == ~E_12~0); 26297#L1464-1 assume { :end_inline_reset_delta_events } true; 25537#L1810-2 [2022-07-22 02:43:03,806 INFO L754 eck$LassoCheckResult]: Loop: 25537#L1810-2 assume !false; 25981#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25897#L1176 assume !false; 26459#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 26029#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25235#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25785#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 25786#L1003 assume !(0 != eval_~tmp~0#1); 25427#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25428#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 26618#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26401#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26402#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26295#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25486#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25487#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25953#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25557#L1231-3 assume !(0 == ~T7_E~0); 25558#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25806#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 26786#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 26687#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 26392#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 25503#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25504#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25549#L1271-3 assume !(0 == ~E_2~0); 25550#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25926#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 25927#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26449#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 26450#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 26864#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 26821#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 26038#L1311-3 assume !(0 == ~E_10~0); 25429#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 25430#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 25505#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26141#L593-42 assume 1 == ~m_pc~0; 26535#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 26300#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26849#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26850#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25328#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25329#L612-42 assume !(1 == ~t1_pc~0); 26250#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 26643#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26764#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25416#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25417#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26112#L631-42 assume 1 == ~t2_pc~0; 25184#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25185#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26101#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25977#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25978#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25578#L650-42 assume 1 == ~t3_pc~0; 25143#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25144#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26792#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25771#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25772#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26756#L669-42 assume !(1 == ~t4_pc~0); 25138#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 25139#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26567#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26457#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 26354#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26355#L688-42 assume 1 == ~t5_pc~0; 26446#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26647#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25281#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25282#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25356#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25170#L707-42 assume !(1 == ~t6_pc~0); 25171#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 26830#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26572#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26573#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26321#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26322#L726-42 assume 1 == ~t7_pc~0; 26598#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26626#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26627#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26041#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 26042#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26145#L745-42 assume 1 == ~t8_pc~0; 26181#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 26183#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25509#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25156#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25157#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25882#L764-42 assume 1 == ~t9_pc~0; 26018#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 26371#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26372#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25442#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 25443#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25496#L783-42 assume 1 == ~t10_pc~0; 25112#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 25113#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25708#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25841#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 26858#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26542#L802-42 assume 1 == ~t11_pc~0; 25641#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25254#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25255#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25205#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 25206#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 26382#L821-42 assume !(1 == ~t12_pc~0); 25747#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 25748#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 25108#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 25109#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 26088#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26075#L1339-3 assume !(1 == ~M_E~0); 26076#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26230#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26340#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25757#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25758#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 26351#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26847#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26754#L1374-3 assume !(1 == ~T8_E~0); 25579#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25580#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25755#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25756#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 25965#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 26761#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 26729#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26730#L1414-3 assume !(1 == ~E_3~0); 26785#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 26544#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25463#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 25464#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 26350#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25391#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 25392#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 25508#L1454-3 assume !(1 == ~E_11~0); 26345#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 26346#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 26004#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25301#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25561#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 25562#L1829 assume !(0 == start_simulation_~tmp~3#1); 25283#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 25284#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 26084#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 26085#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 26364#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26365#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25985#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 25536#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 25537#L1810-2 [2022-07-22 02:43:03,806 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:03,806 INFO L85 PathProgramCache]: Analyzing trace with hash -973893586, now seen corresponding path program 1 times [2022-07-22 02:43:03,807 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:03,807 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [934430178] [2022-07-22 02:43:03,807 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:03,807 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:03,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:03,829 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:03,829 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:03,830 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [934430178] [2022-07-22 02:43:03,830 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [934430178] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:03,830 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:03,830 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:03,830 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2066583180] [2022-07-22 02:43:03,830 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:03,831 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:43:03,831 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:03,831 INFO L85 PathProgramCache]: Analyzing trace with hash -1361569005, now seen corresponding path program 1 times [2022-07-22 02:43:03,831 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:03,832 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [780391702] [2022-07-22 02:43:03,832 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:03,832 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:03,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:03,860 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:03,860 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:03,861 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [780391702] [2022-07-22 02:43:03,861 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [780391702] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:03,861 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:03,861 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:03,861 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1653663385] [2022-07-22 02:43:03,861 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:03,862 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:43:03,862 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:43:03,862 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:43:03,862 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:43:03,862 INFO L87 Difference]: Start difference. First operand 1788 states and 2645 transitions. cyclomatic complexity: 858 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:03,883 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:43:03,883 INFO L93 Difference]: Finished difference Result 1788 states and 2644 transitions. [2022-07-22 02:43:03,884 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:43:03,884 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2644 transitions. [2022-07-22 02:43:03,894 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-07-22 02:43:03,904 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2644 transitions. [2022-07-22 02:43:03,904 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2022-07-22 02:43:03,906 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2022-07-22 02:43:03,906 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2644 transitions. [2022-07-22 02:43:03,908 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:43:03,909 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2644 transitions. [2022-07-22 02:43:03,911 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2644 transitions. [2022-07-22 02:43:03,930 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2022-07-22 02:43:03,933 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4787472035794182) internal successors, (2644), 1787 states have internal predecessors, (2644), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:03,939 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2644 transitions. [2022-07-22 02:43:03,939 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2644 transitions. [2022-07-22 02:43:03,939 INFO L374 stractBuchiCegarLoop]: Abstraction has 1788 states and 2644 transitions. [2022-07-22 02:43:03,939 INFO L287 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-07-22 02:43:03,939 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2644 transitions. [2022-07-22 02:43:03,946 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-07-22 02:43:03,946 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:43:03,946 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:43:03,948 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:03,948 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:03,948 INFO L752 eck$LassoCheckResult]: Stem: 29469#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 29470#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 28990#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28991#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29045#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 30384#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29478#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29281#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28680#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28681#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29903#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30014#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 30450#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 30451#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29409#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 29410#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 29932#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 29851#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29444#L1201 assume !(0 == ~M_E~0); 29445#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30291#L1206-1 assume !(0 == ~T2_E~0); 30277#L1211-1 assume !(0 == ~T3_E~0); 30278#L1216-1 assume !(0 == ~T4_E~0); 29265#L1221-1 assume !(0 == ~T5_E~0); 29266#L1226-1 assume !(0 == ~T6_E~0); 28905#L1231-1 assume !(0 == ~T7_E~0); 28906#L1236-1 assume !(0 == ~T8_E~0); 30314#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29302#L1246-1 assume !(0 == ~T10_E~0); 29303#L1251-1 assume !(0 == ~T11_E~0); 29442#L1256-1 assume !(0 == ~T12_E~0); 28691#L1261-1 assume !(0 == ~E_M~0); 28692#L1266-1 assume !(0 == ~E_1~0); 30436#L1271-1 assume !(0 == ~E_2~0); 29998#L1276-1 assume !(0 == ~E_3~0); 29999#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 29946#L1286-1 assume !(0 == ~E_5~0); 29156#L1291-1 assume !(0 == ~E_6~0); 29157#L1296-1 assume !(0 == ~E_7~0); 29732#L1301-1 assume !(0 == ~E_8~0); 29733#L1306-1 assume !(0 == ~E_9~0); 30213#L1311-1 assume !(0 == ~E_10~0); 29107#L1316-1 assume !(0 == ~E_11~0); 29108#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 29750#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29751#L593 assume 1 == ~m_pc~0; 29895#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 28997#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30423#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29957#L1492 assume !(0 != activate_threads_~tmp~1#1); 29958#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30249#L612 assume !(1 == ~t1_pc~0); 30250#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 30379#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29379#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29001#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29002#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29421#L631 assume 1 == ~t2_pc~0; 29356#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28778#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28779#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29615#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 29616#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29074#L650 assume !(1 == ~t3_pc~0); 29075#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29775#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28998#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28731#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 28732#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29924#L669 assume 1 == ~t4_pc~0; 29925#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30283#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29408#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28940#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 28941#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29165#L688 assume !(1 == ~t5_pc~0); 28956#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 28957#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29875#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29809#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 29810#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29939#L707 assume 1 == ~t6_pc~0; 30348#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29585#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29586#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30346#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 29881#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29443#L726 assume 1 == ~t7_pc~0; 29342#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29041#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30082#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30356#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 28810#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28811#L745 assume !(1 == ~t8_pc~0); 29258#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 29277#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30115#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29663#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29664#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30174#L764 assume 1 == ~t9_pc~0; 29441#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29283#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29960#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 30407#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 28830#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28831#L783 assume !(1 == ~t10_pc~0); 28892#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 28893#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28934#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 28935#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 29397#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30285#L802 assume 1 == ~t11_pc~0; 30267#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 28775#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28776#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 29267#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 29268#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29378#L821 assume !(1 == ~t12_pc~0); 29629#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 29725#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28780#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 28781#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 30323#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29969#L1339 assume !(1 == ~M_E~0); 29970#L1339-2 assume !(1 == ~T1_E~0); 30358#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30359#L1349-1 assume !(1 == ~T3_E~0); 29743#L1354-1 assume !(1 == ~T4_E~0); 29744#L1359-1 assume !(1 == ~T5_E~0); 30145#L1364-1 assume !(1 == ~T6_E~0); 29208#L1369-1 assume !(1 == ~T7_E~0); 29209#L1374-1 assume !(1 == ~T8_E~0); 29746#L1379-1 assume !(1 == ~T9_E~0); 29747#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29846#L1389-1 assume !(1 == ~T11_E~0); 30317#L1394-1 assume !(1 == ~T12_E~0); 30318#L1399-1 assume !(1 == ~E_M~0); 30408#L1404-1 assume !(1 == ~E_1~0); 29307#L1409-1 assume !(1 == ~E_2~0); 29308#L1414-1 assume !(1 == ~E_3~0); 30034#L1419-1 assume !(1 == ~E_4~0); 28948#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 28949#L1429-1 assume !(1 == ~E_6~0); 29759#L1434-1 assume !(1 == ~E_7~0); 30338#L1439-1 assume !(1 == ~E_8~0); 28986#L1444-1 assume !(1 == ~E_9~0); 28987#L1449-1 assume !(1 == ~E_10~0); 29361#L1454-1 assume !(1 == ~E_11~0); 29362#L1459-1 assume !(1 == ~E_12~0); 29880#L1464-1 assume { :end_inline_reset_delta_events } true; 29120#L1810-2 [2022-07-22 02:43:03,949 INFO L754 eck$LassoCheckResult]: Loop: 29120#L1810-2 assume !false; 29564#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29480#L1176 assume !false; 30042#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 29612#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 28818#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 29368#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 29369#L1003 assume !(0 != eval_~tmp~0#1); 29010#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29011#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30201#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 29984#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29985#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29878#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29069#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29070#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29536#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 29140#L1231-3 assume !(0 == ~T7_E~0); 29141#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29387#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 30369#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 30270#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 29975#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 29086#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29087#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29132#L1271-3 assume !(0 == ~E_2~0); 29133#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29509#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 29510#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30031#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30032#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30447#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 30404#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 29621#L1311-3 assume !(0 == ~E_10~0); 29012#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 29013#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 29088#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29724#L593-42 assume 1 == ~m_pc~0; 30117#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29883#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30432#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30433#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28911#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28912#L612-42 assume !(1 == ~t1_pc~0); 29833#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 30226#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30347#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28999#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29000#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29695#L631-42 assume 1 == ~t2_pc~0; 28764#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28765#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29684#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29560#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29561#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29161#L650-42 assume 1 == ~t3_pc~0; 28723#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 28724#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30375#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29354#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29355#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30339#L669-42 assume !(1 == ~t4_pc~0); 28721#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 28722#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30150#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30040#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 29937#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29938#L688-42 assume 1 == ~t5_pc~0; 30029#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30230#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28862#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28863#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 28939#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28753#L707-42 assume !(1 == ~t6_pc~0); 28754#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 30411#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 30155#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30156#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29905#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29906#L726-42 assume 1 == ~t7_pc~0; 30183#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30209#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30210#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29624#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29625#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29728#L745-42 assume 1 == ~t8_pc~0; 29765#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 29767#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29094#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28739#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 28740#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29465#L764-42 assume 1 == ~t9_pc~0; 29601#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29954#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29955#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29025#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 29026#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29079#L783-42 assume 1 == ~t10_pc~0; 28695#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 28696#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29291#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29424#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 30441#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30125#L802-42 assume 1 == ~t11_pc~0; 29226#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 28837#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28838#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28788#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 28789#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29965#L821-42 assume !(1 == ~t12_pc~0); 29330#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 29331#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28693#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 28694#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 29671#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29661#L1339-3 assume !(1 == ~M_E~0); 29662#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29813#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29923#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29340#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29341#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 29934#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30430#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30337#L1374-3 assume !(1 == ~T8_E~0); 29162#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 29163#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29338#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29339#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 29548#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 30344#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30312#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30313#L1414-3 assume !(1 == ~E_3~0); 30368#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30127#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29046#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 29047#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 29933#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28974#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 28975#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 29091#L1454-3 assume !(1 == ~E_11~0); 29928#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 29929#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 29587#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 28884#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 29144#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 29145#L1829 assume !(0 == start_simulation_~tmp~3#1); 28866#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 28867#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 29667#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 29668#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 29947#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 29948#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 29568#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 29119#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 29120#L1810-2 [2022-07-22 02:43:03,949 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:03,950 INFO L85 PathProgramCache]: Analyzing trace with hash 813976236, now seen corresponding path program 1 times [2022-07-22 02:43:03,950 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:03,950 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [924602774] [2022-07-22 02:43:03,950 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:03,950 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:03,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:03,977 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:03,977 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:03,977 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [924602774] [2022-07-22 02:43:03,978 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [924602774] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:03,978 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:03,978 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:03,978 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1011680366] [2022-07-22 02:43:03,978 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:03,979 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:43:03,979 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:03,979 INFO L85 PathProgramCache]: Analyzing trace with hash -1361569005, now seen corresponding path program 2 times [2022-07-22 02:43:03,979 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:03,979 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1594992140] [2022-07-22 02:43:03,979 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:03,980 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:04,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:04,035 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:04,036 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:04,036 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1594992140] [2022-07-22 02:43:04,036 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1594992140] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:04,036 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:04,036 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:04,037 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1123680363] [2022-07-22 02:43:04,037 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:04,037 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:43:04,037 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:43:04,038 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:43:04,038 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:43:04,038 INFO L87 Difference]: Start difference. First operand 1788 states and 2644 transitions. cyclomatic complexity: 857 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:04,059 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:43:04,060 INFO L93 Difference]: Finished difference Result 1788 states and 2643 transitions. [2022-07-22 02:43:04,060 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:43:04,061 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2643 transitions. [2022-07-22 02:43:04,070 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-07-22 02:43:04,075 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2643 transitions. [2022-07-22 02:43:04,076 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2022-07-22 02:43:04,077 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2022-07-22 02:43:04,077 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2643 transitions. [2022-07-22 02:43:04,078 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:43:04,078 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2643 transitions. [2022-07-22 02:43:04,080 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2643 transitions. [2022-07-22 02:43:04,094 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2022-07-22 02:43:04,096 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4781879194630871) internal successors, (2643), 1787 states have internal predecessors, (2643), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:04,100 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2643 transitions. [2022-07-22 02:43:04,100 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2643 transitions. [2022-07-22 02:43:04,100 INFO L374 stractBuchiCegarLoop]: Abstraction has 1788 states and 2643 transitions. [2022-07-22 02:43:04,100 INFO L287 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-07-22 02:43:04,101 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2643 transitions. [2022-07-22 02:43:04,105 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-07-22 02:43:04,105 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:43:04,106 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:43:04,107 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:04,107 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:04,107 INFO L752 eck$LassoCheckResult]: Stem: 33052#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 33053#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 32573#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 32574#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 32628#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 33967#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33061#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32864#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32263#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32264#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33486#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33597#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 34033#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 34034#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 32992#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 32993#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 33515#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 33434#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33027#L1201 assume !(0 == ~M_E~0); 33028#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33874#L1206-1 assume !(0 == ~T2_E~0); 33860#L1211-1 assume !(0 == ~T3_E~0); 33861#L1216-1 assume !(0 == ~T4_E~0); 32848#L1221-1 assume !(0 == ~T5_E~0); 32849#L1226-1 assume !(0 == ~T6_E~0); 32488#L1231-1 assume !(0 == ~T7_E~0); 32489#L1236-1 assume !(0 == ~T8_E~0); 33897#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 32885#L1246-1 assume !(0 == ~T10_E~0); 32886#L1251-1 assume !(0 == ~T11_E~0); 33025#L1256-1 assume !(0 == ~T12_E~0); 32274#L1261-1 assume !(0 == ~E_M~0); 32275#L1266-1 assume !(0 == ~E_1~0); 34019#L1271-1 assume !(0 == ~E_2~0); 33581#L1276-1 assume !(0 == ~E_3~0); 33582#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 33529#L1286-1 assume !(0 == ~E_5~0); 32739#L1291-1 assume !(0 == ~E_6~0); 32740#L1296-1 assume !(0 == ~E_7~0); 33315#L1301-1 assume !(0 == ~E_8~0); 33316#L1306-1 assume !(0 == ~E_9~0); 33796#L1311-1 assume !(0 == ~E_10~0); 32690#L1316-1 assume !(0 == ~E_11~0); 32691#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 33333#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33334#L593 assume 1 == ~m_pc~0; 33478#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 32580#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34006#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33540#L1492 assume !(0 != activate_threads_~tmp~1#1); 33541#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33832#L612 assume !(1 == ~t1_pc~0); 33833#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 33962#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32962#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32584#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32585#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33004#L631 assume 1 == ~t2_pc~0; 32939#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32361#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32362#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33198#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 33199#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32657#L650 assume !(1 == ~t3_pc~0); 32658#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33358#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32581#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32314#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 32315#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33507#L669 assume 1 == ~t4_pc~0; 33508#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33866#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32991#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32523#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 32524#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32748#L688 assume !(1 == ~t5_pc~0); 32539#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 32540#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33458#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33392#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 33393#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33522#L707 assume 1 == ~t6_pc~0; 33931#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33168#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33169#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33929#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 33464#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33026#L726 assume 1 == ~t7_pc~0; 32925#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 32624#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33665#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33939#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 32393#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32394#L745 assume !(1 == ~t8_pc~0); 32841#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 32860#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33698#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33246#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 33247#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33757#L764 assume 1 == ~t9_pc~0; 33024#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32866#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33543#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33990#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 32413#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32414#L783 assume !(1 == ~t10_pc~0); 32475#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 32476#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32517#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 32518#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 32980#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 33868#L802 assume 1 == ~t11_pc~0; 33850#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32358#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32359#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32850#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 32851#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 32961#L821 assume !(1 == ~t12_pc~0); 33212#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 33308#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32363#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 32364#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 33906#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33552#L1339 assume !(1 == ~M_E~0); 33553#L1339-2 assume !(1 == ~T1_E~0); 33941#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33942#L1349-1 assume !(1 == ~T3_E~0); 33326#L1354-1 assume !(1 == ~T4_E~0); 33327#L1359-1 assume !(1 == ~T5_E~0); 33728#L1364-1 assume !(1 == ~T6_E~0); 32791#L1369-1 assume !(1 == ~T7_E~0); 32792#L1374-1 assume !(1 == ~T8_E~0); 33329#L1379-1 assume !(1 == ~T9_E~0); 33330#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 33429#L1389-1 assume !(1 == ~T11_E~0); 33900#L1394-1 assume !(1 == ~T12_E~0); 33901#L1399-1 assume !(1 == ~E_M~0); 33991#L1404-1 assume !(1 == ~E_1~0); 32890#L1409-1 assume !(1 == ~E_2~0); 32891#L1414-1 assume !(1 == ~E_3~0); 33617#L1419-1 assume !(1 == ~E_4~0); 32531#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 32532#L1429-1 assume !(1 == ~E_6~0); 33342#L1434-1 assume !(1 == ~E_7~0); 33921#L1439-1 assume !(1 == ~E_8~0); 32569#L1444-1 assume !(1 == ~E_9~0); 32570#L1449-1 assume !(1 == ~E_10~0); 32944#L1454-1 assume !(1 == ~E_11~0); 32945#L1459-1 assume !(1 == ~E_12~0); 33463#L1464-1 assume { :end_inline_reset_delta_events } true; 32703#L1810-2 [2022-07-22 02:43:04,108 INFO L754 eck$LassoCheckResult]: Loop: 32703#L1810-2 assume !false; 33147#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33063#L1176 assume !false; 33625#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 33195#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 32401#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 32951#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 32952#L1003 assume !(0 != eval_~tmp~0#1); 32593#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 32594#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33784#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 33567#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33568#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 33461#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32652#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32653#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 33119#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32723#L1231-3 assume !(0 == ~T7_E~0); 32724#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32970#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 33952#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 33853#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 33558#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 32669#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 32670#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32715#L1271-3 assume !(0 == ~E_2~0); 32716#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33092#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 33093#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 33614#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 33615#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 34030#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 33987#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 33204#L1311-3 assume !(0 == ~E_10~0); 32595#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32596#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 32671#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33307#L593-42 assume 1 == ~m_pc~0; 33700#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 33466#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34015#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 34016#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 32494#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32495#L612-42 assume !(1 == ~t1_pc~0); 33416#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 33809#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33930#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32582#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32583#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33278#L631-42 assume 1 == ~t2_pc~0; 32347#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32348#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33267#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33143#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33144#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32744#L650-42 assume 1 == ~t3_pc~0; 32306#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 32307#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33958#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32937#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 32938#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33922#L669-42 assume !(1 == ~t4_pc~0); 32304#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 32305#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33733#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33623#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 33520#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33521#L688-42 assume 1 == ~t5_pc~0; 33612#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33813#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32445#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32446#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 32522#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32336#L707-42 assume !(1 == ~t6_pc~0); 32337#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 33994#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33738#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33739#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 33488#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33489#L726-42 assume 1 == ~t7_pc~0; 33766#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 33792#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33793#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33207#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 33208#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33311#L745-42 assume 1 == ~t8_pc~0; 33348#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33350#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32677#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32322#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32323#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33048#L764-42 assume 1 == ~t9_pc~0; 33184#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33537#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33538#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32608#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 32609#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32662#L783-42 assume 1 == ~t10_pc~0; 32278#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 32279#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32874#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33007#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 34024#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 33708#L802-42 assume 1 == ~t11_pc~0; 32809#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32420#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32421#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32371#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 32372#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33548#L821-42 assume !(1 == ~t12_pc~0); 32913#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 32914#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32276#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 32277#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 33254#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33244#L1339-3 assume !(1 == ~M_E~0); 33245#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33396#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33506#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32923#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 32924#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 33517#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34013#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 33920#L1374-3 assume !(1 == ~T8_E~0); 32745#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 32746#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 32921#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 32922#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 33131#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 33927#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 33895#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 33896#L1414-3 assume !(1 == ~E_3~0); 33951#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33710#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32629#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32630#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 33516#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 32557#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 32558#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 32674#L1454-3 assume !(1 == ~E_11~0); 33511#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 33512#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 33170#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 32467#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 32727#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 32728#L1829 assume !(0 == start_simulation_~tmp~3#1); 32449#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 32450#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 33250#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 33251#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 33530#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 33531#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 33151#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 32702#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 32703#L1810-2 [2022-07-22 02:43:04,108 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:04,108 INFO L85 PathProgramCache]: Analyzing trace with hash -1345107858, now seen corresponding path program 1 times [2022-07-22 02:43:04,109 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:04,109 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1088932506] [2022-07-22 02:43:04,109 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:04,109 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:04,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:04,130 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:04,130 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:04,130 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1088932506] [2022-07-22 02:43:04,130 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1088932506] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:04,131 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:04,131 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:04,131 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1560957841] [2022-07-22 02:43:04,131 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:04,131 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:43:04,132 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:04,132 INFO L85 PathProgramCache]: Analyzing trace with hash -1361569005, now seen corresponding path program 3 times [2022-07-22 02:43:04,132 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:04,132 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2047147831] [2022-07-22 02:43:04,132 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:04,132 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:04,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:04,168 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:04,169 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:04,169 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2047147831] [2022-07-22 02:43:04,169 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2047147831] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:04,169 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:04,169 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:04,169 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [822743901] [2022-07-22 02:43:04,170 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:04,170 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:43:04,170 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:43:04,170 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:43:04,171 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:43:04,171 INFO L87 Difference]: Start difference. First operand 1788 states and 2643 transitions. cyclomatic complexity: 856 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:04,197 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:43:04,197 INFO L93 Difference]: Finished difference Result 1788 states and 2642 transitions. [2022-07-22 02:43:04,198 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:43:04,198 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2642 transitions. [2022-07-22 02:43:04,207 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-07-22 02:43:04,215 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2642 transitions. [2022-07-22 02:43:04,216 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2022-07-22 02:43:04,217 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2022-07-22 02:43:04,217 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2642 transitions. [2022-07-22 02:43:04,220 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:43:04,220 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2642 transitions. [2022-07-22 02:43:04,222 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2642 transitions. [2022-07-22 02:43:04,242 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2022-07-22 02:43:04,245 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4776286353467563) internal successors, (2642), 1787 states have internal predecessors, (2642), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:04,251 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2642 transitions. [2022-07-22 02:43:04,251 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2642 transitions. [2022-07-22 02:43:04,251 INFO L374 stractBuchiCegarLoop]: Abstraction has 1788 states and 2642 transitions. [2022-07-22 02:43:04,251 INFO L287 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-07-22 02:43:04,251 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2642 transitions. [2022-07-22 02:43:04,258 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-07-22 02:43:04,258 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:43:04,259 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:43:04,260 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:04,261 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:04,261 INFO L752 eck$LassoCheckResult]: Stem: 36635#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 36636#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 36156#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 36157#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36211#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 37550#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36644#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36447#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35846#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35847#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 37069#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 37180#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 37616#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 37617#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 36575#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 36576#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 37098#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 37017#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36610#L1201 assume !(0 == ~M_E~0); 36611#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37457#L1206-1 assume !(0 == ~T2_E~0); 37443#L1211-1 assume !(0 == ~T3_E~0); 37444#L1216-1 assume !(0 == ~T4_E~0); 36431#L1221-1 assume !(0 == ~T5_E~0); 36432#L1226-1 assume !(0 == ~T6_E~0); 36071#L1231-1 assume !(0 == ~T7_E~0); 36072#L1236-1 assume !(0 == ~T8_E~0); 37480#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 36468#L1246-1 assume !(0 == ~T10_E~0); 36469#L1251-1 assume !(0 == ~T11_E~0); 36608#L1256-1 assume !(0 == ~T12_E~0); 35857#L1261-1 assume !(0 == ~E_M~0); 35858#L1266-1 assume !(0 == ~E_1~0); 37602#L1271-1 assume !(0 == ~E_2~0); 37164#L1276-1 assume !(0 == ~E_3~0); 37165#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 37112#L1286-1 assume !(0 == ~E_5~0); 36322#L1291-1 assume !(0 == ~E_6~0); 36323#L1296-1 assume !(0 == ~E_7~0); 36898#L1301-1 assume !(0 == ~E_8~0); 36899#L1306-1 assume !(0 == ~E_9~0); 37379#L1311-1 assume !(0 == ~E_10~0); 36273#L1316-1 assume !(0 == ~E_11~0); 36274#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 36916#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36917#L593 assume 1 == ~m_pc~0; 37061#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 36163#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37589#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37123#L1492 assume !(0 != activate_threads_~tmp~1#1); 37124#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37415#L612 assume !(1 == ~t1_pc~0); 37416#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 37545#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36545#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36167#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36168#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36587#L631 assume 1 == ~t2_pc~0; 36522#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35944#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35945#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36781#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 36782#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36240#L650 assume !(1 == ~t3_pc~0); 36241#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 36941#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36164#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35897#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 35898#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37090#L669 assume 1 == ~t4_pc~0; 37091#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37449#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36574#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36106#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 36107#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36331#L688 assume !(1 == ~t5_pc~0); 36122#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 36123#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37041#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36975#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 36976#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37105#L707 assume 1 == ~t6_pc~0; 37514#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 36751#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36752#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37512#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 37047#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36609#L726 assume 1 == ~t7_pc~0; 36508#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36207#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37248#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37522#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 35976#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35977#L745 assume !(1 == ~t8_pc~0); 36424#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 36443#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37281#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36829#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36830#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37340#L764 assume 1 == ~t9_pc~0; 36607#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36449#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37126#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37573#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 35996#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35997#L783 assume !(1 == ~t10_pc~0); 36058#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 36059#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36100#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 36101#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 36563#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37451#L802 assume 1 == ~t11_pc~0; 37433#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 35941#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35942#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 36433#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 36434#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 36544#L821 assume !(1 == ~t12_pc~0); 36795#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 36891#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 35946#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 35947#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 37489#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37135#L1339 assume !(1 == ~M_E~0); 37136#L1339-2 assume !(1 == ~T1_E~0); 37524#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37525#L1349-1 assume !(1 == ~T3_E~0); 36909#L1354-1 assume !(1 == ~T4_E~0); 36910#L1359-1 assume !(1 == ~T5_E~0); 37311#L1364-1 assume !(1 == ~T6_E~0); 36374#L1369-1 assume !(1 == ~T7_E~0); 36375#L1374-1 assume !(1 == ~T8_E~0); 36912#L1379-1 assume !(1 == ~T9_E~0); 36913#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 37012#L1389-1 assume !(1 == ~T11_E~0); 37483#L1394-1 assume !(1 == ~T12_E~0); 37484#L1399-1 assume !(1 == ~E_M~0); 37574#L1404-1 assume !(1 == ~E_1~0); 36473#L1409-1 assume !(1 == ~E_2~0); 36474#L1414-1 assume !(1 == ~E_3~0); 37200#L1419-1 assume !(1 == ~E_4~0); 36114#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 36115#L1429-1 assume !(1 == ~E_6~0); 36925#L1434-1 assume !(1 == ~E_7~0); 37504#L1439-1 assume !(1 == ~E_8~0); 36152#L1444-1 assume !(1 == ~E_9~0); 36153#L1449-1 assume !(1 == ~E_10~0); 36527#L1454-1 assume !(1 == ~E_11~0); 36528#L1459-1 assume !(1 == ~E_12~0); 37046#L1464-1 assume { :end_inline_reset_delta_events } true; 36286#L1810-2 [2022-07-22 02:43:04,261 INFO L754 eck$LassoCheckResult]: Loop: 36286#L1810-2 assume !false; 36730#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36646#L1176 assume !false; 37208#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 36778#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 35984#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36534#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 36535#L1003 assume !(0 != eval_~tmp~0#1); 36176#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36177#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37367#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37150#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37151#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 37044#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36235#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36236#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36702#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36306#L1231-3 assume !(0 == ~T7_E~0); 36307#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36553#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37535#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 37436#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 37141#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 36252#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 36253#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 36298#L1271-3 assume !(0 == ~E_2~0); 36299#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36675#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 36676#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 37197#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 37198#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 37613#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37570#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 36787#L1311-3 assume !(0 == ~E_10~0); 36178#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 36179#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 36254#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36890#L593-42 assume 1 == ~m_pc~0; 37283#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 37049#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37598#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37599#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36077#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36078#L612-42 assume !(1 == ~t1_pc~0); 36999#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 37392#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37513#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36165#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36166#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36861#L631-42 assume 1 == ~t2_pc~0; 35930#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35931#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36850#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36726#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36727#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36327#L650-42 assume 1 == ~t3_pc~0; 35889#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 35890#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37541#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36520#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36521#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37505#L669-42 assume 1 == ~t4_pc~0; 36801#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 35888#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37316#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37206#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 37103#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37104#L688-42 assume 1 == ~t5_pc~0; 37195#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37396#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36028#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36029#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 36105#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35919#L707-42 assume !(1 == ~t6_pc~0); 35920#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 37577#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37321#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37322#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 37071#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37072#L726-42 assume 1 == ~t7_pc~0; 37349#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 37375#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37376#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36790#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 36791#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36894#L745-42 assume 1 == ~t8_pc~0; 36931#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36933#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36260#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35905#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 35906#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36631#L764-42 assume !(1 == ~t9_pc~0); 36768#L764-44 is_transmit9_triggered_~__retres1~9#1 := 0; 37120#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37121#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36191#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 36192#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36245#L783-42 assume 1 == ~t10_pc~0; 35861#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 35862#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36457#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 36590#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 37607#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37291#L802-42 assume 1 == ~t11_pc~0; 36392#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 36003#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36004#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 35954#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35955#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37131#L821-42 assume !(1 == ~t12_pc~0); 36496#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 36497#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 35859#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 35860#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 36837#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36827#L1339-3 assume !(1 == ~M_E~0); 36828#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36979#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37089#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36506#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36507#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37100#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 37596#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 37503#L1374-3 assume !(1 == ~T8_E~0); 36328#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 36329#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36504#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 36505#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 36714#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37510#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 37478#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37479#L1414-3 assume !(1 == ~E_3~0); 37534#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37293#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 36212#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 36213#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 37099#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 36140#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 36141#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 36257#L1454-3 assume !(1 == ~E_11~0); 37094#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 37095#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 36753#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 36050#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36310#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 36311#L1829 assume !(0 == start_simulation_~tmp~3#1); 36032#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 36033#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 36833#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36834#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 37113#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37114#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 36734#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 36285#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 36286#L1810-2 [2022-07-22 02:43:04,262 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:04,262 INFO L85 PathProgramCache]: Analyzing trace with hash -1762996560, now seen corresponding path program 1 times [2022-07-22 02:43:04,263 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:04,263 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1493965784] [2022-07-22 02:43:04,263 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:04,263 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:04,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:04,288 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:04,289 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:04,289 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1493965784] [2022-07-22 02:43:04,289 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1493965784] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:04,289 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:04,289 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:04,289 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2093680557] [2022-07-22 02:43:04,289 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:04,290 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:43:04,290 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:04,290 INFO L85 PathProgramCache]: Analyzing trace with hash -1901825325, now seen corresponding path program 1 times [2022-07-22 02:43:04,291 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:04,291 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [91343904] [2022-07-22 02:43:04,291 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:04,291 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:04,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:04,324 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:04,324 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:04,324 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [91343904] [2022-07-22 02:43:04,325 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [91343904] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:04,325 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:04,325 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:04,325 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [187999993] [2022-07-22 02:43:04,325 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:04,325 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:43:04,326 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:43:04,326 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:43:04,326 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:43:04,326 INFO L87 Difference]: Start difference. First operand 1788 states and 2642 transitions. cyclomatic complexity: 855 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:04,346 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:43:04,346 INFO L93 Difference]: Finished difference Result 1788 states and 2641 transitions. [2022-07-22 02:43:04,346 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:43:04,347 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2641 transitions. [2022-07-22 02:43:04,353 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-07-22 02:43:04,358 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2641 transitions. [2022-07-22 02:43:04,358 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2022-07-22 02:43:04,360 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2022-07-22 02:43:04,360 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2641 transitions. [2022-07-22 02:43:04,361 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:43:04,362 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2641 transitions. [2022-07-22 02:43:04,363 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2641 transitions. [2022-07-22 02:43:04,413 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2022-07-22 02:43:04,416 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4770693512304252) internal successors, (2641), 1787 states have internal predecessors, (2641), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:04,422 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2641 transitions. [2022-07-22 02:43:04,423 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2641 transitions. [2022-07-22 02:43:04,423 INFO L374 stractBuchiCegarLoop]: Abstraction has 1788 states and 2641 transitions. [2022-07-22 02:43:04,423 INFO L287 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-07-22 02:43:04,423 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2641 transitions. [2022-07-22 02:43:04,429 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-07-22 02:43:04,429 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:43:04,429 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:43:04,431 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:04,431 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:04,432 INFO L752 eck$LassoCheckResult]: Stem: 40218#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 40219#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 39739#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 39740#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39794#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 41133#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40227#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40030#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39429#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39430#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 40652#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 40763#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 41199#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 41200#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 40158#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 40159#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 40681#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 40600#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40193#L1201 assume !(0 == ~M_E~0); 40194#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41040#L1206-1 assume !(0 == ~T2_E~0); 41026#L1211-1 assume !(0 == ~T3_E~0); 41027#L1216-1 assume !(0 == ~T4_E~0); 40014#L1221-1 assume !(0 == ~T5_E~0); 40015#L1226-1 assume !(0 == ~T6_E~0); 39654#L1231-1 assume !(0 == ~T7_E~0); 39655#L1236-1 assume !(0 == ~T8_E~0); 41063#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 40051#L1246-1 assume !(0 == ~T10_E~0); 40052#L1251-1 assume !(0 == ~T11_E~0); 40191#L1256-1 assume !(0 == ~T12_E~0); 39440#L1261-1 assume !(0 == ~E_M~0); 39441#L1266-1 assume !(0 == ~E_1~0); 41185#L1271-1 assume !(0 == ~E_2~0); 40747#L1276-1 assume !(0 == ~E_3~0); 40748#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 40695#L1286-1 assume !(0 == ~E_5~0); 39905#L1291-1 assume !(0 == ~E_6~0); 39906#L1296-1 assume !(0 == ~E_7~0); 40481#L1301-1 assume !(0 == ~E_8~0); 40482#L1306-1 assume !(0 == ~E_9~0); 40962#L1311-1 assume !(0 == ~E_10~0); 39856#L1316-1 assume !(0 == ~E_11~0); 39857#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 40499#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40500#L593 assume 1 == ~m_pc~0; 40644#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 39746#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41172#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40706#L1492 assume !(0 != activate_threads_~tmp~1#1); 40707#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40998#L612 assume !(1 == ~t1_pc~0); 40999#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 41128#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40128#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 39750#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 39751#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40170#L631 assume 1 == ~t2_pc~0; 40105#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 39527#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39528#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40364#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 40365#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39823#L650 assume !(1 == ~t3_pc~0); 39824#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 40524#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39747#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39480#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 39481#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40673#L669 assume 1 == ~t4_pc~0; 40674#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41032#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40157#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39689#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 39690#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39914#L688 assume !(1 == ~t5_pc~0); 39705#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 39706#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40624#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40558#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 40559#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40688#L707 assume 1 == ~t6_pc~0; 41097#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 40334#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40335#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 41095#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 40630#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40192#L726 assume 1 == ~t7_pc~0; 40091#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 39790#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40831#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41105#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 39559#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39560#L745 assume !(1 == ~t8_pc~0); 40007#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 40026#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40864#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 40412#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 40413#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40923#L764 assume 1 == ~t9_pc~0; 40190#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40032#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40709#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41156#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 39579#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39580#L783 assume !(1 == ~t10_pc~0); 39641#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 39642#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 39683#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 39684#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 40146#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41034#L802 assume 1 == ~t11_pc~0; 41016#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 39524#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39525#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 40016#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 40017#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 40127#L821 assume !(1 == ~t12_pc~0); 40378#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 40474#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 39529#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 39530#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 41072#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40718#L1339 assume !(1 == ~M_E~0); 40719#L1339-2 assume !(1 == ~T1_E~0); 41107#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 41108#L1349-1 assume !(1 == ~T3_E~0); 40492#L1354-1 assume !(1 == ~T4_E~0); 40493#L1359-1 assume !(1 == ~T5_E~0); 40894#L1364-1 assume !(1 == ~T6_E~0); 39957#L1369-1 assume !(1 == ~T7_E~0); 39958#L1374-1 assume !(1 == ~T8_E~0); 40495#L1379-1 assume !(1 == ~T9_E~0); 40496#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 40595#L1389-1 assume !(1 == ~T11_E~0); 41066#L1394-1 assume !(1 == ~T12_E~0); 41067#L1399-1 assume !(1 == ~E_M~0); 41157#L1404-1 assume !(1 == ~E_1~0); 40056#L1409-1 assume !(1 == ~E_2~0); 40057#L1414-1 assume !(1 == ~E_3~0); 40783#L1419-1 assume !(1 == ~E_4~0); 39697#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 39698#L1429-1 assume !(1 == ~E_6~0); 40508#L1434-1 assume !(1 == ~E_7~0); 41087#L1439-1 assume !(1 == ~E_8~0); 39735#L1444-1 assume !(1 == ~E_9~0); 39736#L1449-1 assume !(1 == ~E_10~0); 40110#L1454-1 assume !(1 == ~E_11~0); 40111#L1459-1 assume !(1 == ~E_12~0); 40629#L1464-1 assume { :end_inline_reset_delta_events } true; 39869#L1810-2 [2022-07-22 02:43:04,432 INFO L754 eck$LassoCheckResult]: Loop: 39869#L1810-2 assume !false; 40313#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40229#L1176 assume !false; 40791#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40361#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 39567#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 40117#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 40118#L1003 assume !(0 != eval_~tmp~0#1); 39759#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 39760#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 40950#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 40733#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40734#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 40627#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 39818#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 39819#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40285#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 39889#L1231-3 assume !(0 == ~T7_E~0); 39890#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40136#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 41118#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 41019#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 40724#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 39835#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 39836#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 39881#L1271-3 assume !(0 == ~E_2~0); 39882#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 40258#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 40259#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 40780#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 40781#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 41196#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 41153#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 40370#L1311-3 assume !(0 == ~E_10~0); 39761#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 39762#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 39837#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40473#L593-42 assume 1 == ~m_pc~0; 40866#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 40632#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41181#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41182#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 39660#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39661#L612-42 assume !(1 == ~t1_pc~0); 40582#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 40975#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41096#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 39748#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 39749#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40444#L631-42 assume 1 == ~t2_pc~0; 39513#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 39514#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40433#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40309#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 40310#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39910#L650-42 assume 1 == ~t3_pc~0; 39472#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 39473#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41124#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40103#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 40104#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41088#L669-42 assume 1 == ~t4_pc~0; 40384#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 39471#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40899#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40789#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 40686#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40687#L688-42 assume 1 == ~t5_pc~0; 40778#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 40979#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39611#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 39612#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 39688#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39502#L707-42 assume 1 == ~t6_pc~0; 39504#L708-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 41160#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40904#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40905#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 40654#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40655#L726-42 assume 1 == ~t7_pc~0; 40932#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 40958#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40959#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 40373#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 40374#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40477#L745-42 assume 1 == ~t8_pc~0; 40514#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 40516#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 39843#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 39488#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 39489#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40214#L764-42 assume 1 == ~t9_pc~0; 40350#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40703#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40704#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 39774#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 39775#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39828#L783-42 assume 1 == ~t10_pc~0; 39444#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 39445#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40040#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 40173#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41190#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40874#L802-42 assume 1 == ~t11_pc~0; 39975#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 39586#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39587#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 39537#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 39538#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 40714#L821-42 assume 1 == ~t12_pc~0; 40715#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 40080#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 39442#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 39443#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 40420#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40410#L1339-3 assume !(1 == ~M_E~0); 40411#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 40562#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40672#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40089#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 40090#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 40683#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 41179#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41086#L1374-3 assume !(1 == ~T8_E~0); 39911#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 39912#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 40087#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 40088#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 40297#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41093#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 41061#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 41062#L1414-3 assume !(1 == ~E_3~0); 41117#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 40876#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 39795#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 39796#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 40682#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 39723#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 39724#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 39840#L1454-3 assume !(1 == ~E_11~0); 40677#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 40678#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40336#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 39633#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 39893#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 39894#L1829 assume !(0 == start_simulation_~tmp~3#1); 39615#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 39616#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 40416#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 40417#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 40696#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 40697#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 40317#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 39868#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 39869#L1810-2 [2022-07-22 02:43:04,433 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:04,433 INFO L85 PathProgramCache]: Analyzing trace with hash 1133017134, now seen corresponding path program 1 times [2022-07-22 02:43:04,433 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:04,433 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1479549359] [2022-07-22 02:43:04,433 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:04,434 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:04,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:04,458 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:04,458 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:04,458 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1479549359] [2022-07-22 02:43:04,458 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1479549359] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:04,459 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:04,459 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:04,459 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1853073530] [2022-07-22 02:43:04,459 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:04,459 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:43:04,460 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:04,460 INFO L85 PathProgramCache]: Analyzing trace with hash 1229697104, now seen corresponding path program 1 times [2022-07-22 02:43:04,460 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:04,460 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1308640657] [2022-07-22 02:43:04,460 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:04,461 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:04,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:04,494 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:04,495 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:04,495 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1308640657] [2022-07-22 02:43:04,495 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1308640657] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:04,495 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:04,495 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:04,495 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [283001146] [2022-07-22 02:43:04,495 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:04,496 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:43:04,496 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:43:04,496 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:43:04,497 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:43:04,497 INFO L87 Difference]: Start difference. First operand 1788 states and 2641 transitions. cyclomatic complexity: 854 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:04,521 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:43:04,521 INFO L93 Difference]: Finished difference Result 1788 states and 2640 transitions. [2022-07-22 02:43:04,522 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:43:04,522 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2640 transitions. [2022-07-22 02:43:04,528 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-07-22 02:43:04,532 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2640 transitions. [2022-07-22 02:43:04,533 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2022-07-22 02:43:04,534 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2022-07-22 02:43:04,534 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2640 transitions. [2022-07-22 02:43:04,535 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:43:04,536 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2640 transitions. [2022-07-22 02:43:04,537 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2640 transitions. [2022-07-22 02:43:04,552 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2022-07-22 02:43:04,555 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.476510067114094) internal successors, (2640), 1787 states have internal predecessors, (2640), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:04,562 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2640 transitions. [2022-07-22 02:43:04,562 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2640 transitions. [2022-07-22 02:43:04,562 INFO L374 stractBuchiCegarLoop]: Abstraction has 1788 states and 2640 transitions. [2022-07-22 02:43:04,562 INFO L287 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-07-22 02:43:04,562 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2640 transitions. [2022-07-22 02:43:04,567 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-07-22 02:43:04,567 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:43:04,568 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:43:04,569 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:04,569 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:04,569 INFO L752 eck$LassoCheckResult]: Stem: 43801#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 43802#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 43322#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 43323#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 43377#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 44716#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43810#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43613#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43012#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43013#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 44235#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 44346#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 44782#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 44783#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 43741#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 43742#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 44264#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 44183#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 43776#L1201 assume !(0 == ~M_E~0); 43777#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44623#L1206-1 assume !(0 == ~T2_E~0); 44609#L1211-1 assume !(0 == ~T3_E~0); 44610#L1216-1 assume !(0 == ~T4_E~0); 43597#L1221-1 assume !(0 == ~T5_E~0); 43598#L1226-1 assume !(0 == ~T6_E~0); 43237#L1231-1 assume !(0 == ~T7_E~0); 43238#L1236-1 assume !(0 == ~T8_E~0); 44646#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 43634#L1246-1 assume !(0 == ~T10_E~0); 43635#L1251-1 assume !(0 == ~T11_E~0); 43774#L1256-1 assume !(0 == ~T12_E~0); 43023#L1261-1 assume !(0 == ~E_M~0); 43024#L1266-1 assume !(0 == ~E_1~0); 44768#L1271-1 assume !(0 == ~E_2~0); 44330#L1276-1 assume !(0 == ~E_3~0); 44331#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 44278#L1286-1 assume !(0 == ~E_5~0); 43488#L1291-1 assume !(0 == ~E_6~0); 43489#L1296-1 assume !(0 == ~E_7~0); 44064#L1301-1 assume !(0 == ~E_8~0); 44065#L1306-1 assume !(0 == ~E_9~0); 44545#L1311-1 assume !(0 == ~E_10~0); 43439#L1316-1 assume !(0 == ~E_11~0); 43440#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 44082#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44083#L593 assume 1 == ~m_pc~0; 44227#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 43329#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44755#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44289#L1492 assume !(0 != activate_threads_~tmp~1#1); 44290#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44581#L612 assume !(1 == ~t1_pc~0); 44582#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 44711#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43711#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43333#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 43334#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43753#L631 assume 1 == ~t2_pc~0; 43688#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 43110#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43111#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43947#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 43948#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43406#L650 assume !(1 == ~t3_pc~0); 43407#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 44107#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43330#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43063#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 43064#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44256#L669 assume 1 == ~t4_pc~0; 44257#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 44615#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43740#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43272#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 43273#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43497#L688 assume !(1 == ~t5_pc~0); 43288#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 43289#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44207#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44141#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 44142#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 44271#L707 assume 1 == ~t6_pc~0; 44680#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 43917#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 43918#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 44678#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 44213#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43775#L726 assume 1 == ~t7_pc~0; 43674#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 43373#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44414#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 44688#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 43142#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43143#L745 assume !(1 == ~t8_pc~0); 43590#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 43609#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44447#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43995#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 43996#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44506#L764 assume 1 == ~t9_pc~0; 43773#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 43615#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 44292#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 44739#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 43162#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43163#L783 assume !(1 == ~t10_pc~0); 43224#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 43225#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43266#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 43267#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 43729#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44617#L802 assume 1 == ~t11_pc~0; 44599#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 43107#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43108#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 43599#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 43600#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 43710#L821 assume !(1 == ~t12_pc~0); 43961#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 44057#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 43112#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 43113#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 44655#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44301#L1339 assume !(1 == ~M_E~0); 44302#L1339-2 assume !(1 == ~T1_E~0); 44690#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44691#L1349-1 assume !(1 == ~T3_E~0); 44075#L1354-1 assume !(1 == ~T4_E~0); 44076#L1359-1 assume !(1 == ~T5_E~0); 44477#L1364-1 assume !(1 == ~T6_E~0); 43540#L1369-1 assume !(1 == ~T7_E~0); 43541#L1374-1 assume !(1 == ~T8_E~0); 44078#L1379-1 assume !(1 == ~T9_E~0); 44079#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 44178#L1389-1 assume !(1 == ~T11_E~0); 44649#L1394-1 assume !(1 == ~T12_E~0); 44650#L1399-1 assume !(1 == ~E_M~0); 44740#L1404-1 assume !(1 == ~E_1~0); 43639#L1409-1 assume !(1 == ~E_2~0); 43640#L1414-1 assume !(1 == ~E_3~0); 44366#L1419-1 assume !(1 == ~E_4~0); 43280#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 43281#L1429-1 assume !(1 == ~E_6~0); 44091#L1434-1 assume !(1 == ~E_7~0); 44670#L1439-1 assume !(1 == ~E_8~0); 43318#L1444-1 assume !(1 == ~E_9~0); 43319#L1449-1 assume !(1 == ~E_10~0); 43693#L1454-1 assume !(1 == ~E_11~0); 43694#L1459-1 assume !(1 == ~E_12~0); 44212#L1464-1 assume { :end_inline_reset_delta_events } true; 43452#L1810-2 [2022-07-22 02:43:04,570 INFO L754 eck$LassoCheckResult]: Loop: 43452#L1810-2 assume !false; 43896#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 43812#L1176 assume !false; 44374#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 43944#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43150#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 43700#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 43701#L1003 assume !(0 != eval_~tmp~0#1); 43342#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 43343#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 44533#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 44316#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44317#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 44210#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 43401#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 43402#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 43868#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 43472#L1231-3 assume !(0 == ~T7_E~0); 43473#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 43719#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 44701#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 44602#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 44307#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 43418#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 43419#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 43464#L1271-3 assume !(0 == ~E_2~0); 43465#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 43841#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 43842#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 44363#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 44364#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 44779#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 44736#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 43953#L1311-3 assume !(0 == ~E_10~0); 43344#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 43345#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 43420#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44056#L593-42 assume 1 == ~m_pc~0; 44449#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 44215#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44764#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44765#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 43243#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43244#L612-42 assume !(1 == ~t1_pc~0); 44165#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 44558#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44679#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43331#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 43332#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44027#L631-42 assume 1 == ~t2_pc~0; 43096#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 43097#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44016#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43892#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 43893#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43493#L650-42 assume !(1 == ~t3_pc~0); 43057#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 43056#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44707#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43686#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 43687#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44671#L669-42 assume !(1 == ~t4_pc~0); 43053#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 43054#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44482#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44372#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 44269#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44270#L688-42 assume 1 == ~t5_pc~0; 44361#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 44562#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43194#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 43195#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 43271#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43085#L707-42 assume !(1 == ~t6_pc~0); 43086#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 44743#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 44487#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 44488#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 44237#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 44238#L726-42 assume 1 == ~t7_pc~0; 44515#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 44541#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44542#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43956#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 43957#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 44060#L745-42 assume 1 == ~t8_pc~0; 44097#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 44099#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43426#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43071#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 43072#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 43797#L764-42 assume 1 == ~t9_pc~0; 43933#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 44286#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 44287#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43357#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 43358#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43411#L783-42 assume 1 == ~t10_pc~0; 43027#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 43028#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43623#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 43756#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 44773#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44457#L802-42 assume 1 == ~t11_pc~0; 43558#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 43169#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43170#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 43120#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 43121#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 44297#L821-42 assume 1 == ~t12_pc~0; 44298#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 43663#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 43025#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 43026#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 44003#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43993#L1339-3 assume !(1 == ~M_E~0); 43994#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 44145#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44255#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 43672#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43673#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44266#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 44762#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 44669#L1374-3 assume !(1 == ~T8_E~0); 43494#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 43495#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 43670#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 43671#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 43880#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 44676#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 44644#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 44645#L1414-3 assume !(1 == ~E_3~0); 44700#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 44459#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 43378#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 43379#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 44265#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 43306#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 43307#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 43423#L1454-3 assume !(1 == ~E_11~0); 44260#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 44261#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 43919#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43216#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 43476#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 43477#L1829 assume !(0 == start_simulation_~tmp~3#1); 43198#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 43199#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43999#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 44000#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 44279#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 44280#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 43900#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 43451#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 43452#L1810-2 [2022-07-22 02:43:04,570 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:04,570 INFO L85 PathProgramCache]: Analyzing trace with hash -1544509712, now seen corresponding path program 1 times [2022-07-22 02:43:04,571 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:04,571 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1217799998] [2022-07-22 02:43:04,571 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:04,571 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:04,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:04,594 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:04,594 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:04,594 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1217799998] [2022-07-22 02:43:04,594 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1217799998] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:04,595 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:04,595 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-22 02:43:04,595 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [934242644] [2022-07-22 02:43:04,595 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:04,595 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:43:04,596 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:04,596 INFO L85 PathProgramCache]: Analyzing trace with hash 1696309331, now seen corresponding path program 1 times [2022-07-22 02:43:04,596 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:04,596 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [551679529] [2022-07-22 02:43:04,596 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:04,596 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:04,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:04,622 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:04,622 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:04,622 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [551679529] [2022-07-22 02:43:04,622 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [551679529] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:04,622 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:04,623 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:04,623 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [317857314] [2022-07-22 02:43:04,623 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:04,623 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:43:04,623 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:43:04,624 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:43:04,624 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:43:04,624 INFO L87 Difference]: Start difference. First operand 1788 states and 2640 transitions. cyclomatic complexity: 853 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:04,652 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:43:04,653 INFO L93 Difference]: Finished difference Result 1788 states and 2635 transitions. [2022-07-22 02:43:04,653 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:43:04,653 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2635 transitions. [2022-07-22 02:43:04,659 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-07-22 02:43:04,664 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2635 transitions. [2022-07-22 02:43:04,664 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2022-07-22 02:43:04,665 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2022-07-22 02:43:04,665 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2635 transitions. [2022-07-22 02:43:04,667 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:43:04,667 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2635 transitions. [2022-07-22 02:43:04,669 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2635 transitions. [2022-07-22 02:43:04,684 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2022-07-22 02:43:04,687 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4737136465324385) internal successors, (2635), 1787 states have internal predecessors, (2635), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:04,690 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2635 transitions. [2022-07-22 02:43:04,691 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2635 transitions. [2022-07-22 02:43:04,691 INFO L374 stractBuchiCegarLoop]: Abstraction has 1788 states and 2635 transitions. [2022-07-22 02:43:04,691 INFO L287 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-07-22 02:43:04,691 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2635 transitions. [2022-07-22 02:43:04,696 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-07-22 02:43:04,696 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:43:04,696 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:43:04,697 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:04,698 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:04,698 INFO L752 eck$LassoCheckResult]: Stem: 47384#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 47385#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 46905#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46906#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46960#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 48299#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 47393#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 47196#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46595#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46596#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 47818#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 47931#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 48365#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 48366#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 47324#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 47325#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 47847#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 47766#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 47359#L1201 assume !(0 == ~M_E~0); 47360#L1201-2 assume !(0 == ~T1_E~0); 48206#L1206-1 assume !(0 == ~T2_E~0); 48192#L1211-1 assume !(0 == ~T3_E~0); 48193#L1216-1 assume !(0 == ~T4_E~0); 47181#L1221-1 assume !(0 == ~T5_E~0); 47182#L1226-1 assume !(0 == ~T6_E~0); 46820#L1231-1 assume !(0 == ~T7_E~0); 46821#L1236-1 assume !(0 == ~T8_E~0); 48229#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 47220#L1246-1 assume !(0 == ~T10_E~0); 47221#L1251-1 assume !(0 == ~T11_E~0); 47357#L1256-1 assume !(0 == ~T12_E~0); 46608#L1261-1 assume !(0 == ~E_M~0); 46609#L1266-1 assume !(0 == ~E_1~0); 48351#L1271-1 assume !(0 == ~E_2~0); 47913#L1276-1 assume !(0 == ~E_3~0); 47914#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 47861#L1286-1 assume !(0 == ~E_5~0); 47071#L1291-1 assume !(0 == ~E_6~0); 47072#L1296-1 assume !(0 == ~E_7~0); 47647#L1301-1 assume !(0 == ~E_8~0); 47648#L1306-1 assume !(0 == ~E_9~0); 48128#L1311-1 assume !(0 == ~E_10~0); 47022#L1316-1 assume !(0 == ~E_11~0); 47023#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 47665#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47666#L593 assume 1 == ~m_pc~0; 47810#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 46912#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48338#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47872#L1492 assume !(0 != activate_threads_~tmp~1#1); 47873#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48164#L612 assume !(1 == ~t1_pc~0); 48165#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 48294#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47294#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46916#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 46917#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47336#L631 assume 1 == ~t2_pc~0; 47271#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46693#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46694#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47530#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 47531#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46989#L650 assume !(1 == ~t3_pc~0); 46990#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 47690#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46913#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46646#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 46647#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47839#L669 assume 1 == ~t4_pc~0; 47840#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 48198#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47323#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 46855#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 46856#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47080#L688 assume !(1 == ~t5_pc~0); 46871#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 46872#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47790#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47726#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 47727#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47857#L707 assume 1 == ~t6_pc~0; 48263#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 47500#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47501#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 48261#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 47798#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47358#L726 assume 1 == ~t7_pc~0; 47259#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46956#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47997#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 48272#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 46725#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46726#L745 assume !(1 == ~t8_pc~0); 47173#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 47192#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48030#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 47578#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 47579#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48089#L764 assume 1 == ~t9_pc~0; 47356#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 47198#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47875#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 48322#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 46745#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46746#L783 assume !(1 == ~t10_pc~0); 46807#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 46808#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 46849#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 46850#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 47317#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48200#L802 assume 1 == ~t11_pc~0; 48182#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 46690#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 46691#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 47183#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 47184#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 47293#L821 assume !(1 == ~t12_pc~0); 47544#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 47640#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 46697#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46698#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 48238#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47884#L1339 assume !(1 == ~M_E~0); 47885#L1339-2 assume !(1 == ~T1_E~0); 48273#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48274#L1349-1 assume !(1 == ~T3_E~0); 47659#L1354-1 assume !(1 == ~T4_E~0); 47660#L1359-1 assume !(1 == ~T5_E~0); 48062#L1364-1 assume !(1 == ~T6_E~0); 47123#L1369-1 assume !(1 == ~T7_E~0); 47124#L1374-1 assume !(1 == ~T8_E~0); 47663#L1379-1 assume !(1 == ~T9_E~0); 47664#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 47761#L1389-1 assume !(1 == ~T11_E~0); 48232#L1394-1 assume !(1 == ~T12_E~0); 48233#L1399-1 assume !(1 == ~E_M~0); 48323#L1404-1 assume !(1 == ~E_1~0); 47224#L1409-1 assume !(1 == ~E_2~0); 47225#L1414-1 assume !(1 == ~E_3~0); 47949#L1419-1 assume !(1 == ~E_4~0); 46863#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 46864#L1429-1 assume !(1 == ~E_6~0); 47674#L1434-1 assume !(1 == ~E_7~0); 48253#L1439-1 assume !(1 == ~E_8~0); 46901#L1444-1 assume !(1 == ~E_9~0); 46902#L1449-1 assume !(1 == ~E_10~0); 47276#L1454-1 assume !(1 == ~E_11~0); 47277#L1459-1 assume !(1 == ~E_12~0); 47795#L1464-1 assume { :end_inline_reset_delta_events } true; 47035#L1810-2 [2022-07-22 02:43:04,698 INFO L754 eck$LassoCheckResult]: Loop: 47035#L1810-2 assume !false; 47479#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 47395#L1176 assume !false; 47957#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 47529#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 46733#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 47283#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 47284#L1003 assume !(0 != eval_~tmp~0#1); 46927#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 46928#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 48116#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 47899#L1201-5 assume !(0 == ~T1_E~0); 47900#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 47794#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46984#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 46985#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 47451#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 47055#L1231-3 assume !(0 == ~T7_E~0); 47056#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 47302#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 48284#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 48185#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 47890#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 47001#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 47002#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 47047#L1271-3 assume !(0 == ~E_2~0); 47048#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 47424#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 47425#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 47946#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 47947#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 48362#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 48319#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 47536#L1311-3 assume !(0 == ~E_10~0); 46925#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 46926#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 47003#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47639#L593-42 assume 1 == ~m_pc~0; 48032#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 47797#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48346#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 48347#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 46826#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46827#L612-42 assume !(1 == ~t1_pc~0); 47748#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 48141#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48262#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46914#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 46915#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47610#L631-42 assume 1 == ~t2_pc~0; 46679#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46680#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47599#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47475#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 47476#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47076#L650-42 assume !(1 == ~t3_pc~0); 46640#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 46639#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48290#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47269#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 47270#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48254#L669-42 assume !(1 == ~t4_pc~0); 46636#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 46637#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48065#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47955#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 47852#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47853#L688-42 assume 1 == ~t5_pc~0; 47944#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 48145#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46777#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46778#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 46851#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46668#L707-42 assume !(1 == ~t6_pc~0); 46669#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 48326#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 48070#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 48071#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 47820#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47821#L726-42 assume 1 == ~t7_pc~0; 48098#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 48124#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48125#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47539#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 47540#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47643#L745-42 assume 1 == ~t8_pc~0; 47680#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 47682#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47009#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46654#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 46655#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47380#L764-42 assume 1 == ~t9_pc~0; 47516#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 47869#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47870#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 46940#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 46941#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46994#L783-42 assume 1 == ~t10_pc~0; 46610#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 46611#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47206#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 47339#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 48356#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48040#L802-42 assume 1 == ~t11_pc~0; 47141#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 46752#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 46753#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46703#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 46704#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 47880#L821-42 assume 1 == ~t12_pc~0; 47881#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 47246#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 46606#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46607#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 47586#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47576#L1339-3 assume !(1 == ~M_E~0); 47577#L1339-5 assume !(1 == ~T1_E~0); 47728#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 47838#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 47255#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47256#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 47849#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 48345#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 48252#L1374-3 assume !(1 == ~T8_E~0); 47077#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 47078#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 47253#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 47254#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 47463#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 48259#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 48227#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 48228#L1414-3 assume !(1 == ~E_3~0); 48283#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 48042#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 46961#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 46962#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 47848#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 46889#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 46890#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 47006#L1454-3 assume !(1 == ~E_11~0); 47843#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 47844#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 47502#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 46799#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 47059#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 47060#L1829 assume !(0 == start_simulation_~tmp~3#1); 46781#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 46782#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 47582#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 47583#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 47862#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 47863#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 47483#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 47034#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 47035#L1810-2 [2022-07-22 02:43:04,699 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:04,699 INFO L85 PathProgramCache]: Analyzing trace with hash -2089382286, now seen corresponding path program 1 times [2022-07-22 02:43:04,699 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:04,699 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1855028592] [2022-07-22 02:43:04,699 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:04,699 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:04,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:04,728 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:04,728 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:04,728 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1855028592] [2022-07-22 02:43:04,729 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1855028592] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:04,729 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:04,729 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:04,729 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [674986283] [2022-07-22 02:43:04,729 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:04,729 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:43:04,730 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:04,730 INFO L85 PathProgramCache]: Analyzing trace with hash 1093504531, now seen corresponding path program 1 times [2022-07-22 02:43:04,730 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:04,730 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [323864303] [2022-07-22 02:43:04,730 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:04,730 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:04,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:04,776 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:04,776 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:04,776 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [323864303] [2022-07-22 02:43:04,776 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [323864303] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:04,776 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:04,776 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:04,777 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1976403189] [2022-07-22 02:43:04,777 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:04,777 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:43:04,777 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:43:04,777 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-22 02:43:04,778 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-22 02:43:04,778 INFO L87 Difference]: Start difference. First operand 1788 states and 2635 transitions. cyclomatic complexity: 848 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:04,860 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:43:04,860 INFO L93 Difference]: Finished difference Result 3437 states and 5058 transitions. [2022-07-22 02:43:04,860 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-22 02:43:04,861 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3437 states and 5058 transitions. [2022-07-22 02:43:04,871 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3250 [2022-07-22 02:43:04,879 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3437 states to 3437 states and 5058 transitions. [2022-07-22 02:43:04,879 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3437 [2022-07-22 02:43:04,881 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3437 [2022-07-22 02:43:04,881 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3437 states and 5058 transitions. [2022-07-22 02:43:04,884 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:43:04,884 INFO L369 hiAutomatonCegarLoop]: Abstraction has 3437 states and 5058 transitions. [2022-07-22 02:43:04,886 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3437 states and 5058 transitions. [2022-07-22 02:43:04,919 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3437 to 3437. [2022-07-22 02:43:04,923 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3437 states, 3437 states have (on average 1.4716322374163515) internal successors, (5058), 3436 states have internal predecessors, (5058), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:04,928 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3437 states to 3437 states and 5058 transitions. [2022-07-22 02:43:04,943 INFO L392 hiAutomatonCegarLoop]: Abstraction has 3437 states and 5058 transitions. [2022-07-22 02:43:04,943 INFO L374 stractBuchiCegarLoop]: Abstraction has 3437 states and 5058 transitions. [2022-07-22 02:43:04,943 INFO L287 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-07-22 02:43:04,944 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3437 states and 5058 transitions. [2022-07-22 02:43:04,952 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3250 [2022-07-22 02:43:04,952 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:43:04,964 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:43:04,966 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:04,966 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:04,966 INFO L752 eck$LassoCheckResult]: Stem: 52620#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 52621#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 52140#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 52141#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 52195#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 53576#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 52629#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 52431#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 51830#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 51831#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 53061#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 53178#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 53657#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 53658#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 52559#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 52560#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 53090#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 53007#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 52595#L1201 assume !(0 == ~M_E~0); 52596#L1201-2 assume !(0 == ~T1_E~0); 53474#L1206-1 assume !(0 == ~T2_E~0); 53460#L1211-1 assume !(0 == ~T3_E~0); 53461#L1216-1 assume !(0 == ~T4_E~0); 52416#L1221-1 assume !(0 == ~T5_E~0); 52417#L1226-1 assume !(0 == ~T6_E~0); 52055#L1231-1 assume !(0 == ~T7_E~0); 52056#L1236-1 assume !(0 == ~T8_E~0); 53497#L1241-1 assume !(0 == ~T9_E~0); 52455#L1246-1 assume !(0 == ~T10_E~0); 52456#L1251-1 assume !(0 == ~T11_E~0); 52593#L1256-1 assume !(0 == ~T12_E~0); 51843#L1261-1 assume !(0 == ~E_M~0); 51844#L1266-1 assume !(0 == ~E_1~0); 53641#L1271-1 assume !(0 == ~E_2~0); 53160#L1276-1 assume !(0 == ~E_3~0); 53161#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 53106#L1286-1 assume !(0 == ~E_5~0); 52306#L1291-1 assume !(0 == ~E_6~0); 52307#L1296-1 assume !(0 == ~E_7~0); 52886#L1301-1 assume !(0 == ~E_8~0); 52887#L1306-1 assume !(0 == ~E_9~0); 53390#L1311-1 assume !(0 == ~E_10~0); 52257#L1316-1 assume !(0 == ~E_11~0); 52258#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 52906#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52907#L593 assume 1 == ~m_pc~0; 53053#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 52147#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53626#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 53117#L1492 assume !(0 != activate_threads_~tmp~1#1); 53118#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53431#L612 assume !(1 == ~t1_pc~0); 53432#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 53570#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52529#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 52151#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 52152#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52571#L631 assume 1 == ~t2_pc~0; 52506#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 51928#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51929#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 52767#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 52768#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52224#L650 assume !(1 == ~t3_pc~0); 52225#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 52931#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 52148#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51881#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 51882#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53082#L669 assume 1 == ~t4_pc~0; 53083#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 53466#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 52558#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 52090#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 52091#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 52315#L688 assume !(1 == ~t5_pc~0); 52106#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 52107#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53033#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 52965#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 52966#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 53102#L707 assume 1 == ~t6_pc~0; 53534#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 52737#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 52738#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 53532#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 53041#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 52594#L726 assume 1 == ~t7_pc~0; 52494#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 52191#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53247#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53543#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 51960#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 51961#L745 assume !(1 == ~t8_pc~0); 52408#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 52427#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53284#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 52815#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 52816#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53348#L764 assume 1 == ~t9_pc~0; 52592#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 52433#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 53120#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 53609#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 51980#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 51981#L783 assume !(1 == ~t10_pc~0); 52042#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 52043#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 52084#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 52085#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 52552#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 53468#L802 assume 1 == ~t11_pc~0; 53450#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 51925#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 51926#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 52418#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 52419#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 52528#L821 assume !(1 == ~t12_pc~0); 52781#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 52879#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 51932#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 51933#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 53506#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53129#L1339 assume !(1 == ~M_E~0); 53130#L1339-2 assume !(1 == ~T1_E~0); 53545#L1344-1 assume !(1 == ~T2_E~0); 53546#L1349-1 assume !(1 == ~T3_E~0); 52899#L1354-1 assume !(1 == ~T4_E~0); 52900#L1359-1 assume !(1 == ~T5_E~0); 53320#L1364-1 assume !(1 == ~T6_E~0); 52358#L1369-1 assume !(1 == ~T7_E~0); 52359#L1374-1 assume !(1 == ~T8_E~0); 52903#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 52904#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 53974#L1389-1 assume !(1 == ~T11_E~0); 53500#L1394-1 assume !(1 == ~T12_E~0); 53501#L1399-1 assume !(1 == ~E_M~0); 53610#L1404-1 assume !(1 == ~E_1~0); 52459#L1409-1 assume !(1 == ~E_2~0); 52460#L1414-1 assume !(1 == ~E_3~0); 53963#L1419-1 assume !(1 == ~E_4~0); 53741#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 53740#L1429-1 assume !(1 == ~E_6~0); 53739#L1434-1 assume !(1 == ~E_7~0); 53734#L1439-1 assume !(1 == ~E_8~0); 53730#L1444-1 assume !(1 == ~E_9~0); 53143#L1449-1 assume !(1 == ~E_10~0); 52511#L1454-1 assume !(1 == ~E_11~0); 52512#L1459-1 assume !(1 == ~E_12~0); 53542#L1464-1 assume { :end_inline_reset_delta_events } true; 53712#L1810-2 [2022-07-22 02:43:04,966 INFO L754 eck$LassoCheckResult]: Loop: 53712#L1810-2 assume !false; 53559#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 52634#L1176 assume !false; 53691#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 53705#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 53259#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 52518#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 52519#L1003 assume !(0 != eval_~tmp~0#1); 53692#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 53600#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 53601#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 53146#L1201-5 assume !(0 == ~T1_E~0); 53147#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 53037#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 52219#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 52220#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 52687#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 52292#L1231-3 assume !(0 == ~T7_E~0); 52293#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 52539#L1241-3 assume !(0 == ~T9_E~0); 53558#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 53454#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 53136#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 52237#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 52238#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 52282#L1271-3 assume !(0 == ~E_2~0); 52283#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 52660#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 52661#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 53193#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 53194#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 53652#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 53606#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 52773#L1311-3 assume !(0 == ~E_10~0); 52160#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 52161#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 52236#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52878#L593-42 assume 1 == ~m_pc~0; 53286#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 53040#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53635#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 53636#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 52058#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 52059#L612-42 assume !(1 == ~t1_pc~0); 52989#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 53405#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53533#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 52149#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 52150#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52847#L631-42 assume 1 == ~t2_pc~0; 51914#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 51915#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 52836#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 52711#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 52712#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52311#L650-42 assume 1 == ~t3_pc~0; 51873#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 51874#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53565#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 52504#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 52505#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53522#L669-42 assume 1 == ~t4_pc~0; 52787#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 51872#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53323#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53203#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 53097#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53098#L688-42 assume 1 == ~t5_pc~0; 53191#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 53409#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 52012#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 52013#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 52086#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 51903#L707-42 assume !(1 == ~t6_pc~0); 51904#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 53613#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53328#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 53329#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 53063#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53064#L726-42 assume 1 == ~t7_pc~0; 53357#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 53386#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53387#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 52776#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 52777#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 52882#L745-42 assume 1 == ~t8_pc~0; 52920#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 52922#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 52244#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 51889#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 51890#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 52616#L764-42 assume 1 == ~t9_pc~0; 52753#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 53114#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 53115#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 52175#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 52176#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 52229#L783-42 assume 1 == ~t10_pc~0; 51845#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 51846#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 52441#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 52574#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 53646#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 53294#L802-42 assume 1 == ~t11_pc~0; 52376#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 51987#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 51988#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 51938#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 51939#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 53125#L821-42 assume !(1 == ~t12_pc~0); 52480#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 52481#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 51841#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 51842#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 52823#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 52813#L1339-3 assume !(1 == ~M_E~0); 52814#L1339-5 assume !(1 == ~T1_E~0); 52969#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 53081#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 52490#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 52491#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 53092#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 53634#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 53520#L1374-3 assume !(1 == ~T8_E~0); 52312#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 52313#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 52488#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 52489#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 52699#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 53530#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 53495#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 53496#L1414-3 assume !(1 == ~E_3~0); 53557#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 53296#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 52196#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 52197#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 53091#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 52124#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 52125#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 52241#L1454-3 assume !(1 == ~E_11~0); 53086#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 53087#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 54324#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 54316#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 54314#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 54308#L1829 assume !(0 == start_simulation_~tmp~3#1); 54306#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 53361#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 52819#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 52820#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 53107#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 53108#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 52719#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 52720#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 53712#L1810-2 [2022-07-22 02:43:04,967 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:04,967 INFO L85 PathProgramCache]: Analyzing trace with hash 907144632, now seen corresponding path program 1 times [2022-07-22 02:43:04,967 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:04,967 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [205421402] [2022-07-22 02:43:04,967 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:04,968 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:04,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:05,006 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:05,007 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:05,007 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [205421402] [2022-07-22 02:43:05,007 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [205421402] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:05,007 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:05,007 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:05,007 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1170423725] [2022-07-22 02:43:05,007 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:05,008 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:43:05,008 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:05,008 INFO L85 PathProgramCache]: Analyzing trace with hash -1682605164, now seen corresponding path program 1 times [2022-07-22 02:43:05,008 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:05,008 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1308268332] [2022-07-22 02:43:05,009 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:05,014 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:05,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:05,039 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:05,040 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:05,040 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1308268332] [2022-07-22 02:43:05,040 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1308268332] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:05,040 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:05,040 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:05,040 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [382960619] [2022-07-22 02:43:05,040 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:05,041 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:43:05,041 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:43:05,041 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-22 02:43:05,041 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-22 02:43:05,042 INFO L87 Difference]: Start difference. First operand 3437 states and 5058 transitions. cyclomatic complexity: 1623 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:05,211 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:43:05,212 INFO L93 Difference]: Finished difference Result 6529 states and 9599 transitions. [2022-07-22 02:43:05,212 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-22 02:43:05,213 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6529 states and 9599 transitions. [2022-07-22 02:43:05,240 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6314 [2022-07-22 02:43:05,260 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6529 states to 6529 states and 9599 transitions. [2022-07-22 02:43:05,261 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6529 [2022-07-22 02:43:05,265 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6529 [2022-07-22 02:43:05,265 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6529 states and 9599 transitions. [2022-07-22 02:43:05,272 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:43:05,272 INFO L369 hiAutomatonCegarLoop]: Abstraction has 6529 states and 9599 transitions. [2022-07-22 02:43:05,275 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6529 states and 9599 transitions. [2022-07-22 02:43:05,352 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6529 to 6527. [2022-07-22 02:43:05,360 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6527 states, 6527 states have (on average 1.4703539145089628) internal successors, (9597), 6526 states have internal predecessors, (9597), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:05,374 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6527 states to 6527 states and 9597 transitions. [2022-07-22 02:43:05,374 INFO L392 hiAutomatonCegarLoop]: Abstraction has 6527 states and 9597 transitions. [2022-07-22 02:43:05,374 INFO L374 stractBuchiCegarLoop]: Abstraction has 6527 states and 9597 transitions. [2022-07-22 02:43:05,374 INFO L287 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-07-22 02:43:05,374 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6527 states and 9597 transitions. [2022-07-22 02:43:05,394 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6314 [2022-07-22 02:43:05,394 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:43:05,394 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:43:05,396 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:05,397 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:05,397 INFO L752 eck$LassoCheckResult]: Stem: 62603#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 62604#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 62116#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 62117#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 62171#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 63603#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 62612#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 62412#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 61806#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 61807#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 63050#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 63168#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 63698#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 63699#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 62542#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 62543#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 63080#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 62998#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 62578#L1201 assume !(0 == ~M_E~0); 62579#L1201-2 assume !(0 == ~T1_E~0); 63482#L1206-1 assume !(0 == ~T2_E~0); 63465#L1211-1 assume !(0 == ~T3_E~0); 63466#L1216-1 assume !(0 == ~T4_E~0); 62396#L1221-1 assume !(0 == ~T5_E~0); 62397#L1226-1 assume !(0 == ~T6_E~0); 62031#L1231-1 assume !(0 == ~T7_E~0); 62032#L1236-1 assume !(0 == ~T8_E~0); 63514#L1241-1 assume !(0 == ~T9_E~0); 62433#L1246-1 assume !(0 == ~T10_E~0); 62434#L1251-1 assume !(0 == ~T11_E~0); 62576#L1256-1 assume !(0 == ~T12_E~0); 61817#L1261-1 assume !(0 == ~E_M~0); 61818#L1266-1 assume !(0 == ~E_1~0); 63675#L1271-1 assume !(0 == ~E_2~0); 63151#L1276-1 assume !(0 == ~E_3~0); 63152#L1281-1 assume !(0 == ~E_4~0); 63094#L1286-1 assume !(0 == ~E_5~0); 62284#L1291-1 assume !(0 == ~E_6~0); 62285#L1296-1 assume !(0 == ~E_7~0); 62876#L1301-1 assume !(0 == ~E_8~0); 62877#L1306-1 assume !(0 == ~E_9~0); 63389#L1311-1 assume !(0 == ~E_10~0); 62235#L1316-1 assume !(0 == ~E_11~0); 62236#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 62894#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 62895#L593 assume 1 == ~m_pc~0; 63042#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 62123#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 63660#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 63105#L1492 assume !(0 != activate_threads_~tmp~1#1); 63106#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63432#L612 assume !(1 == ~t1_pc~0); 63433#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 63597#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 62512#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 62127#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 62128#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 62554#L631 assume 1 == ~t2_pc~0; 62488#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 61904#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 61905#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 62755#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 62756#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 62202#L650 assume !(1 == ~t3_pc~0); 62203#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 62920#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 62124#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 61857#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 61858#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 63072#L669 assume 1 == ~t4_pc~0; 63073#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 63471#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 62541#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 62066#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 62067#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 62294#L688 assume !(1 == ~t5_pc~0); 62082#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 62083#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 63022#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 62955#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 62956#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 63087#L707 assume 1 == ~t6_pc~0; 63555#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 62725#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 62726#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 63552#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 63028#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 62577#L726 assume 1 == ~t7_pc~0; 62474#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 62167#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 63241#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 63566#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 61936#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 61937#L745 assume !(1 == ~t8_pc~0); 62389#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 62408#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 63282#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 62803#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 62804#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 63344#L764 assume 1 == ~t9_pc~0; 62575#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 62414#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 63109#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 63638#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 61956#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 61957#L783 assume !(1 == ~t10_pc~0); 62018#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 62019#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 62060#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 62061#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 62530#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 63473#L802 assume 1 == ~t11_pc~0; 63452#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 61901#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 61902#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 62398#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 62399#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 62511#L821 assume !(1 == ~t12_pc~0); 62769#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 62869#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 61906#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 61907#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 63524#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 63119#L1339 assume !(1 == ~M_E~0); 63120#L1339-2 assume !(1 == ~T1_E~0); 63570#L1344-1 assume !(1 == ~T2_E~0); 63571#L1349-1 assume !(1 == ~T3_E~0); 63983#L1354-1 assume !(1 == ~T4_E~0); 63982#L1359-1 assume !(1 == ~T5_E~0); 63981#L1364-1 assume !(1 == ~T6_E~0); 63980#L1369-1 assume !(1 == ~T7_E~0); 63979#L1374-1 assume !(1 == ~T8_E~0); 63978#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 63977#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 63736#L1389-1 assume !(1 == ~T11_E~0); 63517#L1394-1 assume !(1 == ~T12_E~0); 63518#L1399-1 assume !(1 == ~E_M~0); 63639#L1404-1 assume !(1 == ~E_1~0); 62438#L1409-1 assume !(1 == ~E_2~0); 62439#L1414-1 assume !(1 == ~E_3~0); 63627#L1419-1 assume 1 == ~E_4~0;~E_4~0 := 2; 63876#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 63875#L1429-1 assume !(1 == ~E_6~0); 63841#L1434-1 assume !(1 == ~E_7~0); 63813#L1439-1 assume !(1 == ~E_8~0); 63809#L1444-1 assume !(1 == ~E_9~0); 63807#L1449-1 assume !(1 == ~E_10~0); 63796#L1454-1 assume !(1 == ~E_11~0); 63786#L1459-1 assume !(1 == ~E_12~0); 63776#L1464-1 assume { :end_inline_reset_delta_events } true; 63769#L1810-2 [2022-07-22 02:43:05,397 INFO L754 eck$LassoCheckResult]: Loop: 63769#L1810-2 assume !false; 63766#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 63762#L1176 assume !false; 63761#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 63758#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 63747#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 63746#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 63744#L1003 assume !(0 != eval_~tmp~0#1); 63743#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 63742#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 63741#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 63740#L1201-5 assume !(0 == ~T1_E~0); 63738#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 63739#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 65805#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 65803#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 65801#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 65799#L1231-3 assume !(0 == ~T7_E~0); 65797#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 65795#L1241-3 assume !(0 == ~T9_E~0); 65794#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 65792#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 65790#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 65788#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 65786#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 65784#L1271-3 assume !(0 == ~E_2~0); 65782#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 65780#L1281-3 assume !(0 == ~E_4~0); 65778#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 65777#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 65776#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 65775#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 65774#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 65773#L1311-3 assume !(0 == ~E_10~0); 65772#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 65771#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 65769#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 65766#L593-42 assume 1 == ~m_pc~0; 65763#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 65762#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 65761#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 65760#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 65759#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65757#L612-42 assume 1 == ~t1_pc~0; 65755#L613-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 65752#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 65750#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 65522#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 65519#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 65517#L631-42 assume 1 == ~t2_pc~0; 65514#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 65512#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 65510#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 65507#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 65505#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 65503#L650-42 assume !(1 == ~t3_pc~0); 65500#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 65499#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 65498#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 65497#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 65201#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 64844#L669-42 assume 1 == ~t4_pc~0; 64841#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 64839#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64837#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 64834#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 64832#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 64830#L688-42 assume 1 == ~t5_pc~0; 64827#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 64825#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 64824#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 64823#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 64822#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 64821#L707-42 assume 1 == ~t6_pc~0; 64819#L708-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 64815#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 64813#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 64811#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 64810#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 64809#L726-42 assume 1 == ~t7_pc~0; 64807#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 64806#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 64805#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 64804#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 64803#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 64802#L745-42 assume 1 == ~t8_pc~0; 64800#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 64797#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 64794#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 64792#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 64790#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 64788#L764-42 assume 1 == ~t9_pc~0; 64785#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 64782#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 64542#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 64540#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 64538#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 64536#L783-42 assume !(1 == ~t10_pc~0); 64533#L783-44 is_transmit10_triggered_~__retres1~10#1 := 0; 64530#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 64529#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 64528#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 64527#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 64526#L802-42 assume 1 == ~t11_pc~0; 64523#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 64520#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 63489#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 61914#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 61915#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 63114#L821-42 assume 1 == ~t12_pc~0; 63115#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 62463#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 64312#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 64310#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 64308#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64234#L1339-3 assume !(1 == ~M_E~0); 64232#L1339-5 assume !(1 == ~T1_E~0); 64230#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 63128#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 64227#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 64185#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 64183#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 64181#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 64138#L1374-3 assume !(1 == ~T8_E~0); 64136#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 64133#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 64086#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 64084#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 64082#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 64080#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 64078#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 64074#L1414-3 assume !(1 == ~E_3~0); 64023#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 63969#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 63967#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 63918#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 63916#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 63914#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 63912#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 63911#L1454-3 assume !(1 == ~E_11~0); 63910#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 63909#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 63867#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 63860#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 63859#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 63856#L1829 assume !(0 == start_simulation_~tmp~3#1); 63855#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 63828#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 63822#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 63808#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 63806#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 63795#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 63785#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 63775#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 63769#L1810-2 [2022-07-22 02:43:05,398 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:05,398 INFO L85 PathProgramCache]: Analyzing trace with hash -1065863428, now seen corresponding path program 1 times [2022-07-22 02:43:05,398 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:05,398 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [7636450] [2022-07-22 02:43:05,398 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:05,399 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:05,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:05,446 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:05,446 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:05,446 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [7636450] [2022-07-22 02:43:05,447 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [7636450] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:05,447 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:05,447 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:05,447 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1415506218] [2022-07-22 02:43:05,447 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:05,447 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:43:05,448 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:05,449 INFO L85 PathProgramCache]: Analyzing trace with hash -1004038443, now seen corresponding path program 1 times [2022-07-22 02:43:05,449 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:05,449 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1926544427] [2022-07-22 02:43:05,449 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:05,449 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:05,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:05,477 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:05,477 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:05,477 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1926544427] [2022-07-22 02:43:05,477 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1926544427] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:05,477 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:05,478 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:05,478 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2078405942] [2022-07-22 02:43:05,478 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:05,478 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:43:05,478 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:43:05,479 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-22 02:43:05,479 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-22 02:43:05,479 INFO L87 Difference]: Start difference. First operand 6527 states and 9597 transitions. cyclomatic complexity: 3074 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:05,645 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:43:05,645 INFO L93 Difference]: Finished difference Result 12485 states and 18332 transitions. [2022-07-22 02:43:05,645 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-22 02:43:05,646 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12485 states and 18332 transitions. [2022-07-22 02:43:05,699 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 12256 [2022-07-22 02:43:05,733 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12485 states to 12485 states and 18332 transitions. [2022-07-22 02:43:05,733 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12485 [2022-07-22 02:43:05,742 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12485 [2022-07-22 02:43:05,742 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12485 states and 18332 transitions. [2022-07-22 02:43:05,754 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:43:05,755 INFO L369 hiAutomatonCegarLoop]: Abstraction has 12485 states and 18332 transitions. [2022-07-22 02:43:05,765 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12485 states and 18332 transitions. [2022-07-22 02:43:05,943 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12485 to 12481. [2022-07-22 02:43:05,959 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12481 states, 12481 states have (on average 1.468472077557888) internal successors, (18328), 12480 states have internal predecessors, (18328), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:05,990 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12481 states to 12481 states and 18328 transitions. [2022-07-22 02:43:05,991 INFO L392 hiAutomatonCegarLoop]: Abstraction has 12481 states and 18328 transitions. [2022-07-22 02:43:05,991 INFO L374 stractBuchiCegarLoop]: Abstraction has 12481 states and 18328 transitions. [2022-07-22 02:43:05,991 INFO L287 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-07-22 02:43:05,991 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12481 states and 18328 transitions. [2022-07-22 02:43:06,022 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 12256 [2022-07-22 02:43:06,022 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:43:06,022 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:43:06,024 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:06,024 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:06,024 INFO L752 eck$LassoCheckResult]: Stem: 81619#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 81620#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 81138#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 81139#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 81193#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 82552#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 81628#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 81430#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 80828#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 80829#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 82056#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 82169#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 82624#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 82625#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 81558#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 81559#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 82085#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 82003#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 81594#L1201 assume !(0 == ~M_E~0); 81595#L1201-2 assume !(0 == ~T1_E~0); 82453#L1206-1 assume !(0 == ~T2_E~0); 82439#L1211-1 assume !(0 == ~T3_E~0); 82440#L1216-1 assume !(0 == ~T4_E~0); 81414#L1221-1 assume !(0 == ~T5_E~0); 81415#L1226-1 assume !(0 == ~T6_E~0); 81053#L1231-1 assume !(0 == ~T7_E~0); 81054#L1236-1 assume !(0 == ~T8_E~0); 82479#L1241-1 assume !(0 == ~T9_E~0); 81451#L1246-1 assume !(0 == ~T10_E~0); 81452#L1251-1 assume !(0 == ~T11_E~0); 81592#L1256-1 assume !(0 == ~T12_E~0); 80839#L1261-1 assume !(0 == ~E_M~0); 80840#L1266-1 assume !(0 == ~E_1~0); 82610#L1271-1 assume !(0 == ~E_2~0); 82153#L1276-1 assume !(0 == ~E_3~0); 82154#L1281-1 assume !(0 == ~E_4~0); 82099#L1286-1 assume !(0 == ~E_5~0); 81304#L1291-1 assume !(0 == ~E_6~0); 81305#L1296-1 assume !(0 == ~E_7~0); 81884#L1301-1 assume !(0 == ~E_8~0); 81885#L1306-1 assume !(0 == ~E_9~0); 82373#L1311-1 assume !(0 == ~E_10~0); 81255#L1316-1 assume !(0 == ~E_11~0); 81256#L1321-1 assume !(0 == ~E_12~0); 81902#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 81903#L593 assume 1 == ~m_pc~0; 82047#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 81145#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 82597#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 82110#L1492 assume !(0 != activate_threads_~tmp~1#1); 82111#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 82410#L612 assume !(1 == ~t1_pc~0); 82411#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 82547#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 81528#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 81149#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 81150#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 81570#L631 assume 1 == ~t2_pc~0; 81505#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 80926#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 80927#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 81767#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 81768#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 81222#L650 assume !(1 == ~t3_pc~0); 81223#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 81927#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 81146#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 80879#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 80880#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 82077#L669 assume 1 == ~t4_pc~0; 82078#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 82445#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 81557#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 81088#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 81089#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 81314#L688 assume !(1 == ~t5_pc~0); 81104#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 81105#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 82027#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 81961#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 81962#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 82092#L707 assume 1 == ~t6_pc~0; 82514#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 81737#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 81738#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 82512#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 82033#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 81593#L726 assume 1 == ~t7_pc~0; 81491#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 81189#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 82238#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 82523#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 80958#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 80959#L745 assume !(1 == ~t8_pc~0); 81407#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 81426#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 82272#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 81815#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 81816#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 82332#L764 assume 1 == ~t9_pc~0; 81591#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 81432#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 82113#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 82579#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 80978#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 80979#L783 assume !(1 == ~t10_pc~0); 81040#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 81041#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 81082#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 81083#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 81546#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 82447#L802 assume 1 == ~t11_pc~0; 82428#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 80923#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 80924#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 81416#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 81417#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 81527#L821 assume !(1 == ~t12_pc~0); 81781#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 81877#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 80928#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 80929#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 82488#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 82122#L1339 assume !(1 == ~M_E~0); 82123#L1339-2 assume !(1 == ~T1_E~0); 82525#L1344-1 assume !(1 == ~T2_E~0); 82526#L1349-1 assume !(1 == ~T3_E~0); 81895#L1354-1 assume !(1 == ~T4_E~0); 81896#L1359-1 assume !(1 == ~T5_E~0); 82303#L1364-1 assume !(1 == ~T6_E~0); 81357#L1369-1 assume !(1 == ~T7_E~0); 81358#L1374-1 assume !(1 == ~T8_E~0); 82285#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 83060#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 82656#L1389-1 assume !(1 == ~T11_E~0); 82482#L1394-1 assume !(1 == ~T12_E~0); 82483#L1399-1 assume !(1 == ~E_M~0); 82635#L1404-1 assume !(1 == ~E_1~0); 82978#L1409-1 assume !(1 == ~E_2~0); 82915#L1414-1 assume !(1 == ~E_3~0); 82912#L1419-1 assume 1 == ~E_4~0;~E_4~0 := 2; 82874#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 82796#L1429-1 assume !(1 == ~E_6~0); 82759#L1434-1 assume !(1 == ~E_7~0); 82757#L1439-1 assume !(1 == ~E_8~0); 82755#L1444-1 assume !(1 == ~E_9~0); 82737#L1449-1 assume !(1 == ~E_10~0); 82719#L1454-1 assume !(1 == ~E_11~0); 82705#L1459-1 assume 1 == ~E_12~0;~E_12~0 := 2; 82695#L1464-1 assume { :end_inline_reset_delta_events } true; 82688#L1810-2 [2022-07-22 02:43:06,025 INFO L754 eck$LassoCheckResult]: Loop: 82688#L1810-2 assume !false; 82685#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 82681#L1176 assume !false; 82680#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 82677#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 82666#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 82665#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 82663#L1003 assume !(0 != eval_~tmp~0#1); 82662#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 82661#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 82660#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 82659#L1201-5 assume !(0 == ~T1_E~0); 82657#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 82658#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 85411#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 85406#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 85400#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 85398#L1231-3 assume !(0 == ~T7_E~0); 85396#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 85395#L1241-3 assume !(0 == ~T9_E~0); 85394#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 85393#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 85379#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 85377#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 85375#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 85372#L1271-3 assume !(0 == ~E_2~0); 85370#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 85368#L1281-3 assume !(0 == ~E_4~0); 85366#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 85346#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 85340#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 85335#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 84917#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 84915#L1311-3 assume !(0 == ~E_10~0); 84912#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 84910#L1321-3 assume !(0 == ~E_12~0); 84908#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 84906#L593-42 assume !(1 == ~m_pc~0); 84899#L593-44 is_master_triggered_~__retres1~0#1 := 0; 84896#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 84894#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 84892#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 84890#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 84888#L612-42 assume 1 == ~t1_pc~0; 84885#L613-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 84882#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 84880#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 84878#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 84876#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 84874#L631-42 assume !(1 == ~t2_pc~0); 84871#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 84868#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 84866#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 84865#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 84864#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 84863#L650-42 assume !(1 == ~t3_pc~0); 84861#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 84860#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 84859#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 84858#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 84857#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 84856#L669-42 assume 1 == ~t4_pc~0; 84853#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 84851#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 84848#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 84846#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 84844#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 84842#L688-42 assume 1 == ~t5_pc~0; 84839#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 84837#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 84834#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 84832#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 84830#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 84828#L707-42 assume 1 == ~t6_pc~0; 84825#L708-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 84823#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 84820#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 84818#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 84816#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 84814#L726-42 assume 1 == ~t7_pc~0; 84811#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 84809#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 84806#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 84804#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 84802#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 84800#L745-42 assume !(1 == ~t8_pc~0); 84551#L745-44 is_transmit8_triggered_~__retres1~8#1 := 0; 84549#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 84546#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 84544#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 84542#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 84541#L764-42 assume !(1 == ~t9_pc~0); 84419#L764-44 is_transmit9_triggered_~__retres1~9#1 := 0; 84416#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 84414#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 84411#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 84409#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 84407#L783-42 assume 1 == ~t10_pc~0; 84405#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 84402#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 84400#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 84397#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 84395#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 84393#L802-42 assume !(1 == ~t11_pc~0); 84391#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 84388#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 84387#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 84386#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 84385#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 84383#L821-42 assume 1 == ~t12_pc~0; 84381#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 84378#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 84376#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 84375#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 84191#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 84190#L1339-3 assume !(1 == ~M_E~0); 84188#L1339-5 assume !(1 == ~T1_E~0); 84186#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 82129#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 84183#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 84180#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 84178#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 84176#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 84174#L1374-3 assume !(1 == ~T8_E~0); 84172#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 81311#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 84169#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 84167#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 83991#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 83426#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 83423#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 83421#L1414-3 assume !(1 == ~E_3~0); 83325#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 83213#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 83211#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 83209#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 83103#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 83101#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 83098#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 83097#L1454-3 assume !(1 == ~E_11~0); 83096#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 83005#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 82945#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 82937#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 82898#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 82823#L1829 assume !(0 == start_simulation_~tmp~3#1); 82822#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 82786#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 82756#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 82754#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 82736#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 82718#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 82704#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 82694#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 82688#L1810-2 [2022-07-22 02:43:06,025 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:06,025 INFO L85 PathProgramCache]: Analyzing trace with hash 1087243328, now seen corresponding path program 1 times [2022-07-22 02:43:06,025 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:06,026 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1209306825] [2022-07-22 02:43:06,026 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:06,026 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:06,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:06,047 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:06,048 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:06,048 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1209306825] [2022-07-22 02:43:06,048 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1209306825] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:06,048 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:06,048 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-22 02:43:06,048 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [389085259] [2022-07-22 02:43:06,048 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:06,049 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:43:06,049 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:06,049 INFO L85 PathProgramCache]: Analyzing trace with hash 1087177563, now seen corresponding path program 1 times [2022-07-22 02:43:06,050 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:06,050 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1441841848] [2022-07-22 02:43:06,050 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:06,050 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:06,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:06,084 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:06,084 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:06,084 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1441841848] [2022-07-22 02:43:06,085 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1441841848] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:06,085 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:06,085 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:06,085 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [282391594] [2022-07-22 02:43:06,085 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:06,085 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:43:06,085 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:43:06,086 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:43:06,086 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:43:06,086 INFO L87 Difference]: Start difference. First operand 12481 states and 18328 transitions. cyclomatic complexity: 5855 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:06,241 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:43:06,242 INFO L93 Difference]: Finished difference Result 24576 states and 35870 transitions. [2022-07-22 02:43:06,242 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:43:06,243 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24576 states and 35870 transitions. [2022-07-22 02:43:06,335 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 24344 [2022-07-22 02:43:06,547 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24576 states to 24576 states and 35870 transitions. [2022-07-22 02:43:06,547 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 24576 [2022-07-22 02:43:06,561 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 24576 [2022-07-22 02:43:06,562 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24576 states and 35870 transitions. [2022-07-22 02:43:06,576 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:43:06,577 INFO L369 hiAutomatonCegarLoop]: Abstraction has 24576 states and 35870 transitions. [2022-07-22 02:43:06,588 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24576 states and 35870 transitions. [2022-07-22 02:43:06,938 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24576 to 23856. [2022-07-22 02:43:06,963 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23856 states, 23856 states have (on average 1.461016096579477) internal successors, (34854), 23855 states have internal predecessors, (34854), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:07,118 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23856 states to 23856 states and 34854 transitions. [2022-07-22 02:43:07,118 INFO L392 hiAutomatonCegarLoop]: Abstraction has 23856 states and 34854 transitions. [2022-07-22 02:43:07,119 INFO L374 stractBuchiCegarLoop]: Abstraction has 23856 states and 34854 transitions. [2022-07-22 02:43:07,119 INFO L287 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-07-22 02:43:07,119 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23856 states and 34854 transitions. [2022-07-22 02:43:07,165 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 23624 [2022-07-22 02:43:07,165 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:43:07,165 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:43:07,166 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:07,166 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:07,167 INFO L752 eck$LassoCheckResult]: Stem: 118694#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 118695#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 118200#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 118201#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 118255#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 119786#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 118703#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 118499#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 117892#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 117893#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 119182#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 119303#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 119900#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 119901#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 118631#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 118632#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 119212#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 119119#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 118667#L1201 assume !(0 == ~M_E~0); 118668#L1201-2 assume !(0 == ~T1_E~0); 119633#L1206-1 assume !(0 == ~T2_E~0); 119610#L1211-1 assume !(0 == ~T3_E~0); 119611#L1216-1 assume !(0 == ~T4_E~0); 118483#L1221-1 assume !(0 == ~T5_E~0); 118484#L1226-1 assume !(0 == ~T6_E~0); 118115#L1231-1 assume !(0 == ~T7_E~0); 118116#L1236-1 assume !(0 == ~T8_E~0); 119674#L1241-1 assume !(0 == ~T9_E~0); 118524#L1246-1 assume !(0 == ~T10_E~0); 118525#L1251-1 assume !(0 == ~T11_E~0); 118665#L1256-1 assume !(0 == ~T12_E~0); 117904#L1261-1 assume !(0 == ~E_M~0); 117905#L1266-1 assume !(0 == ~E_1~0); 119875#L1271-1 assume !(0 == ~E_2~0); 119285#L1276-1 assume !(0 == ~E_3~0); 119286#L1281-1 assume !(0 == ~E_4~0); 119227#L1286-1 assume !(0 == ~E_5~0); 118372#L1291-1 assume !(0 == ~E_6~0); 118373#L1296-1 assume !(0 == ~E_7~0); 118984#L1301-1 assume !(0 == ~E_8~0); 118985#L1306-1 assume !(0 == ~E_9~0); 119529#L1311-1 assume !(0 == ~E_10~0); 118319#L1316-1 assume !(0 == ~E_11~0); 118320#L1321-1 assume !(0 == ~E_12~0); 119004#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 119005#L593 assume !(1 == ~m_pc~0); 118206#L593-2 is_master_triggered_~__retres1~0#1 := 0; 118207#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 119853#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 119238#L1492 assume !(0 != activate_threads_~tmp~1#1); 119239#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 119576#L612 assume !(1 == ~t1_pc~0); 119577#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 119779#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 118599#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 118211#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 118212#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 118644#L631 assume 1 == ~t2_pc~0; 118575#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 117989#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 117990#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 118855#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 118856#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 118284#L650 assume !(1 == ~t3_pc~0); 118285#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 119030#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 118208#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 117942#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 117943#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 119204#L669 assume 1 == ~t4_pc~0; 119205#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 119618#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 118630#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 118150#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 118151#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 118381#L688 assume !(1 == ~t5_pc~0); 118166#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 118167#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 119148#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 119070#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 119071#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 119223#L707 assume 1 == ~t6_pc~0; 119727#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 118824#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 118825#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 119725#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 119159#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 118666#L726 assume 1 == ~t7_pc~0; 118563#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 118251#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 119376#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 119738#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 118021#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 118022#L745 assume !(1 == ~t8_pc~0); 118474#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 118494#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 119413#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 118906#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 118907#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 119483#L764 assume 1 == ~t9_pc~0; 118664#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 118501#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 119241#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 119826#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 118041#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 118042#L783 assume !(1 == ~t10_pc~0); 118103#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 118104#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 118144#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 118145#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 118624#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 119620#L802 assume 1 == ~t11_pc~0; 119596#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 117986#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 117987#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 118485#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 118486#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 118598#L821 assume !(1 == ~t12_pc~0); 118870#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 118977#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 117993#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 117994#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 119686#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 119250#L1339 assume !(1 == ~M_E~0); 119251#L1339-2 assume !(1 == ~T1_E~0); 119740#L1344-1 assume !(1 == ~T2_E~0); 119741#L1349-1 assume !(1 == ~T3_E~0); 121475#L1354-1 assume !(1 == ~T4_E~0); 121474#L1359-1 assume !(1 == ~T5_E~0); 121472#L1364-1 assume !(1 == ~T6_E~0); 121471#L1369-1 assume !(1 == ~T7_E~0); 121468#L1374-1 assume !(1 == ~T8_E~0); 121466#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 121465#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 121464#L1389-1 assume !(1 == ~T11_E~0); 121462#L1394-1 assume !(1 == ~T12_E~0); 121460#L1399-1 assume !(1 == ~E_M~0); 121458#L1404-1 assume !(1 == ~E_1~0); 118528#L1409-1 assume !(1 == ~E_2~0); 118529#L1414-1 assume !(1 == ~E_3~0); 119814#L1419-1 assume 1 == ~E_4~0;~E_4~0 := 2; 121386#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 121384#L1429-1 assume !(1 == ~E_6~0); 121250#L1434-1 assume !(1 == ~E_7~0); 121247#L1439-1 assume !(1 == ~E_8~0); 121118#L1444-1 assume !(1 == ~E_9~0); 120956#L1449-1 assume !(1 == ~E_10~0); 120954#L1454-1 assume !(1 == ~E_11~0); 120912#L1459-1 assume 1 == ~E_12~0;~E_12~0 := 2; 120886#L1464-1 assume { :end_inline_reset_delta_events } true; 120880#L1810-2 [2022-07-22 02:43:07,167 INFO L754 eck$LassoCheckResult]: Loop: 120880#L1810-2 assume !false; 120867#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 120856#L1176 assume !false; 120849#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 120839#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 120815#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 120813#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 120810#L1003 assume !(0 != eval_~tmp~0#1); 120806#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 120805#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 120804#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 120803#L1201-5 assume !(0 == ~T1_E~0); 120801#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 120802#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 131766#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 131763#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 131761#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 131759#L1231-3 assume !(0 == ~T7_E~0); 131757#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 131755#L1241-3 assume !(0 == ~T9_E~0); 131753#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 131750#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 131748#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 131746#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 131744#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 131742#L1271-3 assume !(0 == ~E_2~0); 131740#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 131737#L1281-3 assume !(0 == ~E_4~0); 131735#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 131733#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 131731#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 131729#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 131727#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 131724#L1311-3 assume !(0 == ~E_10~0); 131722#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 131720#L1321-3 assume !(0 == ~E_12~0); 131718#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 131716#L593-42 assume !(1 == ~m_pc~0); 131714#L593-44 is_master_triggered_~__retres1~0#1 := 0; 131711#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 131709#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 131707#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 131705#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 131703#L612-42 assume !(1 == ~t1_pc~0); 131700#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 131697#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 131695#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 131693#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 131691#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 131689#L631-42 assume 1 == ~t2_pc~0; 131686#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 131683#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 131681#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 131679#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 131677#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 131675#L650-42 assume !(1 == ~t3_pc~0); 131672#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 131669#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 131667#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 131665#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 131663#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 131661#L669-42 assume 1 == ~t4_pc~0; 131658#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 131655#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 131653#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 131651#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 131649#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 131647#L688-42 assume 1 == ~t5_pc~0; 131644#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 131641#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 131639#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 131637#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 131636#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 131635#L707-42 assume !(1 == ~t6_pc~0); 131634#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 131632#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 131631#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 131630#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 131629#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 131628#L726-42 assume 1 == ~t7_pc~0; 131626#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 131625#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 131623#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 131621#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 131619#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 131617#L745-42 assume !(1 == ~t8_pc~0); 131614#L745-44 is_transmit8_triggered_~__retres1~8#1 := 0; 131612#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 131611#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 131609#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 131607#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 131605#L764-42 assume 1 == ~t9_pc~0; 131602#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 131600#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 131598#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 131597#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 131596#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 131595#L783-42 assume 1 == ~t10_pc~0; 131594#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 131592#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 131591#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 131590#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 131589#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 131588#L802-42 assume !(1 == ~t11_pc~0); 131586#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 131583#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 131581#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 131579#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 131577#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 131575#L821-42 assume !(1 == ~t12_pc~0); 131572#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 131569#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 131567#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 131565#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 131563#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 131561#L1339-3 assume !(1 == ~M_E~0); 131559#L1339-5 assume !(1 == ~T1_E~0); 131556#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 119260#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 131553#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 131551#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 131549#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 131547#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 131544#L1374-3 assume !(1 == ~T8_E~0); 131542#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 123499#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 131539#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 131537#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 131535#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 131532#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 131530#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 131528#L1414-3 assume !(1 == ~E_3~0); 131526#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 131522#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 131520#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 131517#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 131515#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 131513#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 131511#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 131509#L1454-3 assume !(1 == ~E_11~0); 131507#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 123643#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 121372#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 121365#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 121364#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 121354#L1829 assume !(0 == start_simulation_~tmp~3#1); 121352#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 121236#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 121116#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 121102#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 121100#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 120953#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 120911#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 120885#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 120880#L1810-2 [2022-07-22 02:43:07,167 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:07,167 INFO L85 PathProgramCache]: Analyzing trace with hash 1374703233, now seen corresponding path program 1 times [2022-07-22 02:43:07,167 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:07,167 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [150703127] [2022-07-22 02:43:07,167 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:07,167 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:07,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:07,198 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:07,198 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:07,198 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [150703127] [2022-07-22 02:43:07,198 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [150703127] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:07,198 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:07,198 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-22 02:43:07,198 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [729113969] [2022-07-22 02:43:07,198 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:07,198 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:43:07,199 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:07,199 INFO L85 PathProgramCache]: Analyzing trace with hash 1534384668, now seen corresponding path program 1 times [2022-07-22 02:43:07,199 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:07,199 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [14921231] [2022-07-22 02:43:07,199 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:07,199 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:07,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:07,220 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:07,220 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:07,220 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [14921231] [2022-07-22 02:43:07,220 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [14921231] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:07,220 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:07,220 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:07,220 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1804844252] [2022-07-22 02:43:07,220 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:07,221 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:43:07,221 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:43:07,221 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-07-22 02:43:07,221 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-07-22 02:43:07,221 INFO L87 Difference]: Start difference. First operand 23856 states and 34854 transitions. cyclomatic complexity: 11014 Second operand has 5 states, 5 states have (on average 30.0) internal successors, (150), 5 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:07,760 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:43:07,761 INFO L93 Difference]: Finished difference Result 68097 states and 99301 transitions. [2022-07-22 02:43:07,761 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-07-22 02:43:07,761 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 68097 states and 99301 transitions. [2022-07-22 02:43:08,214 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 67512 [2022-07-22 02:43:08,371 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 68097 states to 68097 states and 99301 transitions. [2022-07-22 02:43:08,371 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 68097 [2022-07-22 02:43:08,414 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 68097 [2022-07-22 02:43:08,414 INFO L73 IsDeterministic]: Start isDeterministic. Operand 68097 states and 99301 transitions. [2022-07-22 02:43:08,616 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:43:08,616 INFO L369 hiAutomatonCegarLoop]: Abstraction has 68097 states and 99301 transitions. [2022-07-22 02:43:08,657 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68097 states and 99301 transitions. [2022-07-22 02:43:09,059 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68097 to 24507. [2022-07-22 02:43:09,081 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24507 states, 24507 states have (on average 1.448769739258171) internal successors, (35505), 24506 states have internal predecessors, (35505), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:09,112 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24507 states to 24507 states and 35505 transitions. [2022-07-22 02:43:09,112 INFO L392 hiAutomatonCegarLoop]: Abstraction has 24507 states and 35505 transitions. [2022-07-22 02:43:09,112 INFO L374 stractBuchiCegarLoop]: Abstraction has 24507 states and 35505 transitions. [2022-07-22 02:43:09,112 INFO L287 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-07-22 02:43:09,112 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24507 states and 35505 transitions. [2022-07-22 02:43:09,162 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 24272 [2022-07-22 02:43:09,163 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:43:09,163 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:43:09,164 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:09,164 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:09,164 INFO L752 eck$LassoCheckResult]: Stem: 210660#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 210661#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 210166#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 210167#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 210221#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 211751#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 210670#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 210463#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 209858#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 209859#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 211144#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 211267#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 211871#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 211872#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 210596#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 210597#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 211173#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 211080#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 210633#L1201 assume !(0 == ~M_E~0); 210634#L1201-2 assume !(0 == ~T1_E~0); 211609#L1206-1 assume !(0 == ~T2_E~0); 211588#L1211-1 assume !(0 == ~T3_E~0); 211589#L1216-1 assume !(0 == ~T4_E~0); 210445#L1221-1 assume !(0 == ~T5_E~0); 210446#L1226-1 assume !(0 == ~T6_E~0); 210081#L1231-1 assume !(0 == ~T7_E~0); 210082#L1236-1 assume !(0 == ~T8_E~0); 211646#L1241-1 assume !(0 == ~T9_E~0); 210484#L1246-1 assume !(0 == ~T10_E~0); 210485#L1251-1 assume !(0 == ~T11_E~0); 210631#L1256-1 assume !(0 == ~T12_E~0); 209868#L1261-1 assume !(0 == ~E_M~0); 209869#L1266-1 assume !(0 == ~E_1~0); 211844#L1271-1 assume !(0 == ~E_2~0); 211247#L1276-1 assume !(0 == ~E_3~0); 211248#L1281-1 assume !(0 == ~E_4~0); 211188#L1286-1 assume !(0 == ~E_5~0); 210334#L1291-1 assume !(0 == ~E_6~0); 210335#L1296-1 assume !(0 == ~E_7~0); 210941#L1301-1 assume !(0 == ~E_8~0); 210942#L1306-1 assume !(0 == ~E_9~0); 211503#L1311-1 assume !(0 == ~E_10~0); 210284#L1316-1 assume !(0 == ~E_11~0); 210285#L1321-1 assume !(0 == ~E_12~0); 210960#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 210961#L593 assume !(1 == ~m_pc~0); 210172#L593-2 is_master_triggered_~__retres1~0#1 := 0; 210173#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 211822#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 211201#L1492 assume !(0 != activate_threads_~tmp~1#1); 211202#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 211553#L612 assume !(1 == ~t1_pc~0); 211554#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 211858#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 211859#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 210177#L1500 assume !(0 != activate_threads_~tmp___0~0#1); 210178#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 210609#L631 assume 1 == ~t2_pc~0; 210538#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 209955#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 209956#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 210812#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 210813#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 210250#L650 assume !(1 == ~t3_pc~0); 210251#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 210987#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 210174#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 209908#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 209909#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 211165#L669 assume 1 == ~t4_pc~0; 211166#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 211597#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 210595#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 210116#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 210117#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 210344#L688 assume !(1 == ~t5_pc~0); 210132#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 210133#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 211107#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 211025#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 211026#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 211180#L707 assume 1 == ~t6_pc~0; 211696#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 210780#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 210781#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 211692#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 211115#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 210632#L726 assume 1 == ~t7_pc~0; 210524#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 210217#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 211341#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 211708#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 209987#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 209988#L745 assume !(1 == ~t8_pc~0); 210438#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 210458#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 211379#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 210865#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 210866#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 211457#L764 assume 1 == ~t9_pc~0; 210630#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 210465#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 211204#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 211794#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 210007#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 210008#L783 assume !(1 == ~t10_pc~0); 210069#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 210070#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 210110#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 210111#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 210583#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 211599#L802 assume 1 == ~t11_pc~0; 211576#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 209952#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 209953#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 210447#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 210448#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 210561#L821 assume !(1 == ~t12_pc~0); 210827#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 210933#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 209957#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 209958#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 211659#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 211213#L1339 assume !(1 == ~M_E~0); 211214#L1339-2 assume !(1 == ~T1_E~0); 211710#L1344-1 assume !(1 == ~T2_E~0); 211711#L1349-1 assume !(1 == ~T3_E~0); 221554#L1354-1 assume !(1 == ~T4_E~0); 221553#L1359-1 assume !(1 == ~T5_E~0); 211862#L1364-1 assume !(1 == ~T6_E~0); 211863#L1369-1 assume !(1 == ~T7_E~0); 213924#L1374-1 assume !(1 == ~T8_E~0); 213922#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 213915#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 213887#L1389-1 assume !(1 == ~T11_E~0); 213885#L1394-1 assume !(1 == ~T12_E~0); 213884#L1399-1 assume !(1 == ~E_M~0); 213882#L1404-1 assume !(1 == ~E_1~0); 210489#L1409-1 assume !(1 == ~E_2~0); 210490#L1414-1 assume !(1 == ~E_3~0); 211779#L1419-1 assume 1 == ~E_4~0;~E_4~0 := 2; 213848#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 213820#L1429-1 assume !(1 == ~E_6~0); 213818#L1434-1 assume !(1 == ~E_7~0); 213787#L1439-1 assume !(1 == ~E_8~0); 213771#L1444-1 assume !(1 == ~E_9~0); 213769#L1449-1 assume !(1 == ~E_10~0); 213752#L1454-1 assume !(1 == ~E_11~0); 213741#L1459-1 assume 1 == ~E_12~0;~E_12~0 := 2; 213731#L1464-1 assume { :end_inline_reset_delta_events } true; 213724#L1810-2 [2022-07-22 02:43:09,164 INFO L754 eck$LassoCheckResult]: Loop: 213724#L1810-2 assume !false; 213721#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 213717#L1176 assume !false; 213716#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 213713#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 213702#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 213701#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 213699#L1003 assume !(0 != eval_~tmp~0#1); 213698#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 213697#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 213696#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 213695#L1201-5 assume !(0 == ~T1_E~0); 213692#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 213693#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 219890#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 219889#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 219875#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 219873#L1231-3 assume !(0 == ~T7_E~0); 219871#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 219868#L1241-3 assume !(0 == ~T9_E~0); 219866#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 219864#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 219862#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 219860#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 219858#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 219856#L1271-3 assume !(0 == ~E_2~0); 219854#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 219852#L1281-3 assume !(0 == ~E_4~0); 219850#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 219848#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 219846#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 219782#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 219781#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 219780#L1311-3 assume !(0 == ~E_10~0); 219779#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 219778#L1321-3 assume !(0 == ~E_12~0); 219777#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 219776#L593-42 assume !(1 == ~m_pc~0); 219775#L593-44 is_master_triggered_~__retres1~0#1 := 0; 219774#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 219773#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 219772#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 219771#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 211052#L612-42 assume 1 == ~t1_pc~0; 211054#L613-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 213100#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 213101#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 213094#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 213093#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 213091#L631-42 assume !(1 == ~t2_pc~0); 213089#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 213086#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 213083#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 213081#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 213079#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 213077#L650-42 assume 1 == ~t3_pc~0; 213075#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 213072#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 213069#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 213067#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 213065#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 213063#L669-42 assume !(1 == ~t4_pc~0); 213061#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 213058#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 213055#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 213053#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 213051#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 213049#L688-42 assume !(1 == ~t5_pc~0); 213047#L688-44 is_transmit5_triggered_~__retres1~5#1 := 0; 213044#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 213041#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 213039#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 213036#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 213034#L707-42 assume 1 == ~t6_pc~0; 213031#L708-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 213029#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 213026#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 213024#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 213021#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 213022#L726-42 assume !(1 == ~t7_pc~0); 218974#L726-44 is_transmit7_triggered_~__retres1~7#1 := 0; 218971#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 218969#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 218967#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 218506#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 218505#L745-42 assume !(1 == ~t8_pc~0); 218503#L745-44 is_transmit8_triggered_~__retres1~8#1 := 0; 218500#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 218498#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 217666#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 217663#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 217661#L764-42 assume !(1 == ~t9_pc~0); 217659#L764-44 is_transmit9_triggered_~__retres1~9#1 := 0; 217657#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 217656#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 217655#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 217470#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 217468#L783-42 assume 1 == ~t10_pc~0; 217466#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 217463#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 217460#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 217458#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 217456#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 217454#L802-42 assume 1 == ~t11_pc~0; 217451#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 217449#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 217447#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 217444#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 216996#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 216994#L821-42 assume 1 == ~t12_pc~0; 216992#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 216989#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 216986#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 216984#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 216982#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 216980#L1339-3 assume !(1 == ~M_E~0); 216978#L1339-5 assume !(1 == ~T1_E~0); 216976#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 212886#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 216972#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 216970#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 216968#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 216966#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 216964#L1374-3 assume !(1 == ~T8_E~0); 216961#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 212870#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 216958#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 216956#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 216954#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 216952#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 216949#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 216947#L1414-3 assume !(1 == ~E_3~0); 216651#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 216646#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 216644#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 216642#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 216640#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 216638#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 216636#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 216635#L1454-3 assume !(1 == ~E_11~0); 216634#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 214586#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 213966#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 213925#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 213895#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 213867#L1829 assume !(0 == start_simulation_~tmp~3#1); 213834#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 213807#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 213802#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 213785#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 213767#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 213751#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 213740#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 213730#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 213724#L1810-2 [2022-07-22 02:43:09,164 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:09,164 INFO L85 PathProgramCache]: Analyzing trace with hash -1568878845, now seen corresponding path program 1 times [2022-07-22 02:43:09,165 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:09,165 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1387539400] [2022-07-22 02:43:09,165 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:09,165 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:09,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:09,185 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:09,185 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:09,186 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1387539400] [2022-07-22 02:43:09,186 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1387539400] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:09,186 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:09,186 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:09,186 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [750100948] [2022-07-22 02:43:09,186 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:09,186 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:43:09,186 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:09,186 INFO L85 PathProgramCache]: Analyzing trace with hash 776662428, now seen corresponding path program 1 times [2022-07-22 02:43:09,186 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:09,186 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [814069623] [2022-07-22 02:43:09,187 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:09,187 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:09,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:09,205 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:09,205 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:09,206 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [814069623] [2022-07-22 02:43:09,206 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [814069623] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:09,206 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:09,206 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:09,206 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1069106073] [2022-07-22 02:43:09,206 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:09,206 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:43:09,206 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:43:09,206 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-22 02:43:09,206 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-22 02:43:09,207 INFO L87 Difference]: Start difference. First operand 24507 states and 35505 transitions. cyclomatic complexity: 11014 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:09,640 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:43:09,640 INFO L93 Difference]: Finished difference Result 59818 states and 86081 transitions. [2022-07-22 02:43:09,640 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-22 02:43:09,641 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 59818 states and 86081 transitions. [2022-07-22 02:43:09,860 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 58776 [2022-07-22 02:43:10,011 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 59818 states to 59818 states and 86081 transitions. [2022-07-22 02:43:10,011 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 59818 [2022-07-22 02:43:10,050 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 59818 [2022-07-22 02:43:10,050 INFO L73 IsDeterministic]: Start isDeterministic. Operand 59818 states and 86081 transitions. [2022-07-22 02:43:10,128 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:43:10,128 INFO L369 hiAutomatonCegarLoop]: Abstraction has 59818 states and 86081 transitions. [2022-07-22 02:43:10,310 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59818 states and 86081 transitions. [2022-07-22 02:43:10,768 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59818 to 47010. [2022-07-22 02:43:10,830 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47010 states, 47010 states have (on average 1.4430972133588598) internal successors, (67840), 47009 states have internal predecessors, (67840), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:10,909 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47010 states to 47010 states and 67840 transitions. [2022-07-22 02:43:10,910 INFO L392 hiAutomatonCegarLoop]: Abstraction has 47010 states and 67840 transitions. [2022-07-22 02:43:10,910 INFO L374 stractBuchiCegarLoop]: Abstraction has 47010 states and 67840 transitions. [2022-07-22 02:43:10,910 INFO L287 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-07-22 02:43:10,910 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 47010 states and 67840 transitions. [2022-07-22 02:43:11,037 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 46768 [2022-07-22 02:43:11,037 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:43:11,037 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:43:11,039 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:11,039 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:11,039 INFO L752 eck$LassoCheckResult]: Stem: 294998#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 294999#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 294501#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 294502#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 294556#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 296099#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 295007#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 294803#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 294193#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 294194#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 295483#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 295610#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 296221#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 296222#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 294936#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 294937#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 295515#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 295421#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 294973#L1201 assume !(0 == ~M_E~0); 294974#L1201-2 assume !(0 == ~T1_E~0); 295953#L1206-1 assume !(0 == ~T2_E~0); 295932#L1211-1 assume !(0 == ~T3_E~0); 295933#L1216-1 assume !(0 == ~T4_E~0); 294787#L1221-1 assume !(0 == ~T5_E~0); 294788#L1226-1 assume !(0 == ~T6_E~0); 294416#L1231-1 assume !(0 == ~T7_E~0); 294417#L1236-1 assume !(0 == ~T8_E~0); 295989#L1241-1 assume !(0 == ~T9_E~0); 294828#L1246-1 assume !(0 == ~T10_E~0); 294829#L1251-1 assume !(0 == ~T11_E~0); 294971#L1256-1 assume !(0 == ~T12_E~0); 294205#L1261-1 assume !(0 == ~E_M~0); 294206#L1266-1 assume !(0 == ~E_1~0); 296197#L1271-1 assume !(0 == ~E_2~0); 295589#L1276-1 assume !(0 == ~E_3~0); 295590#L1281-1 assume !(0 == ~E_4~0); 295529#L1286-1 assume !(0 == ~E_5~0); 294669#L1291-1 assume !(0 == ~E_6~0); 294670#L1296-1 assume !(0 == ~E_7~0); 295287#L1301-1 assume !(0 == ~E_8~0); 295288#L1306-1 assume !(0 == ~E_9~0); 295844#L1311-1 assume !(0 == ~E_10~0); 294619#L1316-1 assume !(0 == ~E_11~0); 294620#L1321-1 assume !(0 == ~E_12~0); 295307#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 295308#L593 assume !(1 == ~m_pc~0); 294507#L593-2 is_master_triggered_~__retres1~0#1 := 0; 294508#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 296172#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 295542#L1492 assume !(0 != activate_threads_~tmp~1#1); 295543#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 295896#L612 assume !(1 == ~t1_pc~0); 295897#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 296212#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 294905#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 294512#L1500 assume !(0 != activate_threads_~tmp___0~0#1); 294513#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 294949#L631 assume !(1 == ~t2_pc~0); 294950#L631-2 is_transmit2_triggered_~__retres1~2#1 := 0; 294289#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 294290#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 295152#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 295153#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 294585#L650 assume !(1 == ~t3_pc~0); 294586#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 295336#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 294509#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 294243#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 294244#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 295507#L669 assume 1 == ~t4_pc~0; 295508#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 295942#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 294935#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 294451#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 294452#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 294679#L688 assume !(1 == ~t5_pc~0); 294467#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 294468#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 295449#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 295373#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 295374#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 295525#L707 assume 1 == ~t6_pc~0; 296036#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 295121#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 295122#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 296034#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 295462#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 294972#L726 assume 1 == ~t7_pc~0; 294870#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 294552#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 295686#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 296049#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 294321#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 294322#L745 assume !(1 == ~t8_pc~0); 294779#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 294798#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 295726#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 295203#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 295204#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 295795#L764 assume 1 == ~t9_pc~0; 294970#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 294805#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 295546#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 296148#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 294341#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 294342#L783 assume !(1 == ~t10_pc~0); 294403#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 294404#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 294445#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 294446#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 294929#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 295945#L802 assume 1 == ~t11_pc~0; 295916#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 294286#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 294287#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 294789#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 294790#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 294904#L821 assume !(1 == ~t12_pc~0); 295169#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 295278#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 294293#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 294294#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 296001#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 295556#L1339 assume !(1 == ~M_E~0); 295557#L1339-2 assume !(1 == ~T1_E~0); 296050#L1344-1 assume !(1 == ~T2_E~0); 296051#L1349-1 assume !(1 == ~T3_E~0); 312834#L1354-1 assume !(1 == ~T4_E~0); 312833#L1359-1 assume !(1 == ~T5_E~0); 312832#L1364-1 assume !(1 == ~T6_E~0); 312831#L1369-1 assume !(1 == ~T7_E~0); 312830#L1374-1 assume !(1 == ~T8_E~0); 295304#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 295305#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 312828#L1389-1 assume !(1 == ~T11_E~0); 312829#L1394-1 assume !(1 == ~T12_E~0); 312826#L1399-1 assume !(1 == ~E_M~0); 312827#L1404-1 assume !(1 == ~E_1~0); 312824#L1409-1 assume !(1 == ~E_2~0); 312825#L1414-1 assume !(1 == ~E_3~0); 295628#L1419-1 assume 1 == ~E_4~0;~E_4~0 := 2; 295629#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 314213#L1429-1 assume !(1 == ~E_6~0); 314207#L1434-1 assume !(1 == ~E_7~0); 314208#L1439-1 assume !(1 == ~E_8~0); 314200#L1444-1 assume !(1 == ~E_9~0); 314201#L1449-1 assume !(1 == ~E_10~0); 314194#L1454-1 assume !(1 == ~E_11~0); 314195#L1459-1 assume 1 == ~E_12~0;~E_12~0 := 2; 314192#L1464-1 assume { :end_inline_reset_delta_events } true; 316449#L1810-2 [2022-07-22 02:43:11,040 INFO L754 eck$LassoCheckResult]: Loop: 316449#L1810-2 assume !false; 315709#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 315704#L1176 assume !false; 315701#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 315586#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 315572#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 315359#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 307846#L1003 assume !(0 != eval_~tmp~0#1); 307847#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 317408#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 317406#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 317404#L1201-5 assume !(0 == ~T1_E~0); 317402#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 317400#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 317398#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 317395#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 317393#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 317391#L1231-3 assume !(0 == ~T7_E~0); 317389#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 317387#L1241-3 assume !(0 == ~T9_E~0); 317385#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 317382#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 317380#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 317378#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 317376#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 317374#L1271-3 assume !(0 == ~E_2~0); 317372#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 317369#L1281-3 assume !(0 == ~E_4~0); 317367#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 317365#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 317363#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 317361#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 317359#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 317356#L1311-3 assume !(0 == ~E_10~0); 317354#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 317352#L1321-3 assume !(0 == ~E_12~0); 317350#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 317348#L593-42 assume !(1 == ~m_pc~0); 317346#L593-44 is_master_triggered_~__retres1~0#1 := 0; 317343#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 317341#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 317339#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 317337#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 317330#L612-42 assume !(1 == ~t1_pc~0); 317328#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 317326#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 317324#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 317322#L1500-42 assume !(0 != activate_threads_~tmp___0~0#1); 317319#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 317316#L631-42 assume !(1 == ~t2_pc~0); 298097#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 317313#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 317282#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 317275#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 317266#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 317259#L650-42 assume !(1 == ~t3_pc~0); 317250#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 317242#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 317234#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 317224#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 317216#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 317208#L669-42 assume 1 == ~t4_pc~0; 317200#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 317197#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 317195#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 317193#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 317192#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 317190#L688-42 assume !(1 == ~t5_pc~0); 317188#L688-44 is_transmit5_triggered_~__retres1~5#1 := 0; 317185#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 317183#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 317181#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 317178#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 317176#L707-42 assume 1 == ~t6_pc~0; 317173#L708-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 317171#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 317169#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 317167#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 317164#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 317162#L726-42 assume 1 == ~t7_pc~0; 317159#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 317157#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 317155#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 317153#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 317150#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 317148#L745-42 assume !(1 == ~t8_pc~0); 317145#L745-44 is_transmit8_triggered_~__retres1~8#1 := 0; 317143#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 317141#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 317139#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 317136#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 317134#L764-42 assume !(1 == ~t9_pc~0); 317132#L764-44 is_transmit9_triggered_~__retres1~9#1 := 0; 317129#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 317127#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 317125#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 317122#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 317120#L783-42 assume !(1 == ~t10_pc~0); 317117#L783-44 is_transmit10_triggered_~__retres1~10#1 := 0; 317115#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 317113#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 317111#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 317108#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 317106#L802-42 assume !(1 == ~t11_pc~0); 317104#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 317101#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 317099#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 317097#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 317094#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 317092#L821-42 assume !(1 == ~t12_pc~0); 317089#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 317087#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 317085#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 317083#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 317080#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 317078#L1339-3 assume !(1 == ~M_E~0); 317076#L1339-5 assume !(1 == ~T1_E~0); 317074#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 310651#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 317069#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 317066#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 317064#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 317062#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 317060#L1374-3 assume !(1 == ~T8_E~0); 317058#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 311061#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 317054#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 317052#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 317050#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 317048#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 317046#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 317045#L1414-3 assume !(1 == ~E_3~0); 317044#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 313923#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 317039#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 317037#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 317036#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 317035#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 317034#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 317033#L1454-3 assume !(1 == ~E_11~0); 317032#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 317005#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 317025#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 317018#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 317017#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 316574#L1829 assume !(0 == start_simulation_~tmp~3#1); 316573#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 316548#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 316543#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 316541#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 316539#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 316537#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 316534#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 316451#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 316449#L1810-2 [2022-07-22 02:43:11,040 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:11,040 INFO L85 PathProgramCache]: Analyzing trace with hash -451693884, now seen corresponding path program 1 times [2022-07-22 02:43:11,041 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:11,041 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [631702245] [2022-07-22 02:43:11,041 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:11,041 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:11,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:11,066 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:11,067 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:11,067 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [631702245] [2022-07-22 02:43:11,067 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [631702245] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:11,067 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:11,067 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-22 02:43:11,067 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [577556856] [2022-07-22 02:43:11,067 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:11,068 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:43:11,068 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:11,068 INFO L85 PathProgramCache]: Analyzing trace with hash 1846913249, now seen corresponding path program 1 times [2022-07-22 02:43:11,068 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:11,068 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [441857960] [2022-07-22 02:43:11,069 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:11,069 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:11,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:11,090 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:11,091 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:11,091 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [441857960] [2022-07-22 02:43:11,091 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [441857960] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:11,091 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:11,091 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:11,091 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [122439850] [2022-07-22 02:43:11,091 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:11,092 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:43:11,092 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:43:11,092 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:43:11,092 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:43:11,092 INFO L87 Difference]: Start difference. First operand 47010 states and 67840 transitions. cyclomatic complexity: 20846 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:11,635 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:43:11,635 INFO L93 Difference]: Finished difference Result 90337 states and 129873 transitions. [2022-07-22 02:43:11,635 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:43:11,636 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 90337 states and 129873 transitions. [2022-07-22 02:43:12,261 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 90016 [2022-07-22 02:43:12,482 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 90337 states to 90337 states and 129873 transitions. [2022-07-22 02:43:12,483 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 90337 [2022-07-22 02:43:12,528 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 90337 [2022-07-22 02:43:12,528 INFO L73 IsDeterministic]: Start isDeterministic. Operand 90337 states and 129873 transitions. [2022-07-22 02:43:12,587 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:43:12,587 INFO L369 hiAutomatonCegarLoop]: Abstraction has 90337 states and 129873 transitions. [2022-07-22 02:43:12,648 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90337 states and 129873 transitions. [2022-07-22 02:43:13,534 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90337 to 90273. [2022-07-22 02:43:13,619 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 90273 states, 90273 states have (on average 1.4379604089816447) internal successors, (129809), 90272 states have internal predecessors, (129809), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:14,100 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90273 states to 90273 states and 129809 transitions. [2022-07-22 02:43:14,103 INFO L392 hiAutomatonCegarLoop]: Abstraction has 90273 states and 129809 transitions. [2022-07-22 02:43:14,103 INFO L374 stractBuchiCegarLoop]: Abstraction has 90273 states and 129809 transitions. [2022-07-22 02:43:14,103 INFO L287 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-07-22 02:43:14,103 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 90273 states and 129809 transitions. [2022-07-22 02:43:14,292 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 89952 [2022-07-22 02:43:14,292 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:43:14,292 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:43:14,309 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:14,309 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:14,310 INFO L752 eck$LassoCheckResult]: Stem: 432348#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 432349#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 431857#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 431858#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 431911#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 433422#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 432359#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 432153#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 431547#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 431548#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 432826#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 432950#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 433531#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 433532#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 432284#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 432285#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 432856#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 432769#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 432322#L1201 assume !(0 == ~M_E~0); 432323#L1201-2 assume !(0 == ~T1_E~0); 433283#L1206-1 assume !(0 == ~T2_E~0); 433263#L1211-1 assume !(0 == ~T3_E~0); 433264#L1216-1 assume !(0 == ~T4_E~0); 432137#L1221-1 assume !(0 == ~T5_E~0); 432138#L1226-1 assume !(0 == ~T6_E~0); 431771#L1231-1 assume !(0 == ~T7_E~0); 431772#L1236-1 assume !(0 == ~T8_E~0); 433325#L1241-1 assume !(0 == ~T9_E~0); 432177#L1246-1 assume !(0 == ~T10_E~0); 432178#L1251-1 assume !(0 == ~T11_E~0); 432320#L1256-1 assume !(0 == ~T12_E~0); 431560#L1261-1 assume !(0 == ~E_M~0); 431561#L1266-1 assume !(0 == ~E_1~0); 433502#L1271-1 assume !(0 == ~E_2~0); 432930#L1276-1 assume !(0 == ~E_3~0); 432931#L1281-1 assume !(0 == ~E_4~0); 432870#L1286-1 assume !(0 == ~E_5~0); 432023#L1291-1 assume !(0 == ~E_6~0); 432024#L1296-1 assume !(0 == ~E_7~0); 432642#L1301-1 assume !(0 == ~E_8~0); 432643#L1306-1 assume !(0 == ~E_9~0); 433187#L1311-1 assume !(0 == ~E_10~0); 431974#L1316-1 assume !(0 == ~E_11~0); 431975#L1321-1 assume !(0 == ~E_12~0); 432661#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 432662#L593 assume !(1 == ~m_pc~0); 431863#L593-2 is_master_triggered_~__retres1~0#1 := 0; 431864#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 433482#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 432884#L1492 assume !(0 != activate_threads_~tmp~1#1); 432885#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 433226#L612 assume !(1 == ~t1_pc~0); 433227#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 433520#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 432253#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 431868#L1500 assume !(0 != activate_threads_~tmp___0~0#1); 431869#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 432297#L631 assume !(1 == ~t2_pc~0); 432298#L631-2 is_transmit2_triggered_~__retres1~2#1 := 0; 431644#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 431645#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 432508#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 432509#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 431940#L650 assume !(1 == ~t3_pc~0); 431941#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 432686#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 431865#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 431598#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 431599#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 432848#L669 assume !(1 == ~t4_pc~0); 432849#L669-2 is_transmit4_triggered_~__retres1~4#1 := 0; 433272#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 432283#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 431807#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 431808#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 432035#L688 assume !(1 == ~t5_pc~0); 431823#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 431824#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 432794#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 432724#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 432725#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 432866#L707 assume 1 == ~t6_pc~0; 433371#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 432474#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 432475#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 433366#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 432804#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 432321#L726 assume 1 == ~t7_pc~0; 432219#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 431907#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 433024#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 433379#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 431676#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 431677#L745 assume !(1 == ~t8_pc~0); 432130#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 432148#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 433064#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 432560#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 432561#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 433140#L764 assume 1 == ~t9_pc~0; 432319#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 432155#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 432887#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 433457#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 431696#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 431697#L783 assume !(1 == ~t10_pc~0); 431758#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 431759#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 431800#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 431801#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 432277#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 433274#L802 assume 1 == ~t11_pc~0; 433250#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 431640#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 431641#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 432139#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 432140#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 432252#L821 assume !(1 == ~t12_pc~0); 432523#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 432632#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 431648#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 431649#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 433336#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 432896#L1339 assume !(1 == ~M_E~0); 432897#L1339-2 assume !(1 == ~T1_E~0); 433381#L1344-1 assume !(1 == ~T2_E~0); 433382#L1349-1 assume !(1 == ~T3_E~0); 432655#L1354-1 assume !(1 == ~T4_E~0); 432656#L1359-1 assume !(1 == ~T5_E~0); 433522#L1364-1 assume !(1 == ~T6_E~0); 433523#L1369-1 assume !(1 == ~T7_E~0); 433081#L1374-1 assume !(1 == ~T8_E~0); 433082#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 457581#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 462762#L1389-1 assume !(1 == ~T11_E~0); 462760#L1394-1 assume !(1 == ~T12_E~0); 462758#L1399-1 assume !(1 == ~E_M~0); 462756#L1404-1 assume !(1 == ~E_1~0); 462754#L1409-1 assume !(1 == ~E_2~0); 462752#L1414-1 assume !(1 == ~E_3~0); 462749#L1419-1 assume 1 == ~E_4~0;~E_4~0 := 2; 462747#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 462745#L1429-1 assume !(1 == ~E_6~0); 462743#L1434-1 assume !(1 == ~E_7~0); 462741#L1439-1 assume !(1 == ~E_8~0); 462738#L1444-1 assume !(1 == ~E_9~0); 462736#L1449-1 assume !(1 == ~E_10~0); 462734#L1454-1 assume !(1 == ~E_11~0); 462732#L1459-1 assume 1 == ~E_12~0;~E_12~0 := 2; 432800#L1464-1 assume { :end_inline_reset_delta_events } true; 432801#L1810-2 [2022-07-22 02:43:14,311 INFO L754 eck$LassoCheckResult]: Loop: 432801#L1810-2 assume !false; 475020#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 475015#L1176 assume !false; 475013#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 474979#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 474962#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 474954#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 474943#L1003 assume !(0 != eval_~tmp~0#1); 474944#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 476337#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 476333#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 476329#L1201-5 assume !(0 == ~T1_E~0); 476325#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 476321#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 476316#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 476312#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 476307#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 476302#L1231-3 assume !(0 == ~T7_E~0); 476296#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 476291#L1241-3 assume !(0 == ~T9_E~0); 476287#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 476283#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 476280#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 476276#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 476271#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 476267#L1271-3 assume !(0 == ~E_2~0); 476262#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 476258#L1281-3 assume !(0 == ~E_4~0); 476253#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 476248#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 476242#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 476237#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 476231#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 476226#L1311-3 assume !(0 == ~E_10~0); 476221#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 476216#L1321-3 assume !(0 == ~E_12~0); 476209#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 476203#L593-42 assume !(1 == ~m_pc~0); 476196#L593-44 is_master_triggered_~__retres1~0#1 := 0; 476190#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 476184#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 476179#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 476174#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 476169#L612-42 assume !(1 == ~t1_pc~0); 476163#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 476157#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 476149#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 476142#L1500-42 assume !(0 != activate_threads_~tmp___0~0#1); 476133#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 476127#L631-42 assume !(1 == ~t2_pc~0); 474607#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 476115#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 476108#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 476101#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 476093#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 476086#L650-42 assume 1 == ~t3_pc~0; 476078#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 476071#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 476064#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 476059#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 476050#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 476043#L669-42 assume !(1 == ~t4_pc~0); 476035#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 476028#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 476019#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 476003#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 475995#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 475990#L688-42 assume !(1 == ~t5_pc~0); 475986#L688-44 is_transmit5_triggered_~__retres1~5#1 := 0; 475981#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 475976#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 475970#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 475965#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 475960#L707-42 assume !(1 == ~t6_pc~0); 475955#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 475949#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 475942#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 475935#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 475929#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 475923#L726-42 assume !(1 == ~t7_pc~0); 475917#L726-44 is_transmit7_triggered_~__retres1~7#1 := 0; 475911#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 475905#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 475900#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 475895#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 475890#L745-42 assume 1 == ~t8_pc~0; 475885#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 475878#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 475872#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 475865#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 475858#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 475854#L764-42 assume !(1 == ~t9_pc~0); 475850#L764-44 is_transmit9_triggered_~__retres1~9#1 := 0; 475845#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 475839#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 475833#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 475828#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 475823#L783-42 assume 1 == ~t10_pc~0; 475818#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 475812#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 475806#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 475798#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 475792#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 475786#L802-42 assume !(1 == ~t11_pc~0); 475780#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 475774#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 475766#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 475761#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 475757#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 475753#L821-42 assume 1 == ~t12_pc~0; 475748#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 475742#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 475736#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 475729#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 475724#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 475719#L1339-3 assume !(1 == ~M_E~0); 475714#L1339-5 assume !(1 == ~T1_E~0); 475708#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 457665#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 475695#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 475689#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 475684#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 475679#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 475675#L1374-3 assume !(1 == ~T8_E~0); 475669#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 466945#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 475658#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 475653#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 475648#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 475642#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 475636#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 475629#L1414-3 assume !(1 == ~E_3~0); 475624#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 473197#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 475615#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 475608#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 475604#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 475598#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 475594#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 475590#L1454-3 assume !(1 == ~E_11~0); 475586#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 463073#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 475137#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 475129#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 475127#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 475112#L1829 assume !(0 == start_simulation_~tmp~3#1); 475102#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 475078#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 475073#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 475071#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 475069#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 475066#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 475064#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 475062#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 432801#L1810-2 [2022-07-22 02:43:14,311 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:14,311 INFO L85 PathProgramCache]: Analyzing trace with hash 1008300037, now seen corresponding path program 1 times [2022-07-22 02:43:14,312 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:14,315 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [364625164] [2022-07-22 02:43:14,315 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:14,316 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:14,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:14,352 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:14,352 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:14,352 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [364625164] [2022-07-22 02:43:14,352 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [364625164] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:14,353 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:14,353 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:14,353 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [343048675] [2022-07-22 02:43:14,353 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:14,353 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:43:14,353 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:14,354 INFO L85 PathProgramCache]: Analyzing trace with hash 1876372512, now seen corresponding path program 1 times [2022-07-22 02:43:14,354 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:14,354 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1938061238] [2022-07-22 02:43:14,354 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:14,354 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:14,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:14,378 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:14,378 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:14,378 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1938061238] [2022-07-22 02:43:14,378 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1938061238] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:14,378 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:14,378 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:14,379 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1840546744] [2022-07-22 02:43:14,379 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:14,379 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:43:14,379 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:43:14,380 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-22 02:43:14,380 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-22 02:43:14,380 INFO L87 Difference]: Start difference. First operand 90273 states and 129809 transitions. cyclomatic complexity: 39568 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:15,542 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:43:15,542 INFO L93 Difference]: Finished difference Result 219312 states and 313482 transitions. [2022-07-22 02:43:15,542 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-22 02:43:15,543 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 219312 states and 313482 transitions. [2022-07-22 02:43:16,674 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 215696 [2022-07-22 02:43:17,143 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 219312 states to 219312 states and 313482 transitions. [2022-07-22 02:43:17,155 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 219312 [2022-07-22 02:43:17,259 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 219312 [2022-07-22 02:43:17,260 INFO L73 IsDeterministic]: Start isDeterministic. Operand 219312 states and 313482 transitions. [2022-07-22 02:43:17,363 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:43:17,364 INFO L369 hiAutomatonCegarLoop]: Abstraction has 219312 states and 313482 transitions. [2022-07-22 02:43:17,445 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 219312 states and 313482 transitions. [2022-07-22 02:43:19,193 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 219312 to 173344. [2022-07-22 02:43:19,346 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 173344 states, 173344 states have (on average 1.4332079564334503) internal successors, (248438), 173343 states have internal predecessors, (248438), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:19,631 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 173344 states to 173344 states and 248438 transitions. [2022-07-22 02:43:19,631 INFO L392 hiAutomatonCegarLoop]: Abstraction has 173344 states and 248438 transitions. [2022-07-22 02:43:19,631 INFO L374 stractBuchiCegarLoop]: Abstraction has 173344 states and 248438 transitions. [2022-07-22 02:43:19,631 INFO L287 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-07-22 02:43:19,632 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 173344 states and 248438 transitions. [2022-07-22 02:43:20,597 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 172928 [2022-07-22 02:43:20,598 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:43:20,598 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:43:20,599 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:20,600 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:20,600 INFO L752 eck$LassoCheckResult]: Stem: 741936#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 741937#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 741447#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 741448#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 741501#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 743015#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 741945#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 741742#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 741142#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 741143#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 742426#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 742553#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 743123#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 743124#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 741872#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 741873#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 742456#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 742362#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 741910#L1201 assume !(0 == ~M_E~0); 741911#L1201-2 assume !(0 == ~T1_E~0); 742881#L1206-1 assume !(0 == ~T2_E~0); 742862#L1211-1 assume !(0 == ~T3_E~0); 742863#L1216-1 assume !(0 == ~T4_E~0); 741727#L1221-1 assume !(0 == ~T5_E~0); 741728#L1226-1 assume !(0 == ~T6_E~0); 741362#L1231-1 assume !(0 == ~T7_E~0); 741363#L1236-1 assume !(0 == ~T8_E~0); 742918#L1241-1 assume !(0 == ~T9_E~0); 741765#L1246-1 assume !(0 == ~T10_E~0); 741766#L1251-1 assume !(0 == ~T11_E~0); 741908#L1256-1 assume !(0 == ~T12_E~0); 741154#L1261-1 assume !(0 == ~E_M~0); 741155#L1266-1 assume !(0 == ~E_1~0); 743103#L1271-1 assume !(0 == ~E_2~0); 742529#L1276-1 assume !(0 == ~E_3~0); 742530#L1281-1 assume !(0 == ~E_4~0); 742472#L1286-1 assume !(0 == ~E_5~0); 741615#L1291-1 assume !(0 == ~E_6~0); 741616#L1296-1 assume !(0 == ~E_7~0); 742227#L1301-1 assume !(0 == ~E_8~0); 742228#L1306-1 assume !(0 == ~E_9~0); 742786#L1311-1 assume !(0 == ~E_10~0); 741566#L1316-1 assume !(0 == ~E_11~0); 741567#L1321-1 assume !(0 == ~E_12~0); 742249#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 742250#L593 assume !(1 == ~m_pc~0); 741453#L593-2 is_master_triggered_~__retres1~0#1 := 0; 741454#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 743076#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 742485#L1492 assume !(0 != activate_threads_~tmp~1#1); 742486#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 742831#L612 assume !(1 == ~t1_pc~0); 742832#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 743118#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 741842#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 741458#L1500 assume !(0 != activate_threads_~tmp___0~0#1); 741459#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 741885#L631 assume !(1 == ~t2_pc~0); 741886#L631-2 is_transmit2_triggered_~__retres1~2#1 := 0; 741236#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 741237#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 742093#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 742094#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 741530#L650 assume !(1 == ~t3_pc~0); 741531#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 742275#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 741455#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 741192#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 741193#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 742449#L669 assume !(1 == ~t4_pc~0); 742450#L669-2 is_transmit4_triggered_~__retres1~4#1 := 0; 742871#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 741871#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 741397#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 741398#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 741624#L688 assume !(1 == ~t5_pc~0); 741413#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 741414#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 742393#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 742313#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 742314#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 742468#L707 assume !(1 == ~t6_pc~0); 742711#L707-2 is_transmit6_triggered_~__retres1~6#1 := 0; 742060#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 742061#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 742960#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 742402#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 741909#L726 assume 1 == ~t7_pc~0; 741806#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 741497#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 742627#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 742972#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 741268#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 741269#L745 assume !(1 == ~t8_pc~0); 741718#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 741738#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 742663#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 742147#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 742148#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 742738#L764 assume 1 == ~t9_pc~0; 741907#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 741744#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 742488#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 743050#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 741288#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 741289#L783 assume !(1 == ~t10_pc~0); 741350#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 741351#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 741391#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 741392#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 741865#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 742873#L802 assume 1 == ~t11_pc~0; 742849#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 741233#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 741234#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 741729#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 741730#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 741841#L821 assume !(1 == ~t12_pc~0); 742109#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 742218#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 741240#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 741241#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 742930#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 742497#L1339 assume !(1 == ~M_E~0); 742498#L1339-2 assume !(1 == ~T1_E~0); 742975#L1344-1 assume !(1 == ~T2_E~0); 742976#L1349-1 assume !(1 == ~T3_E~0); 742243#L1354-1 assume !(1 == ~T4_E~0); 742244#L1359-1 assume !(1 == ~T5_E~0); 845845#L1364-1 assume !(1 == ~T6_E~0); 845842#L1369-1 assume !(1 == ~T7_E~0); 845840#L1374-1 assume !(1 == ~T8_E~0); 845837#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 845838#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 855572#L1389-1 assume !(1 == ~T11_E~0); 855571#L1394-1 assume !(1 == ~T12_E~0); 855570#L1399-1 assume !(1 == ~E_M~0); 855569#L1404-1 assume !(1 == ~E_1~0); 855568#L1409-1 assume !(1 == ~E_2~0); 855567#L1414-1 assume !(1 == ~E_3~0); 855565#L1419-1 assume 1 == ~E_4~0;~E_4~0 := 2; 855564#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 855563#L1429-1 assume !(1 == ~E_6~0); 855549#L1434-1 assume !(1 == ~E_7~0); 855547#L1439-1 assume !(1 == ~E_8~0); 855545#L1444-1 assume !(1 == ~E_9~0); 855543#L1449-1 assume !(1 == ~E_10~0); 855541#L1454-1 assume !(1 == ~E_11~0); 855539#L1459-1 assume 1 == ~E_12~0;~E_12~0 := 2; 841260#L1464-1 assume { :end_inline_reset_delta_events } true; 841257#L1810-2 [2022-07-22 02:43:20,600 INFO L754 eck$LassoCheckResult]: Loop: 841257#L1810-2 assume !false; 840878#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 840873#L1176 assume !false; 840870#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 840863#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 840851#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 840850#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 840847#L1003 assume !(0 != eval_~tmp~0#1); 840848#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 856578#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 856576#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 856574#L1201-5 assume !(0 == ~T1_E~0); 856571#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 856569#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 856567#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 856565#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 856563#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 856561#L1231-3 assume !(0 == ~T7_E~0); 856559#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 856557#L1241-3 assume !(0 == ~T9_E~0); 856555#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 856553#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 856551#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 856549#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 856546#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 856544#L1271-3 assume !(0 == ~E_2~0); 856542#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 856540#L1281-3 assume !(0 == ~E_4~0); 856538#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 856536#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 856535#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 856532#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 856530#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 856528#L1311-3 assume !(0 == ~E_10~0); 856526#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 856524#L1321-3 assume !(0 == ~E_12~0); 856522#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 856520#L593-42 assume !(1 == ~m_pc~0); 856518#L593-44 is_master_triggered_~__retres1~0#1 := 0; 856516#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 856514#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 856512#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 856510#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 856504#L612-42 assume 1 == ~t1_pc~0; 856505#L613-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 856506#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 856624#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 856495#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 856494#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 856493#L631-42 assume !(1 == ~t2_pc~0); 855086#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 856491#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 856490#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 856489#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 856488#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 856487#L650-42 assume !(1 == ~t3_pc~0); 856485#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 856484#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 856483#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 856482#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 856480#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 856478#L669-42 assume !(1 == ~t4_pc~0); 856476#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 856474#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 856472#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 856470#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 856468#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 856466#L688-42 assume 1 == ~t5_pc~0; 856463#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 856461#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 856459#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 856457#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 856455#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 856453#L707-42 assume !(1 == ~t6_pc~0); 795542#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 856450#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 856448#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 856446#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 856444#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 856442#L726-42 assume !(1 == ~t7_pc~0); 856440#L726-44 is_transmit7_triggered_~__retres1~7#1 := 0; 856437#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 856435#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 856433#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 856431#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 856429#L745-42 assume 1 == ~t8_pc~0; 856427#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 856424#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 856422#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 856419#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 856417#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 856415#L764-42 assume !(1 == ~t9_pc~0); 856413#L764-44 is_transmit9_triggered_~__retres1~9#1 := 0; 856410#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 856409#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 856405#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 856403#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 856401#L783-42 assume 1 == ~t10_pc~0; 856399#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 856395#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 856392#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 856390#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 856388#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 856386#L802-42 assume 1 == ~t11_pc~0; 856383#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 856381#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 856378#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 856376#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 856374#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 856372#L821-42 assume !(1 == ~t12_pc~0); 856369#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 856367#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 856364#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 856362#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 856360#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 856358#L1339-3 assume !(1 == ~M_E~0); 856356#L1339-5 assume !(1 == ~T1_E~0); 856354#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 844224#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 856348#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 856346#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 856344#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 856342#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 856340#L1374-3 assume !(1 == ~T8_E~0); 856337#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 850614#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 856334#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 856332#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 856330#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 856328#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 856325#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 856323#L1414-3 assume !(1 == ~E_3~0); 856321#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 856203#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 856318#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 856316#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 856313#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 856311#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 856309#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 856307#L1454-3 assume !(1 == ~E_11~0); 856305#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 848142#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 847621#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 847613#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 847611#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 847605#L1829 assume !(0 == start_simulation_~tmp~3#1); 847604#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 847594#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 847590#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 847586#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 847584#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 847582#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 847581#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 841259#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 841257#L1810-2 [2022-07-22 02:43:20,601 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:20,601 INFO L85 PathProgramCache]: Analyzing trace with hash 2145928902, now seen corresponding path program 1 times [2022-07-22 02:43:20,601 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:20,601 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [305919363] [2022-07-22 02:43:20,601 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:20,602 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:20,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:20,626 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:20,627 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:20,627 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [305919363] [2022-07-22 02:43:20,627 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [305919363] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:20,627 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:20,627 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:20,627 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [266789457] [2022-07-22 02:43:20,628 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:20,628 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:43:20,628 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:20,628 INFO L85 PathProgramCache]: Analyzing trace with hash -399776675, now seen corresponding path program 1 times [2022-07-22 02:43:20,628 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:20,629 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1259852791] [2022-07-22 02:43:20,629 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:20,629 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:20,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:20,653 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:20,653 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:20,653 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1259852791] [2022-07-22 02:43:20,653 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1259852791] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:20,653 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:20,654 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:20,654 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1881304160] [2022-07-22 02:43:20,654 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:20,654 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:43:20,654 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:43:20,654 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-22 02:43:20,655 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-22 02:43:20,655 INFO L87 Difference]: Start difference. First operand 173344 states and 248438 transitions. cyclomatic complexity: 75126 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:22,661 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:43:22,661 INFO L93 Difference]: Finished difference Result 420255 states and 598859 transitions. [2022-07-22 02:43:22,662 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-22 02:43:22,662 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 420255 states and 598859 transitions. [2022-07-22 02:43:24,767 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 413280 [2022-07-22 02:43:25,787 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 420255 states to 420255 states and 598859 transitions. [2022-07-22 02:43:25,787 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 420255 [2022-07-22 02:43:26,375 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 420255 [2022-07-22 02:43:26,375 INFO L73 IsDeterministic]: Start isDeterministic. Operand 420255 states and 598859 transitions. [2022-07-22 02:43:26,475 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:43:26,475 INFO L369 hiAutomatonCegarLoop]: Abstraction has 420255 states and 598859 transitions. [2022-07-22 02:43:26,654 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 420255 states and 598859 transitions. [2022-07-22 02:43:29,351 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 420255 to 332639. [2022-07-22 02:43:29,617 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 332639 states, 332639 states have (on average 1.4287771427884284) internal successors, (475267), 332638 states have internal predecessors, (475267), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:30,812 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 332639 states to 332639 states and 475267 transitions. [2022-07-22 02:43:30,812 INFO L392 hiAutomatonCegarLoop]: Abstraction has 332639 states and 475267 transitions. [2022-07-22 02:43:30,813 INFO L374 stractBuchiCegarLoop]: Abstraction has 332639 states and 475267 transitions. [2022-07-22 02:43:30,813 INFO L287 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-07-22 02:43:30,813 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 332639 states and 475267 transitions. [2022-07-22 02:43:31,540 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 332032 [2022-07-22 02:43:31,540 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:43:31,540 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:43:31,542 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:31,542 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:31,543 INFO L752 eck$LassoCheckResult]: Stem: 1335545#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 1335546#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 1335059#L1773 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1335060#L841 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1335112#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 1336652#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1335556#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1335355#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1334751#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1334752#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1336033#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1336155#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1336780#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1336781#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1335480#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1335481#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1336063#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1335970#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1335518#L1201 assume !(0 == ~M_E~0); 1335519#L1201-2 assume !(0 == ~T1_E~0); 1336502#L1206-1 assume !(0 == ~T2_E~0); 1336483#L1211-1 assume !(0 == ~T3_E~0); 1336484#L1216-1 assume !(0 == ~T4_E~0); 1335340#L1221-1 assume !(0 == ~T5_E~0); 1335341#L1226-1 assume !(0 == ~T6_E~0); 1334972#L1231-1 assume !(0 == ~T7_E~0); 1334973#L1236-1 assume !(0 == ~T8_E~0); 1336537#L1241-1 assume !(0 == ~T9_E~0); 1335378#L1246-1 assume !(0 == ~T10_E~0); 1335379#L1251-1 assume !(0 == ~T11_E~0); 1335516#L1256-1 assume !(0 == ~T12_E~0); 1334763#L1261-1 assume !(0 == ~E_M~0); 1334764#L1266-1 assume !(0 == ~E_1~0); 1336752#L1271-1 assume !(0 == ~E_2~0); 1336134#L1276-1 assume !(0 == ~E_3~0); 1336135#L1281-1 assume !(0 == ~E_4~0); 1336077#L1286-1 assume !(0 == ~E_5~0); 1335230#L1291-1 assume !(0 == ~E_6~0); 1335231#L1296-1 assume !(0 == ~E_7~0); 1335839#L1301-1 assume !(0 == ~E_8~0); 1335840#L1306-1 assume !(0 == ~E_9~0); 1336398#L1311-1 assume !(0 == ~E_10~0); 1335178#L1316-1 assume !(0 == ~E_11~0); 1335179#L1321-1 assume !(0 == ~E_12~0); 1335857#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1335858#L593 assume !(1 == ~m_pc~0); 1335065#L593-2 is_master_triggered_~__retres1~0#1 := 0; 1335066#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1336730#L605 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1336090#L1492 assume !(0 != activate_threads_~tmp~1#1); 1336091#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1336450#L612 assume !(1 == ~t1_pc~0); 1336451#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1336764#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1335449#L624 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1335070#L1500 assume !(0 != activate_threads_~tmp___0~0#1); 1335071#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1335493#L631 assume !(1 == ~t2_pc~0); 1335494#L631-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1334845#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1334846#L643 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1335703#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 1335704#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1335141#L650 assume !(1 == ~t3_pc~0); 1335142#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1335883#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1335067#L662 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1334800#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 1334801#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1336056#L669 assume !(1 == ~t4_pc~0); 1336057#L669-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1336491#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1335479#L681 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1335007#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 1335008#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1335239#L688 assume !(1 == ~t5_pc~0); 1335023#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1335024#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1336001#L700 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1335920#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 1335921#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1336073#L707 assume !(1 == ~t6_pc~0); 1336322#L707-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1335670#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1335671#L719 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1336588#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 1336011#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1335517#L726 assume !(1 == ~t7_pc~0); 1335107#L726-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1335108#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1336231#L738 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1336601#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 1334877#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1334878#L745 assume !(1 == ~t8_pc~0); 1335332#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1335351#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1336266#L757 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1335759#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1335760#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1336350#L764 assume 1 == ~t9_pc~0; 1335515#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1335357#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1336093#L776 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1336697#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 1334897#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1334898#L783 assume !(1 == ~t10_pc~0); 1334960#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1334961#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1335001#L795 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1335002#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 1335473#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1336493#L802 assume 1 == ~t11_pc~0; 1336471#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1334841#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1334842#L814 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1335342#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 1335343#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1335448#L821 assume !(1 == ~t12_pc~0); 1335722#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 1335830#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1334849#L833 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1334850#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 1336554#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1336102#L1339 assume !(1 == ~M_E~0); 1336103#L1339-2 assume !(1 == ~T1_E~0); 1336602#L1344-1 assume !(1 == ~T2_E~0); 1336603#L1349-1 assume !(1 == ~T3_E~0); 1335851#L1354-1 assume !(1 == ~T4_E~0); 1335852#L1359-1 assume !(1 == ~T5_E~0); 1336767#L1364-1 assume !(1 == ~T6_E~0); 1336768#L1369-1 assume !(1 == ~T7_E~0); 1336282#L1374-1 assume !(1 == ~T8_E~0); 1336283#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1431188#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1431187#L1389-1 assume !(1 == ~T11_E~0); 1431186#L1394-1 assume !(1 == ~T12_E~0); 1431185#L1399-1 assume !(1 == ~E_M~0); 1431184#L1404-1 assume !(1 == ~E_1~0); 1431183#L1409-1 assume !(1 == ~E_2~0); 1431182#L1414-1 assume !(1 == ~E_3~0); 1431180#L1419-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1431181#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 1431616#L1429-1 assume !(1 == ~E_6~0); 1431615#L1434-1 assume !(1 == ~E_7~0); 1431614#L1439-1 assume !(1 == ~E_8~0); 1431613#L1444-1 assume !(1 == ~E_9~0); 1431612#L1449-1 assume !(1 == ~E_10~0); 1431611#L1454-1 assume !(1 == ~E_11~0); 1431610#L1459-1 assume 1 == ~E_12~0;~E_12~0 := 2; 1336007#L1464-1 assume { :end_inline_reset_delta_events } true; 1336008#L1810-2 [2022-07-22 02:43:31,543 INFO L754 eck$LassoCheckResult]: Loop: 1336008#L1810-2 assume !false; 1450946#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1450941#L1176 assume !false; 1450940#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1450766#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1450754#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1450752#L989 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1450749#L1003 assume !(0 != eval_~tmp~0#1); 1450750#L1191 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1451724#L841-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1451722#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1451720#L1201-5 assume !(0 == ~T1_E~0); 1451718#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1451716#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1451714#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1451713#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1451711#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1451709#L1231-3 assume !(0 == ~T7_E~0); 1451707#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1451705#L1241-3 assume !(0 == ~T9_E~0); 1451703#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1451700#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1451698#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1451696#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1451694#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1451692#L1271-3 assume !(0 == ~E_2~0); 1451690#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1451687#L1281-3 assume !(0 == ~E_4~0); 1451685#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1451683#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1451681#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1451679#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1451677#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1451674#L1311-3 assume !(0 == ~E_10~0); 1451672#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1451670#L1321-3 assume !(0 == ~E_12~0); 1451668#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1451666#L593-42 assume !(1 == ~m_pc~0); 1451664#L593-44 is_master_triggered_~__retres1~0#1 := 0; 1451661#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1451659#L605-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1451657#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1451655#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1451648#L612-42 assume !(1 == ~t1_pc~0); 1451646#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 1451644#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1451642#L624-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1451640#L1500-42 assume !(0 != activate_threads_~tmp___0~0#1); 1451638#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1451637#L631-42 assume !(1 == ~t2_pc~0); 1445776#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 1451632#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1451630#L643-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1451629#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1451628#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1451627#L650-42 assume 1 == ~t3_pc~0; 1451626#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1451624#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1451623#L662-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1451622#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1451621#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1451620#L669-42 assume !(1 == ~t4_pc~0); 1451619#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 1451618#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1451617#L681-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1451616#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 1451615#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1451614#L688-42 assume 1 == ~t5_pc~0; 1451612#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1451611#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1451610#L700-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1451609#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1451608#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1451607#L707-42 assume !(1 == ~t6_pc~0); 1419919#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 1451605#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1451603#L719-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1451602#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1451601#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1451600#L726-42 assume !(1 == ~t7_pc~0); 1397497#L726-44 is_transmit7_triggered_~__retres1~7#1 := 0; 1451597#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1451595#L738-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1451593#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1451591#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1451589#L745-42 assume !(1 == ~t8_pc~0); 1451586#L745-44 is_transmit8_triggered_~__retres1~8#1 := 0; 1451583#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1451581#L757-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1451579#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1451576#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1451574#L764-42 assume !(1 == ~t9_pc~0); 1451572#L764-44 is_transmit9_triggered_~__retres1~9#1 := 0; 1451570#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1451568#L776-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1451566#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1451564#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1451562#L783-42 assume !(1 == ~t10_pc~0); 1451559#L783-44 is_transmit10_triggered_~__retres1~10#1 := 0; 1451556#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1451554#L795-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1451552#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1451550#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1451548#L802-42 assume !(1 == ~t11_pc~0); 1451546#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 1451543#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1451541#L814-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1451539#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1451537#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1451535#L821-42 assume !(1 == ~t12_pc~0); 1451532#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 1451529#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1451527#L833-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1451525#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1451523#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1451521#L1339-3 assume !(1 == ~M_E~0); 1451519#L1339-5 assume !(1 == ~T1_E~0); 1451518#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1432095#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1451515#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1451513#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1451511#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1451509#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1451508#L1374-3 assume !(1 == ~T8_E~0); 1451506#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1439692#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1451503#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1451501#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1451499#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1451496#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1451494#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1451492#L1414-3 assume !(1 == ~E_3~0); 1451490#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1449726#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1451487#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1451484#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1451482#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1451480#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1451478#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1451476#L1454-3 assume !(1 == ~E_11~0); 1451474#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1432044#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1451455#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1451447#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1451445#L989-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1451386#L1829 assume !(0 == start_simulation_~tmp~3#1); 1451384#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1451361#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1451357#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1451355#L989-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 1451353#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1451351#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1451349#L1792 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1451347#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 1336008#L1810-2 [2022-07-22 02:43:31,544 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:31,545 INFO L85 PathProgramCache]: Analyzing trace with hash -1572109753, now seen corresponding path program 1 times [2022-07-22 02:43:31,545 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:31,558 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1093257937] [2022-07-22 02:43:31,559 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:31,559 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:31,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:31,604 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:31,604 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:31,604 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1093257937] [2022-07-22 02:43:31,604 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1093257937] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:31,604 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:31,604 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-22 02:43:31,605 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1078706461] [2022-07-22 02:43:31,605 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:31,605 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:43:31,605 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:31,605 INFO L85 PathProgramCache]: Analyzing trace with hash -428936094, now seen corresponding path program 1 times [2022-07-22 02:43:31,606 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:31,606 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1324309417] [2022-07-22 02:43:31,606 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:31,606 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:31,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:31,626 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:31,626 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:31,626 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1324309417] [2022-07-22 02:43:31,626 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1324309417] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:31,626 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:31,626 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:31,626 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1247894202] [2022-07-22 02:43:31,627 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:31,627 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:43:31,627 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:43:31,627 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-07-22 02:43:31,627 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-07-22 02:43:31,628 INFO L87 Difference]: Start difference. First operand 332639 states and 475267 transitions. cyclomatic complexity: 142660 Second operand has 5 states, 5 states have (on average 30.0) internal successors, (150), 5 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:34,938 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:43:34,939 INFO L93 Difference]: Finished difference Result 804430 states and 1157994 transitions. [2022-07-22 02:43:34,939 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-07-22 02:43:34,940 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 804430 states and 1157994 transitions. [2022-07-22 02:43:39,731 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 802816