./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.10.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 35987657 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.10.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash c68befe0cb772d649d152823cc17c89d77797d55cc04257d4beaaad2b518a7a0 --- Real Ultimate output --- This is Ultimate 0.2.2-?-3598765 [2022-07-22 02:43:38,452 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-07-22 02:43:38,454 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-07-22 02:43:38,491 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-07-22 02:43:38,492 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-07-22 02:43:38,493 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-07-22 02:43:38,496 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-07-22 02:43:38,498 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-07-22 02:43:38,500 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-07-22 02:43:38,503 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-07-22 02:43:38,504 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-07-22 02:43:38,506 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-07-22 02:43:38,506 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-07-22 02:43:38,507 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-07-22 02:43:38,508 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-07-22 02:43:38,512 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-07-22 02:43:38,513 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-07-22 02:43:38,514 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-07-22 02:43:38,515 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-07-22 02:43:38,518 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-07-22 02:43:38,519 INFO L181 SettingsManager]: Resetting HornVerifier preferences to default values [2022-07-22 02:43:38,519 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-07-22 02:43:38,520 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-07-22 02:43:38,521 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-07-22 02:43:38,522 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-07-22 02:43:38,527 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-07-22 02:43:38,528 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-07-22 02:43:38,528 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-07-22 02:43:38,529 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-07-22 02:43:38,529 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-07-22 02:43:38,530 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-07-22 02:43:38,530 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-07-22 02:43:38,531 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-07-22 02:43:38,532 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-07-22 02:43:38,533 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-07-22 02:43:38,533 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-07-22 02:43:38,533 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-07-22 02:43:38,534 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-07-22 02:43:38,534 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-07-22 02:43:38,534 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-07-22 02:43:38,535 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-07-22 02:43:38,536 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-07-22 02:43:38,540 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-07-22 02:43:38,565 INFO L113 SettingsManager]: Loading preferences was successful [2022-07-22 02:43:38,566 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-07-22 02:43:38,566 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-07-22 02:43:38,566 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-07-22 02:43:38,567 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-07-22 02:43:38,567 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-07-22 02:43:38,567 INFO L138 SettingsManager]: * Use SBE=true [2022-07-22 02:43:38,567 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-07-22 02:43:38,568 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-07-22 02:43:38,568 INFO L138 SettingsManager]: * Use old map elimination=false [2022-07-22 02:43:38,568 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-07-22 02:43:38,568 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-07-22 02:43:38,569 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-07-22 02:43:38,569 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-07-22 02:43:38,569 INFO L138 SettingsManager]: * sizeof long=4 [2022-07-22 02:43:38,569 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-07-22 02:43:38,569 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-07-22 02:43:38,569 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-07-22 02:43:38,569 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-07-22 02:43:38,570 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-07-22 02:43:38,570 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-07-22 02:43:38,570 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-07-22 02:43:38,570 INFO L138 SettingsManager]: * sizeof long double=12 [2022-07-22 02:43:38,570 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-07-22 02:43:38,570 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-07-22 02:43:38,570 INFO L138 SettingsManager]: * Use constant arrays=true [2022-07-22 02:43:38,570 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-07-22 02:43:38,571 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-07-22 02:43:38,571 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-07-22 02:43:38,571 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-07-22 02:43:38,571 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-07-22 02:43:38,573 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-07-22 02:43:38,573 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c68befe0cb772d649d152823cc17c89d77797d55cc04257d4beaaad2b518a7a0 [2022-07-22 02:43:38,824 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-07-22 02:43:38,846 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-07-22 02:43:38,848 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-07-22 02:43:38,848 INFO L271 PluginConnector]: Initializing CDTParser... [2022-07-22 02:43:38,849 INFO L275 PluginConnector]: CDTParser initialized [2022-07-22 02:43:38,851 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.10.cil.c [2022-07-22 02:43:38,900 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c86f24d8b/f121216cd9884b1d908788e2c0a6259c/FLAGa6dd28c91 [2022-07-22 02:43:39,343 INFO L306 CDTParser]: Found 1 translation units. [2022-07-22 02:43:39,344 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.10.cil.c [2022-07-22 02:43:39,357 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c86f24d8b/f121216cd9884b1d908788e2c0a6259c/FLAGa6dd28c91 [2022-07-22 02:43:39,372 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c86f24d8b/f121216cd9884b1d908788e2c0a6259c [2022-07-22 02:43:39,374 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-07-22 02:43:39,375 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-07-22 02:43:39,376 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-07-22 02:43:39,376 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-07-22 02:43:39,393 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-07-22 02:43:39,393 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 22.07 02:43:39" (1/1) ... [2022-07-22 02:43:39,394 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3e4a9707 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:43:39, skipping insertion in model container [2022-07-22 02:43:39,394 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 22.07 02:43:39" (1/1) ... [2022-07-22 02:43:39,399 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-07-22 02:43:39,439 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-07-22 02:43:39,527 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.10.cil.c[706,719] [2022-07-22 02:43:39,639 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-22 02:43:39,650 INFO L203 MainTranslator]: Completed pre-run [2022-07-22 02:43:39,664 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.10.cil.c[706,719] [2022-07-22 02:43:39,730 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-22 02:43:39,750 INFO L208 MainTranslator]: Completed translation [2022-07-22 02:43:39,751 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:43:39 WrapperNode [2022-07-22 02:43:39,751 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-07-22 02:43:39,752 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-07-22 02:43:39,752 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-07-22 02:43:39,752 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-07-22 02:43:39,757 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:43:39" (1/1) ... [2022-07-22 02:43:39,777 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:43:39" (1/1) ... [2022-07-22 02:43:39,827 INFO L137 Inliner]: procedures = 48, calls = 60, calls flagged for inlining = 55, calls inlined = 196, statements flattened = 2994 [2022-07-22 02:43:39,827 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-07-22 02:43:39,828 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-07-22 02:43:39,828 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-07-22 02:43:39,828 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-07-22 02:43:39,834 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:43:39" (1/1) ... [2022-07-22 02:43:39,834 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:43:39" (1/1) ... [2022-07-22 02:43:39,868 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:43:39" (1/1) ... [2022-07-22 02:43:39,869 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:43:39" (1/1) ... [2022-07-22 02:43:39,902 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:43:39" (1/1) ... [2022-07-22 02:43:39,935 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:43:39" (1/1) ... [2022-07-22 02:43:39,942 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:43:39" (1/1) ... [2022-07-22 02:43:39,952 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-07-22 02:43:39,954 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-07-22 02:43:39,954 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-07-22 02:43:39,955 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-07-22 02:43:39,955 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:43:39" (1/1) ... [2022-07-22 02:43:39,961 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-22 02:43:39,969 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-22 02:43:39,980 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-22 02:43:39,987 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-07-22 02:43:40,012 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-07-22 02:43:40,013 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-07-22 02:43:40,013 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-07-22 02:43:40,013 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-07-22 02:43:40,126 INFO L234 CfgBuilder]: Building ICFG [2022-07-22 02:43:40,127 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-07-22 02:43:41,307 INFO L275 CfgBuilder]: Performing block encoding [2022-07-22 02:43:41,326 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-07-22 02:43:41,326 INFO L299 CfgBuilder]: Removed 14 assume(true) statements. [2022-07-22 02:43:41,330 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.07 02:43:41 BoogieIcfgContainer [2022-07-22 02:43:41,330 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-07-22 02:43:41,331 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-07-22 02:43:41,331 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-07-22 02:43:41,333 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-07-22 02:43:41,334 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-22 02:43:41,334 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 22.07 02:43:39" (1/3) ... [2022-07-22 02:43:41,335 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@25fb390c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 22.07 02:43:41, skipping insertion in model container [2022-07-22 02:43:41,335 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-22 02:43:41,335 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.07 02:43:39" (2/3) ... [2022-07-22 02:43:41,335 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@25fb390c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 22.07 02:43:41, skipping insertion in model container [2022-07-22 02:43:41,336 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-22 02:43:41,336 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.07 02:43:41" (3/3) ... [2022-07-22 02:43:41,337 INFO L354 chiAutomizerObserver]: Analyzing ICFG transmitter.10.cil.c [2022-07-22 02:43:41,403 INFO L255 stractBuchiCegarLoop]: Interprodecural is true [2022-07-22 02:43:41,404 INFO L256 stractBuchiCegarLoop]: Hoare is false [2022-07-22 02:43:41,404 INFO L257 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-07-22 02:43:41,404 INFO L258 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-07-22 02:43:41,404 INFO L259 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-07-22 02:43:41,404 INFO L260 stractBuchiCegarLoop]: Difference is false [2022-07-22 02:43:41,404 INFO L261 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-07-22 02:43:41,404 INFO L265 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-07-22 02:43:41,412 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1285 states, 1284 states have (on average 1.5093457943925233) internal successors, (1938), 1284 states have internal predecessors, (1938), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:41,471 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1144 [2022-07-22 02:43:41,472 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:43:41,472 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:43:41,484 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:41,486 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:41,487 INFO L287 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-07-22 02:43:41,489 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1285 states, 1284 states have (on average 1.5093457943925233) internal successors, (1938), 1284 states have internal predecessors, (1938), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:41,505 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1144 [2022-07-22 02:43:41,506 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:43:41,506 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:43:41,514 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:41,514 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:41,525 INFO L752 eck$LassoCheckResult]: Stem: 616#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 1165#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 1095#L1483true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1050#L694true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1269#L701true assume !(1 == ~m_i~0);~m_st~0 := 2; 1143#L701-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 1163#L706-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 283#L711-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 131#L716-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1185#L721-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 877#L726-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1068#L731-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 849#L736-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 923#L741-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 1223#L746-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 158#L751-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 791#L1006true assume !(0 == ~M_E~0); 82#L1006-2true assume !(0 == ~T1_E~0); 977#L1011-1true assume !(0 == ~T2_E~0); 1016#L1016-1true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1168#L1021-1true assume !(0 == ~T4_E~0); 24#L1026-1true assume !(0 == ~T5_E~0); 1236#L1031-1true assume !(0 == ~T6_E~0); 561#L1036-1true assume !(0 == ~T7_E~0); 558#L1041-1true assume !(0 == ~T8_E~0); 895#L1046-1true assume !(0 == ~T9_E~0); 177#L1051-1true assume !(0 == ~T10_E~0); 701#L1056-1true assume 0 == ~E_1~0;~E_1~0 := 1; 747#L1061-1true assume !(0 == ~E_2~0); 133#L1066-1true assume !(0 == ~E_3~0); 1060#L1071-1true assume !(0 == ~E_4~0); 679#L1076-1true assume !(0 == ~E_5~0); 87#L1081-1true assume !(0 == ~E_6~0); 270#L1086-1true assume !(0 == ~E_7~0); 1074#L1091-1true assume !(0 == ~E_8~0); 950#L1096-1true assume 0 == ~E_9~0;~E_9~0 := 1; 1169#L1101-1true assume !(0 == ~E_10~0); 307#L1106-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1085#L484true assume !(1 == ~m_pc~0); 370#L484-2true is_master_triggered_~__retres1~0#1 := 0; 494#L495true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 878#L496true activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 794#L1245true assume !(0 != activate_threads_~tmp~1#1); 1205#L1245-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 553#L503true assume 1 == ~t1_pc~0; 565#L504true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 733#L514true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 693#L515true activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 383#L1253true assume !(0 != activate_threads_~tmp___0~0#1); 39#L1253-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 899#L522true assume !(1 == ~t2_pc~0); 521#L522-2true is_transmit2_triggered_~__retres1~2#1 := 0; 140#L533true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 423#L534true activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 879#L1261true assume !(0 != activate_threads_~tmp___1~0#1); 1196#L1261-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1039#L541true assume 1 == ~t3_pc~0; 482#L542true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 824#L552true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 237#L553true activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 590#L1269true assume !(0 != activate_threads_~tmp___2~0#1); 524#L1269-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 963#L560true assume !(1 == ~t4_pc~0); 1066#L560-2true is_transmit4_triggered_~__retres1~4#1 := 0; 462#L571true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 446#L572true activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23#L1277true assume !(0 != activate_threads_~tmp___3~0#1); 887#L1277-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 165#L579true assume 1 == ~t5_pc~0; 2#L580true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 54#L590true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 452#L591true activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1014#L1285true assume !(0 != activate_threads_~tmp___4~0#1); 1089#L1285-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1262#L598true assume 1 == ~t6_pc~0; 219#L599true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 408#L609true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1184#L610true activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 832#L1293true assume !(0 != activate_threads_~tmp___5~0#1); 597#L1293-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 547#L617true assume !(1 == ~t7_pc~0); 458#L617-2true is_transmit7_triggered_~__retres1~7#1 := 0; 1179#L628true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 371#L629true activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 901#L1301true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 326#L1301-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 594#L636true assume 1 == ~t8_pc~0; 444#L637true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 781#L647true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 308#L648true activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 604#L1309true assume !(0 != activate_threads_~tmp___7~0#1); 414#L1309-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 683#L655true assume !(1 == ~t9_pc~0); 760#L655-2true is_transmit9_triggered_~__retres1~9#1 := 0; 1120#L666true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 195#L667true activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1018#L1317true assume !(0 != activate_threads_~tmp___8~0#1); 617#L1317-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 960#L674true assume 1 == ~t10_pc~0; 77#L675true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1045#L685true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1202#L686true activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1283#L1325true assume !(0 != activate_threads_~tmp___9~0#1); 407#L1325-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 889#L1119true assume !(1 == ~M_E~0); 122#L1119-2true assume !(1 == ~T1_E~0); 353#L1124-1true assume !(1 == ~T2_E~0); 35#L1129-1true assume !(1 == ~T3_E~0); 532#L1134-1true assume !(1 == ~T4_E~0); 196#L1139-1true assume !(1 == ~T5_E~0); 324#L1144-1true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1243#L1149-1true assume !(1 == ~T7_E~0); 119#L1154-1true assume !(1 == ~T8_E~0); 168#L1159-1true assume !(1 == ~T9_E~0); 1212#L1164-1true assume !(1 == ~T10_E~0); 425#L1169-1true assume !(1 == ~E_1~0); 346#L1174-1true assume !(1 == ~E_2~0); 226#L1179-1true assume !(1 == ~E_3~0); 161#L1184-1true assume 1 == ~E_4~0;~E_4~0 := 2; 192#L1189-1true assume !(1 == ~E_5~0); 259#L1194-1true assume !(1 == ~E_6~0); 1256#L1199-1true assume !(1 == ~E_7~0); 232#L1204-1true assume !(1 == ~E_8~0); 1118#L1209-1true assume !(1 == ~E_9~0); 614#L1214-1true assume !(1 == ~E_10~0); 1210#L1219-1true assume { :end_inline_reset_delta_events } true; 17#L1520-2true [2022-07-22 02:43:41,533 INFO L754 eck$LassoCheckResult]: Loop: 17#L1520-2true assume !false; 1266#L1521true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 163#L981true assume !true; 321#L996true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1259#L694-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 320#L1006-3true assume 0 == ~M_E~0;~M_E~0 := 1; 958#L1006-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 730#L1011-3true assume !(0 == ~T2_E~0); 967#L1016-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 776#L1021-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 463#L1026-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 1138#L1031-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 697#L1036-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1206#L1041-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 768#L1046-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1084#L1051-3true assume !(0 == ~T10_E~0); 698#L1056-3true assume 0 == ~E_1~0;~E_1~0 := 1; 174#L1061-3true assume 0 == ~E_2~0;~E_2~0 := 1; 176#L1066-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1226#L1071-3true assume 0 == ~E_4~0;~E_4~0 := 1; 991#L1076-3true assume 0 == ~E_5~0;~E_5~0 := 1; 66#L1081-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1139#L1086-3true assume 0 == ~E_7~0;~E_7~0 := 1; 90#L1091-3true assume !(0 == ~E_8~0); 1051#L1096-3true assume 0 == ~E_9~0;~E_9~0 := 1; 927#L1101-3true assume 0 == ~E_10~0;~E_10~0 := 1; 984#L1106-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 479#L484-33true assume !(1 == ~m_pc~0); 812#L484-35true is_master_triggered_~__retres1~0#1 := 0; 417#L495-11true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 942#L496-11true activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20#L1245-33true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 631#L1245-35true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 264#L503-33true assume 1 == ~t1_pc~0; 1177#L504-11true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 599#L514-11true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 529#L515-11true activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 215#L1253-33true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 644#L1253-35true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 505#L522-33true assume 1 == ~t2_pc~0; 630#L523-11true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 84#L533-11true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 607#L534-11true activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 803#L1261-33true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 520#L1261-35true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 874#L541-33true assume 1 == ~t3_pc~0; 96#L542-11true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19#L552-11true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 972#L553-11true activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 499#L1269-33true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 931#L1269-35true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 692#L560-33true assume 1 == ~t4_pc~0; 421#L561-11true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 56#L571-11true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 188#L572-11true activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1073#L1277-33true assume !(0 != activate_threads_~tmp___3~0#1); 671#L1277-35true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15#L579-33true assume !(1 == ~t5_pc~0); 137#L579-35true is_transmit5_triggered_~__retres1~5#1 := 0; 1032#L590-11true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1046#L591-11true activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 548#L1285-33true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 568#L1285-35true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1034#L598-33true assume !(1 == ~t6_pc~0); 391#L598-35true is_transmit6_triggered_~__retres1~6#1 := 0; 277#L609-11true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 752#L610-11true activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 191#L1293-33true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 900#L1293-35true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1154#L617-33true assume 1 == ~t7_pc~0; 917#L618-11true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 775#L628-11true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1001#L629-11true activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1122#L1301-33true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 993#L1301-35true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49#L636-33true assume !(1 == ~t8_pc~0); 1009#L636-35true is_transmit8_triggered_~__retres1~8#1 := 0; 663#L647-11true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1164#L648-11true activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1054#L1309-33true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 651#L1309-35true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1254#L655-33true assume !(1 == ~t9_pc~0); 1182#L655-35true is_transmit9_triggered_~__retres1~9#1 := 0; 246#L666-11true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 486#L667-11true activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 749#L1317-33true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 999#L1317-35true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 345#L674-33true assume !(1 == ~t10_pc~0); 1028#L674-35true is_transmit10_triggered_~__retres1~10#1 := 0; 1065#L685-11true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 201#L686-11true activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 511#L1325-33true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1059#L1325-35true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1092#L1119-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1100#L1119-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1260#L1124-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1149#L1129-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 213#L1134-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 496#L1139-3true assume !(1 == ~T5_E~0); 341#L1144-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 449#L1149-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1247#L1154-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 707#L1159-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1229#L1164-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1004#L1169-3true assume 1 == ~E_1~0;~E_1~0 := 2; 276#L1174-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1082#L1179-3true assume !(1 == ~E_3~0); 834#L1184-3true assume 1 == ~E_4~0;~E_4~0 := 2; 79#L1189-3true assume 1 == ~E_5~0;~E_5~0 := 2; 839#L1194-3true assume 1 == ~E_6~0;~E_6~0 := 2; 243#L1199-3true assume 1 == ~E_7~0;~E_7~0 := 2; 1265#L1204-3true assume 1 == ~E_8~0;~E_8~0 := 2; 437#L1209-3true assume 1 == ~E_9~0;~E_9~0 := 2; 26#L1214-3true assume 1 == ~E_10~0;~E_10~0 := 2; 936#L1219-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 606#L764-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 944#L821-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 253#L822-1true start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 305#L1539true assume !(0 == start_simulation_~tmp~3#1); 500#L1539-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 427#L764-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 862#L821-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 385#L822-2true stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 249#L1494true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 738#L1501true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 902#L1502true start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 306#L1552true assume !(0 != start_simulation_~tmp___0~1#1); 17#L1520-2true [2022-07-22 02:43:41,538 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:41,539 INFO L85 PathProgramCache]: Analyzing trace with hash 1310232617, now seen corresponding path program 1 times [2022-07-22 02:43:41,552 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:41,553 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1997815846] [2022-07-22 02:43:41,553 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:41,554 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:41,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:41,736 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:41,737 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:41,738 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1997815846] [2022-07-22 02:43:41,739 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1997815846] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:41,739 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:41,739 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:41,740 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1996254032] [2022-07-22 02:43:41,740 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:41,744 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:43:41,746 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:41,746 INFO L85 PathProgramCache]: Analyzing trace with hash -1908840754, now seen corresponding path program 1 times [2022-07-22 02:43:41,746 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:41,747 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1653485611] [2022-07-22 02:43:41,747 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:41,747 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:41,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:41,794 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:41,794 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:41,795 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1653485611] [2022-07-22 02:43:41,795 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1653485611] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:41,795 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:41,795 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-22 02:43:41,795 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1512105168] [2022-07-22 02:43:41,796 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:41,796 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:43:41,797 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:43:41,817 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:43:41,818 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:43:41,821 INFO L87 Difference]: Start difference. First operand has 1285 states, 1284 states have (on average 1.5093457943925233) internal successors, (1938), 1284 states have internal predecessors, (1938), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:41,879 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:43:41,879 INFO L93 Difference]: Finished difference Result 1284 states and 1907 transitions. [2022-07-22 02:43:41,896 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:43:41,899 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1284 states and 1907 transitions. [2022-07-22 02:43:41,910 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2022-07-22 02:43:41,923 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1284 states to 1278 states and 1901 transitions. [2022-07-22 02:43:41,924 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1278 [2022-07-22 02:43:41,926 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1278 [2022-07-22 02:43:41,926 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1278 states and 1901 transitions. [2022-07-22 02:43:41,933 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:43:41,933 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1278 states and 1901 transitions. [2022-07-22 02:43:41,947 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1278 states and 1901 transitions. [2022-07-22 02:43:41,988 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1278 to 1278. [2022-07-22 02:43:41,991 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1278 states, 1278 states have (on average 1.4874804381846636) internal successors, (1901), 1277 states have internal predecessors, (1901), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:41,994 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1278 states to 1278 states and 1901 transitions. [2022-07-22 02:43:41,995 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1278 states and 1901 transitions. [2022-07-22 02:43:41,995 INFO L374 stractBuchiCegarLoop]: Abstraction has 1278 states and 1901 transitions. [2022-07-22 02:43:41,996 INFO L287 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-07-22 02:43:41,996 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1278 states and 1901 transitions. [2022-07-22 02:43:42,000 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2022-07-22 02:43:42,001 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:43:42,001 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:43:42,003 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:42,004 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:42,004 INFO L752 eck$LassoCheckResult]: Stem: 3560#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 3561#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 3835#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3823#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3824#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 3844#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3845#L706-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3128#L711-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2846#L716-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2847#L721-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3753#L726-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3754#L731-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3739#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3740#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3775#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 2900#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2901#L1006 assume !(0 == ~M_E~0); 2749#L1006-2 assume !(0 == ~T1_E~0); 2750#L1011-1 assume !(0 == ~T2_E~0); 3797#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3812#L1021-1 assume !(0 == ~T4_E~0); 2631#L1026-1 assume !(0 == ~T5_E~0); 2632#L1031-1 assume !(0 == ~T6_E~0); 3505#L1036-1 assume !(0 == ~T7_E~0); 3501#L1041-1 assume !(0 == ~T8_E~0); 3502#L1046-1 assume !(0 == ~T9_E~0); 2931#L1051-1 assume !(0 == ~T10_E~0); 2932#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 3634#L1061-1 assume !(0 == ~E_2~0); 2850#L1066-1 assume !(0 == ~E_3~0); 2851#L1071-1 assume !(0 == ~E_4~0); 3613#L1076-1 assume !(0 == ~E_5~0); 2760#L1081-1 assume !(0 == ~E_6~0); 2761#L1086-1 assume !(0 == ~E_7~0); 3103#L1091-1 assume !(0 == ~E_8~0); 3790#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 3791#L1101-1 assume !(0 == ~E_10~0); 3165#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3166#L484 assume !(1 == ~m_pc~0); 2809#L484-2 is_master_triggered_~__retres1~0#1 := 0; 2808#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3424#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3708#L1245 assume !(0 != activate_threads_~tmp~1#1); 3709#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3493#L503 assume 1 == ~t1_pc~0; 3494#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3511#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3626#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3279#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 2659#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2660#L522 assume !(1 == ~t2_pc~0); 3460#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2863#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2864#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3334#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 3755#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3820#L541 assume 1 == ~t3_pc~0; 3409#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3225#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3040#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3041#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 3463#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3464#L560 assume !(1 == ~t4_pc~0); 2743#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2742#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3368#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2627#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 2628#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2914#L579 assume 1 == ~t5_pc~0; 2578#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2579#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2687#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3371#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 3811#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3832#L598 assume 1 == ~t6_pc~0; 3008#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3009#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3311#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3731#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 3542#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3484#L617 assume !(1 == ~t7_pc~0); 2981#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2980#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3266#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3267#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3202#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3203#L636 assume 1 == ~t8_pc~0; 3365#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3366#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3167#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3168#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 3318#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3319#L655 assume !(1 == ~t9_pc~0); 3348#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3349#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2960#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2961#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 3562#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3563#L674 assume 1 == ~t10_pc~0; 2736#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 2737#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3822#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3853#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 3308#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3309#L1119 assume !(1 == ~M_E~0); 2832#L1119-2 assume !(1 == ~T1_E~0); 2833#L1124-1 assume !(1 == ~T2_E~0); 2651#L1129-1 assume !(1 == ~T3_E~0); 2652#L1134-1 assume !(1 == ~T4_E~0); 2965#L1139-1 assume !(1 == ~T5_E~0); 2966#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3198#L1149-1 assume !(1 == ~T7_E~0); 2827#L1154-1 assume !(1 == ~T8_E~0); 2828#L1159-1 assume !(1 == ~T9_E~0); 2915#L1164-1 assume !(1 == ~T10_E~0); 3337#L1169-1 assume !(1 == ~E_1~0); 3235#L1174-1 assume !(1 == ~E_2~0); 3022#L1179-1 assume !(1 == ~E_3~0); 2904#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 2905#L1189-1 assume !(1 == ~E_5~0); 2958#L1194-1 assume !(1 == ~E_6~0); 3081#L1199-1 assume !(1 == ~E_7~0); 3032#L1204-1 assume !(1 == ~E_8~0); 3033#L1209-1 assume !(1 == ~E_9~0); 3556#L1214-1 assume !(1 == ~E_10~0); 3557#L1219-1 assume { :end_inline_reset_delta_events } true; 2615#L1520-2 [2022-07-22 02:43:42,006 INFO L754 eck$LassoCheckResult]: Loop: 2615#L1520-2 assume !false; 2616#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2719#L981 assume !false; 2911#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3583#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2601#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3701#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3751#L836 assume !(0 != eval_~tmp~0#1); 3193#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3194#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3189#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3190#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3660#L1011-3 assume !(0 == ~T2_E~0); 3661#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3700#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3383#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3384#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3628#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3629#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3691#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3692#L1051-3 assume !(0 == ~T10_E~0); 3630#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2928#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2929#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2930#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3801#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2713#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2714#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2768#L1091-3 assume !(0 == ~E_8~0); 2769#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3776#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3777#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3403#L484-33 assume 1 == ~m_pc~0; 3404#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3323#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3324#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2621#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2622#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3093#L503-33 assume !(1 == ~t1_pc~0); 3094#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 3544#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3473#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3000#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3001#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3440#L522-33 assume 1 == ~t2_pc~0; 3441#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2756#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2757#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3550#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3458#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3459#L541-33 assume 1 == ~t3_pc~0; 2780#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2619#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2620#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3430#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3431#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3625#L560-33 assume 1 == ~t4_pc~0; 3330#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2691#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2692#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2948#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 3607#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2607#L579-33 assume 1 == ~t5_pc~0; 2608#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2856#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3816#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3485#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3486#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3510#L598-33 assume !(1 == ~t6_pc~0); 3283#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 3114#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3115#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2955#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2956#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3765#L617-33 assume 1 == ~t7_pc~0; 3771#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2748#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3699#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3806#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3802#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2679#L636-33 assume !(1 == ~t8_pc~0); 2680#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 3599#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3600#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3825#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3588#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3589#L655-33 assume 1 == ~t9_pc~0; 3849#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3055#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3056#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3414#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3678#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3234#L674-33 assume 1 == ~t10_pc~0; 3109#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 3110#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2971#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2972#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3449#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3826#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3833#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3836#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3847#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2993#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2994#L1139-3 assume !(1 == ~T5_E~0); 3227#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3228#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3370#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3640#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3641#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3807#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3112#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3113#L1179-3 assume !(1 == ~E_3~0); 3732#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2739#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2740#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3053#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3054#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3357#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2633#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 2634#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3547#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2716#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3070#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 3071#L1539 assume !(0 == start_simulation_~tmp~3#1); 3163#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3339#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3146#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3278#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 3062#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3063#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3667#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 3164#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 2615#L1520-2 [2022-07-22 02:43:42,007 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:42,007 INFO L85 PathProgramCache]: Analyzing trace with hash -934325781, now seen corresponding path program 1 times [2022-07-22 02:43:42,007 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:42,008 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1914626649] [2022-07-22 02:43:42,008 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:42,008 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:42,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:42,091 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:42,092 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:42,093 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1914626649] [2022-07-22 02:43:42,093 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1914626649] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:42,094 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:42,094 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:42,094 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [540907251] [2022-07-22 02:43:42,095 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:42,095 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:43:42,096 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:42,096 INFO L85 PathProgramCache]: Analyzing trace with hash -1410939798, now seen corresponding path program 1 times [2022-07-22 02:43:42,097 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:42,097 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1030768529] [2022-07-22 02:43:42,098 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:42,098 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:42,129 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:42,211 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:42,214 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:42,214 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1030768529] [2022-07-22 02:43:42,215 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1030768529] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:42,215 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:42,215 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:42,215 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1055103508] [2022-07-22 02:43:42,215 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:42,216 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:43:42,217 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:43:42,217 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:43:42,219 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:43:42,219 INFO L87 Difference]: Start difference. First operand 1278 states and 1901 transitions. cyclomatic complexity: 624 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:42,238 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:43:42,239 INFO L93 Difference]: Finished difference Result 1278 states and 1900 transitions. [2022-07-22 02:43:42,239 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:43:42,240 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1278 states and 1900 transitions. [2022-07-22 02:43:42,246 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2022-07-22 02:43:42,251 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1278 states to 1278 states and 1900 transitions. [2022-07-22 02:43:42,252 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1278 [2022-07-22 02:43:42,253 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1278 [2022-07-22 02:43:42,253 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1278 states and 1900 transitions. [2022-07-22 02:43:42,255 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:43:42,255 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1278 states and 1900 transitions. [2022-07-22 02:43:42,256 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1278 states and 1900 transitions. [2022-07-22 02:43:42,292 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1278 to 1278. [2022-07-22 02:43:42,294 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1278 states, 1278 states have (on average 1.486697965571205) internal successors, (1900), 1277 states have internal predecessors, (1900), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:42,298 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1278 states to 1278 states and 1900 transitions. [2022-07-22 02:43:42,298 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1278 states and 1900 transitions. [2022-07-22 02:43:42,298 INFO L374 stractBuchiCegarLoop]: Abstraction has 1278 states and 1900 transitions. [2022-07-22 02:43:42,298 INFO L287 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-07-22 02:43:42,298 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1278 states and 1900 transitions. [2022-07-22 02:43:42,303 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2022-07-22 02:43:42,303 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:43:42,303 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:43:42,308 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:42,308 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:42,308 INFO L752 eck$LassoCheckResult]: Stem: 6123#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 6124#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 6398#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6386#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6387#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 6407#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6408#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5691#L711-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5411#L716-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5412#L721-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6316#L726-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6317#L731-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6302#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6303#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 6338#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5463#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5464#L1006 assume !(0 == ~M_E~0); 5315#L1006-2 assume !(0 == ~T1_E~0); 5316#L1011-1 assume !(0 == ~T2_E~0); 6360#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6375#L1021-1 assume !(0 == ~T4_E~0); 5194#L1026-1 assume !(0 == ~T5_E~0); 5195#L1031-1 assume !(0 == ~T6_E~0); 6070#L1036-1 assume !(0 == ~T7_E~0); 6064#L1041-1 assume !(0 == ~T8_E~0); 6065#L1046-1 assume !(0 == ~T9_E~0); 5494#L1051-1 assume !(0 == ~T10_E~0); 5495#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 6197#L1061-1 assume !(0 == ~E_2~0); 5413#L1066-1 assume !(0 == ~E_3~0); 5414#L1071-1 assume !(0 == ~E_4~0); 6176#L1076-1 assume !(0 == ~E_5~0); 5323#L1081-1 assume !(0 == ~E_6~0); 5324#L1086-1 assume !(0 == ~E_7~0); 5667#L1091-1 assume !(0 == ~E_8~0); 6353#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 6354#L1101-1 assume !(0 == ~E_10~0); 5728#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5729#L484 assume !(1 == ~m_pc~0); 5372#L484-2 is_master_triggered_~__retres1~0#1 := 0; 5371#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5987#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6271#L1245 assume !(0 != activate_threads_~tmp~1#1); 6272#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6056#L503 assume 1 == ~t1_pc~0; 6057#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6075#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6189#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5842#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 5224#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5225#L522 assume !(1 == ~t2_pc~0); 6023#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5427#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5428#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5897#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 6318#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6383#L541 assume 1 == ~t3_pc~0; 5974#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5788#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5603#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5604#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 6030#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6031#L560 assume !(1 == ~t4_pc~0); 5306#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5305#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5931#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5190#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 5191#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5477#L579 assume 1 == ~t5_pc~0; 5141#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5142#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5250#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5934#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 6374#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6395#L598 assume 1 == ~t6_pc~0; 5573#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5574#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5876#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6294#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 6105#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6047#L617 assume !(1 == ~t7_pc~0); 5544#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5543#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5829#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5830#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5766#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5767#L636 assume 1 == ~t8_pc~0; 5928#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5929#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5730#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5731#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 5883#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5884#L655 assume !(1 == ~t9_pc~0); 5913#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 5914#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5523#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5524#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 6125#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6126#L674 assume 1 == ~t10_pc~0; 5299#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 5300#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6385#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6416#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 5871#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5872#L1119 assume !(1 == ~M_E~0); 5395#L1119-2 assume !(1 == ~T1_E~0); 5396#L1124-1 assume !(1 == ~T2_E~0); 5214#L1129-1 assume !(1 == ~T3_E~0); 5215#L1134-1 assume !(1 == ~T4_E~0); 5528#L1139-1 assume !(1 == ~T5_E~0); 5529#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5761#L1149-1 assume !(1 == ~T7_E~0); 5390#L1154-1 assume !(1 == ~T8_E~0); 5391#L1159-1 assume !(1 == ~T9_E~0); 5478#L1164-1 assume !(1 == ~T10_E~0); 5900#L1169-1 assume !(1 == ~E_1~0); 5798#L1174-1 assume !(1 == ~E_2~0); 5587#L1179-1 assume !(1 == ~E_3~0); 5467#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 5468#L1189-1 assume !(1 == ~E_5~0); 5522#L1194-1 assume !(1 == ~E_6~0); 5644#L1199-1 assume !(1 == ~E_7~0); 5595#L1204-1 assume !(1 == ~E_8~0); 5596#L1209-1 assume !(1 == ~E_9~0); 6119#L1214-1 assume !(1 == ~E_10~0); 6120#L1219-1 assume { :end_inline_reset_delta_events } true; 5178#L1520-2 [2022-07-22 02:43:42,309 INFO L754 eck$LassoCheckResult]: Loop: 5178#L1520-2 assume !false; 5179#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5279#L981 assume !false; 5474#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6146#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5164#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6264#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6314#L836 assume !(0 != eval_~tmp~0#1); 5759#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5760#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5752#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5753#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6223#L1011-3 assume !(0 == ~T2_E~0); 6224#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6263#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5946#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5947#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6191#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6192#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 6252#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 6253#L1051-3 assume !(0 == ~T10_E~0); 6193#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5489#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5490#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5493#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6364#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5276#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5277#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5329#L1091-3 assume !(0 == ~E_8~0); 5330#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 6339#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 6340#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5966#L484-33 assume !(1 == ~m_pc~0); 5968#L484-35 is_master_triggered_~__retres1~0#1 := 0; 5886#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5887#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5184#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5185#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5653#L503-33 assume !(1 == ~t1_pc~0); 5654#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 6107#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6033#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5561#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5562#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6003#L522-33 assume 1 == ~t2_pc~0; 6004#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5317#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5318#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6112#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6021#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6022#L541-33 assume !(1 == ~t3_pc~0); 5344#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 5182#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5183#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5993#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5994#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6188#L560-33 assume 1 == ~t4_pc~0; 5893#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5254#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5255#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5513#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 6170#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5173#L579-33 assume 1 == ~t5_pc~0; 5174#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5420#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6379#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6048#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6049#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6074#L598-33 assume !(1 == ~t6_pc~0); 5851#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 5677#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5678#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5518#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5519#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6328#L617-33 assume 1 == ~t7_pc~0; 6334#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5311#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6262#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6369#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6365#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5242#L636-33 assume !(1 == ~t8_pc~0); 5243#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 6162#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6163#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6388#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 6153#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6154#L655-33 assume 1 == ~t9_pc~0; 6412#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5618#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5619#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5977#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 6241#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5797#L674-33 assume 1 == ~t10_pc~0; 5672#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 5673#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5534#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5535#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 6012#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6389#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6396#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6399#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6410#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5559#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5560#L1139-3 assume !(1 == ~T5_E~0); 5790#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5791#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5933#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6203#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 6204#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 6370#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5675#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5676#L1179-3 assume !(1 == ~E_3~0); 6295#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5302#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5303#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5616#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5617#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5920#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5196#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 5197#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6111#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5282#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5633#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 5634#L1539 assume !(0 == start_simulation_~tmp~3#1); 5726#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 5902#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5709#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5841#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 5625#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5626#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6230#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 5727#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 5178#L1520-2 [2022-07-22 02:43:42,310 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:42,310 INFO L85 PathProgramCache]: Analyzing trace with hash 158309421, now seen corresponding path program 1 times [2022-07-22 02:43:42,310 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:42,311 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1622756426] [2022-07-22 02:43:42,311 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:42,311 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:42,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:42,353 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:42,354 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:42,354 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1622756426] [2022-07-22 02:43:42,354 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1622756426] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:42,354 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:42,355 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:42,355 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1192331680] [2022-07-22 02:43:42,355 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:42,355 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:43:42,356 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:42,356 INFO L85 PathProgramCache]: Analyzing trace with hash -103858072, now seen corresponding path program 1 times [2022-07-22 02:43:42,356 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:42,356 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1464610307] [2022-07-22 02:43:42,356 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:42,356 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:42,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:42,405 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:42,405 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:42,406 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1464610307] [2022-07-22 02:43:42,406 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1464610307] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:42,406 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:42,406 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:42,406 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2142820732] [2022-07-22 02:43:42,407 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:42,407 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:43:42,408 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:43:42,408 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:43:42,408 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:43:42,408 INFO L87 Difference]: Start difference. First operand 1278 states and 1900 transitions. cyclomatic complexity: 623 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:42,425 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:43:42,425 INFO L93 Difference]: Finished difference Result 1278 states and 1899 transitions. [2022-07-22 02:43:42,426 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:43:42,427 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1278 states and 1899 transitions. [2022-07-22 02:43:42,433 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2022-07-22 02:43:42,437 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1278 states to 1278 states and 1899 transitions. [2022-07-22 02:43:42,438 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1278 [2022-07-22 02:43:42,438 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1278 [2022-07-22 02:43:42,439 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1278 states and 1899 transitions. [2022-07-22 02:43:42,440 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:43:42,440 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1278 states and 1899 transitions. [2022-07-22 02:43:42,441 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1278 states and 1899 transitions. [2022-07-22 02:43:42,452 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1278 to 1278. [2022-07-22 02:43:42,454 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1278 states, 1278 states have (on average 1.4859154929577465) internal successors, (1899), 1277 states have internal predecessors, (1899), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:42,458 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1278 states to 1278 states and 1899 transitions. [2022-07-22 02:43:42,458 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1278 states and 1899 transitions. [2022-07-22 02:43:42,458 INFO L374 stractBuchiCegarLoop]: Abstraction has 1278 states and 1899 transitions. [2022-07-22 02:43:42,459 INFO L287 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-07-22 02:43:42,459 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1278 states and 1899 transitions. [2022-07-22 02:43:42,463 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2022-07-22 02:43:42,464 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:43:42,464 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:43:42,465 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:42,465 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:42,466 INFO L752 eck$LassoCheckResult]: Stem: 8685#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 8686#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 8961#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8949#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8950#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 8970#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8971#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8254#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7972#L716-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 7973#L721-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8879#L726-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8880#L731-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8865#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8866#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 8901#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 8024#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8025#L1006 assume !(0 == ~M_E~0); 7875#L1006-2 assume !(0 == ~T1_E~0); 7876#L1011-1 assume !(0 == ~T2_E~0); 8923#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8938#L1021-1 assume !(0 == ~T4_E~0); 7755#L1026-1 assume !(0 == ~T5_E~0); 7756#L1031-1 assume !(0 == ~T6_E~0); 8631#L1036-1 assume !(0 == ~T7_E~0); 8627#L1041-1 assume !(0 == ~T8_E~0); 8628#L1046-1 assume !(0 == ~T9_E~0); 8057#L1051-1 assume !(0 == ~T10_E~0); 8058#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 8760#L1061-1 assume !(0 == ~E_2~0); 7976#L1066-1 assume !(0 == ~E_3~0); 7977#L1071-1 assume !(0 == ~E_4~0); 8739#L1076-1 assume !(0 == ~E_5~0); 7886#L1081-1 assume !(0 == ~E_6~0); 7887#L1086-1 assume !(0 == ~E_7~0); 8229#L1091-1 assume !(0 == ~E_8~0); 8915#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 8916#L1101-1 assume !(0 == ~E_10~0); 8291#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8292#L484 assume !(1 == ~m_pc~0); 7935#L484-2 is_master_triggered_~__retres1~0#1 := 0; 7934#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8550#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8834#L1245 assume !(0 != activate_threads_~tmp~1#1); 8835#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8619#L503 assume 1 == ~t1_pc~0; 8620#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8636#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8752#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8402#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 7785#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7786#L522 assume !(1 == ~t2_pc~0); 8586#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7989#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7990#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8460#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 8881#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8946#L541 assume 1 == ~t3_pc~0; 8535#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8351#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8166#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8167#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 8589#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8590#L560 assume !(1 == ~t4_pc~0); 7867#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7866#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8494#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7753#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 7754#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8038#L579 assume 1 == ~t5_pc~0; 7704#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7705#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7813#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8497#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 8936#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8958#L598 assume 1 == ~t6_pc~0; 8134#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8135#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8436#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8857#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 8668#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8610#L617 assume !(1 == ~t7_pc~0); 8107#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8106#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8392#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8393#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8328#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8329#L636 assume 1 == ~t8_pc~0; 8491#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8492#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8293#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8294#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 8444#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8445#L655 assume !(1 == ~t9_pc~0); 8472#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 8473#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8086#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8087#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 8687#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8688#L674 assume 1 == ~t10_pc~0; 7862#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 7863#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8948#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8979#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 8434#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8435#L1119 assume !(1 == ~M_E~0); 7958#L1119-2 assume !(1 == ~T1_E~0); 7959#L1124-1 assume !(1 == ~T2_E~0); 7777#L1129-1 assume !(1 == ~T3_E~0); 7778#L1134-1 assume !(1 == ~T4_E~0); 8088#L1139-1 assume !(1 == ~T5_E~0); 8089#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8324#L1149-1 assume !(1 == ~T7_E~0); 7953#L1154-1 assume !(1 == ~T8_E~0); 7954#L1159-1 assume !(1 == ~T9_E~0); 8041#L1164-1 assume !(1 == ~T10_E~0); 8463#L1169-1 assume !(1 == ~E_1~0); 8361#L1174-1 assume !(1 == ~E_2~0); 8148#L1179-1 assume !(1 == ~E_3~0); 8030#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 8031#L1189-1 assume !(1 == ~E_5~0); 8083#L1194-1 assume !(1 == ~E_6~0); 8207#L1199-1 assume !(1 == ~E_7~0); 8158#L1204-1 assume !(1 == ~E_8~0); 8159#L1209-1 assume !(1 == ~E_9~0); 8682#L1214-1 assume !(1 == ~E_10~0); 8683#L1219-1 assume { :end_inline_reset_delta_events } true; 7741#L1520-2 [2022-07-22 02:43:42,466 INFO L754 eck$LassoCheckResult]: Loop: 7741#L1520-2 assume !false; 7742#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7842#L981 assume !false; 8034#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8709#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 7727#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8827#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8877#L836 assume !(0 != eval_~tmp~0#1); 8319#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8320#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8315#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8316#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8786#L1011-3 assume !(0 == ~T2_E~0); 8787#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8826#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8507#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8508#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8754#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8755#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8815#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8816#L1051-3 assume !(0 == ~T10_E~0); 8756#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8052#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8053#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8056#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8927#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7839#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7840#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7892#L1091-3 assume !(0 == ~E_8~0); 7893#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8902#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 8903#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8529#L484-33 assume 1 == ~m_pc~0; 8530#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 8449#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8450#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7747#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7748#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8216#L503-33 assume !(1 == ~t1_pc~0); 8217#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 8670#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8597#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8126#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8127#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8566#L522-33 assume 1 == ~t2_pc~0; 8567#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7880#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7881#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8675#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8584#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8585#L541-33 assume 1 == ~t3_pc~0; 7906#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7745#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7746#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8556#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8557#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8751#L560-33 assume 1 == ~t4_pc~0; 8456#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7817#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7818#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8076#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 8733#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7736#L579-33 assume 1 == ~t5_pc~0; 7737#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7983#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8942#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8611#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8612#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8640#L598-33 assume 1 == ~t6_pc~0; 8944#L599-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8240#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8241#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8081#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8082#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8891#L617-33 assume 1 == ~t7_pc~0; 8897#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7874#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8825#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8932#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8928#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7805#L636-33 assume !(1 == ~t8_pc~0); 7806#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 8725#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8726#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8951#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8716#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8717#L655-33 assume !(1 == ~t9_pc~0); 8976#L655-35 is_transmit9_triggered_~__retres1~9#1 := 0; 8183#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8184#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8540#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8804#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8360#L674-33 assume 1 == ~t10_pc~0; 8235#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8236#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8097#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8098#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8575#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8952#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8959#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8963#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8973#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8122#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8123#L1139-3 assume !(1 == ~T5_E~0); 8353#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8354#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8496#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8766#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 8767#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8934#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8238#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8239#L1179-3 assume !(1 == ~E_3~0); 8858#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7868#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7869#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8179#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8180#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8483#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 7759#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 7760#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8674#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 7845#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8196#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 8197#L1539 assume !(0 == start_simulation_~tmp~3#1); 8289#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8465#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8272#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8405#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 8188#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8189#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8793#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 8290#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 7741#L1520-2 [2022-07-22 02:43:42,467 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:42,467 INFO L85 PathProgramCache]: Analyzing trace with hash 1440481707, now seen corresponding path program 1 times [2022-07-22 02:43:42,467 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:42,467 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1881585965] [2022-07-22 02:43:42,467 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:42,467 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:42,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:42,489 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:42,490 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:42,490 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1881585965] [2022-07-22 02:43:42,490 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1881585965] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:42,491 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:42,491 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:42,493 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1081617860] [2022-07-22 02:43:42,493 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:42,494 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:43:42,494 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:42,494 INFO L85 PathProgramCache]: Analyzing trace with hash 871104042, now seen corresponding path program 1 times [2022-07-22 02:43:42,495 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:42,497 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [771086327] [2022-07-22 02:43:42,497 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:42,498 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:42,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:42,560 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:42,560 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:42,561 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [771086327] [2022-07-22 02:43:42,561 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [771086327] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:42,561 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:42,561 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:42,561 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [991615879] [2022-07-22 02:43:42,561 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:42,561 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:43:42,561 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:43:42,562 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:43:42,562 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:43:42,562 INFO L87 Difference]: Start difference. First operand 1278 states and 1899 transitions. cyclomatic complexity: 622 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:42,578 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:43:42,578 INFO L93 Difference]: Finished difference Result 1278 states and 1898 transitions. [2022-07-22 02:43:42,578 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:43:42,579 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1278 states and 1898 transitions. [2022-07-22 02:43:42,584 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2022-07-22 02:43:42,589 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1278 states to 1278 states and 1898 transitions. [2022-07-22 02:43:42,589 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1278 [2022-07-22 02:43:42,590 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1278 [2022-07-22 02:43:42,590 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1278 states and 1898 transitions. [2022-07-22 02:43:42,591 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:43:42,591 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1278 states and 1898 transitions. [2022-07-22 02:43:42,592 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1278 states and 1898 transitions. [2022-07-22 02:43:42,602 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1278 to 1278. [2022-07-22 02:43:42,604 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1278 states, 1278 states have (on average 1.4851330203442878) internal successors, (1898), 1277 states have internal predecessors, (1898), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:42,606 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1278 states to 1278 states and 1898 transitions. [2022-07-22 02:43:42,606 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1278 states and 1898 transitions. [2022-07-22 02:43:42,606 INFO L374 stractBuchiCegarLoop]: Abstraction has 1278 states and 1898 transitions. [2022-07-22 02:43:42,606 INFO L287 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-07-22 02:43:42,607 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1278 states and 1898 transitions. [2022-07-22 02:43:42,611 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2022-07-22 02:43:42,611 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:43:42,611 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:43:42,612 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:42,612 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:42,612 INFO L752 eck$LassoCheckResult]: Stem: 11248#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 11249#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 11524#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11512#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11513#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 11533#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11534#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10817#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10535#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10536#L721-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11442#L726-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 11443#L731-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11428#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11429#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11464#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 10587#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10588#L1006 assume !(0 == ~M_E~0); 10438#L1006-2 assume !(0 == ~T1_E~0); 10439#L1011-1 assume !(0 == ~T2_E~0); 11486#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11501#L1021-1 assume !(0 == ~T4_E~0); 10318#L1026-1 assume !(0 == ~T5_E~0); 10319#L1031-1 assume !(0 == ~T6_E~0); 11194#L1036-1 assume !(0 == ~T7_E~0); 11190#L1041-1 assume !(0 == ~T8_E~0); 11191#L1046-1 assume !(0 == ~T9_E~0); 10620#L1051-1 assume !(0 == ~T10_E~0); 10621#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 11323#L1061-1 assume !(0 == ~E_2~0); 10539#L1066-1 assume !(0 == ~E_3~0); 10540#L1071-1 assume !(0 == ~E_4~0); 11302#L1076-1 assume !(0 == ~E_5~0); 10449#L1081-1 assume !(0 == ~E_6~0); 10450#L1086-1 assume !(0 == ~E_7~0); 10792#L1091-1 assume !(0 == ~E_8~0); 11478#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 11479#L1101-1 assume !(0 == ~E_10~0); 10854#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10855#L484 assume !(1 == ~m_pc~0); 10498#L484-2 is_master_triggered_~__retres1~0#1 := 0; 10497#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11113#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11397#L1245 assume !(0 != activate_threads_~tmp~1#1); 11398#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11182#L503 assume 1 == ~t1_pc~0; 11183#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11199#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11315#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10965#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 10348#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10349#L522 assume !(1 == ~t2_pc~0); 11149#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10552#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10553#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11023#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 11444#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11509#L541 assume 1 == ~t3_pc~0; 11098#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10914#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10729#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10730#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 11152#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11153#L560 assume !(1 == ~t4_pc~0); 10430#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10429#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11057#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10316#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 10317#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10601#L579 assume 1 == ~t5_pc~0; 10267#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10268#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10376#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11060#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 11499#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11521#L598 assume 1 == ~t6_pc~0; 10697#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10698#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10999#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11420#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 11231#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11173#L617 assume !(1 == ~t7_pc~0); 10670#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 10669#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10955#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10956#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10891#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10892#L636 assume 1 == ~t8_pc~0; 11054#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11055#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10856#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10857#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 11007#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11008#L655 assume !(1 == ~t9_pc~0); 11035#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 11036#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10649#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10650#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 11250#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11251#L674 assume 1 == ~t10_pc~0; 10425#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 10426#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11511#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11542#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 10997#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10998#L1119 assume !(1 == ~M_E~0); 10521#L1119-2 assume !(1 == ~T1_E~0); 10522#L1124-1 assume !(1 == ~T2_E~0); 10340#L1129-1 assume !(1 == ~T3_E~0); 10341#L1134-1 assume !(1 == ~T4_E~0); 10652#L1139-1 assume !(1 == ~T5_E~0); 10653#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10887#L1149-1 assume !(1 == ~T7_E~0); 10516#L1154-1 assume !(1 == ~T8_E~0); 10517#L1159-1 assume !(1 == ~T9_E~0); 10604#L1164-1 assume !(1 == ~T10_E~0); 11026#L1169-1 assume !(1 == ~E_1~0); 10924#L1174-1 assume !(1 == ~E_2~0); 10711#L1179-1 assume !(1 == ~E_3~0); 10593#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 10594#L1189-1 assume !(1 == ~E_5~0); 10646#L1194-1 assume !(1 == ~E_6~0); 10770#L1199-1 assume !(1 == ~E_7~0); 10721#L1204-1 assume !(1 == ~E_8~0); 10722#L1209-1 assume !(1 == ~E_9~0); 11245#L1214-1 assume !(1 == ~E_10~0); 11246#L1219-1 assume { :end_inline_reset_delta_events } true; 10304#L1520-2 [2022-07-22 02:43:42,612 INFO L754 eck$LassoCheckResult]: Loop: 10304#L1520-2 assume !false; 10305#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10405#L981 assume !false; 10597#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11272#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 10290#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11390#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11440#L836 assume !(0 != eval_~tmp~0#1); 10882#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10883#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10878#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10879#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11349#L1011-3 assume !(0 == ~T2_E~0); 11350#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11389#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11070#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11071#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11317#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11318#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 11378#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11379#L1051-3 assume !(0 == ~T10_E~0); 11319#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10615#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10616#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10619#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11490#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10402#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10403#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10455#L1091-3 assume !(0 == ~E_8~0); 10456#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11465#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 11466#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11092#L484-33 assume 1 == ~m_pc~0; 11093#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11012#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11013#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10310#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10311#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10779#L503-33 assume !(1 == ~t1_pc~0); 10780#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 11233#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11160#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10689#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10690#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11129#L522-33 assume 1 == ~t2_pc~0; 11130#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10443#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10444#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11238#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11147#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11148#L541-33 assume 1 == ~t3_pc~0; 10469#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10308#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10309#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11119#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11120#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11314#L560-33 assume 1 == ~t4_pc~0; 11019#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10380#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10381#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10639#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 11296#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10299#L579-33 assume 1 == ~t5_pc~0; 10300#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10546#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11505#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11174#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11175#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11203#L598-33 assume !(1 == ~t6_pc~0); 10977#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 10803#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10804#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10644#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10645#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11454#L617-33 assume 1 == ~t7_pc~0; 11460#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10437#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11388#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11495#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11491#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10368#L636-33 assume !(1 == ~t8_pc~0); 10369#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 11288#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11289#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11514#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11279#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11280#L655-33 assume 1 == ~t9_pc~0; 11538#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10746#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10747#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11103#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11367#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10923#L674-33 assume !(1 == ~t10_pc~0); 10800#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 10799#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 10660#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10661#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 11138#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11515#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11522#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11526#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11536#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10685#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10686#L1139-3 assume !(1 == ~T5_E~0); 10916#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10917#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11059#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11329#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11330#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11497#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10801#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10802#L1179-3 assume !(1 == ~E_3~0); 11421#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10431#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10432#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10742#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10743#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11046#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 10322#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 10323#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11237#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 10408#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 10759#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 10760#L1539 assume !(0 == start_simulation_~tmp~3#1); 10852#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11028#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 10835#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 10968#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 10751#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10752#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11356#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 10853#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 10304#L1520-2 [2022-07-22 02:43:42,613 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:42,613 INFO L85 PathProgramCache]: Analyzing trace with hash -1012009875, now seen corresponding path program 1 times [2022-07-22 02:43:42,613 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:42,613 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1522529614] [2022-07-22 02:43:42,613 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:42,613 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:42,620 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:42,631 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:42,631 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:42,632 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1522529614] [2022-07-22 02:43:42,632 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1522529614] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:42,632 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:42,632 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:42,632 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1995143603] [2022-07-22 02:43:42,632 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:42,632 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:43:42,632 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:42,632 INFO L85 PathProgramCache]: Analyzing trace with hash -1010948599, now seen corresponding path program 1 times [2022-07-22 02:43:42,633 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:42,633 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1086106834] [2022-07-22 02:43:42,633 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:42,633 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:42,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:42,657 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:42,657 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:42,657 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1086106834] [2022-07-22 02:43:42,658 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1086106834] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:42,658 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:42,658 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:42,658 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1954535510] [2022-07-22 02:43:42,658 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:42,658 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:43:42,658 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:43:42,658 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:43:42,659 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:43:42,659 INFO L87 Difference]: Start difference. First operand 1278 states and 1898 transitions. cyclomatic complexity: 621 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:42,674 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:43:42,674 INFO L93 Difference]: Finished difference Result 1278 states and 1897 transitions. [2022-07-22 02:43:42,675 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:43:42,675 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1278 states and 1897 transitions. [2022-07-22 02:43:42,681 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2022-07-22 02:43:42,685 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1278 states to 1278 states and 1897 transitions. [2022-07-22 02:43:42,685 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1278 [2022-07-22 02:43:42,686 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1278 [2022-07-22 02:43:42,686 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1278 states and 1897 transitions. [2022-07-22 02:43:42,687 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:43:42,687 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1278 states and 1897 transitions. [2022-07-22 02:43:42,688 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1278 states and 1897 transitions. [2022-07-22 02:43:42,698 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1278 to 1278. [2022-07-22 02:43:42,699 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1278 states, 1278 states have (on average 1.4843505477308294) internal successors, (1897), 1277 states have internal predecessors, (1897), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:42,702 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1278 states to 1278 states and 1897 transitions. [2022-07-22 02:43:42,702 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1278 states and 1897 transitions. [2022-07-22 02:43:42,702 INFO L374 stractBuchiCegarLoop]: Abstraction has 1278 states and 1897 transitions. [2022-07-22 02:43:42,702 INFO L287 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-07-22 02:43:42,702 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1278 states and 1897 transitions. [2022-07-22 02:43:42,717 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2022-07-22 02:43:42,718 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:43:42,718 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:43:42,719 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:42,719 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:42,719 INFO L752 eck$LassoCheckResult]: Stem: 13812#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 13813#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 14087#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14075#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14076#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 14096#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14097#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13380#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13098#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13099#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14005#L726-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 14006#L731-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 13991#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 13992#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14027#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13152#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13153#L1006 assume !(0 == ~M_E~0); 13001#L1006-2 assume !(0 == ~T1_E~0); 13002#L1011-1 assume !(0 == ~T2_E~0); 14049#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14064#L1021-1 assume !(0 == ~T4_E~0); 12883#L1026-1 assume !(0 == ~T5_E~0); 12884#L1031-1 assume !(0 == ~T6_E~0); 13757#L1036-1 assume !(0 == ~T7_E~0); 13753#L1041-1 assume !(0 == ~T8_E~0); 13754#L1046-1 assume !(0 == ~T9_E~0); 13183#L1051-1 assume !(0 == ~T10_E~0); 13184#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 13886#L1061-1 assume !(0 == ~E_2~0); 13102#L1066-1 assume !(0 == ~E_3~0); 13103#L1071-1 assume !(0 == ~E_4~0); 13865#L1076-1 assume !(0 == ~E_5~0); 13012#L1081-1 assume !(0 == ~E_6~0); 13013#L1086-1 assume !(0 == ~E_7~0); 13355#L1091-1 assume !(0 == ~E_8~0); 14042#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 14043#L1101-1 assume !(0 == ~E_10~0); 13417#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13418#L484 assume !(1 == ~m_pc~0); 13061#L484-2 is_master_triggered_~__retres1~0#1 := 0; 13060#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13676#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13960#L1245 assume !(0 != activate_threads_~tmp~1#1); 13961#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13745#L503 assume 1 == ~t1_pc~0; 13746#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13763#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13878#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13531#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 12911#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12912#L522 assume !(1 == ~t2_pc~0); 13712#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 13115#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13116#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13586#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 14007#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14072#L541 assume 1 == ~t3_pc~0; 13661#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13477#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13292#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13293#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 13715#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13716#L560 assume !(1 == ~t4_pc~0); 12995#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12994#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13620#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12879#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 12880#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13166#L579 assume 1 == ~t5_pc~0; 12830#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12831#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12939#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13623#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 14063#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14084#L598 assume 1 == ~t6_pc~0; 13260#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13261#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13563#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13983#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 13794#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13736#L617 assume !(1 == ~t7_pc~0); 13233#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 13232#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13518#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13519#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 13454#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13455#L636 assume 1 == ~t8_pc~0; 13617#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13618#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13419#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13420#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 13572#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13573#L655 assume !(1 == ~t9_pc~0); 13600#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 13601#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13212#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13213#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 13814#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13815#L674 assume 1 == ~t10_pc~0; 12988#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 12989#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14074#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14105#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 13560#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13561#L1119 assume !(1 == ~M_E~0); 13084#L1119-2 assume !(1 == ~T1_E~0); 13085#L1124-1 assume !(1 == ~T2_E~0); 12903#L1129-1 assume !(1 == ~T3_E~0); 12904#L1134-1 assume !(1 == ~T4_E~0); 13217#L1139-1 assume !(1 == ~T5_E~0); 13218#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13450#L1149-1 assume !(1 == ~T7_E~0); 13079#L1154-1 assume !(1 == ~T8_E~0); 13080#L1159-1 assume !(1 == ~T9_E~0); 13167#L1164-1 assume !(1 == ~T10_E~0); 13589#L1169-1 assume !(1 == ~E_1~0); 13487#L1174-1 assume !(1 == ~E_2~0); 13274#L1179-1 assume !(1 == ~E_3~0); 13156#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 13157#L1189-1 assume !(1 == ~E_5~0); 13210#L1194-1 assume !(1 == ~E_6~0); 13333#L1199-1 assume !(1 == ~E_7~0); 13284#L1204-1 assume !(1 == ~E_8~0); 13285#L1209-1 assume !(1 == ~E_9~0); 13808#L1214-1 assume !(1 == ~E_10~0); 13809#L1219-1 assume { :end_inline_reset_delta_events } true; 12867#L1520-2 [2022-07-22 02:43:42,720 INFO L754 eck$LassoCheckResult]: Loop: 12867#L1520-2 assume !false; 12868#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12971#L981 assume !false; 13163#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 13835#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 12853#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 13953#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 14003#L836 assume !(0 != eval_~tmp~0#1); 13445#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13446#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13441#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13442#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13912#L1011-3 assume !(0 == ~T2_E~0); 13913#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13952#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13635#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13636#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13880#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13881#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13943#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13944#L1051-3 assume !(0 == ~T10_E~0); 13882#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13180#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13181#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13182#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14053#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12965#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12966#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13020#L1091-3 assume !(0 == ~E_8~0); 13021#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 14028#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 14029#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13655#L484-33 assume 1 == ~m_pc~0; 13656#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13575#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13576#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12873#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12874#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13345#L503-33 assume !(1 == ~t1_pc~0); 13346#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 13796#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13725#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13252#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13253#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13692#L522-33 assume 1 == ~t2_pc~0; 13693#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13008#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13009#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13802#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13710#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13711#L541-33 assume 1 == ~t3_pc~0; 13032#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12871#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12872#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13682#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13683#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13877#L560-33 assume 1 == ~t4_pc~0; 13582#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12943#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12944#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13200#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 13859#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12859#L579-33 assume 1 == ~t5_pc~0; 12860#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13108#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14068#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13737#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13738#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13762#L598-33 assume 1 == ~t6_pc~0; 14069#L599-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13366#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13367#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13207#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13208#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14017#L617-33 assume 1 == ~t7_pc~0; 14023#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13000#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13951#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14058#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14054#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12931#L636-33 assume !(1 == ~t8_pc~0); 12932#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 13851#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13852#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14077#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 13840#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13841#L655-33 assume 1 == ~t9_pc~0; 14101#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 13307#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13308#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13666#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13930#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13486#L674-33 assume 1 == ~t10_pc~0; 13361#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 13362#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13223#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13224#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 13701#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14078#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14085#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14088#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14099#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13245#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13246#L1139-3 assume !(1 == ~T5_E~0); 13479#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13480#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13622#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13892#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 13893#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 14059#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13364#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13365#L1179-3 assume !(1 == ~E_3~0); 13984#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12991#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12992#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13305#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13306#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 13609#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12885#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12886#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 13799#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 12968#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 13322#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 13323#L1539 assume !(0 == start_simulation_~tmp~3#1); 13415#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 13591#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13398#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 13530#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 13314#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13315#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13919#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 13416#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 12867#L1520-2 [2022-07-22 02:43:42,720 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:42,720 INFO L85 PathProgramCache]: Analyzing trace with hash 709992811, now seen corresponding path program 1 times [2022-07-22 02:43:42,720 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:42,720 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2073770389] [2022-07-22 02:43:42,720 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:42,720 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:42,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:42,739 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:42,739 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:42,739 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2073770389] [2022-07-22 02:43:42,739 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2073770389] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:42,739 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:42,740 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:42,740 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [527293696] [2022-07-22 02:43:42,740 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:42,740 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:43:42,740 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:42,740 INFO L85 PathProgramCache]: Analyzing trace with hash -2115858485, now seen corresponding path program 1 times [2022-07-22 02:43:42,740 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:42,741 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1901929929] [2022-07-22 02:43:42,741 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:42,741 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:42,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:42,767 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:42,767 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:42,768 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1901929929] [2022-07-22 02:43:42,768 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1901929929] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:42,768 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:42,768 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:42,768 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1484459045] [2022-07-22 02:43:42,768 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:42,768 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:43:42,768 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:43:42,769 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:43:42,769 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:43:42,769 INFO L87 Difference]: Start difference. First operand 1278 states and 1897 transitions. cyclomatic complexity: 620 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:42,786 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:43:42,786 INFO L93 Difference]: Finished difference Result 1278 states and 1896 transitions. [2022-07-22 02:43:42,786 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:43:42,787 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1278 states and 1896 transitions. [2022-07-22 02:43:42,793 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2022-07-22 02:43:42,797 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1278 states to 1278 states and 1896 transitions. [2022-07-22 02:43:42,797 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1278 [2022-07-22 02:43:42,798 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1278 [2022-07-22 02:43:42,798 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1278 states and 1896 transitions. [2022-07-22 02:43:42,799 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:43:42,799 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1278 states and 1896 transitions. [2022-07-22 02:43:42,800 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1278 states and 1896 transitions. [2022-07-22 02:43:42,812 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1278 to 1278. [2022-07-22 02:43:42,813 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1278 states, 1278 states have (on average 1.483568075117371) internal successors, (1896), 1277 states have internal predecessors, (1896), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:42,816 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1278 states to 1278 states and 1896 transitions. [2022-07-22 02:43:42,816 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1278 states and 1896 transitions. [2022-07-22 02:43:42,816 INFO L374 stractBuchiCegarLoop]: Abstraction has 1278 states and 1896 transitions. [2022-07-22 02:43:42,816 INFO L287 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-07-22 02:43:42,816 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1278 states and 1896 transitions. [2022-07-22 02:43:42,820 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2022-07-22 02:43:42,820 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:43:42,820 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:43:42,822 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:42,822 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:42,822 INFO L752 eck$LassoCheckResult]: Stem: 16375#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 16376#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 16650#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16638#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16639#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 16659#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16660#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15943#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15663#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15664#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16568#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16569#L731-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 16554#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16555#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16590#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 15715#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15716#L1006 assume !(0 == ~M_E~0); 15567#L1006-2 assume !(0 == ~T1_E~0); 15568#L1011-1 assume !(0 == ~T2_E~0); 16612#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16627#L1021-1 assume !(0 == ~T4_E~0); 15446#L1026-1 assume !(0 == ~T5_E~0); 15447#L1031-1 assume !(0 == ~T6_E~0); 16322#L1036-1 assume !(0 == ~T7_E~0); 16316#L1041-1 assume !(0 == ~T8_E~0); 16317#L1046-1 assume !(0 == ~T9_E~0); 15746#L1051-1 assume !(0 == ~T10_E~0); 15747#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 16449#L1061-1 assume !(0 == ~E_2~0); 15665#L1066-1 assume !(0 == ~E_3~0); 15666#L1071-1 assume !(0 == ~E_4~0); 16428#L1076-1 assume !(0 == ~E_5~0); 15575#L1081-1 assume !(0 == ~E_6~0); 15576#L1086-1 assume !(0 == ~E_7~0); 15919#L1091-1 assume !(0 == ~E_8~0); 16605#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 16606#L1101-1 assume !(0 == ~E_10~0); 15980#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15981#L484 assume !(1 == ~m_pc~0); 15624#L484-2 is_master_triggered_~__retres1~0#1 := 0; 15623#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16239#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16523#L1245 assume !(0 != activate_threads_~tmp~1#1); 16524#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16308#L503 assume 1 == ~t1_pc~0; 16309#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16327#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16441#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16094#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 15476#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15477#L522 assume !(1 == ~t2_pc~0); 16275#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15679#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15680#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16149#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 16570#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16635#L541 assume 1 == ~t3_pc~0; 16226#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16040#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15855#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15856#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 16282#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16283#L560 assume !(1 == ~t4_pc~0); 15558#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 15557#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16183#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15442#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 15443#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15729#L579 assume 1 == ~t5_pc~0; 15393#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15394#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15502#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16186#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 16626#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16647#L598 assume 1 == ~t6_pc~0; 15825#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15826#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16128#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16546#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 16357#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16299#L617 assume !(1 == ~t7_pc~0); 15796#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 15795#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16081#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16082#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16018#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16019#L636 assume 1 == ~t8_pc~0; 16180#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16181#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15982#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15983#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 16135#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16136#L655 assume !(1 == ~t9_pc~0); 16165#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 16166#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15775#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15776#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 16377#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16378#L674 assume 1 == ~t10_pc~0; 15551#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 15552#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16637#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16668#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 16123#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16124#L1119 assume !(1 == ~M_E~0); 15647#L1119-2 assume !(1 == ~T1_E~0); 15648#L1124-1 assume !(1 == ~T2_E~0); 15466#L1129-1 assume !(1 == ~T3_E~0); 15467#L1134-1 assume !(1 == ~T4_E~0); 15780#L1139-1 assume !(1 == ~T5_E~0); 15781#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16013#L1149-1 assume !(1 == ~T7_E~0); 15642#L1154-1 assume !(1 == ~T8_E~0); 15643#L1159-1 assume !(1 == ~T9_E~0); 15730#L1164-1 assume !(1 == ~T10_E~0); 16152#L1169-1 assume !(1 == ~E_1~0); 16050#L1174-1 assume !(1 == ~E_2~0); 15839#L1179-1 assume !(1 == ~E_3~0); 15719#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 15720#L1189-1 assume !(1 == ~E_5~0); 15774#L1194-1 assume !(1 == ~E_6~0); 15896#L1199-1 assume !(1 == ~E_7~0); 15847#L1204-1 assume !(1 == ~E_8~0); 15848#L1209-1 assume !(1 == ~E_9~0); 16371#L1214-1 assume !(1 == ~E_10~0); 16372#L1219-1 assume { :end_inline_reset_delta_events } true; 15430#L1520-2 [2022-07-22 02:43:42,822 INFO L754 eck$LassoCheckResult]: Loop: 15430#L1520-2 assume !false; 15431#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15531#L981 assume !false; 15726#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 16398#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 15416#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 16516#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 16566#L836 assume !(0 != eval_~tmp~0#1); 16011#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16012#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16004#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16005#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16475#L1011-3 assume !(0 == ~T2_E~0); 16476#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16515#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16198#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16199#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16443#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16444#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16504#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16505#L1051-3 assume !(0 == ~T10_E~0); 16445#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15741#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15742#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15745#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16616#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15528#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15529#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15581#L1091-3 assume !(0 == ~E_8~0); 15582#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 16591#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 16592#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16218#L484-33 assume 1 == ~m_pc~0; 16219#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 16138#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16139#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15436#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15437#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15905#L503-33 assume !(1 == ~t1_pc~0); 15906#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 16359#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16285#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15813#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15814#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16255#L522-33 assume 1 == ~t2_pc~0; 16256#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15569#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15570#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16364#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16273#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16274#L541-33 assume 1 == ~t3_pc~0; 15595#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15434#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15435#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16245#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16246#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16440#L560-33 assume 1 == ~t4_pc~0; 16145#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15506#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15507#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15765#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 16422#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15425#L579-33 assume 1 == ~t5_pc~0; 15426#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15672#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16631#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16300#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 16301#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16326#L598-33 assume !(1 == ~t6_pc~0); 16103#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 15929#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15930#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15770#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15771#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16580#L617-33 assume 1 == ~t7_pc~0; 16586#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15563#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16514#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16621#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16617#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15494#L636-33 assume !(1 == ~t8_pc~0); 15495#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 16414#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16415#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16640#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16405#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16406#L655-33 assume 1 == ~t9_pc~0; 16664#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15870#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15871#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16229#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 16493#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16049#L674-33 assume 1 == ~t10_pc~0; 15924#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 15925#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 15786#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15787#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16264#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16641#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16648#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16652#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16662#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15811#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15812#L1139-3 assume !(1 == ~T5_E~0); 16042#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16043#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16185#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16455#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16456#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 16623#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15927#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15928#L1179-3 assume !(1 == ~E_3~0); 16547#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15554#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15555#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15868#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15869#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16172#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 15448#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 15449#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 16363#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 15534#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 15885#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 15886#L1539 assume !(0 == start_simulation_~tmp~3#1); 15978#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 16154#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 15961#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 16093#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 15877#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15878#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16482#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 15979#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 15430#L1520-2 [2022-07-22 02:43:42,823 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:42,823 INFO L85 PathProgramCache]: Analyzing trace with hash 1042635949, now seen corresponding path program 1 times [2022-07-22 02:43:42,823 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:42,823 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [330425651] [2022-07-22 02:43:42,823 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:42,823 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:42,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:42,842 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:42,842 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:42,842 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [330425651] [2022-07-22 02:43:42,842 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [330425651] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:42,842 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:42,842 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:42,843 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1869911838] [2022-07-22 02:43:42,843 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:42,843 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:43:42,843 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:42,843 INFO L85 PathProgramCache]: Analyzing trace with hash -1410939798, now seen corresponding path program 2 times [2022-07-22 02:43:42,843 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:42,843 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [805923224] [2022-07-22 02:43:42,844 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:42,844 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:42,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:42,867 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:42,868 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:42,868 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [805923224] [2022-07-22 02:43:42,868 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [805923224] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:42,868 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:42,868 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:42,868 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2127701969] [2022-07-22 02:43:42,868 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:42,868 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:43:42,868 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:43:42,869 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:43:42,869 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:43:42,869 INFO L87 Difference]: Start difference. First operand 1278 states and 1896 transitions. cyclomatic complexity: 619 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:42,884 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:43:42,884 INFO L93 Difference]: Finished difference Result 1278 states and 1895 transitions. [2022-07-22 02:43:42,884 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:43:42,885 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1278 states and 1895 transitions. [2022-07-22 02:43:42,890 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2022-07-22 02:43:42,894 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1278 states to 1278 states and 1895 transitions. [2022-07-22 02:43:42,894 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1278 [2022-07-22 02:43:42,895 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1278 [2022-07-22 02:43:42,895 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1278 states and 1895 transitions. [2022-07-22 02:43:42,896 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:43:42,896 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1278 states and 1895 transitions. [2022-07-22 02:43:42,897 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1278 states and 1895 transitions. [2022-07-22 02:43:42,909 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1278 to 1278. [2022-07-22 02:43:42,911 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1278 states, 1278 states have (on average 1.4827856025039123) internal successors, (1895), 1277 states have internal predecessors, (1895), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:42,914 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1278 states to 1278 states and 1895 transitions. [2022-07-22 02:43:42,914 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1278 states and 1895 transitions. [2022-07-22 02:43:42,914 INFO L374 stractBuchiCegarLoop]: Abstraction has 1278 states and 1895 transitions. [2022-07-22 02:43:42,914 INFO L287 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-07-22 02:43:42,914 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1278 states and 1895 transitions. [2022-07-22 02:43:42,917 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2022-07-22 02:43:42,917 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:43:42,917 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:43:42,918 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:42,918 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:42,919 INFO L752 eck$LassoCheckResult]: Stem: 18937#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 18938#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 19213#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19201#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19202#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 19222#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19223#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18506#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18224#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18225#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19131#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19132#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19117#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19118#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 19153#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 18276#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18277#L1006 assume !(0 == ~M_E~0); 18127#L1006-2 assume !(0 == ~T1_E~0); 18128#L1011-1 assume !(0 == ~T2_E~0); 19175#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19190#L1021-1 assume !(0 == ~T4_E~0); 18007#L1026-1 assume !(0 == ~T5_E~0); 18008#L1031-1 assume !(0 == ~T6_E~0); 18883#L1036-1 assume !(0 == ~T7_E~0); 18879#L1041-1 assume !(0 == ~T8_E~0); 18880#L1046-1 assume !(0 == ~T9_E~0); 18309#L1051-1 assume !(0 == ~T10_E~0); 18310#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 19012#L1061-1 assume !(0 == ~E_2~0); 18228#L1066-1 assume !(0 == ~E_3~0); 18229#L1071-1 assume !(0 == ~E_4~0); 18991#L1076-1 assume !(0 == ~E_5~0); 18138#L1081-1 assume !(0 == ~E_6~0); 18139#L1086-1 assume !(0 == ~E_7~0); 18481#L1091-1 assume !(0 == ~E_8~0); 19167#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 19168#L1101-1 assume !(0 == ~E_10~0); 18543#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18544#L484 assume !(1 == ~m_pc~0); 18187#L484-2 is_master_triggered_~__retres1~0#1 := 0; 18186#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18802#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19086#L1245 assume !(0 != activate_threads_~tmp~1#1); 19087#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18871#L503 assume 1 == ~t1_pc~0; 18872#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18888#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19004#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18654#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 18037#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18038#L522 assume !(1 == ~t2_pc~0); 18838#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18241#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18242#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18712#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 19133#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19198#L541 assume 1 == ~t3_pc~0; 18787#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18603#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18418#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18419#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 18841#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18842#L560 assume !(1 == ~t4_pc~0); 18119#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 18118#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18746#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18005#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 18006#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18290#L579 assume 1 == ~t5_pc~0; 17956#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17957#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18065#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18749#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 19188#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19210#L598 assume 1 == ~t6_pc~0; 18386#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18387#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18688#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19109#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 18920#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18862#L617 assume !(1 == ~t7_pc~0); 18359#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 18358#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18644#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18645#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18580#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18581#L636 assume 1 == ~t8_pc~0; 18743#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18744#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18545#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18546#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 18696#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18697#L655 assume !(1 == ~t9_pc~0); 18724#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 18725#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18338#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18339#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 18939#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18940#L674 assume 1 == ~t10_pc~0; 18114#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 18115#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19200#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19231#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 18686#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18687#L1119 assume !(1 == ~M_E~0); 18210#L1119-2 assume !(1 == ~T1_E~0); 18211#L1124-1 assume !(1 == ~T2_E~0); 18029#L1129-1 assume !(1 == ~T3_E~0); 18030#L1134-1 assume !(1 == ~T4_E~0); 18340#L1139-1 assume !(1 == ~T5_E~0); 18341#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18576#L1149-1 assume !(1 == ~T7_E~0); 18205#L1154-1 assume !(1 == ~T8_E~0); 18206#L1159-1 assume !(1 == ~T9_E~0); 18293#L1164-1 assume !(1 == ~T10_E~0); 18715#L1169-1 assume !(1 == ~E_1~0); 18613#L1174-1 assume !(1 == ~E_2~0); 18400#L1179-1 assume !(1 == ~E_3~0); 18282#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 18283#L1189-1 assume !(1 == ~E_5~0); 18335#L1194-1 assume !(1 == ~E_6~0); 18459#L1199-1 assume !(1 == ~E_7~0); 18410#L1204-1 assume !(1 == ~E_8~0); 18411#L1209-1 assume !(1 == ~E_9~0); 18934#L1214-1 assume !(1 == ~E_10~0); 18935#L1219-1 assume { :end_inline_reset_delta_events } true; 17993#L1520-2 [2022-07-22 02:43:42,919 INFO L754 eck$LassoCheckResult]: Loop: 17993#L1520-2 assume !false; 17994#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18094#L981 assume !false; 18286#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 18961#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 17979#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 19079#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 19129#L836 assume !(0 != eval_~tmp~0#1); 18571#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18572#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18567#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 18568#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19038#L1011-3 assume !(0 == ~T2_E~0); 19039#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19078#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18759#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18760#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19006#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19007#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19067#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19068#L1051-3 assume !(0 == ~T10_E~0); 19008#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18304#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18305#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18308#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19179#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18091#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 18092#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 18144#L1091-3 assume !(0 == ~E_8~0); 18145#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19154#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 19155#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18781#L484-33 assume 1 == ~m_pc~0; 18782#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 18701#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18702#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17999#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18000#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18468#L503-33 assume !(1 == ~t1_pc~0); 18469#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 18922#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18849#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18378#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18379#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18818#L522-33 assume 1 == ~t2_pc~0; 18819#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18132#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18133#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18927#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18836#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18837#L541-33 assume 1 == ~t3_pc~0; 18158#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17997#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17998#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18808#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18809#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19003#L560-33 assume 1 == ~t4_pc~0; 18708#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18069#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18070#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18328#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 18985#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17988#L579-33 assume 1 == ~t5_pc~0; 17989#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 18235#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19194#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18863#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18864#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18892#L598-33 assume !(1 == ~t6_pc~0); 18666#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 18492#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18493#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18333#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 18334#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19143#L617-33 assume 1 == ~t7_pc~0; 19149#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18126#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19077#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19184#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19180#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18057#L636-33 assume !(1 == ~t8_pc~0); 18058#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 18977#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18978#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19203#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18968#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18969#L655-33 assume 1 == ~t9_pc~0; 19227#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18435#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18436#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18792#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 19056#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18612#L674-33 assume 1 == ~t10_pc~0; 18487#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 18488#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18349#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18350#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 18827#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19204#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19211#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19215#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19225#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18374#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18375#L1139-3 assume !(1 == ~T5_E~0); 18605#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18606#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18748#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19018#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19019#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19186#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18490#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18491#L1179-3 assume !(1 == ~E_3~0); 19110#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18120#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18121#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18431#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18432#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 18735#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 18011#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 18012#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 18926#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 18097#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 18448#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 18449#L1539 assume !(0 == start_simulation_~tmp~3#1); 18541#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 18717#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 18524#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 18657#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 18440#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18441#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19045#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 18542#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 17993#L1520-2 [2022-07-22 02:43:42,919 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:42,919 INFO L85 PathProgramCache]: Analyzing trace with hash -886296277, now seen corresponding path program 1 times [2022-07-22 02:43:42,919 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:42,919 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [829223592] [2022-07-22 02:43:42,920 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:42,920 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:42,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:42,957 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:42,958 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:42,958 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [829223592] [2022-07-22 02:43:42,958 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [829223592] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:42,958 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:42,958 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:42,958 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [367378523] [2022-07-22 02:43:42,958 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:42,958 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:43:42,959 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:42,959 INFO L85 PathProgramCache]: Analyzing trace with hash -1410939798, now seen corresponding path program 3 times [2022-07-22 02:43:42,959 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:42,959 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1412359651] [2022-07-22 02:43:42,959 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:42,959 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:42,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:42,984 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:42,985 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:42,985 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1412359651] [2022-07-22 02:43:42,985 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1412359651] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:42,985 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:42,985 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:42,985 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [473341137] [2022-07-22 02:43:42,985 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:42,985 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:43:42,985 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:43:42,986 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:43:42,986 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:43:42,986 INFO L87 Difference]: Start difference. First operand 1278 states and 1895 transitions. cyclomatic complexity: 618 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:43,002 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:43:43,002 INFO L93 Difference]: Finished difference Result 1278 states and 1894 transitions. [2022-07-22 02:43:43,002 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:43:43,003 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1278 states and 1894 transitions. [2022-07-22 02:43:43,007 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2022-07-22 02:43:43,011 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1278 states to 1278 states and 1894 transitions. [2022-07-22 02:43:43,011 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1278 [2022-07-22 02:43:43,012 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1278 [2022-07-22 02:43:43,012 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1278 states and 1894 transitions. [2022-07-22 02:43:43,013 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:43:43,013 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1278 states and 1894 transitions. [2022-07-22 02:43:43,015 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1278 states and 1894 transitions. [2022-07-22 02:43:43,024 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1278 to 1278. [2022-07-22 02:43:43,026 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1278 states, 1278 states have (on average 1.482003129890454) internal successors, (1894), 1277 states have internal predecessors, (1894), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:43,029 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1278 states to 1278 states and 1894 transitions. [2022-07-22 02:43:43,029 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1278 states and 1894 transitions. [2022-07-22 02:43:43,029 INFO L374 stractBuchiCegarLoop]: Abstraction has 1278 states and 1894 transitions. [2022-07-22 02:43:43,029 INFO L287 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-07-22 02:43:43,029 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1278 states and 1894 transitions. [2022-07-22 02:43:43,032 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2022-07-22 02:43:43,032 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:43:43,032 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:43:43,033 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:43,033 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:43,034 INFO L752 eck$LassoCheckResult]: Stem: 21500#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 21501#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 21776#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21764#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21765#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 21785#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21786#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21069#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20787#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20788#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 21694#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 21695#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 21680#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 21681#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21716#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 20839#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20840#L1006 assume !(0 == ~M_E~0); 20690#L1006-2 assume !(0 == ~T1_E~0); 20691#L1011-1 assume !(0 == ~T2_E~0); 21738#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21753#L1021-1 assume !(0 == ~T4_E~0); 20570#L1026-1 assume !(0 == ~T5_E~0); 20571#L1031-1 assume !(0 == ~T6_E~0); 21446#L1036-1 assume !(0 == ~T7_E~0); 21442#L1041-1 assume !(0 == ~T8_E~0); 21443#L1046-1 assume !(0 == ~T9_E~0); 20872#L1051-1 assume !(0 == ~T10_E~0); 20873#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 21575#L1061-1 assume !(0 == ~E_2~0); 20791#L1066-1 assume !(0 == ~E_3~0); 20792#L1071-1 assume !(0 == ~E_4~0); 21554#L1076-1 assume !(0 == ~E_5~0); 20701#L1081-1 assume !(0 == ~E_6~0); 20702#L1086-1 assume !(0 == ~E_7~0); 21044#L1091-1 assume !(0 == ~E_8~0); 21730#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 21731#L1101-1 assume !(0 == ~E_10~0); 21106#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21107#L484 assume !(1 == ~m_pc~0); 20750#L484-2 is_master_triggered_~__retres1~0#1 := 0; 20749#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21365#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 21649#L1245 assume !(0 != activate_threads_~tmp~1#1); 21650#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21434#L503 assume 1 == ~t1_pc~0; 21435#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21451#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21567#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 21217#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 20600#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20601#L522 assume !(1 == ~t2_pc~0); 21401#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 20804#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20805#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21275#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 21696#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21761#L541 assume 1 == ~t3_pc~0; 21350#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21166#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20981#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20982#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 21404#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21405#L560 assume !(1 == ~t4_pc~0); 20682#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 20681#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21309#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20568#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 20569#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20855#L579 assume 1 == ~t5_pc~0; 20519#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20520#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20628#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21312#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 21751#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21773#L598 assume 1 == ~t6_pc~0; 20949#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20950#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21251#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21672#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 21483#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21425#L617 assume !(1 == ~t7_pc~0); 20922#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 20921#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21207#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21208#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21143#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21144#L636 assume 1 == ~t8_pc~0; 21306#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21307#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21108#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21109#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 21259#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21260#L655 assume !(1 == ~t9_pc~0); 21287#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 21288#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20901#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20902#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 21502#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21503#L674 assume 1 == ~t10_pc~0; 20677#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 20678#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21763#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21794#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 21249#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21250#L1119 assume !(1 == ~M_E~0); 20773#L1119-2 assume !(1 == ~T1_E~0); 20774#L1124-1 assume !(1 == ~T2_E~0); 20592#L1129-1 assume !(1 == ~T3_E~0); 20593#L1134-1 assume !(1 == ~T4_E~0); 20904#L1139-1 assume !(1 == ~T5_E~0); 20905#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21139#L1149-1 assume !(1 == ~T7_E~0); 20768#L1154-1 assume !(1 == ~T8_E~0); 20769#L1159-1 assume !(1 == ~T9_E~0); 20856#L1164-1 assume !(1 == ~T10_E~0); 21278#L1169-1 assume !(1 == ~E_1~0); 21176#L1174-1 assume !(1 == ~E_2~0); 20963#L1179-1 assume !(1 == ~E_3~0); 20845#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 20846#L1189-1 assume !(1 == ~E_5~0); 20898#L1194-1 assume !(1 == ~E_6~0); 21022#L1199-1 assume !(1 == ~E_7~0); 20973#L1204-1 assume !(1 == ~E_8~0); 20974#L1209-1 assume !(1 == ~E_9~0); 21497#L1214-1 assume !(1 == ~E_10~0); 21498#L1219-1 assume { :end_inline_reset_delta_events } true; 20556#L1520-2 [2022-07-22 02:43:43,034 INFO L754 eck$LassoCheckResult]: Loop: 20556#L1520-2 assume !false; 20557#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20657#L981 assume !false; 20849#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 21524#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 20542#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 21642#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 21692#L836 assume !(0 != eval_~tmp~0#1); 21134#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21135#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21130#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21131#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21601#L1011-3 assume !(0 == ~T2_E~0); 21602#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21641#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21322#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21323#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 21569#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 21570#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21630#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21631#L1051-3 assume !(0 == ~T10_E~0); 21571#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20867#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20868#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20871#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 21742#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20654#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20655#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20707#L1091-3 assume !(0 == ~E_8~0); 20708#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 21717#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 21718#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21344#L484-33 assume 1 == ~m_pc~0; 21345#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 21264#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21265#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20562#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20563#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21031#L503-33 assume !(1 == ~t1_pc~0); 21032#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 21485#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21412#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20941#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20942#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21381#L522-33 assume 1 == ~t2_pc~0; 21382#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20695#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20696#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21490#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21399#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21400#L541-33 assume 1 == ~t3_pc~0; 20721#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20560#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20561#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 21371#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21372#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21566#L560-33 assume 1 == ~t4_pc~0; 21271#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20632#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20633#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20891#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 21548#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20551#L579-33 assume 1 == ~t5_pc~0; 20552#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20798#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21757#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21426#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21427#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21455#L598-33 assume !(1 == ~t6_pc~0); 21229#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 21055#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21056#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20896#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20897#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21706#L617-33 assume 1 == ~t7_pc~0; 21712#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20689#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21640#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21747#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21743#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20620#L636-33 assume !(1 == ~t8_pc~0); 20621#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 21540#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21541#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21766#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21531#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21532#L655-33 assume 1 == ~t9_pc~0; 21790#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20998#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20999#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21355#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21619#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21175#L674-33 assume 1 == ~t10_pc~0; 21050#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21051#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20912#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20913#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 21390#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21767#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21774#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21778#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21788#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20937#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20938#L1139-3 assume !(1 == ~T5_E~0); 21168#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21169#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 21311#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 21581#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21582#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 21749#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21053#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21054#L1179-3 assume !(1 == ~E_3~0); 21673#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20683#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20684#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 20994#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 20995#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21298#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 20574#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20575#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 21489#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 20660#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 21011#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 21012#L1539 assume !(0 == start_simulation_~tmp~3#1); 21104#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 21280#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 21087#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 21220#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 21003#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21004#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21608#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 21105#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 20556#L1520-2 [2022-07-22 02:43:43,034 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:43,034 INFO L85 PathProgramCache]: Analyzing trace with hash 1406784749, now seen corresponding path program 1 times [2022-07-22 02:43:43,034 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:43,034 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [656131806] [2022-07-22 02:43:43,035 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:43,035 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:43,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:43,052 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:43,052 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:43,053 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [656131806] [2022-07-22 02:43:43,053 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [656131806] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:43,053 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:43,053 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:43,053 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [449996393] [2022-07-22 02:43:43,053 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:43,053 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:43:43,053 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:43,054 INFO L85 PathProgramCache]: Analyzing trace with hash -1410939798, now seen corresponding path program 4 times [2022-07-22 02:43:43,054 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:43,054 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [200158933] [2022-07-22 02:43:43,054 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:43,054 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:43,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:43,078 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:43,078 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:43,078 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [200158933] [2022-07-22 02:43:43,078 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [200158933] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:43,078 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:43,078 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:43,078 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1527495232] [2022-07-22 02:43:43,079 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:43,079 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:43:43,079 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:43:43,079 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:43:43,079 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:43:43,079 INFO L87 Difference]: Start difference. First operand 1278 states and 1894 transitions. cyclomatic complexity: 617 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:43,095 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:43:43,096 INFO L93 Difference]: Finished difference Result 1278 states and 1893 transitions. [2022-07-22 02:43:43,096 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:43:43,096 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1278 states and 1893 transitions. [2022-07-22 02:43:43,101 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2022-07-22 02:43:43,105 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1278 states to 1278 states and 1893 transitions. [2022-07-22 02:43:43,105 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1278 [2022-07-22 02:43:43,106 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1278 [2022-07-22 02:43:43,106 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1278 states and 1893 transitions. [2022-07-22 02:43:43,107 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:43:43,107 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1278 states and 1893 transitions. [2022-07-22 02:43:43,108 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1278 states and 1893 transitions. [2022-07-22 02:43:43,118 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1278 to 1278. [2022-07-22 02:43:43,120 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1278 states, 1278 states have (on average 1.4812206572769953) internal successors, (1893), 1277 states have internal predecessors, (1893), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:43,123 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1278 states to 1278 states and 1893 transitions. [2022-07-22 02:43:43,123 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1278 states and 1893 transitions. [2022-07-22 02:43:43,123 INFO L374 stractBuchiCegarLoop]: Abstraction has 1278 states and 1893 transitions. [2022-07-22 02:43:43,123 INFO L287 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-07-22 02:43:43,123 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1278 states and 1893 transitions. [2022-07-22 02:43:43,126 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2022-07-22 02:43:43,126 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:43:43,126 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:43:43,127 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:43,127 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:43,128 INFO L752 eck$LassoCheckResult]: Stem: 24064#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 24065#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 24339#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24327#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24328#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 24348#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24349#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23632#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23350#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 23351#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 24257#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 24258#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 24243#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 24244#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24279#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 23404#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23405#L1006 assume !(0 == ~M_E~0); 23253#L1006-2 assume !(0 == ~T1_E~0); 23254#L1011-1 assume !(0 == ~T2_E~0); 24301#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24316#L1021-1 assume !(0 == ~T4_E~0); 23135#L1026-1 assume !(0 == ~T5_E~0); 23136#L1031-1 assume !(0 == ~T6_E~0); 24009#L1036-1 assume !(0 == ~T7_E~0); 24005#L1041-1 assume !(0 == ~T8_E~0); 24006#L1046-1 assume !(0 == ~T9_E~0); 23435#L1051-1 assume !(0 == ~T10_E~0); 23436#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 24138#L1061-1 assume !(0 == ~E_2~0); 23354#L1066-1 assume !(0 == ~E_3~0); 23355#L1071-1 assume !(0 == ~E_4~0); 24117#L1076-1 assume !(0 == ~E_5~0); 23264#L1081-1 assume !(0 == ~E_6~0); 23265#L1086-1 assume !(0 == ~E_7~0); 23608#L1091-1 assume !(0 == ~E_8~0); 24294#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 24295#L1101-1 assume !(0 == ~E_10~0); 23669#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23670#L484 assume !(1 == ~m_pc~0); 23313#L484-2 is_master_triggered_~__retres1~0#1 := 0; 23312#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23928#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 24212#L1245 assume !(0 != activate_threads_~tmp~1#1); 24213#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23997#L503 assume 1 == ~t1_pc~0; 23998#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24015#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24130#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 23783#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 23163#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23164#L522 assume !(1 == ~t2_pc~0); 23964#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 23367#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23368#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 23838#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 24259#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24324#L541 assume 1 == ~t3_pc~0; 23913#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23729#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23544#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23545#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 23967#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23968#L560 assume !(1 == ~t4_pc~0); 23247#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 23246#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23872#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23131#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 23132#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23418#L579 assume 1 == ~t5_pc~0; 23082#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23083#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23191#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23875#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 24315#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24336#L598 assume 1 == ~t6_pc~0; 23512#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23513#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23815#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24235#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 24046#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23988#L617 assume !(1 == ~t7_pc~0); 23485#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 23484#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23770#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23771#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 23706#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23707#L636 assume 1 == ~t8_pc~0; 23869#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 23870#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23671#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23672#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 23824#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 23825#L655 assume !(1 == ~t9_pc~0); 23852#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 23853#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23464#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23465#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 24066#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24067#L674 assume 1 == ~t10_pc~0; 23240#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 23241#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24326#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24357#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 23812#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23813#L1119 assume !(1 == ~M_E~0); 23336#L1119-2 assume !(1 == ~T1_E~0); 23337#L1124-1 assume !(1 == ~T2_E~0); 23155#L1129-1 assume !(1 == ~T3_E~0); 23156#L1134-1 assume !(1 == ~T4_E~0); 23469#L1139-1 assume !(1 == ~T5_E~0); 23470#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23702#L1149-1 assume !(1 == ~T7_E~0); 23331#L1154-1 assume !(1 == ~T8_E~0); 23332#L1159-1 assume !(1 == ~T9_E~0); 23419#L1164-1 assume !(1 == ~T10_E~0); 23841#L1169-1 assume !(1 == ~E_1~0); 23739#L1174-1 assume !(1 == ~E_2~0); 23526#L1179-1 assume !(1 == ~E_3~0); 23408#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 23409#L1189-1 assume !(1 == ~E_5~0); 23462#L1194-1 assume !(1 == ~E_6~0); 23585#L1199-1 assume !(1 == ~E_7~0); 23536#L1204-1 assume !(1 == ~E_8~0); 23537#L1209-1 assume !(1 == ~E_9~0); 24060#L1214-1 assume !(1 == ~E_10~0); 24061#L1219-1 assume { :end_inline_reset_delta_events } true; 23119#L1520-2 [2022-07-22 02:43:43,128 INFO L754 eck$LassoCheckResult]: Loop: 23119#L1520-2 assume !false; 23120#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 23223#L981 assume !false; 23415#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 24087#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 23105#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 24205#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 24255#L836 assume !(0 != eval_~tmp~0#1); 23697#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 23698#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 23693#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 23694#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 24164#L1011-3 assume !(0 == ~T2_E~0); 24165#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24204#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 23887#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 23888#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24132#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24133#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24195#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 24196#L1051-3 assume !(0 == ~T10_E~0); 24134#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23432#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23433#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23434#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 24305#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 23217#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 23218#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 23272#L1091-3 assume !(0 == ~E_8~0); 23273#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 24280#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 24281#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23907#L484-33 assume 1 == ~m_pc~0; 23908#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 23827#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23828#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 23125#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 23126#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23597#L503-33 assume !(1 == ~t1_pc~0); 23598#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 24048#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23977#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 23504#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23505#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23944#L522-33 assume 1 == ~t2_pc~0; 23945#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 23260#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23261#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24054#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23962#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23963#L541-33 assume 1 == ~t3_pc~0; 23284#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23123#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23124#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23934#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23935#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24129#L560-33 assume 1 == ~t4_pc~0; 23834#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 23195#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23196#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23452#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 24111#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23111#L579-33 assume 1 == ~t5_pc~0; 23112#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23360#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24320#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23989#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 23990#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24014#L598-33 assume 1 == ~t6_pc~0; 24321#L599-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23618#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23619#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23459#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23460#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24269#L617-33 assume 1 == ~t7_pc~0; 24275#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23252#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24203#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24310#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 24306#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23183#L636-33 assume !(1 == ~t8_pc~0); 23184#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 24103#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24104#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24329#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24092#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24093#L655-33 assume 1 == ~t9_pc~0; 24353#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 23559#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23560#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23918#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24182#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23738#L674-33 assume 1 == ~t10_pc~0; 23613#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 23614#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 23475#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23476#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 23953#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24330#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 24337#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24340#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24351#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23497#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23498#L1139-3 assume !(1 == ~T5_E~0); 23731#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23732#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23874#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 24144#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 24145#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 24311#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 23616#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23617#L1179-3 assume !(1 == ~E_3~0); 24236#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23243#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 23244#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 23557#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 23558#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 23861#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 23137#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 23138#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 24051#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 23220#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 23574#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 23575#L1539 assume !(0 == start_simulation_~tmp~3#1); 23667#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 23843#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 23650#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 23782#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 23566#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23567#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24171#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 23668#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 23119#L1520-2 [2022-07-22 02:43:43,128 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:43,128 INFO L85 PathProgramCache]: Analyzing trace with hash 935428399, now seen corresponding path program 1 times [2022-07-22 02:43:43,128 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:43,128 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1460771785] [2022-07-22 02:43:43,129 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:43,129 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:43,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:43,160 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:43,161 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:43,161 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1460771785] [2022-07-22 02:43:43,161 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1460771785] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:43,161 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:43,161 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:43,161 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1575625459] [2022-07-22 02:43:43,161 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:43,161 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:43:43,161 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:43,162 INFO L85 PathProgramCache]: Analyzing trace with hash -2115858485, now seen corresponding path program 2 times [2022-07-22 02:43:43,162 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:43,162 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1439136684] [2022-07-22 02:43:43,162 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:43,162 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:43,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:43,203 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:43,203 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:43,203 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1439136684] [2022-07-22 02:43:43,203 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1439136684] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:43,203 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:43,203 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:43,203 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1433456932] [2022-07-22 02:43:43,203 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:43,204 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:43:43,204 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:43:43,204 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-22 02:43:43,204 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-22 02:43:43,204 INFO L87 Difference]: Start difference. First operand 1278 states and 1893 transitions. cyclomatic complexity: 616 Second operand has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:43,315 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:43:43,316 INFO L93 Difference]: Finished difference Result 2438 states and 3604 transitions. [2022-07-22 02:43:43,316 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-22 02:43:43,316 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2438 states and 3604 transitions. [2022-07-22 02:43:43,326 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2282 [2022-07-22 02:43:43,336 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2438 states to 2438 states and 3604 transitions. [2022-07-22 02:43:43,337 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2438 [2022-07-22 02:43:43,338 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2438 [2022-07-22 02:43:43,338 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2438 states and 3604 transitions. [2022-07-22 02:43:43,341 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:43:43,341 INFO L369 hiAutomatonCegarLoop]: Abstraction has 2438 states and 3604 transitions. [2022-07-22 02:43:43,343 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2438 states and 3604 transitions. [2022-07-22 02:43:43,375 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2438 to 2438. [2022-07-22 02:43:43,379 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2438 states, 2438 states have (on average 1.4782608695652173) internal successors, (3604), 2437 states have internal predecessors, (3604), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:43,386 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2438 states to 2438 states and 3604 transitions. [2022-07-22 02:43:43,386 INFO L392 hiAutomatonCegarLoop]: Abstraction has 2438 states and 3604 transitions. [2022-07-22 02:43:43,386 INFO L374 stractBuchiCegarLoop]: Abstraction has 2438 states and 3604 transitions. [2022-07-22 02:43:43,386 INFO L287 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-07-22 02:43:43,386 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2438 states and 3604 transitions. [2022-07-22 02:43:43,393 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2282 [2022-07-22 02:43:43,393 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:43:43,393 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:43:43,394 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:43,394 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:43,395 INFO L752 eck$LassoCheckResult]: Stem: 27800#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 27801#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 28097#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28079#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28080#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 28113#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28114#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27362#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27079#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 27080#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 28001#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 28002#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 27985#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 27986#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 28023#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 27132#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27133#L1006 assume !(0 == ~M_E~0); 26983#L1006-2 assume !(0 == ~T1_E~0); 26984#L1011-1 assume !(0 == ~T2_E~0); 28048#L1016-1 assume !(0 == ~T3_E~0); 28066#L1021-1 assume !(0 == ~T4_E~0); 26861#L1026-1 assume !(0 == ~T5_E~0); 26862#L1031-1 assume !(0 == ~T6_E~0); 27746#L1036-1 assume !(0 == ~T7_E~0); 27740#L1041-1 assume !(0 == ~T8_E~0); 27741#L1046-1 assume !(0 == ~T9_E~0); 27163#L1051-1 assume !(0 == ~T10_E~0); 27164#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 27876#L1061-1 assume !(0 == ~E_2~0); 27081#L1066-1 assume !(0 == ~E_3~0); 27082#L1071-1 assume !(0 == ~E_4~0); 27855#L1076-1 assume !(0 == ~E_5~0); 26991#L1081-1 assume !(0 == ~E_6~0); 26992#L1086-1 assume !(0 == ~E_7~0); 27338#L1091-1 assume !(0 == ~E_8~0); 28038#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 28039#L1101-1 assume !(0 == ~E_10~0); 27400#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27401#L484 assume !(1 == ~m_pc~0); 27040#L484-2 is_master_triggered_~__retres1~0#1 := 0; 27039#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27663#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 27952#L1245 assume !(0 != activate_threads_~tmp~1#1); 27953#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27732#L503 assume 1 == ~t1_pc~0; 27733#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27753#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27868#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27518#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 26891#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26892#L522 assume !(1 == ~t2_pc~0); 27699#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 27095#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27096#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 27573#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 28003#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28075#L541 assume 1 == ~t3_pc~0; 27650#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27460#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27273#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27274#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 27706#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27707#L560 assume !(1 == ~t4_pc~0); 26974#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 26973#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27607#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26857#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 26858#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27146#L579 assume 1 == ~t5_pc~0; 26808#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26809#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26917#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27610#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 28065#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28092#L598 assume 1 == ~t6_pc~0; 27243#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 27244#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27552#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27977#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 27782#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27723#L617 assume !(1 == ~t7_pc~0); 27213#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 27212#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27505#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27506#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 27438#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27439#L636 assume 1 == ~t8_pc~0; 27604#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 27605#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27402#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27403#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 27559#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27560#L655 assume !(1 == ~t9_pc~0); 27589#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 27590#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27192#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27193#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 27802#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 27803#L674 assume 1 == ~t10_pc~0; 26967#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 26968#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28078#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 28128#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 27547#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27548#L1119 assume !(1 == ~M_E~0); 27063#L1119-2 assume !(1 == ~T1_E~0); 27064#L1124-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26881#L1129-1 assume !(1 == ~T3_E~0); 26882#L1134-1 assume !(1 == ~T4_E~0); 27197#L1139-1 assume !(1 == ~T5_E~0); 27198#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27436#L1149-1 assume !(1 == ~T7_E~0); 27058#L1154-1 assume !(1 == ~T8_E~0); 27059#L1159-1 assume !(1 == ~T9_E~0); 27147#L1164-1 assume !(1 == ~T10_E~0); 28334#L1169-1 assume !(1 == ~E_1~0); 28332#L1174-1 assume !(1 == ~E_2~0); 28330#L1179-1 assume !(1 == ~E_3~0); 28194#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 28182#L1189-1 assume !(1 == ~E_5~0); 28180#L1194-1 assume !(1 == ~E_6~0); 28178#L1199-1 assume !(1 == ~E_7~0); 28176#L1204-1 assume !(1 == ~E_8~0); 28174#L1209-1 assume !(1 == ~E_9~0); 28172#L1214-1 assume !(1 == ~E_10~0); 28167#L1219-1 assume { :end_inline_reset_delta_events } true; 28161#L1520-2 [2022-07-22 02:43:43,395 INFO L754 eck$LassoCheckResult]: Loop: 28161#L1520-2 assume !false; 28157#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28156#L981 assume !false; 28155#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 28146#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 28143#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 28142#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 28141#L836 assume !(0 != eval_~tmp~0#1); 28140#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28139#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28138#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28137#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28136#L1011-3 assume !(0 == ~T2_E~0); 28045#L1016-3 assume !(0 == ~T3_E~0); 27943#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 27620#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 27621#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27870#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27871#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 27932#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 27933#L1051-3 assume !(0 == ~T10_E~0); 27872#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27158#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 27159#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27162#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 28052#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26944#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 26945#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 26997#L1091-3 assume !(0 == ~E_8~0); 26998#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 28024#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 28025#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27642#L484-33 assume 1 == ~m_pc~0; 27643#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 27562#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27563#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 26851#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 26852#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27324#L503-33 assume !(1 == ~t1_pc~0); 27325#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 27784#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27710#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27233#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 27234#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27679#L522-33 assume 1 == ~t2_pc~0; 27680#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 26985#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26986#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 27789#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 27697#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27698#L541-33 assume 1 == ~t3_pc~0; 27011#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26849#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26850#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27669#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 27670#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27867#L560-33 assume 1 == ~t4_pc~0; 27569#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 26921#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26922#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27182#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 27848#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26840#L579-33 assume 1 == ~t5_pc~0; 26841#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27088#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28071#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27724#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 27725#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 27752#L598-33 assume !(1 == ~t6_pc~0); 27527#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 27348#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27349#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27187#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 27188#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28013#L617-33 assume 1 == ~t7_pc~0; 28388#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28387#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28386#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28384#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 28382#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28380#L636-33 assume !(1 == ~t8_pc~0); 28340#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 28338#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28336#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28081#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 27830#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27831#L655-33 assume 1 == ~t9_pc~0; 28123#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27290#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27291#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27653#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 27920#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 27469#L674-33 assume 1 == ~t10_pc~0; 27470#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 28312#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28310#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 28308#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28306#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28304#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 28301#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28299#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 28133#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28117#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28295#L1139-3 assume !(1 == ~T5_E~0); 28293#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 28290#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 28288#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 28286#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28284#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 28282#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28280#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 28277#L1179-3 assume !(1 == ~E_3~0); 28275#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 28273#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 28271#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 28269#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28267#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28265#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 28263#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 28262#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 28237#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 28235#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 28233#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 28232#L1539 assume !(0 == start_simulation_~tmp~3#1); 28227#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 28187#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 28181#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 28179#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 28177#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 28175#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28173#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 28168#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 28161#L1520-2 [2022-07-22 02:43:43,396 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:43,396 INFO L85 PathProgramCache]: Analyzing trace with hash -388783629, now seen corresponding path program 1 times [2022-07-22 02:43:43,396 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:43,396 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1624184706] [2022-07-22 02:43:43,396 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:43,396 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:43,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:43,443 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:43,443 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:43,443 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1624184706] [2022-07-22 02:43:43,443 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1624184706] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:43,443 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:43,443 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:43,444 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [166696512] [2022-07-22 02:43:43,444 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:43,444 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:43:43,444 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:43,444 INFO L85 PathProgramCache]: Analyzing trace with hash 1601855212, now seen corresponding path program 1 times [2022-07-22 02:43:43,445 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:43,445 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1106661716] [2022-07-22 02:43:43,445 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:43,445 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:43,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:43,472 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:43,473 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:43,473 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1106661716] [2022-07-22 02:43:43,473 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1106661716] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:43,473 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:43,473 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:43,473 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1858755468] [2022-07-22 02:43:43,474 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:43,474 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:43:43,474 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:43:43,474 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-22 02:43:43,475 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-22 02:43:43,475 INFO L87 Difference]: Start difference. First operand 2438 states and 3604 transitions. cyclomatic complexity: 1168 Second operand has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:43,606 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:43:43,607 INFO L93 Difference]: Finished difference Result 4592 states and 6785 transitions. [2022-07-22 02:43:43,607 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-22 02:43:43,607 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4592 states and 6785 transitions. [2022-07-22 02:43:43,624 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4404 [2022-07-22 02:43:43,645 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4592 states to 4592 states and 6785 transitions. [2022-07-22 02:43:43,646 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4592 [2022-07-22 02:43:43,648 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4592 [2022-07-22 02:43:43,649 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4592 states and 6785 transitions. [2022-07-22 02:43:43,653 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:43:43,653 INFO L369 hiAutomatonCegarLoop]: Abstraction has 4592 states and 6785 transitions. [2022-07-22 02:43:43,656 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4592 states and 6785 transitions. [2022-07-22 02:43:43,703 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4592 to 4588. [2022-07-22 02:43:43,710 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4588 states, 4588 states have (on average 1.4779860505666957) internal successors, (6781), 4587 states have internal predecessors, (6781), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:43,720 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4588 states to 4588 states and 6781 transitions. [2022-07-22 02:43:43,721 INFO L392 hiAutomatonCegarLoop]: Abstraction has 4588 states and 6781 transitions. [2022-07-22 02:43:43,721 INFO L374 stractBuchiCegarLoop]: Abstraction has 4588 states and 6781 transitions. [2022-07-22 02:43:43,721 INFO L287 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-07-22 02:43:43,721 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4588 states and 6781 transitions. [2022-07-22 02:43:43,738 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4404 [2022-07-22 02:43:43,738 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:43:43,738 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:43:43,739 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:43,740 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:43,740 INFO L752 eck$LassoCheckResult]: Stem: 34840#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 34841#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 35129#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 35117#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 35118#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 35138#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 35139#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34402#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34118#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34119#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 35040#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 35041#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35024#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 35025#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 35064#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 34174#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 34175#L1006 assume !(0 == ~M_E~0); 34020#L1006-2 assume !(0 == ~T1_E~0); 34021#L1011-1 assume !(0 == ~T2_E~0); 35089#L1016-1 assume !(0 == ~T3_E~0); 35104#L1021-1 assume !(0 == ~T4_E~0); 33901#L1026-1 assume !(0 == ~T5_E~0); 33902#L1031-1 assume !(0 == ~T6_E~0); 34785#L1036-1 assume !(0 == ~T7_E~0); 34781#L1041-1 assume !(0 == ~T8_E~0); 34782#L1046-1 assume !(0 == ~T9_E~0); 34205#L1051-1 assume !(0 == ~T10_E~0); 34206#L1056-1 assume !(0 == ~E_1~0); 34916#L1061-1 assume !(0 == ~E_2~0); 34122#L1066-1 assume !(0 == ~E_3~0); 34123#L1071-1 assume !(0 == ~E_4~0); 34895#L1076-1 assume !(0 == ~E_5~0); 34031#L1081-1 assume !(0 == ~E_6~0); 34032#L1086-1 assume !(0 == ~E_7~0); 34377#L1091-1 assume !(0 == ~E_8~0); 35080#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 35081#L1101-1 assume !(0 == ~E_10~0); 34439#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34440#L484 assume !(1 == ~m_pc~0); 34080#L484-2 is_master_triggered_~__retres1~0#1 := 0; 34079#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34703#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 34993#L1245 assume !(0 != activate_threads_~tmp~1#1); 34994#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34773#L503 assume 1 == ~t1_pc~0; 34774#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 34790#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34908#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 34554#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 33929#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33930#L522 assume !(1 == ~t2_pc~0); 34739#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 34135#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34136#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 34611#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 35042#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35114#L541 assume 1 == ~t3_pc~0; 34688#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34499#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34314#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 34315#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 34742#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34743#L560 assume !(1 == ~t4_pc~0); 34014#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 34013#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34646#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33897#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 33898#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34188#L579 assume 1 == ~t5_pc~0; 33848#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33849#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33957#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34649#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 35102#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35126#L598 assume 1 == ~t6_pc~0; 34282#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 34283#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34588#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35016#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 34823#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 34764#L617 assume !(1 == ~t7_pc~0); 34255#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 34254#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34542#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34543#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 34476#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 34477#L636 assume 1 == ~t8_pc~0; 34643#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 34644#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34441#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34442#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 34595#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 34596#L655 assume !(1 == ~t9_pc~0); 34626#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 34627#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34234#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34235#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 34842#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 34843#L674 assume 1 == ~t10_pc~0; 34007#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 34008#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35116#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 35150#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 34585#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34586#L1119 assume !(1 == ~M_E~0); 34103#L1119-2 assume !(1 == ~T1_E~0); 34104#L1124-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33921#L1129-1 assume !(1 == ~T3_E~0); 33922#L1134-1 assume !(1 == ~T4_E~0); 34239#L1139-1 assume !(1 == ~T5_E~0); 34240#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34472#L1149-1 assume !(1 == ~T7_E~0); 35155#L1154-1 assume !(1 == ~T8_E~0); 35345#L1159-1 assume !(1 == ~T9_E~0); 35342#L1164-1 assume !(1 == ~T10_E~0); 35340#L1169-1 assume !(1 == ~E_1~0); 35337#L1174-1 assume !(1 == ~E_2~0); 35335#L1179-1 assume !(1 == ~E_3~0); 35238#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 35226#L1189-1 assume !(1 == ~E_5~0); 35224#L1194-1 assume !(1 == ~E_6~0); 35222#L1199-1 assume !(1 == ~E_7~0); 35220#L1204-1 assume !(1 == ~E_8~0); 35209#L1209-1 assume !(1 == ~E_9~0); 35201#L1214-1 assume !(1 == ~E_10~0); 35193#L1219-1 assume { :end_inline_reset_delta_events } true; 35187#L1520-2 [2022-07-22 02:43:43,740 INFO L754 eck$LassoCheckResult]: Loop: 35187#L1520-2 assume !false; 35182#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 35180#L981 assume !false; 35179#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 35170#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 35167#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 35166#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 35164#L836 assume !(0 != eval_~tmp~0#1); 35163#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 35162#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35161#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 35160#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 35158#L1011-3 assume !(0 == ~T2_E~0); 35159#L1016-3 assume !(0 == ~T3_E~0); 36821#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36819#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36817#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36815#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36813#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36811#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 36808#L1051-3 assume !(0 == ~T10_E~0); 36806#L1056-3 assume !(0 == ~E_1~0); 36804#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36802#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36800#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 36798#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 36795#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 36793#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 36791#L1091-3 assume !(0 == ~E_8~0); 36789#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 36787#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 36786#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36785#L484-33 assume 1 == ~m_pc~0; 36780#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 36778#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36776#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 36775#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36774#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36773#L503-33 assume !(1 == ~t1_pc~0); 36771#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 36766#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36761#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 36755#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36753#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36751#L522-33 assume 1 == ~t2_pc~0; 36746#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36744#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36742#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 36740#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36738#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36736#L541-33 assume !(1 == ~t3_pc~0); 36731#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 36729#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36727#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36725#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36723#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36720#L560-33 assume 1 == ~t4_pc~0; 36717#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 36715#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36713#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36711#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 36709#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36708#L579-33 assume 1 == ~t5_pc~0; 36706#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35109#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35110#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34765#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 34766#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34794#L598-33 assume !(1 == ~t6_pc~0); 34566#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 34388#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34389#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34229#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 34230#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35053#L617-33 assume !(1 == ~t7_pc~0); 34018#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 34019#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34983#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35098#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 35094#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33946#L636-33 assume !(1 == ~t8_pc~0); 33947#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 34880#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34881#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36616#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36610#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36602#L655-33 assume 1 == ~t9_pc~0; 36594#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36588#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36582#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36577#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 36568#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36559#L674-33 assume !(1 == ~t10_pc~0); 36551#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 36545#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36539#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36538#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 36537#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36536#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 36534#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36531#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 35156#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 35143#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36527#L1139-3 assume !(1 == ~T5_E~0); 36525#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36523#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 36146#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 36143#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 36141#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36139#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 35578#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 36136#L1179-3 assume !(1 == ~E_3~0); 36134#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36131#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 36129#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 36127#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 36125#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 36123#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 35979#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 35687#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 35368#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 35367#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 35268#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 35262#L1539 assume !(0 == start_simulation_~tmp~3#1); 35256#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 35231#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 35225#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 35223#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 35221#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 35210#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 35202#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 35194#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 35187#L1520-2 [2022-07-22 02:43:43,741 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:43,741 INFO L85 PathProgramCache]: Analyzing trace with hash 642257269, now seen corresponding path program 1 times [2022-07-22 02:43:43,741 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:43,742 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [346866131] [2022-07-22 02:43:43,742 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:43,743 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:43,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:43,767 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:43,767 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:43,767 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [346866131] [2022-07-22 02:43:43,769 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [346866131] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:43,769 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:43,769 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:43,769 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [467390972] [2022-07-22 02:43:43,769 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:43,770 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:43:43,770 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:43,770 INFO L85 PathProgramCache]: Analyzing trace with hash 1522974667, now seen corresponding path program 1 times [2022-07-22 02:43:43,770 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:43,770 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1752959369] [2022-07-22 02:43:43,771 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:43,771 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:43,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:43,797 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:43,797 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:43,797 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1752959369] [2022-07-22 02:43:43,798 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1752959369] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:43,798 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:43,798 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:43,798 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1526734918] [2022-07-22 02:43:43,798 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:43,798 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:43:43,799 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:43:43,799 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-22 02:43:43,799 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-22 02:43:43,799 INFO L87 Difference]: Start difference. First operand 4588 states and 6781 transitions. cyclomatic complexity: 2197 Second operand has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:43,982 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:43:43,982 INFO L93 Difference]: Finished difference Result 8696 states and 12834 transitions. [2022-07-22 02:43:43,983 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-22 02:43:43,984 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8696 states and 12834 transitions. [2022-07-22 02:43:44,028 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8492 [2022-07-22 02:43:44,067 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8696 states to 8696 states and 12834 transitions. [2022-07-22 02:43:44,067 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8696 [2022-07-22 02:43:44,075 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8696 [2022-07-22 02:43:44,075 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8696 states and 12834 transitions. [2022-07-22 02:43:44,085 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:43:44,086 INFO L369 hiAutomatonCegarLoop]: Abstraction has 8696 states and 12834 transitions. [2022-07-22 02:43:44,092 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8696 states and 12834 transitions. [2022-07-22 02:43:44,193 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8696 to 8692. [2022-07-22 02:43:44,213 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8692 states, 8692 states have (on average 1.476069949378739) internal successors, (12830), 8691 states have internal predecessors, (12830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:44,232 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8692 states to 8692 states and 12830 transitions. [2022-07-22 02:43:44,233 INFO L392 hiAutomatonCegarLoop]: Abstraction has 8692 states and 12830 transitions. [2022-07-22 02:43:44,233 INFO L374 stractBuchiCegarLoop]: Abstraction has 8692 states and 12830 transitions. [2022-07-22 02:43:44,233 INFO L287 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-07-22 02:43:44,233 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8692 states and 12830 transitions. [2022-07-22 02:43:44,262 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8492 [2022-07-22 02:43:44,262 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:43:44,262 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:43:44,265 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:44,265 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:44,265 INFO L752 eck$LassoCheckResult]: Stem: 48146#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 48147#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 48452#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 48438#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 48439#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 48467#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 48468#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 47699#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 47413#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47414#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 48355#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 48356#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 48337#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 48338#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 48382#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 47467#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 47468#L1006 assume !(0 == ~M_E~0); 47316#L1006-2 assume !(0 == ~T1_E~0); 47317#L1011-1 assume !(0 == ~T2_E~0); 48407#L1016-1 assume !(0 == ~T3_E~0); 48425#L1021-1 assume !(0 == ~T4_E~0); 47193#L1026-1 assume !(0 == ~T5_E~0); 47194#L1031-1 assume !(0 == ~T6_E~0); 48090#L1036-1 assume !(0 == ~T7_E~0); 48086#L1041-1 assume !(0 == ~T8_E~0); 48087#L1046-1 assume !(0 == ~T9_E~0); 47500#L1051-1 assume !(0 == ~T10_E~0); 47501#L1056-1 assume !(0 == ~E_1~0); 48225#L1061-1 assume !(0 == ~E_2~0); 47417#L1066-1 assume !(0 == ~E_3~0); 47418#L1071-1 assume !(0 == ~E_4~0); 48202#L1076-1 assume !(0 == ~E_5~0); 47327#L1081-1 assume !(0 == ~E_6~0); 47328#L1086-1 assume !(0 == ~E_7~0); 47674#L1091-1 assume !(0 == ~E_8~0); 48396#L1096-1 assume !(0 == ~E_9~0); 48397#L1101-1 assume !(0 == ~E_10~0); 47738#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47739#L484 assume !(1 == ~m_pc~0); 47376#L484-2 is_master_triggered_~__retres1~0#1 := 0; 47375#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48008#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 48304#L1245 assume !(0 != activate_threads_~tmp~1#1); 48305#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48078#L503 assume 1 == ~t1_pc~0; 48079#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 48095#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48216#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 47855#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 47224#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47225#L522 assume !(1 == ~t2_pc~0); 48044#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 47430#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47431#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 47914#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 48357#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 48435#L541 assume 1 == ~t3_pc~0; 47992#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 47798#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47610#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47611#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 48047#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48048#L560 assume !(1 == ~t4_pc~0); 47308#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 47307#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47951#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47191#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 47192#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47481#L579 assume 1 == ~t5_pc~0; 47142#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47143#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47253#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47954#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 48423#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 48449#L598 assume 1 == ~t6_pc~0; 47578#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 47579#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47890#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 48328#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 48128#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 48069#L617 assume !(1 == ~t7_pc~0); 47550#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 47549#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47843#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47844#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 47775#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47776#L636 assume 1 == ~t8_pc~0; 47948#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 47949#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47740#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47741#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 47898#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47899#L655 assume !(1 == ~t9_pc~0); 47928#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 47929#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47529#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47530#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 48148#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 48149#L674 assume 1 == ~t10_pc~0; 47303#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 47304#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 48437#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 48479#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 47888#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47889#L1119 assume !(1 == ~M_E~0); 47399#L1119-2 assume !(1 == ~T1_E~0); 47400#L1124-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 47816#L1129-1 assume !(1 == ~T3_E~0); 48797#L1134-1 assume !(1 == ~T4_E~0); 48795#L1139-1 assume !(1 == ~T5_E~0); 48791#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 48789#L1149-1 assume !(1 == ~T7_E~0); 48622#L1154-1 assume !(1 == ~T8_E~0); 48620#L1159-1 assume !(1 == ~T9_E~0); 48619#L1164-1 assume !(1 == ~T10_E~0); 48618#L1169-1 assume !(1 == ~E_1~0); 48617#L1174-1 assume !(1 == ~E_2~0); 48616#L1179-1 assume !(1 == ~E_3~0); 48612#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 48610#L1189-1 assume !(1 == ~E_5~0); 48609#L1194-1 assume !(1 == ~E_6~0); 48608#L1199-1 assume !(1 == ~E_7~0); 48557#L1204-1 assume !(1 == ~E_8~0); 48542#L1209-1 assume !(1 == ~E_9~0); 48532#L1214-1 assume !(1 == ~E_10~0); 48524#L1219-1 assume { :end_inline_reset_delta_events } true; 48518#L1520-2 [2022-07-22 02:43:44,266 INFO L754 eck$LassoCheckResult]: Loop: 48518#L1520-2 assume !false; 48513#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 48511#L981 assume !false; 48510#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 48501#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 48498#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 48497#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 48495#L836 assume !(0 != eval_~tmp~0#1); 48494#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 48493#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 48492#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 48491#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 48489#L1011-3 assume !(0 == ~T2_E~0); 48490#L1016-3 assume !(0 == ~T3_E~0); 50631#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 50629#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 50627#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 50625#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 50622#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 50620#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 50618#L1051-3 assume !(0 == ~T10_E~0); 50616#L1056-3 assume !(0 == ~E_1~0); 50614#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 50612#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50609#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 50607#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 50605#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 50603#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 50601#L1091-3 assume !(0 == ~E_8~0); 50599#L1096-3 assume !(0 == ~E_9~0); 50596#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 50594#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50592#L484-33 assume 1 == ~m_pc~0; 50588#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 50586#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50583#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 50581#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 50579#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50577#L503-33 assume !(1 == ~t1_pc~0); 50574#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 50572#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50571#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 50568#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50566#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50564#L522-33 assume 1 == ~t2_pc~0; 50561#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50559#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50557#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 50554#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50552#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50550#L541-33 assume !(1 == ~t3_pc~0); 50546#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 50544#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50541#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 50539#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 50537#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50535#L560-33 assume 1 == ~t4_pc~0; 50532#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 50530#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50529#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50526#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 50524#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50522#L579-33 assume 1 == ~t5_pc~0; 50519#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50517#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50515#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50512#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 50510#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50508#L598-33 assume !(1 == ~t6_pc~0); 50503#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 50501#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50499#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49712#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 49709#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49707#L617-33 assume 1 == ~t7_pc~0; 49704#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49702#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49700#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49698#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 49695#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49693#L636-33 assume !(1 == ~t8_pc~0); 49690#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 49688#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49686#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49684#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 49681#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49679#L655-33 assume 1 == ~t9_pc~0; 49633#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 49631#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49628#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49626#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 49624#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49622#L674-33 assume !(1 == ~t10_pc~0); 49619#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 49617#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 49616#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49613#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 49611#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49609#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 49607#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 49605#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48485#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 49599#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 49597#L1139-3 assume !(1 == ~T5_E~0); 49595#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 49593#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 49591#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 49589#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 49588#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 49091#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 49088#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 49086#L1179-3 assume !(1 == ~E_3~0); 49084#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49082#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 49080#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 49078#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 49076#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 49073#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 49069#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 49068#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 48774#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 48772#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 48770#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 48614#L1539 assume !(0 == start_simulation_~tmp~3#1); 48611#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 48568#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 48562#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 48560#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 48558#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 48543#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 48533#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 48525#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 48518#L1520-2 [2022-07-22 02:43:44,266 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:44,266 INFO L85 PathProgramCache]: Analyzing trace with hash -1298324745, now seen corresponding path program 1 times [2022-07-22 02:43:44,266 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:44,267 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [803307668] [2022-07-22 02:43:44,267 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:44,267 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:44,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:44,292 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:44,292 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:44,292 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [803307668] [2022-07-22 02:43:44,292 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [803307668] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:44,292 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:44,293 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:44,293 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1589878795] [2022-07-22 02:43:44,293 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:44,294 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:43:44,294 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:44,294 INFO L85 PathProgramCache]: Analyzing trace with hash 631228014, now seen corresponding path program 1 times [2022-07-22 02:43:44,294 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:44,294 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1915454486] [2022-07-22 02:43:44,295 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:44,295 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:44,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:44,376 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:44,377 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:44,377 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1915454486] [2022-07-22 02:43:44,377 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1915454486] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:44,377 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:44,377 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:44,377 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1590600605] [2022-07-22 02:43:44,378 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:44,378 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:43:44,378 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:43:44,379 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-22 02:43:44,379 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-22 02:43:44,379 INFO L87 Difference]: Start difference. First operand 8692 states and 12830 transitions. cyclomatic complexity: 4146 Second operand has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:44,634 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:43:44,634 INFO L93 Difference]: Finished difference Result 24690 states and 36034 transitions. [2022-07-22 02:43:44,634 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-22 02:43:44,635 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24690 states and 36034 transitions. [2022-07-22 02:43:44,757 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 24124 [2022-07-22 02:43:44,884 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24690 states to 24690 states and 36034 transitions. [2022-07-22 02:43:44,885 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 24690 [2022-07-22 02:43:44,902 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 24690 [2022-07-22 02:43:44,902 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24690 states and 36034 transitions. [2022-07-22 02:43:44,921 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:43:44,922 INFO L369 hiAutomatonCegarLoop]: Abstraction has 24690 states and 36034 transitions. [2022-07-22 02:43:44,936 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24690 states and 36034 transitions. [2022-07-22 02:43:45,224 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24690 to 23774. [2022-07-22 02:43:45,264 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23774 states, 23774 states have (on average 1.4623538319172205) internal successors, (34766), 23773 states have internal predecessors, (34766), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:45,323 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23774 states to 23774 states and 34766 transitions. [2022-07-22 02:43:45,324 INFO L392 hiAutomatonCegarLoop]: Abstraction has 23774 states and 34766 transitions. [2022-07-22 02:43:45,324 INFO L374 stractBuchiCegarLoop]: Abstraction has 23774 states and 34766 transitions. [2022-07-22 02:43:45,324 INFO L287 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-07-22 02:43:45,324 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23774 states and 34766 transitions. [2022-07-22 02:43:45,405 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 23556 [2022-07-22 02:43:45,405 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:43:45,405 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:43:45,407 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:45,407 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:45,408 INFO L752 eck$LassoCheckResult]: Stem: 81537#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 81538#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 81886#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 81866#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 81867#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 81901#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 81902#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 81081#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 80797#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 80798#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 81778#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 81779#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 81760#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 81761#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 81806#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 80852#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 80853#L1006 assume !(0 == ~M_E~0); 80706#L1006-2 assume !(0 == ~T1_E~0); 80707#L1011-1 assume !(0 == ~T2_E~0); 81836#L1016-1 assume !(0 == ~T3_E~0); 81852#L1021-1 assume !(0 == ~T4_E~0); 80587#L1026-1 assume !(0 == ~T5_E~0); 80588#L1031-1 assume !(0 == ~T6_E~0); 81481#L1036-1 assume !(0 == ~T7_E~0); 81476#L1041-1 assume !(0 == ~T8_E~0); 81477#L1046-1 assume !(0 == ~T9_E~0); 80883#L1051-1 assume !(0 == ~T10_E~0); 80884#L1056-1 assume !(0 == ~E_1~0); 81623#L1061-1 assume !(0 == ~E_2~0); 80801#L1066-1 assume !(0 == ~E_3~0); 80802#L1071-1 assume !(0 == ~E_4~0); 81602#L1076-1 assume !(0 == ~E_5~0); 80714#L1081-1 assume !(0 == ~E_6~0); 80715#L1086-1 assume !(0 == ~E_7~0); 81057#L1091-1 assume !(0 == ~E_8~0); 81824#L1096-1 assume !(0 == ~E_9~0); 81825#L1101-1 assume !(0 == ~E_10~0); 81118#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 81119#L484 assume !(1 == ~m_pc~0); 81225#L484-2 is_master_triggered_~__retres1~0#1 := 0; 81226#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 81392#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 81719#L1245 assume !(0 != activate_threads_~tmp~1#1); 81720#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 81469#L503 assume !(1 == ~t1_pc~0); 81470#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 81664#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 81615#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 81242#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 80615#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 80616#L522 assume !(1 == ~t2_pc~0); 81429#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 80814#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 80815#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 81300#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 81780#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 81862#L541 assume 1 == ~t3_pc~0; 81376#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 81181#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 80994#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 80995#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 81435#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 81436#L560 assume !(1 == ~t4_pc~0); 80698#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 80697#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 81335#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 80583#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 80584#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 80866#L579 assume 1 == ~t5_pc~0; 80534#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 80535#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 80643#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 81338#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 81851#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 81883#L598 assume 1 == ~t6_pc~0; 80960#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 80961#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 81279#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 81750#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 81519#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 81460#L617 assume !(1 == ~t7_pc~0); 80932#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 80931#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 81227#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 81228#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 81155#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 81156#L636 assume 1 == ~t8_pc~0; 81331#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 81332#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 81120#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 81121#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 81286#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 81287#L655 assume !(1 == ~t9_pc~0); 81314#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 81315#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 80912#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 80913#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 81539#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 81540#L674 assume 1 == ~t10_pc~0; 80691#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 80692#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 81864#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 81921#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 81274#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 81275#L1119 assume !(1 == ~M_E~0); 80783#L1119-2 assume !(1 == ~T1_E~0); 80784#L1124-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 80607#L1129-1 assume !(1 == ~T3_E~0); 80608#L1134-1 assume !(1 == ~T4_E~0); 80917#L1139-1 assume !(1 == ~T5_E~0); 80918#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 81154#L1149-1 assume !(1 == ~T7_E~0); 80778#L1154-1 assume !(1 == ~T8_E~0); 80779#L1159-1 assume !(1 == ~T9_E~0); 80867#L1164-1 assume !(1 == ~T10_E~0); 81303#L1169-1 assume !(1 == ~E_1~0); 81191#L1174-1 assume !(1 == ~E_2~0); 80974#L1179-1 assume !(1 == ~E_3~0); 80856#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 80857#L1189-1 assume !(1 == ~E_5~0); 80911#L1194-1 assume !(1 == ~E_6~0); 81035#L1199-1 assume !(1 == ~E_7~0); 80984#L1204-1 assume !(1 == ~E_8~0); 80985#L1209-1 assume !(1 == ~E_9~0); 81897#L1214-1 assume !(1 == ~E_10~0); 101116#L1219-1 assume { :end_inline_reset_delta_events } true; 101096#L1520-2 [2022-07-22 02:43:45,408 INFO L754 eck$LassoCheckResult]: Loop: 101096#L1520-2 assume !false; 101092#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 101088#L981 assume !false; 101086#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 100875#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 100862#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 100859#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 100855#L836 assume !(0 != eval_~tmp~0#1); 100856#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 103171#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 103169#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 103166#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 103164#L1011-3 assume !(0 == ~T2_E~0); 103162#L1016-3 assume !(0 == ~T3_E~0); 103160#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 103158#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 103156#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 103153#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 103151#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 103149#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 103147#L1051-3 assume !(0 == ~T10_E~0); 103145#L1056-3 assume !(0 == ~E_1~0); 103143#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 103140#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 103138#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 103136#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 103134#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 103132#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 103130#L1091-3 assume !(0 == ~E_8~0); 103127#L1096-3 assume !(0 == ~E_9~0); 103125#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 81839#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 81371#L484-33 assume !(1 == ~m_pc~0); 81372#L484-35 is_master_triggered_~__retres1~0#1 := 0; 103341#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 103340#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 103339#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 103338#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 103337#L503-33 assume !(1 == ~t1_pc~0); 103336#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 103335#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 103334#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 103333#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 103332#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 103331#L522-33 assume 1 == ~t2_pc~0; 103329#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 101437#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 101434#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 101432#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 101430#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 101428#L541-33 assume !(1 == ~t3_pc~0); 101425#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 101423#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 101420#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 101418#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 101416#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 101414#L560-33 assume 1 == ~t4_pc~0; 101411#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 101409#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 101406#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 101404#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 101402#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 101400#L579-33 assume !(1 == ~t5_pc~0); 101395#L579-35 is_transmit5_triggered_~__retres1~5#1 := 0; 101392#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 101390#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 101388#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 101386#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 101384#L598-33 assume 1 == ~t6_pc~0; 101381#L599-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 101378#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 101376#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 101374#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 101372#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 101370#L617-33 assume !(1 == ~t7_pc~0); 101367#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 101364#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 101362#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 101360#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 101358#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 101356#L636-33 assume 1 == ~t8_pc~0; 101353#L637-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 101350#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 101348#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 101346#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 101344#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 101342#L655-33 assume !(1 == ~t9_pc~0); 101339#L655-35 is_transmit9_triggered_~__retres1~9#1 := 0; 101336#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 101334#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 101332#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 101330#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 101328#L674-33 assume !(1 == ~t10_pc~0); 101325#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 101324#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 101323#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 101322#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 101320#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 101318#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 101316#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 101314#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 90966#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 91417#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 101309#L1139-3 assume !(1 == ~T5_E~0); 101308#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 101307#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 101305#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 101302#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 101300#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 101298#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 101294#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 101292#L1179-3 assume !(1 == ~E_3~0); 101290#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 101289#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 101287#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 101285#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 101283#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 101281#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 98268#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 101277#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 101251#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 101249#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 101247#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 101244#L1539 assume !(0 == start_simulation_~tmp~3#1); 101241#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 101222#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 101216#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 101214#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 101211#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 101209#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 101207#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 101117#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 101096#L1520-2 [2022-07-22 02:43:45,408 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:45,409 INFO L85 PathProgramCache]: Analyzing trace with hash 1011813846, now seen corresponding path program 1 times [2022-07-22 02:43:45,409 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:45,409 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1971136248] [2022-07-22 02:43:45,409 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:45,409 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:45,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:45,535 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:45,536 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:45,536 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1971136248] [2022-07-22 02:43:45,536 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1971136248] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:45,537 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:45,537 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:45,538 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2084735785] [2022-07-22 02:43:45,538 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:45,539 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:43:45,539 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:45,540 INFO L85 PathProgramCache]: Analyzing trace with hash -1918075028, now seen corresponding path program 1 times [2022-07-22 02:43:45,540 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:45,540 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [564118958] [2022-07-22 02:43:45,540 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:45,540 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:45,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:45,573 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:45,574 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:45,574 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [564118958] [2022-07-22 02:43:45,574 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [564118958] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:45,574 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:45,574 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:45,574 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [33700617] [2022-07-22 02:43:45,574 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:45,575 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:43:45,576 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:43:45,576 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-22 02:43:45,576 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-22 02:43:45,576 INFO L87 Difference]: Start difference. First operand 23774 states and 34766 transitions. cyclomatic complexity: 11008 Second operand has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:46,034 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:43:46,034 INFO L93 Difference]: Finished difference Result 67829 states and 98345 transitions. [2022-07-22 02:43:46,035 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-22 02:43:46,036 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 67829 states and 98345 transitions. [2022-07-22 02:43:46,458 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 66808 [2022-07-22 02:43:46,852 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 67829 states to 67829 states and 98345 transitions. [2022-07-22 02:43:46,852 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 67829 [2022-07-22 02:43:46,954 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 67829 [2022-07-22 02:43:46,954 INFO L73 IsDeterministic]: Start isDeterministic. Operand 67829 states and 98345 transitions. [2022-07-22 02:43:47,023 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:43:47,023 INFO L369 hiAutomatonCegarLoop]: Abstraction has 67829 states and 98345 transitions. [2022-07-22 02:43:47,063 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67829 states and 98345 transitions. [2022-07-22 02:43:47,735 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67829 to 65697. [2022-07-22 02:43:47,814 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 65697 states, 65697 states have (on average 1.452440750719211) internal successors, (95421), 65696 states have internal predecessors, (95421), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:48,140 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65697 states to 65697 states and 95421 transitions. [2022-07-22 02:43:48,141 INFO L392 hiAutomatonCegarLoop]: Abstraction has 65697 states and 95421 transitions. [2022-07-22 02:43:48,141 INFO L374 stractBuchiCegarLoop]: Abstraction has 65697 states and 95421 transitions. [2022-07-22 02:43:48,141 INFO L287 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-07-22 02:43:48,151 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 65697 states and 95421 transitions. [2022-07-22 02:43:48,323 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 65440 [2022-07-22 02:43:48,323 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:43:48,323 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:43:48,324 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:48,325 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:48,325 INFO L752 eck$LassoCheckResult]: Stem: 173148#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 173149#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 173503#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 173484#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 173485#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 173525#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 173526#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 172700#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 172414#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 172415#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 173394#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 173395#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 173371#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 173372#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 173423#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 172466#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 172467#L1006 assume !(0 == ~M_E~0); 172320#L1006-2 assume !(0 == ~T1_E~0); 172321#L1011-1 assume !(0 == ~T2_E~0); 173450#L1016-1 assume !(0 == ~T3_E~0); 173469#L1021-1 assume !(0 == ~T4_E~0); 172200#L1026-1 assume !(0 == ~T5_E~0); 172201#L1031-1 assume !(0 == ~T6_E~0); 173095#L1036-1 assume !(0 == ~T7_E~0); 173089#L1041-1 assume !(0 == ~T8_E~0); 173090#L1046-1 assume !(0 == ~T9_E~0); 172497#L1051-1 assume !(0 == ~T10_E~0); 172498#L1056-1 assume !(0 == ~E_1~0); 173240#L1061-1 assume !(0 == ~E_2~0); 172416#L1066-1 assume !(0 == ~E_3~0); 172417#L1071-1 assume !(0 == ~E_4~0); 173218#L1076-1 assume !(0 == ~E_5~0); 172328#L1081-1 assume !(0 == ~E_6~0); 172329#L1086-1 assume !(0 == ~E_7~0); 172675#L1091-1 assume !(0 == ~E_8~0); 173441#L1096-1 assume !(0 == ~E_9~0); 173442#L1101-1 assume !(0 == ~E_10~0); 172737#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 172738#L484 assume !(1 == ~m_pc~0); 172843#L484-2 is_master_triggered_~__retres1~0#1 := 0; 172844#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 173009#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 173333#L1245 assume !(0 != activate_threads_~tmp~1#1); 173334#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 173082#L503 assume !(1 == ~t1_pc~0); 173083#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 173281#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 173232#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 172859#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 172229#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 172230#L522 assume !(1 == ~t2_pc~0); 173046#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 172429#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 172430#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 172915#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 173396#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 173480#L541 assume !(1 == ~t3_pc~0); 172798#L541-2 is_transmit3_triggered_~__retres1~3#1 := 0; 172799#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 172610#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 172611#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 173055#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 173056#L560 assume !(1 == ~t4_pc~0); 172312#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 172311#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 172950#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 172196#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 172197#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 172480#L579 assume 1 == ~t5_pc~0; 172147#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 172148#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 172258#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 172953#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 173468#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 173500#L598 assume 1 == ~t6_pc~0; 172575#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 172576#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 172894#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 173362#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 173130#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 173073#L617 assume !(1 == ~t7_pc~0); 172548#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 172547#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 172845#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 172846#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 172774#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 172775#L636 assume 1 == ~t8_pc~0; 172947#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 172948#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 172739#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 172740#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 172899#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 172900#L655 assume !(1 == ~t9_pc~0); 172931#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 172932#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 172528#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 172529#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 173150#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 173151#L674 assume 1 == ~t10_pc~0; 172305#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 172306#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 173482#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 173548#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 172889#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 172890#L1119 assume !(1 == ~M_E~0); 172398#L1119-2 assume !(1 == ~T1_E~0); 172399#L1124-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 172819#L1129-1 assume !(1 == ~T3_E~0); 180412#L1134-1 assume !(1 == ~T4_E~0); 180411#L1139-1 assume !(1 == ~T5_E~0); 180410#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 180409#L1149-1 assume !(1 == ~T7_E~0); 180408#L1154-1 assume !(1 == ~T8_E~0); 180407#L1159-1 assume !(1 == ~T9_E~0); 180406#L1164-1 assume !(1 == ~T10_E~0); 180405#L1169-1 assume !(1 == ~E_1~0); 180404#L1174-1 assume !(1 == ~E_2~0); 180403#L1179-1 assume !(1 == ~E_3~0); 180402#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 180401#L1189-1 assume !(1 == ~E_5~0); 180400#L1194-1 assume !(1 == ~E_6~0); 180399#L1199-1 assume !(1 == ~E_7~0); 180398#L1204-1 assume !(1 == ~E_8~0); 180397#L1209-1 assume !(1 == ~E_9~0); 180394#L1214-1 assume !(1 == ~E_10~0); 180391#L1219-1 assume { :end_inline_reset_delta_events } true; 180392#L1520-2 [2022-07-22 02:43:48,325 INFO L754 eck$LassoCheckResult]: Loop: 180392#L1520-2 assume !false; 232828#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 232825#L981 assume !false; 232823#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 232812#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 180293#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 180286#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 180287#L836 assume !(0 != eval_~tmp~0#1); 230276#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 233078#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 233077#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 233076#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 233075#L1011-3 assume !(0 == ~T2_E~0); 233074#L1016-3 assume !(0 == ~T3_E~0); 233073#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 233072#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 233071#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 233070#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 233069#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 233068#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 233067#L1051-3 assume !(0 == ~T10_E~0); 233066#L1056-3 assume !(0 == ~E_1~0); 233065#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 233064#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 233063#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 233062#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 233061#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 233060#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 233059#L1091-3 assume !(0 == ~E_8~0); 233058#L1096-3 assume !(0 == ~E_9~0); 233057#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 233056#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 233055#L484-33 assume !(1 == ~m_pc~0); 233054#L484-35 is_master_triggered_~__retres1~0#1 := 0; 233053#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 233052#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 233051#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 233050#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 233049#L503-33 assume !(1 == ~t1_pc~0); 233048#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 233047#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 233046#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 233045#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 233044#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 233043#L522-33 assume !(1 == ~t2_pc~0); 233042#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 233040#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 233039#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 233038#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 233037#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 233036#L541-33 assume !(1 == ~t3_pc~0); 233035#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 233034#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 233033#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 233032#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 233031#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 233030#L560-33 assume !(1 == ~t4_pc~0); 233029#L560-35 is_transmit4_triggered_~__retres1~4#1 := 0; 233027#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 233026#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 233025#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 233024#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 233023#L579-33 assume !(1 == ~t5_pc~0); 233022#L579-35 is_transmit5_triggered_~__retres1~5#1 := 0; 233020#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 233019#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 233018#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 233017#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 233016#L598-33 assume 1 == ~t6_pc~0; 233015#L599-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 233013#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 233012#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 233011#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 233010#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 233009#L617-33 assume !(1 == ~t7_pc~0); 233008#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 233006#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 233005#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 233004#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 233003#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 233002#L636-33 assume 1 == ~t8_pc~0; 233001#L637-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 232999#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 232998#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 232997#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 232996#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 232995#L655-33 assume !(1 == ~t9_pc~0); 232994#L655-35 is_transmit9_triggered_~__retres1~9#1 := 0; 232992#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 232991#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 232990#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 232989#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 232988#L674-33 assume 1 == ~t10_pc~0; 232987#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 232985#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 232984#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 232983#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 232982#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 232981#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 232980#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 232979#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 182372#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 232975#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 232974#L1139-3 assume !(1 == ~T5_E~0); 232973#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 232972#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 232971#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 232970#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 232969#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 232968#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 182347#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 232967#L1179-3 assume !(1 == ~E_3~0); 232966#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 232965#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 232964#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 232963#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 232962#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 232961#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 182325#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 232960#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 232949#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 232948#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 232947#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 232945#L1539 assume !(0 == start_simulation_~tmp~3#1); 232943#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 232936#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 232931#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 232930#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 232929#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 232928#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 232927#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 232926#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 180392#L1520-2 [2022-07-22 02:43:48,326 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:48,326 INFO L85 PathProgramCache]: Analyzing trace with hash 1918570293, now seen corresponding path program 1 times [2022-07-22 02:43:48,326 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:48,326 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [215505204] [2022-07-22 02:43:48,327 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:48,327 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:48,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:48,352 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:48,353 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:48,353 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [215505204] [2022-07-22 02:43:48,353 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [215505204] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:48,353 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:48,353 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-22 02:43:48,353 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1792200864] [2022-07-22 02:43:48,354 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:48,354 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:43:48,354 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:48,354 INFO L85 PathProgramCache]: Analyzing trace with hash -1036754037, now seen corresponding path program 1 times [2022-07-22 02:43:48,355 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:48,355 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1545003945] [2022-07-22 02:43:48,355 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:48,355 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:48,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:48,377 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:48,378 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:48,378 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1545003945] [2022-07-22 02:43:48,378 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1545003945] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:48,378 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:48,378 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:48,378 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [717296948] [2022-07-22 02:43:48,379 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:48,379 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:43:48,379 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:43:48,379 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-22 02:43:48,379 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-22 02:43:48,380 INFO L87 Difference]: Start difference. First operand 65697 states and 95421 transitions. cyclomatic complexity: 29756 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 2 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:49,047 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:43:49,048 INFO L93 Difference]: Finished difference Result 124968 states and 180907 transitions. [2022-07-22 02:43:49,048 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-22 02:43:49,048 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 124968 states and 180907 transitions. [2022-07-22 02:43:49,689 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 124508 [2022-07-22 02:43:50,043 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 124968 states to 124968 states and 180907 transitions. [2022-07-22 02:43:50,043 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 124968 [2022-07-22 02:43:50,117 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 124968 [2022-07-22 02:43:50,118 INFO L73 IsDeterministic]: Start isDeterministic. Operand 124968 states and 180907 transitions. [2022-07-22 02:43:50,354 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:43:50,354 INFO L369 hiAutomatonCegarLoop]: Abstraction has 124968 states and 180907 transitions. [2022-07-22 02:43:50,415 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 124968 states and 180907 transitions. [2022-07-22 02:43:51,512 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 124968 to 124824. [2022-07-22 02:43:51,632 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 124824 states, 124824 states have (on average 1.4481429853233352) internal successors, (180763), 124823 states have internal predecessors, (180763), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:51,873 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124824 states to 124824 states and 180763 transitions. [2022-07-22 02:43:51,873 INFO L392 hiAutomatonCegarLoop]: Abstraction has 124824 states and 180763 transitions. [2022-07-22 02:43:51,873 INFO L374 stractBuchiCegarLoop]: Abstraction has 124824 states and 180763 transitions. [2022-07-22 02:43:51,873 INFO L287 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-07-22 02:43:51,873 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 124824 states and 180763 transitions. [2022-07-22 02:43:52,526 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 124364 [2022-07-22 02:43:52,526 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:43:52,533 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:43:52,536 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:52,537 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:43:52,537 INFO L752 eck$LassoCheckResult]: Stem: 363844#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 363845#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 364246#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 364220#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 364221#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 364273#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 364274#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 363366#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 363080#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 363081#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 364107#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 364108#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 364083#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 364084#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 364136#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 363132#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 363133#L1006 assume !(0 == ~M_E~0); 362987#L1006-2 assume !(0 == ~T1_E~0); 362988#L1011-1 assume !(0 == ~T2_E~0); 364174#L1016-1 assume !(0 == ~T3_E~0); 364198#L1021-1 assume !(0 == ~T4_E~0); 362869#L1026-1 assume !(0 == ~T5_E~0); 362870#L1031-1 assume !(0 == ~T6_E~0); 363784#L1036-1 assume !(0 == ~T7_E~0); 363777#L1041-1 assume !(0 == ~T8_E~0); 363778#L1046-1 assume !(0 == ~T9_E~0); 363164#L1051-1 assume !(0 == ~T10_E~0); 363165#L1056-1 assume !(0 == ~E_1~0); 363944#L1061-1 assume !(0 == ~E_2~0); 363082#L1066-1 assume !(0 == ~E_3~0); 363083#L1071-1 assume !(0 == ~E_4~0); 363919#L1076-1 assume !(0 == ~E_5~0); 362995#L1081-1 assume !(0 == ~E_6~0); 362996#L1086-1 assume !(0 == ~E_7~0); 363342#L1091-1 assume !(0 == ~E_8~0); 364155#L1096-1 assume !(0 == ~E_9~0); 364156#L1101-1 assume !(0 == ~E_10~0); 363407#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 363408#L484 assume !(1 == ~m_pc~0); 363518#L484-2 is_master_triggered_~__retres1~0#1 := 0; 363519#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 363690#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 364041#L1245 assume !(0 != activate_threads_~tmp~1#1); 364042#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 363770#L503 assume !(1 == ~t1_pc~0); 363771#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 363985#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 363933#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 363535#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 362899#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 362900#L522 assume !(1 == ~t2_pc~0); 363731#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 363096#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 363097#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 363593#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 364109#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 364215#L541 assume !(1 == ~t3_pc~0); 363471#L541-2 is_transmit3_triggered_~__retres1~3#1 := 0; 363472#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 363274#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 363275#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 363738#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 363739#L560 assume !(1 == ~t4_pc~0); 362979#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 362978#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 363628#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 362865#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 362866#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 363146#L579 assume !(1 == ~t5_pc~0); 363147#L579-2 is_transmit5_triggered_~__retres1~5#1 := 0; 362925#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 362926#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 363632#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 364197#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 364242#L598 assume 1 == ~t6_pc~0; 363243#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 363244#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 363572#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 364071#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 363822#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 363761#L617 assume !(1 == ~t7_pc~0); 363215#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 363214#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 363520#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 363521#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 363446#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 363447#L636 assume 1 == ~t8_pc~0; 363625#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 363626#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 363409#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 363410#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 363579#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 363580#L655 assume !(1 == ~t9_pc~0); 363609#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 363610#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 363195#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 363196#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 363846#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 363847#L674 assume 1 == ~t10_pc~0; 362972#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 362973#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 364219#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 364299#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 363567#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 363568#L1119 assume !(1 == ~M_E~0); 363064#L1119-2 assume !(1 == ~T1_E~0); 363065#L1124-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 362889#L1129-1 assume !(1 == ~T3_E~0); 362890#L1134-1 assume !(1 == ~T4_E~0); 363747#L1139-1 assume !(1 == ~T5_E~0); 363443#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 363444#L1149-1 assume !(1 == ~T7_E~0); 363059#L1154-1 assume !(1 == ~T8_E~0); 363060#L1159-1 assume !(1 == ~T9_E~0); 364303#L1164-1 assume !(1 == ~T10_E~0); 363596#L1169-1 assume !(1 == ~E_1~0); 363483#L1174-1 assume !(1 == ~E_2~0); 363484#L1179-1 assume !(1 == ~E_3~0); 363136#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 363137#L1189-1 assume !(1 == ~E_5~0); 363317#L1194-1 assume !(1 == ~E_6~0); 363318#L1199-1 assume !(1 == ~E_7~0); 363266#L1204-1 assume !(1 == ~E_8~0); 363267#L1209-1 assume !(1 == ~E_9~0); 363839#L1214-1 assume !(1 == ~E_10~0); 363840#L1219-1 assume { :end_inline_reset_delta_events } true; 364302#L1520-2 [2022-07-22 02:43:52,538 INFO L754 eck$LassoCheckResult]: Loop: 364302#L1520-2 assume !false; 378143#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 378140#L981 assume !false; 378052#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 378039#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 373672#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 373396#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 372754#L836 assume !(0 != eval_~tmp~0#1); 372755#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 378824#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 378822#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 378820#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 378818#L1011-3 assume !(0 == ~T2_E~0); 378815#L1016-3 assume !(0 == ~T3_E~0); 378813#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 378811#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 378809#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 378807#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 378805#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 378803#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 378801#L1051-3 assume !(0 == ~T10_E~0); 378799#L1056-3 assume !(0 == ~E_1~0); 378797#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 378795#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 378793#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 378790#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 378788#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 378786#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 378784#L1091-3 assume !(0 == ~E_8~0); 378782#L1096-3 assume !(0 == ~E_9~0); 378780#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 378778#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 378776#L484-33 assume !(1 == ~m_pc~0); 378774#L484-35 is_master_triggered_~__retres1~0#1 := 0; 378772#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 378770#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 378768#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 378765#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 378763#L503-33 assume !(1 == ~t1_pc~0); 378761#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 378759#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 378757#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 378755#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 378752#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 378750#L522-33 assume !(1 == ~t2_pc~0); 378748#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 378745#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 378743#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 378741#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 378738#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 378736#L541-33 assume !(1 == ~t3_pc~0); 378734#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 378732#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 378730#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 378728#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 378725#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 378723#L560-33 assume !(1 == ~t4_pc~0); 378721#L560-35 is_transmit4_triggered_~__retres1~4#1 := 0; 378718#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 378716#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 378714#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 378711#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 378709#L579-33 assume !(1 == ~t5_pc~0); 378707#L579-35 is_transmit5_triggered_~__retres1~5#1 := 0; 378705#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 378703#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 378702#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 378622#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 378551#L598-33 assume 1 == ~t6_pc~0; 378548#L599-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 378545#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 378543#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 378541#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 378539#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 378537#L617-33 assume 1 == ~t7_pc~0; 378533#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 378531#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 378529#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 378527#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 378525#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 378523#L636-33 assume !(1 == ~t8_pc~0); 378519#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 378517#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 378515#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 378513#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 378511#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 378509#L655-33 assume 1 == ~t9_pc~0; 378505#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 378503#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 378501#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 378499#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 378497#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 378495#L674-33 assume 1 == ~t10_pc~0; 378492#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 378489#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 378487#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 378485#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 378483#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 378481#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 378479#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 378477#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 374806#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 377132#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 378475#L1139-3 assume !(1 == ~T5_E~0); 378473#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 378471#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 378469#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 378467#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 378465#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 378463#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 374784#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 378461#L1179-3 assume !(1 == ~E_3~0); 378459#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 378457#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 378455#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 378453#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 378451#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 378449#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 377713#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 378448#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 378434#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 378432#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 378429#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 378426#L1539 assume !(0 == start_simulation_~tmp~3#1); 378423#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 378407#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 378400#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 378398#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 378396#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 378394#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 378392#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 378390#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 364302#L1520-2 [2022-07-22 02:43:52,538 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:52,539 INFO L85 PathProgramCache]: Analyzing trace with hash 776922900, now seen corresponding path program 1 times [2022-07-22 02:43:52,539 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:52,539 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [129221295] [2022-07-22 02:43:52,539 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:52,539 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:52,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:52,571 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:52,572 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:52,572 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [129221295] [2022-07-22 02:43:52,572 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [129221295] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:52,572 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:52,572 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:52,572 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1503693753] [2022-07-22 02:43:52,572 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:52,573 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:43:52,573 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:43:52,573 INFO L85 PathProgramCache]: Analyzing trace with hash 711329900, now seen corresponding path program 1 times [2022-07-22 02:43:52,573 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:43:52,573 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1123729451] [2022-07-22 02:43:52,573 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:43:52,573 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:43:52,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:43:52,599 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:43:52,599 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:43:52,599 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1123729451] [2022-07-22 02:43:52,599 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1123729451] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:43:52,599 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:43:52,600 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:43:52,600 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1466259495] [2022-07-22 02:43:52,600 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:43:52,600 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:43:52,600 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:43:52,601 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-22 02:43:52,601 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-22 02:43:52,601 INFO L87 Difference]: Start difference. First operand 124824 states and 180763 transitions. cyclomatic complexity: 56003 Second operand has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:43:54,076 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:43:54,076 INFO L93 Difference]: Finished difference Result 353679 states and 509012 transitions. [2022-07-22 02:43:54,076 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-22 02:43:54,077 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 353679 states and 509012 transitions. [2022-07-22 02:43:55,794 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 349476 [2022-07-22 02:43:56,632 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 353679 states to 353679 states and 509012 transitions. [2022-07-22 02:43:56,632 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 353679 [2022-07-22 02:43:56,794 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 353679 [2022-07-22 02:43:56,795 INFO L73 IsDeterministic]: Start isDeterministic. Operand 353679 states and 509012 transitions. [2022-07-22 02:43:56,975 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:43:56,975 INFO L369 hiAutomatonCegarLoop]: Abstraction has 353679 states and 509012 transitions. [2022-07-22 02:43:57,190 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 353679 states and 509012 transitions. [2022-07-22 02:43:59,965 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 353679 to 345199. [2022-07-22 02:44:00,275 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 345199 states, 345199 states have (on average 1.4414989614686022) internal successors, (497604), 345198 states have internal predecessors, (497604), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:44:01,622 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 345199 states to 345199 states and 497604 transitions. [2022-07-22 02:44:01,622 INFO L392 hiAutomatonCegarLoop]: Abstraction has 345199 states and 497604 transitions. [2022-07-22 02:44:01,622 INFO L374 stractBuchiCegarLoop]: Abstraction has 345199 states and 497604 transitions. [2022-07-22 02:44:01,622 INFO L287 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-07-22 02:44:01,622 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 345199 states and 497604 transitions. [2022-07-22 02:44:02,989 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 344292 [2022-07-22 02:44:02,990 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-22 02:44:02,990 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-22 02:44:02,991 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:44:02,991 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-22 02:44:02,991 INFO L752 eck$LassoCheckResult]: Stem: 842352#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 842353#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 842762#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 842740#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 842741#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 842785#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 842786#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 841872#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 841596#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 841597#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 842622#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 842623#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 842601#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 842602#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 842653#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 841648#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 841649#L1006 assume !(0 == ~M_E~0); 841503#L1006-2 assume !(0 == ~T1_E~0); 841504#L1011-1 assume !(0 == ~T2_E~0); 842699#L1016-1 assume !(0 == ~T3_E~0); 842722#L1021-1 assume !(0 == ~T4_E~0); 841382#L1026-1 assume !(0 == ~T5_E~0); 841383#L1031-1 assume !(0 == ~T6_E~0); 842295#L1036-1 assume !(0 == ~T7_E~0); 842288#L1041-1 assume !(0 == ~T8_E~0); 842289#L1046-1 assume !(0 == ~T9_E~0); 841679#L1051-1 assume !(0 == ~T10_E~0); 841680#L1056-1 assume !(0 == ~E_1~0); 842448#L1061-1 assume !(0 == ~E_2~0); 841598#L1066-1 assume !(0 == ~E_3~0); 841599#L1071-1 assume !(0 == ~E_4~0); 842424#L1076-1 assume !(0 == ~E_5~0); 841511#L1081-1 assume !(0 == ~E_6~0); 841512#L1086-1 assume !(0 == ~E_7~0); 841848#L1091-1 assume !(0 == ~E_8~0); 842676#L1096-1 assume !(0 == ~E_9~0); 842677#L1101-1 assume !(0 == ~E_10~0); 841913#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 841914#L484 assume !(1 == ~m_pc~0); 842016#L484-2 is_master_triggered_~__retres1~0#1 := 0; 842017#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 842202#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 842556#L1245 assume !(0 != activate_threads_~tmp~1#1); 842557#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 842281#L503 assume !(1 == ~t1_pc~0); 842282#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 842493#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 842439#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 842033#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 841412#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 841413#L522 assume !(1 == ~t2_pc~0); 842242#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 841612#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 841613#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 842094#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 842624#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 842735#L541 assume !(1 == ~t3_pc~0); 841972#L541-2 is_transmit3_triggered_~__retres1~3#1 := 0; 841973#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 841782#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 841783#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 842249#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 842250#L560 assume !(1 == ~t4_pc~0); 841495#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 841494#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 842129#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 841378#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 841379#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 841662#L579 assume !(1 == ~t5_pc~0); 841663#L579-2 is_transmit5_triggered_~__retres1~5#1 := 0; 841439#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 841440#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 842136#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 842721#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 842757#L598 assume !(1 == ~t6_pc~0); 842469#L598-2 is_transmit6_triggered_~__retres1~6#1 := 0; 842070#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 842071#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 842590#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 842334#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 842272#L617 assume !(1 == ~t7_pc~0); 841729#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 841728#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 842018#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 842019#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 841951#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 841952#L636 assume 1 == ~t8_pc~0; 842126#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 842127#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 841915#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 841916#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 842079#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 842080#L655 assume !(1 == ~t9_pc~0); 842110#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 842111#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 841709#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 841710#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 842354#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 842355#L674 assume 1 == ~t10_pc~0; 841488#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 841489#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 842737#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 842805#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 842065#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 842066#L1119 assume !(1 == ~M_E~0); 841580#L1119-2 assume !(1 == ~T1_E~0); 841581#L1124-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 841402#L1129-1 assume !(1 == ~T3_E~0); 841403#L1134-1 assume !(1 == ~T4_E~0); 841714#L1139-1 assume !(1 == ~T5_E~0); 841715#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 841949#L1149-1 assume !(1 == ~T7_E~0); 841575#L1154-1 assume !(1 == ~T8_E~0); 841576#L1159-1 assume !(1 == ~T9_E~0); 841664#L1164-1 assume !(1 == ~T10_E~0); 842097#L1169-1 assume !(1 == ~E_1~0); 841983#L1174-1 assume !(1 == ~E_2~0); 841767#L1179-1 assume !(1 == ~E_3~0); 841652#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 841653#L1189-1 assume !(1 == ~E_5~0); 841708#L1194-1 assume !(1 == ~E_6~0); 841825#L1199-1 assume !(1 == ~E_7~0); 841774#L1204-1 assume !(1 == ~E_8~0); 841775#L1209-1 assume !(1 == ~E_9~0); 842348#L1214-1 assume !(1 == ~E_10~0); 842349#L1219-1 assume { :end_inline_reset_delta_events } true; 842810#L1520-2 [2022-07-22 02:44:02,992 INFO L754 eck$LassoCheckResult]: Loop: 842810#L1520-2 assume !false; 1142493#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1142491#L981 assume !false; 1142490#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1142481#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1142478#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1142477#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1142475#L836 assume !(0 != eval_~tmp~0#1); 1142476#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1143581#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1143580#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1143579#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1143578#L1011-3 assume !(0 == ~T2_E~0); 1143577#L1016-3 assume !(0 == ~T3_E~0); 1143576#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1143575#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1143574#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1143573#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1143572#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1143571#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1143570#L1051-3 assume !(0 == ~T10_E~0); 1143569#L1056-3 assume !(0 == ~E_1~0); 1143568#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1143567#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1143566#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1143565#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1143564#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1143563#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1143562#L1091-3 assume !(0 == ~E_8~0); 1143561#L1096-3 assume !(0 == ~E_9~0); 1143560#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1143559#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1143558#L484-33 assume !(1 == ~m_pc~0); 1143557#L484-35 is_master_triggered_~__retres1~0#1 := 0; 1143556#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1143555#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1143554#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1143553#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1143552#L503-33 assume !(1 == ~t1_pc~0); 1143551#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 1143550#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1143549#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1143548#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1143547#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1143546#L522-33 assume !(1 == ~t2_pc~0); 1143545#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 1143543#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1143542#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1143541#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1143540#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1143539#L541-33 assume !(1 == ~t3_pc~0); 1143538#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 1143537#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1143536#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1143535#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1143534#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1143533#L560-33 assume 1 == ~t4_pc~0; 1143531#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1143530#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1143529#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1143528#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 1143527#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1143526#L579-33 assume !(1 == ~t5_pc~0); 1143525#L579-35 is_transmit5_triggered_~__retres1~5#1 := 0; 1143524#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1143523#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1143522#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1143521#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1143520#L598-33 assume !(1 == ~t6_pc~0); 1143519#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 1143518#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1143517#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1143516#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1143515#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1143514#L617-33 assume !(1 == ~t7_pc~0); 1143513#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 1143511#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1143510#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1143509#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1143508#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1143507#L636-33 assume !(1 == ~t8_pc~0); 1143505#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 1143504#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1143503#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1143502#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1143501#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1143500#L655-33 assume !(1 == ~t9_pc~0); 1143499#L655-35 is_transmit9_triggered_~__retres1~9#1 := 0; 1143497#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1143496#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1143495#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1143494#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1143493#L674-33 assume !(1 == ~t10_pc~0); 1143491#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 1143490#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1143489#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1143488#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1143487#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1143486#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1143485#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1143484#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 993968#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1057489#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1143483#L1139-3 assume !(1 == ~T5_E~0); 1143482#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1143481#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1143480#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1143479#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1143478#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1142783#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1142782#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1142781#L1179-3 assume !(1 == ~E_3~0); 1142780#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1142779#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1142778#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1142777#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1142776#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1142775#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1010259#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1142774#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1142763#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1142762#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1142761#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 1142759#L1539 assume !(0 == start_simulation_~tmp~3#1); 1142757#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1142750#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1142745#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1142744#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 1142743#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1142742#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1142741#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 1142740#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 842810#L1520-2 [2022-07-22 02:44:02,992 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:44:02,992 INFO L85 PathProgramCache]: Analyzing trace with hash 75354675, now seen corresponding path program 1 times [2022-07-22 02:44:02,993 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:44:02,993 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [637470138] [2022-07-22 02:44:02,993 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:44:02,993 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:44:03,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:44:03,020 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:44:03,020 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:44:03,020 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [637470138] [2022-07-22 02:44:03,020 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [637470138] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:44:03,020 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:44:03,020 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-22 02:44:03,021 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [69388352] [2022-07-22 02:44:03,021 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:44:03,021 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-22 02:44:03,021 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-22 02:44:03,021 INFO L85 PathProgramCache]: Analyzing trace with hash -712530231, now seen corresponding path program 1 times [2022-07-22 02:44:03,021 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-22 02:44:03,022 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [264992012] [2022-07-22 02:44:03,022 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-22 02:44:03,022 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-22 02:44:03,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-22 02:44:03,042 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-22 02:44:03,042 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-22 02:44:03,042 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [264992012] [2022-07-22 02:44:03,042 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [264992012] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-22 02:44:03,042 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-22 02:44:03,042 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-22 02:44:03,043 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1384673377] [2022-07-22 02:44:03,043 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-22 02:44:03,043 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-22 02:44:03,043 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-22 02:44:03,043 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-07-22 02:44:03,044 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-07-22 02:44:03,044 INFO L87 Difference]: Start difference. First operand 345199 states and 497604 transitions. cyclomatic complexity: 152533 Second operand has 5 states, 5 states have (on average 25.2) internal successors, (126), 5 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-22 02:44:05,861 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-22 02:44:05,861 INFO L93 Difference]: Finished difference Result 841948 states and 1225537 transitions. [2022-07-22 02:44:05,861 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-07-22 02:44:05,862 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 841948 states and 1225537 transitions. [2022-07-22 02:44:11,502 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 839456 [2022-07-22 02:44:14,382 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 841948 states to 841948 states and 1225537 transitions. [2022-07-22 02:44:14,382 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 841948 [2022-07-22 02:44:14,740 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 841948 [2022-07-22 02:44:14,740 INFO L73 IsDeterministic]: Start isDeterministic. Operand 841948 states and 1225537 transitions. [2022-07-22 02:44:15,048 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-22 02:44:15,048 INFO L369 hiAutomatonCegarLoop]: Abstraction has 841948 states and 1225537 transitions. [2022-07-22 02:44:15,460 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 841948 states and 1225537 transitions. [2022-07-22 02:44:20,453 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 841948 to 355762. [2022-07-22 02:44:20,743 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 355762 states, 355762 states have (on average 1.4283903283655928) internal successors, (508167), 355761 states have internal predecessors, (508167), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)