./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/termination-memory-alloca/Urban-2013WST-Fig2-modified1000-alloca.i --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 6c24879c Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/termination-memory-alloca/Urban-2013WST-Fig2-modified1000-alloca.i -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 68763c9a2179c48c1fc2989bd19031bbd8829c13b9c8eeaf244defd8aef53cfe --- Real Ultimate output --- This is Ultimate 0.2.2-?-6c24879 [2022-07-13 03:18:29,906 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-07-13 03:18:29,934 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-07-13 03:18:29,952 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-07-13 03:18:29,953 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-07-13 03:18:29,953 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-07-13 03:18:29,954 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-07-13 03:18:29,955 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-07-13 03:18:29,956 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-07-13 03:18:29,957 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-07-13 03:18:29,958 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-07-13 03:18:29,958 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-07-13 03:18:29,959 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-07-13 03:18:29,959 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-07-13 03:18:29,971 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-07-13 03:18:29,972 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-07-13 03:18:29,972 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-07-13 03:18:29,973 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-07-13 03:18:29,974 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-07-13 03:18:29,975 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-07-13 03:18:29,976 INFO L181 SettingsManager]: Resetting HornVerifier preferences to default values [2022-07-13 03:18:29,977 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-07-13 03:18:29,978 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-07-13 03:18:29,978 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-07-13 03:18:29,979 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-07-13 03:18:29,981 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-07-13 03:18:29,981 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-07-13 03:18:29,981 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-07-13 03:18:29,981 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-07-13 03:18:29,982 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-07-13 03:18:29,982 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-07-13 03:18:29,982 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-07-13 03:18:29,983 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-07-13 03:18:29,984 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-07-13 03:18:29,984 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-07-13 03:18:29,985 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-07-13 03:18:29,985 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-07-13 03:18:29,986 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-07-13 03:18:29,986 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-07-13 03:18:29,986 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-07-13 03:18:29,987 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-07-13 03:18:29,989 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-07-13 03:18:29,992 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-64bit-Automizer_Default.epf [2022-07-13 03:18:30,006 INFO L113 SettingsManager]: Loading preferences was successful [2022-07-13 03:18:30,013 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-07-13 03:18:30,013 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-07-13 03:18:30,013 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-07-13 03:18:30,015 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-07-13 03:18:30,015 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-07-13 03:18:30,015 INFO L138 SettingsManager]: * Use SBE=true [2022-07-13 03:18:30,015 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-07-13 03:18:30,015 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-07-13 03:18:30,016 INFO L138 SettingsManager]: * Use old map elimination=false [2022-07-13 03:18:30,016 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-07-13 03:18:30,016 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-07-13 03:18:30,016 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-07-13 03:18:30,017 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-07-13 03:18:30,017 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-07-13 03:18:30,018 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-07-13 03:18:30,018 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-07-13 03:18:30,018 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-07-13 03:18:30,018 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-07-13 03:18:30,018 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-07-13 03:18:30,018 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-07-13 03:18:30,018 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-07-13 03:18:30,019 INFO L138 SettingsManager]: * Use constant arrays=true [2022-07-13 03:18:30,019 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-07-13 03:18:30,019 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-07-13 03:18:30,019 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-07-13 03:18:30,019 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-07-13 03:18:30,020 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-07-13 03:18:30,020 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-07-13 03:18:30,020 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 68763c9a2179c48c1fc2989bd19031bbd8829c13b9c8eeaf244defd8aef53cfe [2022-07-13 03:18:30,212 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-07-13 03:18:30,232 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-07-13 03:18:30,234 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-07-13 03:18:30,235 INFO L271 PluginConnector]: Initializing CDTParser... [2022-07-13 03:18:30,235 INFO L275 PluginConnector]: CDTParser initialized [2022-07-13 03:18:30,236 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/termination-memory-alloca/Urban-2013WST-Fig2-modified1000-alloca.i [2022-07-13 03:18:30,291 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/81e27dc5f/3fdb73e2b9d342218a36be7054e039d8/FLAG2526bf631 [2022-07-13 03:18:30,676 INFO L306 CDTParser]: Found 1 translation units. [2022-07-13 03:18:30,678 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/termination-memory-alloca/Urban-2013WST-Fig2-modified1000-alloca.i [2022-07-13 03:18:30,687 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/81e27dc5f/3fdb73e2b9d342218a36be7054e039d8/FLAG2526bf631 [2022-07-13 03:18:31,041 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/81e27dc5f/3fdb73e2b9d342218a36be7054e039d8 [2022-07-13 03:18:31,044 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-07-13 03:18:31,045 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-07-13 03:18:31,046 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-07-13 03:18:31,046 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-07-13 03:18:31,048 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-07-13 03:18:31,049 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.07 03:18:31" (1/1) ... [2022-07-13 03:18:31,050 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@50a3613e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.07 03:18:31, skipping insertion in model container [2022-07-13 03:18:31,050 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.07 03:18:31" (1/1) ... [2022-07-13 03:18:31,054 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-07-13 03:18:31,081 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-07-13 03:18:31,323 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-13 03:18:31,330 INFO L203 MainTranslator]: Completed pre-run [2022-07-13 03:18:31,358 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-13 03:18:31,386 INFO L208 MainTranslator]: Completed translation [2022-07-13 03:18:31,386 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.07 03:18:31 WrapperNode [2022-07-13 03:18:31,386 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-07-13 03:18:31,387 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-07-13 03:18:31,387 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-07-13 03:18:31,387 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-07-13 03:18:31,392 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.07 03:18:31" (1/1) ... [2022-07-13 03:18:31,406 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.07 03:18:31" (1/1) ... [2022-07-13 03:18:31,419 INFO L137 Inliner]: procedures = 109, calls = 13, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 34 [2022-07-13 03:18:31,420 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-07-13 03:18:31,421 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-07-13 03:18:31,421 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-07-13 03:18:31,421 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-07-13 03:18:31,426 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.07 03:18:31" (1/1) ... [2022-07-13 03:18:31,426 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.07 03:18:31" (1/1) ... [2022-07-13 03:18:31,436 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.07 03:18:31" (1/1) ... [2022-07-13 03:18:31,436 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.07 03:18:31" (1/1) ... [2022-07-13 03:18:31,442 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.07 03:18:31" (1/1) ... [2022-07-13 03:18:31,445 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.07 03:18:31" (1/1) ... [2022-07-13 03:18:31,448 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.07 03:18:31" (1/1) ... [2022-07-13 03:18:31,449 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-07-13 03:18:31,450 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-07-13 03:18:31,451 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-07-13 03:18:31,451 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-07-13 03:18:31,452 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.07 03:18:31" (1/1) ... [2022-07-13 03:18:31,456 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-13 03:18:31,464 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-13 03:18:31,483 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-13 03:18:31,499 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-07-13 03:18:31,518 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-07-13 03:18:31,518 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-07-13 03:18:31,518 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-07-13 03:18:31,518 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-07-13 03:18:31,518 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-07-13 03:18:31,519 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-07-13 03:18:31,568 INFO L234 CfgBuilder]: Building ICFG [2022-07-13 03:18:31,569 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-07-13 03:18:31,679 INFO L275 CfgBuilder]: Performing block encoding [2022-07-13 03:18:31,682 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-07-13 03:18:31,683 INFO L299 CfgBuilder]: Removed 2 assume(true) statements. [2022-07-13 03:18:31,688 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.07 03:18:31 BoogieIcfgContainer [2022-07-13 03:18:31,688 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-07-13 03:18:31,692 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-07-13 03:18:31,692 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-07-13 03:18:31,694 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-07-13 03:18:31,694 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-13 03:18:31,695 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.07 03:18:31" (1/3) ... [2022-07-13 03:18:31,695 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7be3dd69 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.07 03:18:31, skipping insertion in model container [2022-07-13 03:18:31,696 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-13 03:18:31,696 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.07 03:18:31" (2/3) ... [2022-07-13 03:18:31,696 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7be3dd69 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.07 03:18:31, skipping insertion in model container [2022-07-13 03:18:31,696 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-13 03:18:31,696 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.07 03:18:31" (3/3) ... [2022-07-13 03:18:31,697 INFO L354 chiAutomizerObserver]: Analyzing ICFG Urban-2013WST-Fig2-modified1000-alloca.i [2022-07-13 03:18:31,739 INFO L255 stractBuchiCegarLoop]: Interprodecural is true [2022-07-13 03:18:31,739 INFO L256 stractBuchiCegarLoop]: Hoare is false [2022-07-13 03:18:31,739 INFO L257 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-07-13 03:18:31,739 INFO L258 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-07-13 03:18:31,739 INFO L259 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-07-13 03:18:31,740 INFO L260 stractBuchiCegarLoop]: Difference is false [2022-07-13 03:18:31,740 INFO L261 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-07-13 03:18:31,740 INFO L265 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-07-13 03:18:31,742 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 11 states, 10 states have (on average 1.4) internal successors, (14), 10 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 03:18:31,752 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2022-07-13 03:18:31,753 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-13 03:18:31,753 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-13 03:18:31,756 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-07-13 03:18:31,756 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2022-07-13 03:18:31,757 INFO L287 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-07-13 03:18:31,757 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 11 states, 10 states have (on average 1.4) internal successors, (14), 10 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 03:18:31,758 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2022-07-13 03:18:31,758 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-13 03:18:31,758 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-13 03:18:31,758 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-07-13 03:18:31,758 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2022-07-13 03:18:31,762 INFO L752 eck$LassoCheckResult]: Stem: 4#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 10#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem6#1, main_#t~mem5#1, main_#t~mem7#1, main_#t~mem4#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset; 6#L549-3true [2022-07-13 03:18:31,763 INFO L754 eck$LassoCheckResult]: Loop: 6#L549-3true call main_#t~mem4#1 := read~int(main_~x1~0#1.base, main_~x1~0#1.offset, 4); 2#L549-1true assume !!(main_#t~mem4#1 <= 10);havoc main_#t~mem4#1;call write~int(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4); 7#L551-3true assume !true; 11#L551-4true call main_#t~mem7#1 := read~int(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1; 6#L549-3true [2022-07-13 03:18:31,766 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 03:18:31,766 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times [2022-07-13 03:18:31,788 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 03:18:31,788 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [769849298] [2022-07-13 03:18:31,789 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 03:18:31,789 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 03:18:31,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-13 03:18:31,877 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-13 03:18:31,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-13 03:18:31,907 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-13 03:18:31,909 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 03:18:31,909 INFO L85 PathProgramCache]: Analyzing trace with hash 1144360, now seen corresponding path program 1 times [2022-07-13 03:18:31,910 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 03:18:31,910 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [285813423] [2022-07-13 03:18:31,911 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 03:18:31,911 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 03:18:31,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 03:18:31,957 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 03:18:31,958 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 03:18:31,958 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [285813423] [2022-07-13 03:18:31,959 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [285813423] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 03:18:31,959 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 03:18:31,959 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-13 03:18:31,959 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1327065352] [2022-07-13 03:18:31,960 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 03:18:31,962 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-13 03:18:31,963 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-13 03:18:31,986 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-07-13 03:18:31,987 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-07-13 03:18:31,988 INFO L87 Difference]: Start difference. First operand has 11 states, 10 states have (on average 1.4) internal successors, (14), 10 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 2.0) internal successors, (4), 2 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 03:18:31,992 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-13 03:18:31,992 INFO L93 Difference]: Finished difference Result 11 states and 12 transitions. [2022-07-13 03:18:31,993 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-07-13 03:18:31,998 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11 states and 12 transitions. [2022-07-13 03:18:32,000 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2022-07-13 03:18:32,002 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11 states to 7 states and 8 transitions. [2022-07-13 03:18:32,003 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2022-07-13 03:18:32,003 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2022-07-13 03:18:32,003 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7 states and 8 transitions. [2022-07-13 03:18:32,004 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-13 03:18:32,004 INFO L369 hiAutomatonCegarLoop]: Abstraction has 7 states and 8 transitions. [2022-07-13 03:18:32,013 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7 states and 8 transitions. [2022-07-13 03:18:32,018 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7 to 7. [2022-07-13 03:18:32,018 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7 states, 7 states have (on average 1.1428571428571428) internal successors, (8), 6 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 03:18:32,019 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 8 transitions. [2022-07-13 03:18:32,019 INFO L392 hiAutomatonCegarLoop]: Abstraction has 7 states and 8 transitions. [2022-07-13 03:18:32,020 INFO L374 stractBuchiCegarLoop]: Abstraction has 7 states and 8 transitions. [2022-07-13 03:18:32,020 INFO L287 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-07-13 03:18:32,020 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7 states and 8 transitions. [2022-07-13 03:18:32,021 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2022-07-13 03:18:32,021 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-13 03:18:32,021 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-13 03:18:32,021 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-07-13 03:18:32,021 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2022-07-13 03:18:32,022 INFO L752 eck$LassoCheckResult]: Stem: 32#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 33#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem6#1, main_#t~mem5#1, main_#t~mem7#1, main_#t~mem4#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset; 34#L549-3 [2022-07-13 03:18:32,022 INFO L754 eck$LassoCheckResult]: Loop: 34#L549-3 call main_#t~mem4#1 := read~int(main_~x1~0#1.base, main_~x1~0#1.offset, 4); 30#L549-1 assume !!(main_#t~mem4#1 <= 10);havoc main_#t~mem4#1;call write~int(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4); 31#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 35#L551-1 assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1; 36#L551-4 call main_#t~mem7#1 := read~int(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1; 34#L549-3 [2022-07-13 03:18:32,023 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 03:18:32,023 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 2 times [2022-07-13 03:18:32,024 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 03:18:32,024 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1912739659] [2022-07-13 03:18:32,030 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 03:18:32,031 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 03:18:32,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-13 03:18:32,059 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-13 03:18:32,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-13 03:18:32,068 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-13 03:18:32,069 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 03:18:32,070 INFO L85 PathProgramCache]: Analyzing trace with hash 35468273, now seen corresponding path program 1 times [2022-07-13 03:18:32,070 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 03:18:32,070 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [431759668] [2022-07-13 03:18:32,070 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 03:18:32,070 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 03:18:32,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 03:18:32,129 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 03:18:32,131 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 03:18:32,131 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [431759668] [2022-07-13 03:18:32,131 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [431759668] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 03:18:32,131 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 03:18:32,132 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-07-13 03:18:32,133 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1070917857] [2022-07-13 03:18:32,133 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 03:18:32,133 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-13 03:18:32,133 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-13 03:18:32,136 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-13 03:18:32,136 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-13 03:18:32,137 INFO L87 Difference]: Start difference. First operand 7 states and 8 transitions. cyclomatic complexity: 2 Second operand has 4 states, 4 states have (on average 1.25) internal successors, (5), 4 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 03:18:32,161 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-13 03:18:32,161 INFO L93 Difference]: Finished difference Result 9 states and 10 transitions. [2022-07-13 03:18:32,161 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-13 03:18:32,162 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9 states and 10 transitions. [2022-07-13 03:18:32,162 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 7 [2022-07-13 03:18:32,163 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9 states to 9 states and 10 transitions. [2022-07-13 03:18:32,163 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2022-07-13 03:18:32,163 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2022-07-13 03:18:32,163 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9 states and 10 transitions. [2022-07-13 03:18:32,163 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-13 03:18:32,163 INFO L369 hiAutomatonCegarLoop]: Abstraction has 9 states and 10 transitions. [2022-07-13 03:18:32,163 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9 states and 10 transitions. [2022-07-13 03:18:32,164 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9 to 9. [2022-07-13 03:18:32,164 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9 states, 9 states have (on average 1.1111111111111112) internal successors, (10), 8 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 03:18:32,165 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 10 transitions. [2022-07-13 03:18:32,165 INFO L392 hiAutomatonCegarLoop]: Abstraction has 9 states and 10 transitions. [2022-07-13 03:18:32,165 INFO L374 stractBuchiCegarLoop]: Abstraction has 9 states and 10 transitions. [2022-07-13 03:18:32,165 INFO L287 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-07-13 03:18:32,165 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9 states and 10 transitions. [2022-07-13 03:18:32,166 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 7 [2022-07-13 03:18:32,166 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-13 03:18:32,166 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-13 03:18:32,167 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-07-13 03:18:32,167 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1, 1, 1, 1] [2022-07-13 03:18:32,167 INFO L752 eck$LassoCheckResult]: Stem: 57#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 58#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem6#1, main_#t~mem5#1, main_#t~mem7#1, main_#t~mem4#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset; 59#L549-3 [2022-07-13 03:18:32,167 INFO L754 eck$LassoCheckResult]: Loop: 59#L549-3 call main_#t~mem4#1 := read~int(main_~x1~0#1.base, main_~x1~0#1.offset, 4); 55#L549-1 assume !!(main_#t~mem4#1 <= 10);havoc main_#t~mem4#1;call write~int(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4); 56#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 60#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 61#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 63#L551-1 assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1; 62#L551-4 call main_#t~mem7#1 := read~int(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1; 59#L549-3 [2022-07-13 03:18:32,167 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 03:18:32,167 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 3 times [2022-07-13 03:18:32,168 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 03:18:32,168 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1106925446] [2022-07-13 03:18:32,168 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 03:18:32,168 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 03:18:32,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-13 03:18:32,190 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-13 03:18:32,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-13 03:18:32,197 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-13 03:18:32,197 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 03:18:32,197 INFO L85 PathProgramCache]: Analyzing trace with hash -274676436, now seen corresponding path program 1 times [2022-07-13 03:18:32,197 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 03:18:32,197 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1083325304] [2022-07-13 03:18:32,198 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 03:18:32,198 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 03:18:32,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 03:18:32,255 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 03:18:32,256 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 03:18:32,256 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1083325304] [2022-07-13 03:18:32,256 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1083325304] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-13 03:18:32,256 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [993770060] [2022-07-13 03:18:32,257 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 03:18:32,257 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-13 03:18:32,257 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-13 03:18:32,273 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-13 03:18:32,314 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-07-13 03:18:32,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 03:18:32,340 INFO L263 TraceCheckSpWp]: Trace formula consists of 47 conjuncts, 8 conjunts are in the unsatisfiable core [2022-07-13 03:18:32,342 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-13 03:18:32,378 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2022-07-13 03:18:32,397 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:32,406 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-07-13 03:18:32,409 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 03:18:32,409 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-13 03:18:32,435 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 03:18:32,435 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [993770060] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-13 03:18:32,435 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-13 03:18:32,436 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 5, 5] total 10 [2022-07-13 03:18:32,436 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1625307246] [2022-07-13 03:18:32,436 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-13 03:18:32,436 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-13 03:18:32,436 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-13 03:18:32,437 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2022-07-13 03:18:32,437 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=55, Unknown=0, NotChecked=0, Total=90 [2022-07-13 03:18:32,437 INFO L87 Difference]: Start difference. First operand 9 states and 10 transitions. cyclomatic complexity: 2 Second operand has 10 states, 10 states have (on average 1.5) internal successors, (15), 10 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 03:18:32,477 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-13 03:18:32,478 INFO L93 Difference]: Finished difference Result 15 states and 16 transitions. [2022-07-13 03:18:32,478 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-07-13 03:18:32,478 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15 states and 16 transitions. [2022-07-13 03:18:32,479 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 13 [2022-07-13 03:18:32,479 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15 states to 15 states and 16 transitions. [2022-07-13 03:18:32,479 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15 [2022-07-13 03:18:32,480 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15 [2022-07-13 03:18:32,480 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15 states and 16 transitions. [2022-07-13 03:18:32,480 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-13 03:18:32,480 INFO L369 hiAutomatonCegarLoop]: Abstraction has 15 states and 16 transitions. [2022-07-13 03:18:32,480 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15 states and 16 transitions. [2022-07-13 03:18:32,481 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15 to 15. [2022-07-13 03:18:32,481 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15 states, 15 states have (on average 1.0666666666666667) internal successors, (16), 14 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 03:18:32,481 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 16 transitions. [2022-07-13 03:18:32,481 INFO L392 hiAutomatonCegarLoop]: Abstraction has 15 states and 16 transitions. [2022-07-13 03:18:32,481 INFO L374 stractBuchiCegarLoop]: Abstraction has 15 states and 16 transitions. [2022-07-13 03:18:32,482 INFO L287 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-07-13 03:18:32,482 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15 states and 16 transitions. [2022-07-13 03:18:32,482 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 13 [2022-07-13 03:18:32,482 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-13 03:18:32,482 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-13 03:18:32,483 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-07-13 03:18:32,483 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [5, 4, 1, 1, 1, 1] [2022-07-13 03:18:32,483 INFO L752 eck$LassoCheckResult]: Stem: 136#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 137#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem6#1, main_#t~mem5#1, main_#t~mem7#1, main_#t~mem4#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset; 138#L549-3 [2022-07-13 03:18:32,483 INFO L754 eck$LassoCheckResult]: Loop: 138#L549-3 call main_#t~mem4#1 := read~int(main_~x1~0#1.base, main_~x1~0#1.offset, 4); 134#L549-1 assume !!(main_#t~mem4#1 <= 10);havoc main_#t~mem4#1;call write~int(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4); 135#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 139#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 140#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 141#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 148#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 147#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 146#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 145#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 144#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 143#L551-1 assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1; 142#L551-4 call main_#t~mem7#1 := read~int(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1; 138#L549-3 [2022-07-13 03:18:32,483 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 03:18:32,483 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 4 times [2022-07-13 03:18:32,484 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 03:18:32,484 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1858872843] [2022-07-13 03:18:32,484 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 03:18:32,484 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 03:18:32,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-13 03:18:32,489 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-13 03:18:32,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-13 03:18:32,493 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-13 03:18:32,493 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 03:18:32,493 INFO L85 PathProgramCache]: Analyzing trace with hash 351922269, now seen corresponding path program 2 times [2022-07-13 03:18:32,493 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 03:18:32,494 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [601736785] [2022-07-13 03:18:32,494 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 03:18:32,494 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 03:18:32,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 03:18:32,590 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 03:18:32,590 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 03:18:32,591 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [601736785] [2022-07-13 03:18:32,591 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [601736785] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-13 03:18:32,592 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1024103918] [2022-07-13 03:18:32,592 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-07-13 03:18:32,592 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-13 03:18:32,592 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-13 03:18:32,617 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-13 03:18:32,635 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-07-13 03:18:32,700 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-07-13 03:18:32,700 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-07-13 03:18:32,701 INFO L263 TraceCheckSpWp]: Trace formula consists of 92 conjuncts, 17 conjunts are in the unsatisfiable core [2022-07-13 03:18:32,703 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-13 03:18:32,710 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2022-07-13 03:18:32,731 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:32,740 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:32,749 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:32,758 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:32,763 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-07-13 03:18:32,765 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 03:18:32,766 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-13 03:18:32,832 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 03:18:32,832 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1024103918] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-13 03:18:32,832 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-13 03:18:32,832 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 8, 8] total 19 [2022-07-13 03:18:32,832 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1368786040] [2022-07-13 03:18:32,832 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-13 03:18:32,833 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-13 03:18:32,833 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-13 03:18:32,833 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2022-07-13 03:18:32,834 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=140, Invalid=202, Unknown=0, NotChecked=0, Total=342 [2022-07-13 03:18:32,834 INFO L87 Difference]: Start difference. First operand 15 states and 16 transitions. cyclomatic complexity: 2 Second operand has 19 states, 19 states have (on average 1.736842105263158) internal successors, (33), 19 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 03:18:32,928 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-13 03:18:32,928 INFO L93 Difference]: Finished difference Result 27 states and 28 transitions. [2022-07-13 03:18:32,929 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2022-07-13 03:18:32,929 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27 states and 28 transitions. [2022-07-13 03:18:32,930 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 25 [2022-07-13 03:18:32,930 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27 states to 27 states and 28 transitions. [2022-07-13 03:18:32,930 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27 [2022-07-13 03:18:32,930 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27 [2022-07-13 03:18:32,931 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27 states and 28 transitions. [2022-07-13 03:18:32,931 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-13 03:18:32,931 INFO L369 hiAutomatonCegarLoop]: Abstraction has 27 states and 28 transitions. [2022-07-13 03:18:32,931 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states and 28 transitions. [2022-07-13 03:18:32,932 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 27. [2022-07-13 03:18:32,932 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27 states, 27 states have (on average 1.037037037037037) internal successors, (28), 26 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 03:18:32,932 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 28 transitions. [2022-07-13 03:18:32,932 INFO L392 hiAutomatonCegarLoop]: Abstraction has 27 states and 28 transitions. [2022-07-13 03:18:32,932 INFO L374 stractBuchiCegarLoop]: Abstraction has 27 states and 28 transitions. [2022-07-13 03:18:32,933 INFO L287 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-07-13 03:18:32,933 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27 states and 28 transitions. [2022-07-13 03:18:32,933 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 25 [2022-07-13 03:18:32,933 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-13 03:18:32,933 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-13 03:18:32,933 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-07-13 03:18:32,933 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [11, 10, 1, 1, 1, 1] [2022-07-13 03:18:32,934 INFO L752 eck$LassoCheckResult]: Stem: 284#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 285#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem6#1, main_#t~mem5#1, main_#t~mem7#1, main_#t~mem4#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset; 286#L549-3 [2022-07-13 03:18:32,934 INFO L754 eck$LassoCheckResult]: Loop: 286#L549-3 call main_#t~mem4#1 := read~int(main_~x1~0#1.base, main_~x1~0#1.offset, 4); 282#L549-1 assume !!(main_#t~mem4#1 <= 10);havoc main_#t~mem4#1;call write~int(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4); 283#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 287#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 288#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 289#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 308#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 307#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 306#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 305#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 304#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 303#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 302#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 301#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 300#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 299#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 298#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 297#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 296#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 295#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 294#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 293#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 292#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 291#L551-1 assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1; 290#L551-4 call main_#t~mem7#1 := read~int(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1; 286#L549-3 [2022-07-13 03:18:32,934 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 03:18:32,934 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 5 times [2022-07-13 03:18:32,934 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 03:18:32,934 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2023353699] [2022-07-13 03:18:32,934 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 03:18:32,934 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 03:18:32,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-13 03:18:32,941 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-13 03:18:32,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-13 03:18:32,944 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-13 03:18:32,944 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 03:18:32,944 INFO L85 PathProgramCache]: Analyzing trace with hash 646907007, now seen corresponding path program 3 times [2022-07-13 03:18:32,944 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 03:18:32,944 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1080044235] [2022-07-13 03:18:32,945 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 03:18:32,945 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 03:18:32,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 03:18:33,226 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 03:18:33,226 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 03:18:33,226 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1080044235] [2022-07-13 03:18:33,226 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1080044235] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-13 03:18:33,226 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [78992706] [2022-07-13 03:18:33,226 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-07-13 03:18:33,226 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-13 03:18:33,227 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-13 03:18:33,252 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-13 03:18:33,264 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2022-07-13 03:18:33,348 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2022-07-13 03:18:33,348 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-07-13 03:18:33,350 INFO L263 TraceCheckSpWp]: Trace formula consists of 182 conjuncts, 35 conjunts are in the unsatisfiable core [2022-07-13 03:18:33,353 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-13 03:18:33,359 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2022-07-13 03:18:33,367 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:33,375 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:33,382 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:33,390 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:33,397 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:33,405 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:33,413 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:33,420 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:33,427 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:33,435 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:33,439 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-07-13 03:18:33,441 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 03:18:33,441 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-13 03:18:33,635 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 03:18:33,636 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [78992706] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-13 03:18:33,636 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-13 03:18:33,636 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 14, 14] total 36 [2022-07-13 03:18:33,636 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1223014681] [2022-07-13 03:18:33,636 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-13 03:18:33,637 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-13 03:18:33,637 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-13 03:18:33,637 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2022-07-13 03:18:33,638 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=541, Invalid=719, Unknown=0, NotChecked=0, Total=1260 [2022-07-13 03:18:33,638 INFO L87 Difference]: Start difference. First operand 27 states and 28 transitions. cyclomatic complexity: 2 Second operand has 36 states, 36 states have (on average 1.8888888888888888) internal successors, (68), 36 states have internal predecessors, (68), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 03:18:33,869 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-13 03:18:33,869 INFO L93 Difference]: Finished difference Result 51 states and 52 transitions. [2022-07-13 03:18:33,869 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2022-07-13 03:18:33,870 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51 states and 52 transitions. [2022-07-13 03:18:33,871 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 49 [2022-07-13 03:18:33,871 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51 states to 51 states and 52 transitions. [2022-07-13 03:18:33,871 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 51 [2022-07-13 03:18:33,871 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 51 [2022-07-13 03:18:33,871 INFO L73 IsDeterministic]: Start isDeterministic. Operand 51 states and 52 transitions. [2022-07-13 03:18:33,872 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-13 03:18:33,872 INFO L369 hiAutomatonCegarLoop]: Abstraction has 51 states and 52 transitions. [2022-07-13 03:18:33,872 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51 states and 52 transitions. [2022-07-13 03:18:33,873 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51 to 51. [2022-07-13 03:18:33,874 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51 states, 51 states have (on average 1.0196078431372548) internal successors, (52), 50 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 03:18:33,874 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 52 transitions. [2022-07-13 03:18:33,874 INFO L392 hiAutomatonCegarLoop]: Abstraction has 51 states and 52 transitions. [2022-07-13 03:18:33,874 INFO L374 stractBuchiCegarLoop]: Abstraction has 51 states and 52 transitions. [2022-07-13 03:18:33,874 INFO L287 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-07-13 03:18:33,874 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51 states and 52 transitions. [2022-07-13 03:18:33,875 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 49 [2022-07-13 03:18:33,875 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-13 03:18:33,875 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-13 03:18:33,875 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-07-13 03:18:33,875 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [23, 22, 1, 1, 1, 1] [2022-07-13 03:18:33,876 INFO L752 eck$LassoCheckResult]: Stem: 569#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 570#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem6#1, main_#t~mem5#1, main_#t~mem7#1, main_#t~mem4#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset; 571#L549-3 [2022-07-13 03:18:33,876 INFO L754 eck$LassoCheckResult]: Loop: 571#L549-3 call main_#t~mem4#1 := read~int(main_~x1~0#1.base, main_~x1~0#1.offset, 4); 567#L549-1 assume !!(main_#t~mem4#1 <= 10);havoc main_#t~mem4#1;call write~int(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4); 568#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 574#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 572#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 573#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 617#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 616#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 615#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 614#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 613#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 612#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 611#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 610#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 609#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 608#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 607#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 606#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 605#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 604#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 603#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 602#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 601#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 600#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 599#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 598#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 597#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 596#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 595#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 594#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 593#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 592#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 591#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 590#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 589#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 588#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 587#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 586#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 585#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 584#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 583#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 582#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 581#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 580#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 579#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 578#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 577#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 576#L551-1 assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1; 575#L551-4 call main_#t~mem7#1 := read~int(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1; 571#L549-3 [2022-07-13 03:18:33,876 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 03:18:33,876 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 6 times [2022-07-13 03:18:33,876 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 03:18:33,876 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [627246044] [2022-07-13 03:18:33,876 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 03:18:33,876 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 03:18:33,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-13 03:18:33,881 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-13 03:18:33,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-13 03:18:33,884 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-13 03:18:33,884 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 03:18:33,884 INFO L85 PathProgramCache]: Analyzing trace with hash 1009537987, now seen corresponding path program 4 times [2022-07-13 03:18:33,884 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 03:18:33,885 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1153983131] [2022-07-13 03:18:33,885 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 03:18:33,885 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 03:18:33,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 03:18:34,581 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 03:18:34,581 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 03:18:34,581 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1153983131] [2022-07-13 03:18:34,582 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1153983131] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-13 03:18:34,582 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [309107164] [2022-07-13 03:18:34,582 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-07-13 03:18:34,582 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-13 03:18:34,582 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-13 03:18:34,618 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-13 03:18:34,619 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2022-07-13 03:18:34,839 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-07-13 03:18:34,839 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-07-13 03:18:34,842 INFO L263 TraceCheckSpWp]: Trace formula consists of 362 conjuncts, 71 conjunts are in the unsatisfiable core [2022-07-13 03:18:34,848 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-13 03:18:34,853 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2022-07-13 03:18:34,873 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:34,880 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:34,888 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:34,895 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:34,902 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:34,910 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:34,917 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:34,926 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:34,934 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:34,940 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:34,961 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:34,967 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:34,976 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:34,982 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:34,987 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:34,993 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:35,001 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:35,007 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:35,013 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:35,019 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:35,026 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:35,032 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:35,036 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-07-13 03:18:35,038 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 03:18:35,039 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-13 03:18:35,673 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 03:18:35,673 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [309107164] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-13 03:18:35,673 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-13 03:18:35,673 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 26, 26] total 73 [2022-07-13 03:18:35,673 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2000768964] [2022-07-13 03:18:35,674 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-13 03:18:35,674 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-13 03:18:35,674 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-13 03:18:35,675 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 73 interpolants. [2022-07-13 03:18:35,676 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2282, Invalid=2974, Unknown=0, NotChecked=0, Total=5256 [2022-07-13 03:18:35,677 INFO L87 Difference]: Start difference. First operand 51 states and 52 transitions. cyclomatic complexity: 2 Second operand has 73 states, 73 states have (on average 1.9315068493150684) internal successors, (141), 73 states have internal predecessors, (141), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 03:18:36,383 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-13 03:18:36,383 INFO L93 Difference]: Finished difference Result 99 states and 100 transitions. [2022-07-13 03:18:36,384 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 94 states. [2022-07-13 03:18:36,384 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 99 states and 100 transitions. [2022-07-13 03:18:36,385 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2022-07-13 03:18:36,386 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 99 states to 99 states and 100 transitions. [2022-07-13 03:18:36,386 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 99 [2022-07-13 03:18:36,386 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 99 [2022-07-13 03:18:36,386 INFO L73 IsDeterministic]: Start isDeterministic. Operand 99 states and 100 transitions. [2022-07-13 03:18:36,387 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-13 03:18:36,387 INFO L369 hiAutomatonCegarLoop]: Abstraction has 99 states and 100 transitions. [2022-07-13 03:18:36,387 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99 states and 100 transitions. [2022-07-13 03:18:36,389 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99 to 99. [2022-07-13 03:18:36,390 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99 states, 99 states have (on average 1.0101010101010102) internal successors, (100), 98 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 03:18:36,390 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 100 transitions. [2022-07-13 03:18:36,390 INFO L392 hiAutomatonCegarLoop]: Abstraction has 99 states and 100 transitions. [2022-07-13 03:18:36,390 INFO L374 stractBuchiCegarLoop]: Abstraction has 99 states and 100 transitions. [2022-07-13 03:18:36,390 INFO L287 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-07-13 03:18:36,390 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99 states and 100 transitions. [2022-07-13 03:18:36,391 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2022-07-13 03:18:36,391 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-13 03:18:36,391 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-13 03:18:36,392 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-07-13 03:18:36,392 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [47, 46, 1, 1, 1, 1] [2022-07-13 03:18:36,392 INFO L752 eck$LassoCheckResult]: Stem: 1131#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1132#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem6#1, main_#t~mem5#1, main_#t~mem7#1, main_#t~mem4#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset; 1133#L549-3 [2022-07-13 03:18:36,392 INFO L754 eck$LassoCheckResult]: Loop: 1133#L549-3 call main_#t~mem4#1 := read~int(main_~x1~0#1.base, main_~x1~0#1.offset, 4); 1129#L549-1 assume !!(main_#t~mem4#1 <= 10);havoc main_#t~mem4#1;call write~int(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1130#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1136#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1134#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1135#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1227#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1226#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1225#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1224#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1223#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1222#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1221#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1220#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1219#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1218#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1217#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1216#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1215#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1214#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1213#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1212#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1211#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1210#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1209#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1208#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1207#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1206#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1205#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1204#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1203#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1202#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1201#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1200#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1199#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1198#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1197#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1196#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1195#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1194#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1193#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1192#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1191#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1190#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1189#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1188#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1187#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1186#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1185#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1184#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1183#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1182#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1181#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1180#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1179#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1178#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1177#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1176#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1175#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1174#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1173#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1172#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1171#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1170#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1169#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1168#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1167#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1166#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1165#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1164#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1163#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1162#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1161#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1160#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1159#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1158#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1157#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1156#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1155#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1154#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1153#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1152#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1151#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1150#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1149#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1148#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1147#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1146#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1145#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1144#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1143#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1142#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1141#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1140#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 1139#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 1138#L551-1 assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1; 1137#L551-4 call main_#t~mem7#1 := read~int(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1; 1133#L549-3 [2022-07-13 03:18:36,403 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 03:18:36,403 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 7 times [2022-07-13 03:18:36,404 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 03:18:36,404 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [203584411] [2022-07-13 03:18:36,404 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 03:18:36,404 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 03:18:36,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-13 03:18:36,408 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-13 03:18:36,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-13 03:18:36,411 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-13 03:18:36,411 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 03:18:36,411 INFO L85 PathProgramCache]: Analyzing trace with hash 1846627915, now seen corresponding path program 5 times [2022-07-13 03:18:36,411 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 03:18:36,411 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [246275013] [2022-07-13 03:18:36,411 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 03:18:36,411 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 03:18:36,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 03:18:38,625 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 03:18:38,625 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 03:18:38,625 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [246275013] [2022-07-13 03:18:38,625 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [246275013] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-13 03:18:38,625 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1509428435] [2022-07-13 03:18:38,625 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-07-13 03:18:38,625 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-13 03:18:38,626 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-13 03:18:38,628 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-13 03:18:38,636 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2022-07-13 03:18:47,286 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) [2022-07-13 03:18:47,286 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-07-13 03:18:47,302 INFO L263 TraceCheckSpWp]: Trace formula consists of 722 conjuncts, 143 conjunts are in the unsatisfiable core [2022-07-13 03:18:47,314 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-13 03:18:47,320 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2022-07-13 03:18:47,367 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,374 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,380 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,386 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,400 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,407 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,414 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,420 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,426 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,432 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,438 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,444 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,450 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,458 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,465 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,470 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,480 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,489 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,499 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,504 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,511 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,518 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,526 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,534 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,546 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,557 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,566 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,576 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,585 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,592 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,600 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,605 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,614 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,623 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,631 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,636 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,644 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,649 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,655 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,661 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,670 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,680 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,688 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,694 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,699 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,706 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:18:47,709 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-07-13 03:18:47,712 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 03:18:47,712 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-13 03:18:50,195 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 03:18:50,195 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1509428435] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-13 03:18:50,196 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-13 03:18:50,196 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [96, 50, 50] total 145 [2022-07-13 03:18:50,196 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1012744553] [2022-07-13 03:18:50,196 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-13 03:18:50,197 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-13 03:18:50,197 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-13 03:18:50,200 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 145 interpolants. [2022-07-13 03:18:50,207 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9170, Invalid=11710, Unknown=0, NotChecked=0, Total=20880 [2022-07-13 03:18:50,208 INFO L87 Difference]: Start difference. First operand 99 states and 100 transitions. cyclomatic complexity: 2 Second operand has 145 states, 145 states have (on average 1.9655172413793103) internal successors, (285), 145 states have internal predecessors, (285), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 03:18:52,399 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-13 03:18:52,399 INFO L93 Difference]: Finished difference Result 195 states and 196 transitions. [2022-07-13 03:18:52,399 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 190 states. [2022-07-13 03:18:52,401 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 195 states and 196 transitions. [2022-07-13 03:18:52,405 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 193 [2022-07-13 03:18:52,411 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 195 states to 195 states and 196 transitions. [2022-07-13 03:18:52,411 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 195 [2022-07-13 03:18:52,412 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 195 [2022-07-13 03:18:52,412 INFO L73 IsDeterministic]: Start isDeterministic. Operand 195 states and 196 transitions. [2022-07-13 03:18:52,417 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-13 03:18:52,417 INFO L369 hiAutomatonCegarLoop]: Abstraction has 195 states and 196 transitions. [2022-07-13 03:18:52,418 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 195 states and 196 transitions. [2022-07-13 03:18:52,424 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 195 to 195. [2022-07-13 03:18:52,425 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 195 states, 195 states have (on average 1.005128205128205) internal successors, (196), 194 states have internal predecessors, (196), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 03:18:52,426 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 195 states to 195 states and 196 transitions. [2022-07-13 03:18:52,426 INFO L392 hiAutomatonCegarLoop]: Abstraction has 195 states and 196 transitions. [2022-07-13 03:18:52,426 INFO L374 stractBuchiCegarLoop]: Abstraction has 195 states and 196 transitions. [2022-07-13 03:18:52,444 INFO L287 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-07-13 03:18:52,444 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 195 states and 196 transitions. [2022-07-13 03:18:52,445 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 193 [2022-07-13 03:18:52,446 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-13 03:18:52,446 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-13 03:18:52,447 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-07-13 03:18:52,447 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [95, 94, 1, 1, 1, 1] [2022-07-13 03:18:52,447 INFO L752 eck$LassoCheckResult]: Stem: 2245#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2246#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem6#1, main_#t~mem5#1, main_#t~mem7#1, main_#t~mem4#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset; 2247#L549-3 [2022-07-13 03:18:52,447 INFO L754 eck$LassoCheckResult]: Loop: 2247#L549-3 call main_#t~mem4#1 := read~int(main_~x1~0#1.base, main_~x1~0#1.offset, 4); 2243#L549-1 assume !!(main_#t~mem4#1 <= 10);havoc main_#t~mem4#1;call write~int(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2244#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2250#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2248#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2249#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2437#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2436#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2435#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2434#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2433#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2432#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2431#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2430#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2429#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2428#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2427#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2426#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2425#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2424#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2423#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2422#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2421#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2420#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2419#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2418#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2417#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2416#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2415#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2414#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2413#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2412#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2411#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2410#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2409#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2408#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2407#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2406#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2405#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2404#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2403#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2402#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2401#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2400#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2399#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2398#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2397#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2396#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2395#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2394#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2393#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2392#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2391#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2390#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2389#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2388#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2387#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2386#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2385#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2384#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2383#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2382#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2381#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2380#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2379#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2378#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2377#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2376#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2375#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2374#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2373#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2372#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2371#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2370#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2369#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2368#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2367#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2366#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2365#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2364#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2363#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2362#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2361#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2360#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2359#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2358#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2357#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2356#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2355#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2354#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2353#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2352#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2351#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2350#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2349#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2348#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2347#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2346#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2345#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2344#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2343#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2342#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2341#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2340#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2339#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2338#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2337#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2336#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2335#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2334#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2333#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2332#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2331#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2330#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2329#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2328#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2327#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2326#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2325#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2324#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2323#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2322#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2321#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2320#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2319#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2318#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2317#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2316#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2315#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2314#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2313#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2312#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2311#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2310#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2309#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2308#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2307#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2306#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2305#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2304#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2303#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2302#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2301#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2300#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2299#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2298#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2297#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2296#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2295#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2294#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2293#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2292#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2291#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2290#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2289#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2288#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2287#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2286#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2285#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2284#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2283#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2282#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2281#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2280#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2279#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2278#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2277#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2276#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2275#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2274#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2273#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2272#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2271#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2270#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2269#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2268#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2267#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2266#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2265#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2264#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2263#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2262#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2261#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2260#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2259#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2258#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2257#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2256#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2255#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2254#L551-1 assume !!(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1; 2253#L551-3 call main_#t~mem5#1 := read~int(main_~x2~0#1.base, main_~x2~0#1.offset, 4); 2252#L551-1 assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1; 2251#L551-4 call main_#t~mem7#1 := read~int(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1; 2247#L549-3 [2022-07-13 03:18:52,448 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 03:18:52,448 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 8 times [2022-07-13 03:18:52,448 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 03:18:52,448 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [124038602] [2022-07-13 03:18:52,449 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 03:18:52,449 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 03:18:52,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-13 03:18:52,456 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-13 03:18:52,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-13 03:18:52,461 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-13 03:18:52,462 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 03:18:52,462 INFO L85 PathProgramCache]: Analyzing trace with hash -1384860837, now seen corresponding path program 6 times [2022-07-13 03:18:52,462 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 03:18:52,462 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [162591441] [2022-07-13 03:18:52,462 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 03:18:52,462 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 03:18:52,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 03:18:59,816 INFO L134 CoverageAnalysis]: Checked inductivity of 8930 backedges. 0 proven. 8930 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 03:18:59,816 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 03:18:59,816 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [162591441] [2022-07-13 03:18:59,816 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [162591441] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-13 03:18:59,816 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [95618172] [2022-07-13 03:18:59,816 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-07-13 03:18:59,817 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-13 03:18:59,817 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-13 03:18:59,818 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-13 03:18:59,821 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2022-07-13 03:23:04,936 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 95 check-sat command(s) [2022-07-13 03:23:04,936 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-07-13 03:23:05,003 INFO L263 TraceCheckSpWp]: Trace formula consists of 1442 conjuncts, 287 conjunts are in the unsatisfiable core [2022-07-13 03:23:05,031 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-13 03:23:05,034 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2022-07-13 03:23:05,053 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,072 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,079 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,084 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,090 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,105 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,111 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,116 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,122 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,131 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,138 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,143 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,148 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,154 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,159 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,165 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,171 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,176 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,181 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,185 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,190 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,195 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,200 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,205 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,211 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,217 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,226 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,233 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,240 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,245 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,254 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,261 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,268 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,282 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,292 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,298 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,306 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,311 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,317 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,323 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,328 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,336 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,341 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,346 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,350 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,355 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,392 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,398 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,402 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,407 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,412 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,416 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,421 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,428 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,432 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,438 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,444 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,448 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,453 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,459 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,464 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,469 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,474 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,479 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,485 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,490 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,497 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,502 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,508 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,512 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,521 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,526 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,531 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,535 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,540 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,545 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,550 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,555 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,559 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,564 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,573 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,578 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,582 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,589 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,593 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,598 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,603 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,607 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,612 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,617 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,621 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,626 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,631 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,635 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2022-07-13 03:23:05,638 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2022-07-13 03:23:05,643 INFO L134 CoverageAnalysis]: Checked inductivity of 8930 backedges. 0 proven. 8930 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 03:23:05,643 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-13 03:23:15,377 INFO L134 CoverageAnalysis]: Checked inductivity of 8930 backedges. 0 proven. 8930 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 03:23:15,379 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [95618172] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-13 03:23:15,379 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-13 03:23:15,379 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [192, 98, 98] total 288 [2022-07-13 03:23:15,380 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [609432396] [2022-07-13 03:23:15,380 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-13 03:23:15,381 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-13 03:23:15,381 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-13 03:23:15,388 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 288 interpolants. [2022-07-13 03:23:15,396 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=36577, Invalid=46079, Unknown=0, NotChecked=0, Total=82656 [2022-07-13 03:23:15,396 INFO L87 Difference]: Start difference. First operand 195 states and 196 transitions. cyclomatic complexity: 2 Second operand has 288 states, 288 states have (on average 1.9861111111111112) internal successors, (572), 288 states have internal predecessors, (572), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)