./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.16.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 6c24879c Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.16.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 45519c8273c53879cf6a170ed74d5bc0be814b1f3243ce6c30d1d3efe9a3cf32 --- Real Ultimate output --- This is Ultimate 0.2.2-?-6c24879 [2022-07-13 04:23:34,897 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-07-13 04:23:34,899 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-07-13 04:23:34,928 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-07-13 04:23:34,929 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-07-13 04:23:34,930 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-07-13 04:23:34,931 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-07-13 04:23:34,932 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-07-13 04:23:34,933 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-07-13 04:23:34,934 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-07-13 04:23:34,935 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-07-13 04:23:34,935 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-07-13 04:23:34,936 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-07-13 04:23:34,936 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-07-13 04:23:34,937 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-07-13 04:23:34,938 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-07-13 04:23:34,939 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-07-13 04:23:34,939 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-07-13 04:23:34,941 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-07-13 04:23:34,942 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-07-13 04:23:34,943 INFO L181 SettingsManager]: Resetting HornVerifier preferences to default values [2022-07-13 04:23:34,944 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-07-13 04:23:34,944 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-07-13 04:23:34,945 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-07-13 04:23:34,945 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-07-13 04:23:34,947 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-07-13 04:23:34,948 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-07-13 04:23:34,948 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-07-13 04:23:34,948 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-07-13 04:23:34,949 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-07-13 04:23:34,949 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-07-13 04:23:34,950 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-07-13 04:23:34,950 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-07-13 04:23:34,951 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-07-13 04:23:34,951 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-07-13 04:23:34,952 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-07-13 04:23:34,952 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-07-13 04:23:34,954 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-07-13 04:23:34,954 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-07-13 04:23:34,955 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-07-13 04:23:34,955 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-07-13 04:23:34,957 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-07-13 04:23:34,957 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-07-13 04:23:34,972 INFO L113 SettingsManager]: Loading preferences was successful [2022-07-13 04:23:34,972 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-07-13 04:23:34,973 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-07-13 04:23:34,973 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-07-13 04:23:34,973 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-07-13 04:23:34,974 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-07-13 04:23:34,974 INFO L138 SettingsManager]: * Use SBE=true [2022-07-13 04:23:34,974 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-07-13 04:23:34,974 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-07-13 04:23:34,974 INFO L138 SettingsManager]: * Use old map elimination=false [2022-07-13 04:23:34,974 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-07-13 04:23:34,975 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-07-13 04:23:34,975 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-07-13 04:23:34,975 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-07-13 04:23:34,975 INFO L138 SettingsManager]: * sizeof long=4 [2022-07-13 04:23:34,975 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-07-13 04:23:34,975 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-07-13 04:23:34,976 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-07-13 04:23:34,976 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-07-13 04:23:34,976 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-07-13 04:23:34,977 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-07-13 04:23:34,977 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-07-13 04:23:34,977 INFO L138 SettingsManager]: * sizeof long double=12 [2022-07-13 04:23:34,977 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-07-13 04:23:34,977 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-07-13 04:23:34,977 INFO L138 SettingsManager]: * Use constant arrays=true [2022-07-13 04:23:34,978 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-07-13 04:23:34,978 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-07-13 04:23:34,978 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-07-13 04:23:34,978 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-07-13 04:23:34,979 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-07-13 04:23:34,979 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-07-13 04:23:34,980 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 45519c8273c53879cf6a170ed74d5bc0be814b1f3243ce6c30d1d3efe9a3cf32 [2022-07-13 04:23:35,182 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-07-13 04:23:35,208 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-07-13 04:23:35,210 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-07-13 04:23:35,211 INFO L271 PluginConnector]: Initializing CDTParser... [2022-07-13 04:23:35,211 INFO L275 PluginConnector]: CDTParser initialized [2022-07-13 04:23:35,212 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.16.cil.c [2022-07-13 04:23:35,270 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a4cbfa4d0/5f667e6d16414af9ad2ad00a2ca34b24/FLAGaddeaaba0 [2022-07-13 04:23:35,661 INFO L306 CDTParser]: Found 1 translation units. [2022-07-13 04:23:35,662 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.16.cil.c [2022-07-13 04:23:35,682 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a4cbfa4d0/5f667e6d16414af9ad2ad00a2ca34b24/FLAGaddeaaba0 [2022-07-13 04:23:35,691 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a4cbfa4d0/5f667e6d16414af9ad2ad00a2ca34b24 [2022-07-13 04:23:35,693 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-07-13 04:23:35,694 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-07-13 04:23:35,696 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-07-13 04:23:35,696 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-07-13 04:23:35,702 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-07-13 04:23:35,702 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.07 04:23:35" (1/1) ... [2022-07-13 04:23:35,703 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@67ae8f03 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.07 04:23:35, skipping insertion in model container [2022-07-13 04:23:35,703 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.07 04:23:35" (1/1) ... [2022-07-13 04:23:35,708 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-07-13 04:23:35,741 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-07-13 04:23:35,847 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.16.cil.c[706,719] [2022-07-13 04:23:35,926 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-13 04:23:35,933 INFO L203 MainTranslator]: Completed pre-run [2022-07-13 04:23:35,941 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.16.cil.c[706,719] [2022-07-13 04:23:35,987 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-13 04:23:36,004 INFO L208 MainTranslator]: Completed translation [2022-07-13 04:23:36,004 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.07 04:23:36 WrapperNode [2022-07-13 04:23:36,004 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-07-13 04:23:36,005 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-07-13 04:23:36,005 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-07-13 04:23:36,006 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-07-13 04:23:36,011 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.07 04:23:36" (1/1) ... [2022-07-13 04:23:36,027 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.07 04:23:36" (1/1) ... [2022-07-13 04:23:36,127 INFO L137 Inliner]: procedures = 56, calls = 71, calls flagged for inlining = 66, calls inlined = 303, statements flattened = 4715 [2022-07-13 04:23:36,128 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-07-13 04:23:36,128 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-07-13 04:23:36,128 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-07-13 04:23:36,128 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-07-13 04:23:36,134 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.07 04:23:36" (1/1) ... [2022-07-13 04:23:36,134 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.07 04:23:36" (1/1) ... [2022-07-13 04:23:36,143 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.07 04:23:36" (1/1) ... [2022-07-13 04:23:36,143 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.07 04:23:36" (1/1) ... [2022-07-13 04:23:36,170 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.07 04:23:36" (1/1) ... [2022-07-13 04:23:36,221 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.07 04:23:36" (1/1) ... [2022-07-13 04:23:36,227 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.07 04:23:36" (1/1) ... [2022-07-13 04:23:36,252 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-07-13 04:23:36,265 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-07-13 04:23:36,273 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-07-13 04:23:36,273 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-07-13 04:23:36,275 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.07 04:23:36" (1/1) ... [2022-07-13 04:23:36,287 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-13 04:23:36,297 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-13 04:23:36,316 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-13 04:23:36,339 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-07-13 04:23:36,353 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-07-13 04:23:36,354 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-07-13 04:23:36,354 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-07-13 04:23:36,354 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-07-13 04:23:36,468 INFO L234 CfgBuilder]: Building ICFG [2022-07-13 04:23:36,469 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-07-13 04:23:38,069 INFO L275 CfgBuilder]: Performing block encoding [2022-07-13 04:23:38,087 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-07-13 04:23:38,087 INFO L299 CfgBuilder]: Removed 18 assume(true) statements. [2022-07-13 04:23:38,090 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.07 04:23:38 BoogieIcfgContainer [2022-07-13 04:23:38,090 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-07-13 04:23:38,091 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-07-13 04:23:38,091 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-07-13 04:23:38,094 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-07-13 04:23:38,094 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-13 04:23:38,094 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.07 04:23:35" (1/3) ... [2022-07-13 04:23:38,095 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1857f446 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.07 04:23:38, skipping insertion in model container [2022-07-13 04:23:38,095 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-13 04:23:38,095 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.07 04:23:36" (2/3) ... [2022-07-13 04:23:38,095 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1857f446 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.07 04:23:38, skipping insertion in model container [2022-07-13 04:23:38,096 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-13 04:23:38,096 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.07 04:23:38" (3/3) ... [2022-07-13 04:23:38,097 INFO L354 chiAutomizerObserver]: Analyzing ICFG transmitter.16.cil.c [2022-07-13 04:23:38,166 INFO L255 stractBuchiCegarLoop]: Interprodecural is true [2022-07-13 04:23:38,166 INFO L256 stractBuchiCegarLoop]: Hoare is false [2022-07-13 04:23:38,166 INFO L257 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-07-13 04:23:38,167 INFO L258 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-07-13 04:23:38,167 INFO L259 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-07-13 04:23:38,167 INFO L260 stractBuchiCegarLoop]: Difference is false [2022-07-13 04:23:38,167 INFO L261 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-07-13 04:23:38,167 INFO L265 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-07-13 04:23:38,174 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2053 states, 2052 states have (on average 1.4995126705653021) internal successors, (3077), 2052 states have internal predecessors, (3077), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:38,224 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1864 [2022-07-13 04:23:38,225 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-13 04:23:38,225 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-13 04:23:38,237 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:38,237 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:38,238 INFO L287 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-07-13 04:23:38,241 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2053 states, 2052 states have (on average 1.4995126705653021) internal successors, (3077), 2052 states have internal predecessors, (3077), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:38,254 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1864 [2022-07-13 04:23:38,254 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-13 04:23:38,254 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-13 04:23:38,285 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:38,285 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:38,295 INFO L752 eck$LassoCheckResult]: Stem: 489#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 1962#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 966#L1980true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 326#L932true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1918#L939true assume !(1 == ~m_i~0);~m_st~0 := 2; 470#L939-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 1668#L944-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 310#L949-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1323#L954-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1968#L959-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 679#L964-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1175#L969-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1778#L974-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 614#L979-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 951#L984-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 256#L989-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 448#L994-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 1205#L999-1true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 579#L1004-1true assume !(1 == ~t14_i~0);~t14_st~0 := 2; 47#L1009-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 126#L1342true assume !(0 == ~M_E~0); 428#L1342-2true assume !(0 == ~T1_E~0); 1613#L1347-1true assume !(0 == ~T2_E~0); 1303#L1352-1true assume !(0 == ~T3_E~0); 1072#L1357-1true assume !(0 == ~T4_E~0); 444#L1362-1true assume !(0 == ~T5_E~0); 1386#L1367-1true assume !(0 == ~T6_E~0); 214#L1372-1true assume 0 == ~T7_E~0;~T7_E~0 := 1; 567#L1377-1true assume !(0 == ~T8_E~0); 400#L1382-1true assume !(0 == ~T9_E~0); 945#L1387-1true assume !(0 == ~T10_E~0); 1524#L1392-1true assume !(0 == ~T11_E~0); 419#L1397-1true assume !(0 == ~T12_E~0); 1681#L1402-1true assume !(0 == ~T13_E~0); 223#L1407-1true assume !(0 == ~T14_E~0); 1859#L1412-1true assume 0 == ~E_1~0;~E_1~0 := 1; 1200#L1417-1true assume !(0 == ~E_2~0); 2052#L1422-1true assume !(0 == ~E_3~0); 1680#L1427-1true assume !(0 == ~E_4~0); 330#L1432-1true assume !(0 == ~E_5~0); 1531#L1437-1true assume !(0 == ~E_6~0); 1117#L1442-1true assume !(0 == ~E_7~0); 1458#L1447-1true assume !(0 == ~E_8~0); 941#L1452-1true assume 0 == ~E_9~0;~E_9~0 := 1; 112#L1457-1true assume !(0 == ~E_10~0); 1153#L1462-1true assume !(0 == ~E_11~0); 1856#L1467-1true assume !(0 == ~E_12~0); 1171#L1472-1true assume !(0 == ~E_13~0); 1359#L1477-1true assume !(0 == ~E_14~0); 893#L1482-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 209#L646true assume 1 == ~m_pc~0; 623#L647true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 631#L657true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 662#L658true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 257#L1666true assume !(0 != activate_threads_~tmp~1#1); 1983#L1666-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1746#L665true assume !(1 == ~t1_pc~0); 540#L665-2true is_transmit1_triggered_~__retres1~1#1 := 0; 1199#L676true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 261#L677true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1707#L1674true assume !(0 != activate_threads_~tmp___0~0#1); 778#L1674-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 889#L684true assume 1 == ~t2_pc~0; 1867#L685true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 880#L695true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1692#L696true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1307#L1682true assume !(0 != activate_threads_~tmp___1~0#1); 1812#L1682-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1788#L703true assume !(1 == ~t3_pc~0); 341#L703-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1402#L714true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 770#L715true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34#L1690true assume !(0 != activate_threads_~tmp___2~0#1); 273#L1690-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1321#L722true assume 1 == ~t4_pc~0; 751#L723true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 602#L733true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1104#L734true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1622#L1698true assume !(0 != activate_threads_~tmp___3~0#1); 648#L1698-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 127#L741true assume 1 == ~t5_pc~0; 287#L742true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 805#L752true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 373#L753true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 859#L1706true assume !(0 != activate_threads_~tmp___4~0#1); 1384#L1706-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 429#L760true assume !(1 == ~t6_pc~0); 738#L760-2true is_transmit6_triggered_~__retres1~6#1 := 0; 985#L771true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 258#L772true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1659#L1714true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 718#L1714-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1401#L779true assume 1 == ~t7_pc~0; 147#L780true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 75#L790true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 280#L791true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1376#L1722true assume !(0 != activate_threads_~tmp___6~0#1); 294#L1722-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1690#L798true assume !(1 == ~t8_pc~0); 1934#L798-2true is_transmit8_triggered_~__retres1~8#1 := 0; 1261#L809true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 148#L810true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1748#L1730true assume !(0 != activate_threads_~tmp___7~0#1); 1906#L1730-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 65#L817true assume 1 == ~t9_pc~0; 827#L818true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 494#L828true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 898#L829true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1861#L1738true assume !(0 != activate_threads_~tmp___8~0#1); 264#L1738-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 772#L836true assume !(1 == ~t10_pc~0); 275#L836-2true is_transmit10_triggered_~__retres1~10#1 := 0; 237#L847true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1562#L848true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 376#L1746true assume !(0 != activate_threads_~tmp___9~0#1); 1275#L1746-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1276#L855true assume 1 == ~t11_pc~0; 629#L856true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1146#L866true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1244#L867true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 938#L1754true assume !(0 != activate_threads_~tmp___10~0#1); 783#L1754-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 207#L874true assume !(1 == ~t12_pc~0); 1640#L874-2true is_transmit12_triggered_~__retres1~12#1 := 0; 299#L885true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 377#L886true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1986#L1762true assume !(0 != activate_threads_~tmp___11~0#1); 51#L1762-2true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1860#L893true assume 1 == ~t13_pc~0; 1544#L894true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 399#L904true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1385#L905true activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1559#L1770true assume !(0 != activate_threads_~tmp___12~0#1); 1395#L1770-2true assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 1766#L912true assume 1 == ~t14_pc~0; 1122#L913true assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 2022#L923true is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 208#L924true activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 173#L1778true assume !(0 != activate_threads_~tmp___13~0#1); 642#L1778-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1341#L1495true assume 1 == ~M_E~0;~M_E~0 := 2; 1000#L1495-2true assume !(1 == ~T1_E~0); 1673#L1500-1true assume !(1 == ~T2_E~0); 715#L1505-1true assume !(1 == ~T3_E~0); 1913#L1510-1true assume !(1 == ~T4_E~0); 758#L1515-1true assume !(1 == ~T5_E~0); 1726#L1520-1true assume !(1 == ~T6_E~0); 1393#L1525-1true assume !(1 == ~T7_E~0); 1030#L1530-1true assume 1 == ~T8_E~0;~T8_E~0 := 2; 262#L1535-1true assume !(1 == ~T9_E~0); 1836#L1540-1true assume !(1 == ~T10_E~0); 16#L1545-1true assume !(1 == ~T11_E~0); 1972#L1550-1true assume !(1 == ~T12_E~0); 131#L1555-1true assume !(1 == ~T13_E~0); 288#L1560-1true assume !(1 == ~T14_E~0); 1705#L1565-1true assume !(1 == ~E_1~0); 1927#L1570-1true assume 1 == ~E_2~0;~E_2~0 := 2; 912#L1575-1true assume !(1 == ~E_3~0); 445#L1580-1true assume !(1 == ~E_4~0); 773#L1585-1true assume !(1 == ~E_5~0); 1044#L1590-1true assume !(1 == ~E_6~0); 467#L1595-1true assume !(1 == ~E_7~0); 1894#L1600-1true assume !(1 == ~E_8~0); 722#L1605-1true assume !(1 == ~E_9~0); 1648#L1610-1true assume 1 == ~E_10~0;~E_10~0 := 2; 1239#L1615-1true assume !(1 == ~E_11~0); 364#L1620-1true assume !(1 == ~E_12~0); 1102#L1625-1true assume !(1 == ~E_13~0); 942#L1630-1true assume !(1 == ~E_14~0); 466#L1635-1true assume { :end_inline_reset_delta_events } true; 430#L2017-2true [2022-07-13 04:23:38,297 INFO L754 eck$LassoCheckResult]: Loop: 430#L2017-2true assume !false; 49#L2018true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 881#L1316true assume !true; 1266#L1332true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 501#L932-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 628#L1342-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1077#L1342-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1166#L1347-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 750#L1352-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1354#L1357-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 2037#L1362-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 1879#L1367-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 1846#L1372-3true assume !(0 == ~T7_E~0); 41#L1377-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 490#L1382-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 387#L1387-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1123#L1392-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1947#L1397-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 1665#L1402-3true assume 0 == ~T13_E~0;~T13_E~0 := 1; 707#L1407-3true assume 0 == ~T14_E~0;~T14_E~0 := 1; 187#L1412-3true assume !(0 == ~E_1~0); 1396#L1417-3true assume 0 == ~E_2~0;~E_2~0 := 1; 653#L1422-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1346#L1427-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1533#L1432-3true assume 0 == ~E_5~0;~E_5~0 := 1; 975#L1437-3true assume 0 == ~E_6~0;~E_6~0 := 1; 719#L1442-3true assume 0 == ~E_7~0;~E_7~0 := 1; 999#L1447-3true assume 0 == ~E_8~0;~E_8~0 := 1; 72#L1452-3true assume !(0 == ~E_9~0); 1998#L1457-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1257#L1462-3true assume 0 == ~E_11~0;~E_11~0 := 1; 1688#L1467-3true assume 0 == ~E_12~0;~E_12~0 := 1; 1047#L1472-3true assume 0 == ~E_13~0;~E_13~0 := 1; 1713#L1477-3true assume 0 == ~E_14~0;~E_14~0 := 1; 186#L1482-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 522#L646-42true assume !(1 == ~m_pc~0); 1678#L646-44true is_master_triggered_~__retres1~0#1 := 0; 1305#L657-14true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1675#L658-14true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1618#L1666-42true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1710#L1666-44true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1215#L665-42true assume 1 == ~t1_pc~0; 1180#L666-14true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1537#L676-14true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1462#L677-14true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 276#L1674-42true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1882#L1674-44true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1878#L684-42true assume !(1 == ~t2_pc~0); 1792#L684-44true is_transmit2_triggered_~__retres1~2#1 := 0; 1892#L695-14true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1807#L696-14true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 677#L1682-42true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 765#L1682-44true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1740#L703-42true assume !(1 == ~t3_pc~0); 1582#L703-44true is_transmit3_triggered_~__retres1~3#1 := 0; 1850#L714-14true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 433#L715-14true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1629#L1690-42true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1051#L1690-44true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 697#L722-42true assume !(1 == ~t4_pc~0); 1488#L722-44true is_transmit4_triggered_~__retres1~4#1 := 0; 1718#L733-14true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 463#L734-14true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 356#L1698-42true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1919#L1698-44true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1729#L741-42true assume 1 == ~t5_pc~0; 1547#L742-14true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 605#L752-14true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1964#L753-14true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1897#L1706-42true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 535#L1706-44true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 635#L760-42true assume 1 == ~t6_pc~0; 1762#L761-14true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 729#L771-14true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1113#L772-14true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1637#L1714-42true assume !(0 != activate_threads_~tmp___5~0#1); 505#L1714-44true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1314#L779-42true assume 1 == ~t7_pc~0; 1241#L780-14true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1869#L790-14true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 318#L791-14true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1700#L1722-42true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 236#L1722-44true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 499#L798-42true assume 1 == ~t8_pc~0; 1923#L799-14true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1431#L809-14true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1329#L810-14true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 746#L1730-42true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 149#L1730-44true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1369#L817-42true assume 1 == ~t9_pc~0; 608#L818-14true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 302#L828-14true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 371#L829-14true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1185#L1738-42true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 973#L1738-44true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1514#L836-42true assume !(1 == ~t10_pc~0); 1816#L836-44true is_transmit10_triggered_~__retres1~10#1 := 0; 325#L847-14true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1841#L848-14true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1552#L1746-42true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1696#L1746-44true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2045#L855-42true assume 1 == ~t11_pc~0; 1721#L856-14true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 91#L866-14true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 502#L867-14true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1168#L1754-42true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 2047#L1754-44true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 417#L874-42true assume !(1 == ~t12_pc~0); 583#L874-44true is_transmit12_triggered_~__retres1~12#1 := 0; 1486#L885-14true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 50#L886-14true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 891#L1762-42true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 170#L1762-44true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1981#L893-42true assume 1 == ~t13_pc~0; 1006#L894-14true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1835#L904-14true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 807#L905-14true activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 727#L1770-42true assume !(0 != activate_threads_~tmp___12~0#1); 374#L1770-44true assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 1848#L912-42true assume !(1 == ~t14_pc~0); 980#L912-44true is_transmit14_triggered_~__retres1~14#1 := 0; 26#L923-14true is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 1088#L924-14true activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1218#L1778-42true assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 232#L1778-44true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 610#L1495-3true assume !(1 == ~M_E~0); 965#L1495-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1573#L1500-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1069#L1505-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 359#L1510-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 342#L1515-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 782#L1520-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 996#L1525-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1579#L1530-3true assume !(1 == ~T8_E~0); 253#L1535-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 274#L1540-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1288#L1545-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 1532#L1550-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1512#L1555-3true assume 1 == ~T13_E~0;~T13_E~0 := 2; 515#L1560-3true assume 1 == ~T14_E~0;~T14_E~0 := 2; 1024#L1565-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1873#L1570-3true assume !(1 == ~E_2~0); 969#L1575-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1420#L1580-3true assume 1 == ~E_4~0;~E_4~0 := 2; 1521#L1585-3true assume 1 == ~E_5~0;~E_5~0 := 2; 1758#L1590-3true assume 1 == ~E_6~0;~E_6~0 := 2; 1662#L1595-3true assume 1 == ~E_7~0;~E_7~0 := 2; 802#L1600-3true assume 1 == ~E_8~0;~E_8~0 := 2; 1308#L1605-3true assume 1 == ~E_9~0;~E_9~0 := 2; 1397#L1610-3true assume !(1 == ~E_10~0); 365#L1615-3true assume 1 == ~E_11~0;~E_11~0 := 2; 1911#L1620-3true assume 1 == ~E_12~0;~E_12~0 := 2; 775#L1625-3true assume 1 == ~E_13~0;~E_13~0 := 2; 2040#L1630-3true assume 1 == ~E_14~0;~E_14~0 := 2; 699#L1635-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 335#L1022-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 538#L1100-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 1966#L1101-1true start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 998#L2036true assume !(0 == start_simulation_~tmp~3#1); 1174#L2036-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 1630#L1022-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 1421#L1100-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 1926#L1101-2true stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 732#L1991true assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1733#L1998true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1703#L1999true start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 1806#L2049true assume !(0 != start_simulation_~tmp___0~1#1); 430#L2017-2true [2022-07-13 04:23:38,303 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:38,303 INFO L85 PathProgramCache]: Analyzing trace with hash -1440429276, now seen corresponding path program 1 times [2022-07-13 04:23:38,309 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:38,310 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [808482260] [2022-07-13 04:23:38,310 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:38,311 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:38,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:38,462 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:38,462 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:38,463 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [808482260] [2022-07-13 04:23:38,463 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [808482260] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:38,463 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:38,464 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-13 04:23:38,465 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1594664518] [2022-07-13 04:23:38,465 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:38,468 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-13 04:23:38,469 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:38,469 INFO L85 PathProgramCache]: Analyzing trace with hash 1020635087, now seen corresponding path program 1 times [2022-07-13 04:23:38,469 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:38,470 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1443152407] [2022-07-13 04:23:38,470 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:38,470 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:38,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:38,498 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:38,499 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:38,499 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1443152407] [2022-07-13 04:23:38,499 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1443152407] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:38,499 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:38,500 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-13 04:23:38,500 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [555001118] [2022-07-13 04:23:38,500 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:38,501 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-13 04:23:38,502 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-13 04:23:38,523 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-07-13 04:23:38,524 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-07-13 04:23:38,529 INFO L87 Difference]: Start difference. First operand has 2053 states, 2052 states have (on average 1.4995126705653021) internal successors, (3077), 2052 states have internal predecessors, (3077), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 83.5) internal successors, (167), 2 states have internal predecessors, (167), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:38,562 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-13 04:23:38,563 INFO L93 Difference]: Finished difference Result 2052 states and 3039 transitions. [2022-07-13 04:23:38,564 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-07-13 04:23:38,568 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2052 states and 3039 transitions. [2022-07-13 04:23:38,582 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-07-13 04:23:38,598 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2052 states to 2047 states and 3034 transitions. [2022-07-13 04:23:38,599 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2022-07-13 04:23:38,602 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2022-07-13 04:23:38,602 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3034 transitions. [2022-07-13 04:23:38,608 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-13 04:23:38,608 INFO L369 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3034 transitions. [2022-07-13 04:23:38,624 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3034 transitions. [2022-07-13 04:23:38,676 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2022-07-13 04:23:38,683 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4821690278456277) internal successors, (3034), 2046 states have internal predecessors, (3034), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:38,690 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3034 transitions. [2022-07-13 04:23:38,691 INFO L392 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3034 transitions. [2022-07-13 04:23:38,691 INFO L374 stractBuchiCegarLoop]: Abstraction has 2047 states and 3034 transitions. [2022-07-13 04:23:38,691 INFO L287 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-07-13 04:23:38,692 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3034 transitions. [2022-07-13 04:23:38,701 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-07-13 04:23:38,702 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-13 04:23:38,702 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-13 04:23:38,706 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:38,706 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:38,707 INFO L752 eck$LassoCheckResult]: Stem: 5040#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 5041#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 5643#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4760#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4761#L939 assume !(1 == ~m_i~0);~m_st~0 := 2; 5006#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5007#L944-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4734#L949-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4735#L954-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5958#L959-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5310#L964-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5311#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5828#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 5220#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5221#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4641#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4642#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 4973#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 5171#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 4218#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4219#L1342 assume !(0 == ~M_E~0); 4384#L1342-2 assume !(0 == ~T1_E~0); 4940#L1347-1 assume !(0 == ~T2_E~0); 5941#L1352-1 assume !(0 == ~T3_E~0); 5737#L1357-1 assume !(0 == ~T4_E~0); 4965#L1362-1 assume !(0 == ~T5_E~0); 4966#L1367-1 assume !(0 == ~T6_E~0); 4563#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4564#L1377-1 assume !(0 == ~T8_E~0); 4894#L1382-1 assume !(0 == ~T9_E~0); 4895#L1387-1 assume !(0 == ~T10_E~0); 5622#L1392-1 assume !(0 == ~T11_E~0); 4926#L1397-1 assume !(0 == ~T12_E~0); 4927#L1402-1 assume !(0 == ~T13_E~0); 4579#L1407-1 assume !(0 == ~T14_E~0); 4580#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 5858#L1417-1 assume !(0 == ~E_2~0); 5859#L1422-1 assume !(0 == ~E_3~0); 6100#L1427-1 assume !(0 == ~E_4~0); 4767#L1432-1 assume !(0 == ~E_5~0); 4768#L1437-1 assume !(0 == ~E_6~0); 5776#L1442-1 assume !(0 == ~E_7~0); 5777#L1447-1 assume !(0 == ~E_8~0); 5619#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 4354#L1457-1 assume !(0 == ~E_10~0); 4355#L1462-1 assume !(0 == ~E_11~0); 5811#L1467-1 assume !(0 == ~E_12~0); 5823#L1472-1 assume !(0 == ~E_13~0); 5824#L1477-1 assume !(0 == ~E_14~0); 5566#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4553#L646 assume 1 == ~m_pc~0; 4554#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5230#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5245#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4643#L1666 assume !(0 != activate_threads_~tmp~1#1); 4644#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6121#L665 assume !(1 == ~t1_pc~0); 5119#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5120#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4652#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4653#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 5443#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5444#L684 assume 1 == ~t2_pc~0; 5561#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5485#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5550#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5945#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 5946#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6134#L703 assume !(1 == ~t3_pc~0); 4789#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4790#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5436#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4188#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 4189#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4674#L722 assume 1 == ~t4_pc~0; 5412#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4855#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5200#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5760#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 5267#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4385#L741 assume 1 == ~t5_pc~0; 4386#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4696#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4850#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4851#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 5530#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4941#L760 assume !(1 == ~t6_pc~0); 4788#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4787#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4645#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4646#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5367#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5368#L779 assume 1 == ~t7_pc~0; 4430#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4276#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4277#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4685#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 4708#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4709#L798 assume !(1 == ~t8_pc~0); 5990#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 5913#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4432#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4433#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 6123#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4253#L817 assume 1 == ~t9_pc~0; 4254#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5048#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5049#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5571#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 4659#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4660#L836 assume !(1 == ~t10_pc~0); 4676#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4607#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4608#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4856#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 4857#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5923#L855 assume 1 == ~t11_pc~0; 5241#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 5242#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 5806#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5615#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 5450#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4549#L874 assume !(1 == ~t12_pc~0); 4550#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 4717#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4718#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4858#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 4226#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 4227#L893 assume 1 == ~t13_pc~0; 6057#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 4582#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4893#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 5984#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 5992#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 5993#L912 assume 1 == ~t14_pc~0; 5783#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 5784#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 4552#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 4484#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 4485#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5260#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 5676#L1495-2 assume !(1 == ~T1_E~0); 5677#L1500-1 assume !(1 == ~T2_E~0); 5363#L1505-1 assume !(1 == ~T3_E~0); 5364#L1510-1 assume !(1 == ~T4_E~0); 5421#L1515-1 assume !(1 == ~T5_E~0); 5422#L1520-1 assume !(1 == ~T6_E~0); 5991#L1525-1 assume !(1 == ~T7_E~0); 5701#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4654#L1535-1 assume !(1 == ~T9_E~0); 4655#L1540-1 assume !(1 == ~T10_E~0); 4147#L1545-1 assume !(1 == ~T11_E~0); 4148#L1550-1 assume !(1 == ~T12_E~0); 4396#L1555-1 assume !(1 == ~T13_E~0); 4397#L1560-1 assume !(1 == ~T14_E~0); 4697#L1565-1 assume !(1 == ~E_1~0); 6110#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 5588#L1575-1 assume !(1 == ~E_3~0); 4967#L1580-1 assume !(1 == ~E_4~0); 4968#L1585-1 assume !(1 == ~E_5~0); 5438#L1590-1 assume !(1 == ~E_6~0); 5002#L1595-1 assume !(1 == ~E_7~0); 5003#L1600-1 assume !(1 == ~E_8~0); 5375#L1605-1 assume !(1 == ~E_9~0); 5376#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 5893#L1615-1 assume !(1 == ~E_11~0); 4832#L1620-1 assume !(1 == ~E_12~0); 4833#L1625-1 assume !(1 == ~E_13~0); 5620#L1630-1 assume !(1 == ~E_14~0); 5001#L1635-1 assume { :end_inline_reset_delta_events } true; 4942#L2017-2 [2022-07-13 04:23:38,708 INFO L754 eck$LassoCheckResult]: Loop: 4942#L2017-2 assume !false; 4222#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4223#L1316 assume !false; 5551#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 5613#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 4160#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 4302#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4303#L1115 assume !(0 != eval_~tmp~0#1); 5636#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5057#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5058#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5240#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5741#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5410#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5411#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5973#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6148#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6143#L1372-3 assume !(0 == ~T7_E~0); 4204#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4205#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4874#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4875#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 5786#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 6096#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 5354#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 4510#L1412-3 assume !(0 == ~E_1~0); 4511#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5275#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5276#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5970#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5657#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5369#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5370#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4270#L1452-3 assume !(0 == ~E_9~0); 4271#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 5909#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 5910#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 5714#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 5715#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 4508#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4509#L646-42 assume 1 == ~m_pc~0; 5094#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5942#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5943#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6081#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6082#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5874#L665-42 assume 1 == ~t1_pc~0; 5835#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5837#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6023#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4677#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4678#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6147#L684-42 assume 1 == ~t2_pc~0; 5526#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5527#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6137#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5306#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5307#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5429#L703-42 assume 1 == ~t3_pc~0; 5627#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5628#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4946#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4947#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5721#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5341#L722-42 assume 1 == ~t4_pc~0; 5342#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5752#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4995#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4822#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4823#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6117#L741-42 assume !(1 == ~t5_pc~0); 5734#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 5204#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5205#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6150#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5112#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5113#L760-42 assume 1 == ~t6_pc~0; 5248#L761-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5382#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5383#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5771#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 5064#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5065#L779-42 assume !(1 == ~t7_pc~0); 5841#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 5842#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4749#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4750#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4605#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4606#L798-42 assume 1 == ~t8_pc~0; 5056#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4217#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5960#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5406#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4436#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4437#L817-42 assume 1 == ~t9_pc~0; 5210#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4720#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4721#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4847#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5652#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5653#L836-42 assume 1 == ~t10_pc~0; 5745#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4758#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4759#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 6060#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 6061#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6102#L855-42 assume 1 == ~t11_pc~0; 6115#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4309#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4310#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5059#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 5822#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4923#L874-42 assume 1 == ~t12_pc~0; 4924#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 5163#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4224#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4225#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 4478#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 4479#L893-42 assume 1 == ~t13_pc~0; 5681#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 5463#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 5478#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 5380#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 4852#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 4853#L912-42 assume 1 == ~t14_pc~0; 6097#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 4170#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 4171#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 5751#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 4598#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4599#L1495-3 assume !(1 == ~M_E~0); 5214#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5642#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5735#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4828#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4791#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4792#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5449#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5672#L1530-3 assume !(1 == ~T8_E~0); 4637#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4638#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4675#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 5932#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 6041#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 5081#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 5082#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5697#L1570-3 assume !(1 == ~E_2~0); 5648#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5649#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6004#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6048#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6094#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5471#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5472#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5947#L1610-3 assume !(1 == ~E_10~0); 4834#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4835#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 5439#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 5440#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 5344#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 4775#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 4380#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 5118#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 5674#L2036 assume !(0 == start_simulation_~tmp~3#1); 5675#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 5827#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 4987#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 6005#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 5387#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 5388#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6108#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 6109#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 4942#L2017-2 [2022-07-13 04:23:38,709 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:38,709 INFO L85 PathProgramCache]: Analyzing trace with hash -1440429276, now seen corresponding path program 2 times [2022-07-13 04:23:38,709 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:38,710 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1997422144] [2022-07-13 04:23:38,710 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:38,710 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:38,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:38,759 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:38,759 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:38,759 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1997422144] [2022-07-13 04:23:38,759 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1997422144] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:38,760 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:38,760 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-13 04:23:38,760 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [816542678] [2022-07-13 04:23:38,760 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:38,761 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-13 04:23:38,761 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:38,761 INFO L85 PathProgramCache]: Analyzing trace with hash 1105916303, now seen corresponding path program 1 times [2022-07-13 04:23:38,761 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:38,761 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [264956154] [2022-07-13 04:23:38,762 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:38,762 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:38,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:38,885 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:38,886 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:38,886 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [264956154] [2022-07-13 04:23:38,886 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [264956154] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:38,886 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:38,886 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-13 04:23:38,886 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2115509754] [2022-07-13 04:23:38,887 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:38,887 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-13 04:23:38,887 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-13 04:23:38,894 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-13 04:23:38,895 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-13 04:23:38,895 INFO L87 Difference]: Start difference. First operand 2047 states and 3034 transitions. cyclomatic complexity: 988 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:38,936 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-13 04:23:38,937 INFO L93 Difference]: Finished difference Result 2047 states and 3033 transitions. [2022-07-13 04:23:38,937 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-13 04:23:38,938 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3033 transitions. [2022-07-13 04:23:38,953 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-07-13 04:23:38,963 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3033 transitions. [2022-07-13 04:23:38,964 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2022-07-13 04:23:38,965 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2022-07-13 04:23:38,966 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3033 transitions. [2022-07-13 04:23:38,968 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-13 04:23:38,968 INFO L369 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3033 transitions. [2022-07-13 04:23:38,970 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3033 transitions. [2022-07-13 04:23:38,992 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2022-07-13 04:23:38,995 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4816805080605764) internal successors, (3033), 2046 states have internal predecessors, (3033), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:39,000 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3033 transitions. [2022-07-13 04:23:39,001 INFO L392 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3033 transitions. [2022-07-13 04:23:39,001 INFO L374 stractBuchiCegarLoop]: Abstraction has 2047 states and 3033 transitions. [2022-07-13 04:23:39,001 INFO L287 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-07-13 04:23:39,001 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3033 transitions. [2022-07-13 04:23:39,008 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-07-13 04:23:39,008 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-13 04:23:39,009 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-13 04:23:39,010 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:39,011 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:39,011 INFO L752 eck$LassoCheckResult]: Stem: 9141#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 9142#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 9744#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8861#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8862#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 9107#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9108#L944-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 8835#L949-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 8836#L954-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 10059#L959-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9411#L964-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9412#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9929#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9321#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9322#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 8742#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 8743#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 9074#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 9272#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 8319#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8320#L1342 assume !(0 == ~M_E~0); 8485#L1342-2 assume !(0 == ~T1_E~0); 9041#L1347-1 assume !(0 == ~T2_E~0); 10042#L1352-1 assume !(0 == ~T3_E~0); 9838#L1357-1 assume !(0 == ~T4_E~0); 9066#L1362-1 assume !(0 == ~T5_E~0); 9067#L1367-1 assume !(0 == ~T6_E~0); 8664#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8665#L1377-1 assume !(0 == ~T8_E~0); 8995#L1382-1 assume !(0 == ~T9_E~0); 8996#L1387-1 assume !(0 == ~T10_E~0); 9723#L1392-1 assume !(0 == ~T11_E~0); 9027#L1397-1 assume !(0 == ~T12_E~0); 9028#L1402-1 assume !(0 == ~T13_E~0); 8680#L1407-1 assume !(0 == ~T14_E~0); 8681#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 9959#L1417-1 assume !(0 == ~E_2~0); 9960#L1422-1 assume !(0 == ~E_3~0); 10201#L1427-1 assume !(0 == ~E_4~0); 8868#L1432-1 assume !(0 == ~E_5~0); 8869#L1437-1 assume !(0 == ~E_6~0); 9877#L1442-1 assume !(0 == ~E_7~0); 9878#L1447-1 assume !(0 == ~E_8~0); 9720#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 8455#L1457-1 assume !(0 == ~E_10~0); 8456#L1462-1 assume !(0 == ~E_11~0); 9912#L1467-1 assume !(0 == ~E_12~0); 9924#L1472-1 assume !(0 == ~E_13~0); 9925#L1477-1 assume !(0 == ~E_14~0); 9667#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8654#L646 assume 1 == ~m_pc~0; 8655#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9331#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9346#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8744#L1666 assume !(0 != activate_threads_~tmp~1#1); 8745#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10222#L665 assume !(1 == ~t1_pc~0); 9220#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9221#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8753#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8754#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 9544#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9545#L684 assume 1 == ~t2_pc~0; 9662#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9586#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9651#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10046#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 10047#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10235#L703 assume !(1 == ~t3_pc~0); 8890#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8891#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9537#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8289#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 8290#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8775#L722 assume 1 == ~t4_pc~0; 9513#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8956#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9301#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9861#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 9368#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8486#L741 assume 1 == ~t5_pc~0; 8487#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8797#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8951#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8952#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 9631#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9042#L760 assume !(1 == ~t6_pc~0); 8889#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 8888#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8746#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8747#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9468#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9469#L779 assume 1 == ~t7_pc~0; 8531#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8377#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8378#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8786#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 8809#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8810#L798 assume !(1 == ~t8_pc~0); 10091#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 10014#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8533#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8534#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 10224#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8354#L817 assume 1 == ~t9_pc~0; 8355#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9149#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9150#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9672#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 8760#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8761#L836 assume !(1 == ~t10_pc~0); 8777#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8708#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8709#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8957#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 8958#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10024#L855 assume 1 == ~t11_pc~0; 9342#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 9343#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9907#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 9716#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 9551#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8650#L874 assume !(1 == ~t12_pc~0); 8651#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 8818#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8819#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8959#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 8327#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 8328#L893 assume 1 == ~t13_pc~0; 10158#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 8683#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 8994#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 10085#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 10093#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 10094#L912 assume 1 == ~t14_pc~0; 9884#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 9885#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 8653#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 8585#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 8586#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9361#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 9777#L1495-2 assume !(1 == ~T1_E~0); 9778#L1500-1 assume !(1 == ~T2_E~0); 9464#L1505-1 assume !(1 == ~T3_E~0); 9465#L1510-1 assume !(1 == ~T4_E~0); 9522#L1515-1 assume !(1 == ~T5_E~0); 9523#L1520-1 assume !(1 == ~T6_E~0); 10092#L1525-1 assume !(1 == ~T7_E~0); 9802#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8755#L1535-1 assume !(1 == ~T9_E~0); 8756#L1540-1 assume !(1 == ~T10_E~0); 8248#L1545-1 assume !(1 == ~T11_E~0); 8249#L1550-1 assume !(1 == ~T12_E~0); 8497#L1555-1 assume !(1 == ~T13_E~0); 8498#L1560-1 assume !(1 == ~T14_E~0); 8798#L1565-1 assume !(1 == ~E_1~0); 10211#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 9689#L1575-1 assume !(1 == ~E_3~0); 9068#L1580-1 assume !(1 == ~E_4~0); 9069#L1585-1 assume !(1 == ~E_5~0); 9539#L1590-1 assume !(1 == ~E_6~0); 9103#L1595-1 assume !(1 == ~E_7~0); 9104#L1600-1 assume !(1 == ~E_8~0); 9476#L1605-1 assume !(1 == ~E_9~0); 9477#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 9994#L1615-1 assume !(1 == ~E_11~0); 8933#L1620-1 assume !(1 == ~E_12~0); 8934#L1625-1 assume !(1 == ~E_13~0); 9721#L1630-1 assume !(1 == ~E_14~0); 9102#L1635-1 assume { :end_inline_reset_delta_events } true; 9043#L2017-2 [2022-07-13 04:23:39,012 INFO L754 eck$LassoCheckResult]: Loop: 9043#L2017-2 assume !false; 8323#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8324#L1316 assume !false; 9652#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 9714#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 8261#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 8403#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8404#L1115 assume !(0 != eval_~tmp~0#1); 9737#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9158#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9159#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9341#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9842#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9511#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9512#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10074#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10249#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10244#L1372-3 assume !(0 == ~T7_E~0); 8305#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8306#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8975#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 8976#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 9887#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 10197#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 9455#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 8611#L1412-3 assume !(0 == ~E_1~0); 8612#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9376#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9377#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10071#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9758#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9470#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9471#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8371#L1452-3 assume !(0 == ~E_9~0); 8372#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 10010#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 10011#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 9815#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 9816#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 8609#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8610#L646-42 assume 1 == ~m_pc~0; 9195#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 10043#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10044#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10182#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10183#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9975#L665-42 assume 1 == ~t1_pc~0; 9936#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9938#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10124#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8778#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8779#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10248#L684-42 assume 1 == ~t2_pc~0; 9627#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9628#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10238#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9407#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9408#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9530#L703-42 assume 1 == ~t3_pc~0; 9728#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9729#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9047#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9048#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9822#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9442#L722-42 assume 1 == ~t4_pc~0; 9443#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9853#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9096#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8923#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8924#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10218#L741-42 assume 1 == ~t5_pc~0; 10160#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9305#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9306#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10251#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9213#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9214#L760-42 assume !(1 == ~t6_pc~0); 9348#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 9483#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9484#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9872#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 9165#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9166#L779-42 assume !(1 == ~t7_pc~0); 9942#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 9943#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8850#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8851#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8706#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8707#L798-42 assume 1 == ~t8_pc~0; 9157#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8318#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10061#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9507#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8537#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8538#L817-42 assume !(1 == ~t9_pc~0); 9312#L817-44 is_transmit9_triggered_~__retres1~9#1 := 0; 8821#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8822#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8948#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9753#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9754#L836-42 assume 1 == ~t10_pc~0; 9846#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8859#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8860#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 10161#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 10162#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10203#L855-42 assume 1 == ~t11_pc~0; 10216#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 8410#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8411#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 9160#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 9923#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 9024#L874-42 assume 1 == ~t12_pc~0; 9025#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 9264#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8325#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8326#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 8579#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 8580#L893-42 assume 1 == ~t13_pc~0; 9782#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 9564#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 9579#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 9481#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 8953#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 8954#L912-42 assume !(1 == ~t14_pc~0); 9763#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 8271#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 8272#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 9852#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 8699#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8700#L1495-3 assume !(1 == ~M_E~0); 9315#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9743#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9836#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8929#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8892#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8893#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9550#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9773#L1530-3 assume !(1 == ~T8_E~0); 8738#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 8739#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8776#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 10033#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 10142#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 9182#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 9183#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9798#L1570-3 assume !(1 == ~E_2~0); 9749#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9750#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10105#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10149#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10195#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9572#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9573#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 10048#L1610-3 assume !(1 == ~E_10~0); 8935#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 8936#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 9540#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 9541#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 9445#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 8876#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 8481#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 9219#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 9775#L2036 assume !(0 == start_simulation_~tmp~3#1); 9776#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 9928#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 9088#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 10106#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 9488#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 9489#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10209#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 10210#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 9043#L2017-2 [2022-07-13 04:23:39,012 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:39,013 INFO L85 PathProgramCache]: Analyzing trace with hash -1949208090, now seen corresponding path program 1 times [2022-07-13 04:23:39,013 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:39,013 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [822367101] [2022-07-13 04:23:39,013 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:39,013 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:39,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:39,061 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:39,061 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:39,061 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [822367101] [2022-07-13 04:23:39,061 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [822367101] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:39,061 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:39,061 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-13 04:23:39,061 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1066415765] [2022-07-13 04:23:39,062 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:39,062 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-13 04:23:39,062 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:39,062 INFO L85 PathProgramCache]: Analyzing trace with hash -812799539, now seen corresponding path program 1 times [2022-07-13 04:23:39,062 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:39,063 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2080577690] [2022-07-13 04:23:39,063 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:39,063 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:39,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:39,152 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:39,153 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:39,153 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2080577690] [2022-07-13 04:23:39,154 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2080577690] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:39,154 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:39,154 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-13 04:23:39,155 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [290334511] [2022-07-13 04:23:39,155 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:39,156 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-13 04:23:39,156 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-13 04:23:39,156 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-13 04:23:39,157 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-13 04:23:39,157 INFO L87 Difference]: Start difference. First operand 2047 states and 3033 transitions. cyclomatic complexity: 987 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:39,214 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-13 04:23:39,214 INFO L93 Difference]: Finished difference Result 2047 states and 3032 transitions. [2022-07-13 04:23:39,214 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-13 04:23:39,215 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3032 transitions. [2022-07-13 04:23:39,226 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-07-13 04:23:39,233 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3032 transitions. [2022-07-13 04:23:39,234 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2022-07-13 04:23:39,235 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2022-07-13 04:23:39,235 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3032 transitions. [2022-07-13 04:23:39,237 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-13 04:23:39,238 INFO L369 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3032 transitions. [2022-07-13 04:23:39,239 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3032 transitions. [2022-07-13 04:23:39,259 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2022-07-13 04:23:39,263 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4811919882755251) internal successors, (3032), 2046 states have internal predecessors, (3032), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:39,268 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3032 transitions. [2022-07-13 04:23:39,268 INFO L392 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3032 transitions. [2022-07-13 04:23:39,268 INFO L374 stractBuchiCegarLoop]: Abstraction has 2047 states and 3032 transitions. [2022-07-13 04:23:39,269 INFO L287 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-07-13 04:23:39,269 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3032 transitions. [2022-07-13 04:23:39,276 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-07-13 04:23:39,277 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-13 04:23:39,277 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-13 04:23:39,279 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:39,279 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:39,280 INFO L752 eck$LassoCheckResult]: Stem: 13242#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 13243#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 13845#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12962#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12963#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 13208#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13209#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12936#L949-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 12937#L954-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 14160#L959-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13512#L964-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13513#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14030#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 13422#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 13423#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 12843#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12844#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 13175#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 13373#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 12420#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12421#L1342 assume !(0 == ~M_E~0); 12586#L1342-2 assume !(0 == ~T1_E~0); 13142#L1347-1 assume !(0 == ~T2_E~0); 14143#L1352-1 assume !(0 == ~T3_E~0); 13939#L1357-1 assume !(0 == ~T4_E~0); 13167#L1362-1 assume !(0 == ~T5_E~0); 13168#L1367-1 assume !(0 == ~T6_E~0); 12765#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12766#L1377-1 assume !(0 == ~T8_E~0); 13096#L1382-1 assume !(0 == ~T9_E~0); 13097#L1387-1 assume !(0 == ~T10_E~0); 13824#L1392-1 assume !(0 == ~T11_E~0); 13128#L1397-1 assume !(0 == ~T12_E~0); 13129#L1402-1 assume !(0 == ~T13_E~0); 12781#L1407-1 assume !(0 == ~T14_E~0); 12782#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 14060#L1417-1 assume !(0 == ~E_2~0); 14061#L1422-1 assume !(0 == ~E_3~0); 14302#L1427-1 assume !(0 == ~E_4~0); 12969#L1432-1 assume !(0 == ~E_5~0); 12970#L1437-1 assume !(0 == ~E_6~0); 13978#L1442-1 assume !(0 == ~E_7~0); 13979#L1447-1 assume !(0 == ~E_8~0); 13821#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 12556#L1457-1 assume !(0 == ~E_10~0); 12557#L1462-1 assume !(0 == ~E_11~0); 14013#L1467-1 assume !(0 == ~E_12~0); 14025#L1472-1 assume !(0 == ~E_13~0); 14026#L1477-1 assume !(0 == ~E_14~0); 13768#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12755#L646 assume 1 == ~m_pc~0; 12756#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13432#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13447#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12845#L1666 assume !(0 != activate_threads_~tmp~1#1); 12846#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14323#L665 assume !(1 == ~t1_pc~0); 13321#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13322#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12854#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12855#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 13645#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13646#L684 assume 1 == ~t2_pc~0; 13763#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13687#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13752#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14147#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 14148#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14336#L703 assume !(1 == ~t3_pc~0); 12991#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12992#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13638#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12390#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 12391#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12876#L722 assume 1 == ~t4_pc~0; 13614#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13057#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13402#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13962#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 13469#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12587#L741 assume 1 == ~t5_pc~0; 12588#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12898#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13052#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13053#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 13732#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13143#L760 assume !(1 == ~t6_pc~0); 12990#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12989#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12847#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12848#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13569#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13570#L779 assume 1 == ~t7_pc~0; 12632#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12478#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12479#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12887#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 12910#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12911#L798 assume !(1 == ~t8_pc~0); 14192#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 14115#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12634#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12635#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 14325#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12455#L817 assume 1 == ~t9_pc~0; 12456#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 13250#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13251#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13773#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 12861#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12862#L836 assume !(1 == ~t10_pc~0); 12878#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 12809#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12810#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13058#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 13059#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 14125#L855 assume 1 == ~t11_pc~0; 13443#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 13444#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14008#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 13817#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 13652#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12751#L874 assume !(1 == ~t12_pc~0); 12752#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 12919#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12920#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 13060#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 12428#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 12429#L893 assume 1 == ~t13_pc~0; 14259#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 12784#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 13095#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 14186#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 14194#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 14195#L912 assume 1 == ~t14_pc~0; 13985#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 13986#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 12754#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 12686#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 12687#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13462#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 13878#L1495-2 assume !(1 == ~T1_E~0); 13879#L1500-1 assume !(1 == ~T2_E~0); 13565#L1505-1 assume !(1 == ~T3_E~0); 13566#L1510-1 assume !(1 == ~T4_E~0); 13623#L1515-1 assume !(1 == ~T5_E~0); 13624#L1520-1 assume !(1 == ~T6_E~0); 14193#L1525-1 assume !(1 == ~T7_E~0); 13903#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12856#L1535-1 assume !(1 == ~T9_E~0); 12857#L1540-1 assume !(1 == ~T10_E~0); 12349#L1545-1 assume !(1 == ~T11_E~0); 12350#L1550-1 assume !(1 == ~T12_E~0); 12598#L1555-1 assume !(1 == ~T13_E~0); 12599#L1560-1 assume !(1 == ~T14_E~0); 12899#L1565-1 assume !(1 == ~E_1~0); 14312#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 13790#L1575-1 assume !(1 == ~E_3~0); 13169#L1580-1 assume !(1 == ~E_4~0); 13170#L1585-1 assume !(1 == ~E_5~0); 13640#L1590-1 assume !(1 == ~E_6~0); 13204#L1595-1 assume !(1 == ~E_7~0); 13205#L1600-1 assume !(1 == ~E_8~0); 13577#L1605-1 assume !(1 == ~E_9~0); 13578#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 14095#L1615-1 assume !(1 == ~E_11~0); 13034#L1620-1 assume !(1 == ~E_12~0); 13035#L1625-1 assume !(1 == ~E_13~0); 13822#L1630-1 assume !(1 == ~E_14~0); 13203#L1635-1 assume { :end_inline_reset_delta_events } true; 13144#L2017-2 [2022-07-13 04:23:39,281 INFO L754 eck$LassoCheckResult]: Loop: 13144#L2017-2 assume !false; 12424#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12425#L1316 assume !false; 13753#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 13815#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 12362#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 12504#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 12505#L1115 assume !(0 != eval_~tmp~0#1); 13838#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13259#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13260#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13442#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13943#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13612#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13613#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14175#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14350#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14345#L1372-3 assume !(0 == ~T7_E~0); 12406#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12407#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13076#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13077#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 13988#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 14298#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 13556#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 12712#L1412-3 assume !(0 == ~E_1~0); 12713#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13477#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13478#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14172#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13859#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13571#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13572#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12472#L1452-3 assume !(0 == ~E_9~0); 12473#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 14111#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 14112#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 13916#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 13917#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 12710#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12711#L646-42 assume 1 == ~m_pc~0; 13296#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 14144#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14145#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14283#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14284#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14076#L665-42 assume 1 == ~t1_pc~0; 14037#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14039#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14225#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12879#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12880#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14349#L684-42 assume 1 == ~t2_pc~0; 13728#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13729#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14339#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13508#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13509#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13631#L703-42 assume 1 == ~t3_pc~0; 13829#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13830#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13148#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13149#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13923#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13543#L722-42 assume 1 == ~t4_pc~0; 13544#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13954#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13197#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13024#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13025#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14319#L741-42 assume !(1 == ~t5_pc~0); 13936#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 13406#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13407#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14352#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13314#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13315#L760-42 assume !(1 == ~t6_pc~0); 13449#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 13584#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13585#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13973#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 13266#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13267#L779-42 assume 1 == ~t7_pc~0; 14096#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14044#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12951#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12952#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12807#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12808#L798-42 assume !(1 == ~t8_pc~0); 12418#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 12419#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14162#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13608#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12638#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12639#L817-42 assume 1 == ~t9_pc~0; 13412#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12922#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12923#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13049#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13854#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13855#L836-42 assume 1 == ~t10_pc~0; 13947#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 12960#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12961#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 14262#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 14263#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 14304#L855-42 assume 1 == ~t11_pc~0; 14317#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 12511#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12512#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 13261#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 14024#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 13125#L874-42 assume 1 == ~t12_pc~0; 13126#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 13365#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12426#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 12427#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 12680#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 12681#L893-42 assume !(1 == ~t13_pc~0); 13664#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 13665#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 13680#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 13582#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 13054#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 13055#L912-42 assume !(1 == ~t14_pc~0); 13864#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 12372#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 12373#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 13953#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 12800#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12801#L1495-3 assume !(1 == ~M_E~0); 13416#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13844#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13937#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13030#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12993#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12994#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13651#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13874#L1530-3 assume !(1 == ~T8_E~0); 12839#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 12840#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 12877#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 14134#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 14243#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 13283#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 13284#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13899#L1570-3 assume !(1 == ~E_2~0); 13850#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13851#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14206#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14250#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14296#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13673#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 13674#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 14149#L1610-3 assume !(1 == ~E_10~0); 13036#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 13037#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 13641#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 13642#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 13546#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 12977#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 12582#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 13320#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 13876#L2036 assume !(0 == start_simulation_~tmp~3#1); 13877#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 14029#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 13189#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 14207#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 13589#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 13590#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14310#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 14311#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 13144#L2017-2 [2022-07-13 04:23:39,282 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:39,282 INFO L85 PathProgramCache]: Analyzing trace with hash -224599768, now seen corresponding path program 1 times [2022-07-13 04:23:39,283 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:39,283 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [517569565] [2022-07-13 04:23:39,283 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:39,283 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:39,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:39,338 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:39,338 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:39,338 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [517569565] [2022-07-13 04:23:39,338 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [517569565] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:39,338 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:39,338 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-13 04:23:39,338 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [72630016] [2022-07-13 04:23:39,339 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:39,339 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-13 04:23:39,339 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:39,339 INFO L85 PathProgramCache]: Analyzing trace with hash -1715277972, now seen corresponding path program 1 times [2022-07-13 04:23:39,339 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:39,340 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1203498568] [2022-07-13 04:23:39,340 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:39,340 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:39,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:39,373 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:39,373 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:39,373 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1203498568] [2022-07-13 04:23:39,373 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1203498568] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:39,373 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:39,373 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-13 04:23:39,373 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1190516623] [2022-07-13 04:23:39,374 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:39,374 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-13 04:23:39,374 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-13 04:23:39,374 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-13 04:23:39,374 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-13 04:23:39,375 INFO L87 Difference]: Start difference. First operand 2047 states and 3032 transitions. cyclomatic complexity: 986 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:39,398 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-13 04:23:39,398 INFO L93 Difference]: Finished difference Result 2047 states and 3031 transitions. [2022-07-13 04:23:39,399 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-13 04:23:39,399 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3031 transitions. [2022-07-13 04:23:39,408 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-07-13 04:23:39,415 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3031 transitions. [2022-07-13 04:23:39,416 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2022-07-13 04:23:39,417 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2022-07-13 04:23:39,417 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3031 transitions. [2022-07-13 04:23:39,419 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-13 04:23:39,419 INFO L369 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3031 transitions. [2022-07-13 04:23:39,421 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3031 transitions. [2022-07-13 04:23:39,474 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2022-07-13 04:23:39,477 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4807034684904739) internal successors, (3031), 2046 states have internal predecessors, (3031), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:39,481 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3031 transitions. [2022-07-13 04:23:39,481 INFO L392 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3031 transitions. [2022-07-13 04:23:39,481 INFO L374 stractBuchiCegarLoop]: Abstraction has 2047 states and 3031 transitions. [2022-07-13 04:23:39,482 INFO L287 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-07-13 04:23:39,482 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3031 transitions. [2022-07-13 04:23:39,487 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-07-13 04:23:39,487 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-13 04:23:39,487 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-13 04:23:39,489 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:39,489 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:39,489 INFO L752 eck$LassoCheckResult]: Stem: 17343#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 17344#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 17946#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17063#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17064#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 17309#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17310#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17037#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17038#L954-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 18261#L959-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 17613#L964-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17614#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 18131#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17523#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 17524#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 16944#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 16945#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 17276#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 17474#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 16521#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16522#L1342 assume !(0 == ~M_E~0); 16687#L1342-2 assume !(0 == ~T1_E~0); 17243#L1347-1 assume !(0 == ~T2_E~0); 18244#L1352-1 assume !(0 == ~T3_E~0); 18040#L1357-1 assume !(0 == ~T4_E~0); 17268#L1362-1 assume !(0 == ~T5_E~0); 17269#L1367-1 assume !(0 == ~T6_E~0); 16866#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16867#L1377-1 assume !(0 == ~T8_E~0); 17197#L1382-1 assume !(0 == ~T9_E~0); 17198#L1387-1 assume !(0 == ~T10_E~0); 17925#L1392-1 assume !(0 == ~T11_E~0); 17229#L1397-1 assume !(0 == ~T12_E~0); 17230#L1402-1 assume !(0 == ~T13_E~0); 16882#L1407-1 assume !(0 == ~T14_E~0); 16883#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 18161#L1417-1 assume !(0 == ~E_2~0); 18162#L1422-1 assume !(0 == ~E_3~0); 18403#L1427-1 assume !(0 == ~E_4~0); 17070#L1432-1 assume !(0 == ~E_5~0); 17071#L1437-1 assume !(0 == ~E_6~0); 18079#L1442-1 assume !(0 == ~E_7~0); 18080#L1447-1 assume !(0 == ~E_8~0); 17922#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 16657#L1457-1 assume !(0 == ~E_10~0); 16658#L1462-1 assume !(0 == ~E_11~0); 18114#L1467-1 assume !(0 == ~E_12~0); 18126#L1472-1 assume !(0 == ~E_13~0); 18127#L1477-1 assume !(0 == ~E_14~0); 17869#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16856#L646 assume 1 == ~m_pc~0; 16857#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 17533#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17548#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16946#L1666 assume !(0 != activate_threads_~tmp~1#1); 16947#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18424#L665 assume !(1 == ~t1_pc~0); 17422#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 17423#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16955#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16956#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 17746#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17747#L684 assume 1 == ~t2_pc~0; 17864#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17788#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17853#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18248#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 18249#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18437#L703 assume !(1 == ~t3_pc~0); 17092#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 17093#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17739#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16491#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 16492#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16977#L722 assume 1 == ~t4_pc~0; 17715#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17158#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17503#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18063#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 17570#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16688#L741 assume 1 == ~t5_pc~0; 16689#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16999#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17153#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17154#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 17833#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17244#L760 assume !(1 == ~t6_pc~0); 17091#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 17090#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16948#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16949#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17670#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17671#L779 assume 1 == ~t7_pc~0; 16733#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16579#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16580#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16988#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 17011#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17012#L798 assume !(1 == ~t8_pc~0); 18293#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 18216#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16735#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 16736#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 18426#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16556#L817 assume 1 == ~t9_pc~0; 16557#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17351#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17352#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17874#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 16962#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16963#L836 assume !(1 == ~t10_pc~0); 16979#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 16910#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16911#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17159#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 17160#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18226#L855 assume 1 == ~t11_pc~0; 17544#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 17545#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18109#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 17918#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 17753#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 16852#L874 assume !(1 == ~t12_pc~0); 16853#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 17020#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 17021#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 17161#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 16529#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 16530#L893 assume 1 == ~t13_pc~0; 18360#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 16885#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 17196#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 18287#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 18295#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 18296#L912 assume 1 == ~t14_pc~0; 18086#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 18087#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 16855#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 16787#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 16788#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17563#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 17979#L1495-2 assume !(1 == ~T1_E~0); 17980#L1500-1 assume !(1 == ~T2_E~0); 17666#L1505-1 assume !(1 == ~T3_E~0); 17667#L1510-1 assume !(1 == ~T4_E~0); 17724#L1515-1 assume !(1 == ~T5_E~0); 17725#L1520-1 assume !(1 == ~T6_E~0); 18294#L1525-1 assume !(1 == ~T7_E~0); 18004#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16957#L1535-1 assume !(1 == ~T9_E~0); 16958#L1540-1 assume !(1 == ~T10_E~0); 16450#L1545-1 assume !(1 == ~T11_E~0); 16451#L1550-1 assume !(1 == ~T12_E~0); 16699#L1555-1 assume !(1 == ~T13_E~0); 16700#L1560-1 assume !(1 == ~T14_E~0); 17000#L1565-1 assume !(1 == ~E_1~0); 18413#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 17891#L1575-1 assume !(1 == ~E_3~0); 17270#L1580-1 assume !(1 == ~E_4~0); 17271#L1585-1 assume !(1 == ~E_5~0); 17741#L1590-1 assume !(1 == ~E_6~0); 17305#L1595-1 assume !(1 == ~E_7~0); 17306#L1600-1 assume !(1 == ~E_8~0); 17678#L1605-1 assume !(1 == ~E_9~0); 17679#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 18196#L1615-1 assume !(1 == ~E_11~0); 17135#L1620-1 assume !(1 == ~E_12~0); 17136#L1625-1 assume !(1 == ~E_13~0); 17923#L1630-1 assume !(1 == ~E_14~0); 17304#L1635-1 assume { :end_inline_reset_delta_events } true; 17245#L2017-2 [2022-07-13 04:23:39,489 INFO L754 eck$LassoCheckResult]: Loop: 17245#L2017-2 assume !false; 16525#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16526#L1316 assume !false; 17854#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 17916#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 16463#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 16605#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 16606#L1115 assume !(0 != eval_~tmp~0#1); 17939#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17360#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17361#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17543#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18044#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17713#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17714#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18276#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18451#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18446#L1372-3 assume !(0 == ~T7_E~0); 16507#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16508#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 17177#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 17178#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 18089#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 18399#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 17657#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 16813#L1412-3 assume !(0 == ~E_1~0); 16814#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17578#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17579#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18273#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17960#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17672#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17673#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16573#L1452-3 assume !(0 == ~E_9~0); 16574#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 18212#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 18213#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 18017#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 18018#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 16811#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16812#L646-42 assume 1 == ~m_pc~0; 17397#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 18245#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18246#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18384#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18385#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18177#L665-42 assume 1 == ~t1_pc~0; 18138#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18140#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18326#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16980#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16981#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18450#L684-42 assume 1 == ~t2_pc~0; 17829#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17830#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18440#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17609#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17610#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17732#L703-42 assume 1 == ~t3_pc~0; 17930#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17931#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17249#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17250#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18024#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17644#L722-42 assume 1 == ~t4_pc~0; 17645#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18055#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17298#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17125#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17126#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18420#L741-42 assume !(1 == ~t5_pc~0); 18037#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 17507#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17508#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18453#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17415#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17416#L760-42 assume !(1 == ~t6_pc~0); 17550#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 17685#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17686#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18074#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 17367#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17368#L779-42 assume !(1 == ~t7_pc~0); 18144#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 18145#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17052#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17053#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16908#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16909#L798-42 assume !(1 == ~t8_pc~0); 16519#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 16520#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18263#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17709#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16739#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16740#L817-42 assume 1 == ~t9_pc~0; 17513#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17023#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17024#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17150#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 17955#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17956#L836-42 assume 1 == ~t10_pc~0; 18048#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 17061#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17062#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 18363#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 18364#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18405#L855-42 assume 1 == ~t11_pc~0; 18418#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 16612#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 16613#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 17362#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 18125#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 17226#L874-42 assume 1 == ~t12_pc~0; 17227#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 17466#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 16527#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 16528#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 16781#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 16782#L893-42 assume 1 == ~t13_pc~0; 17984#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 17766#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 17781#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 17683#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 17155#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 17156#L912-42 assume 1 == ~t14_pc~0; 18400#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 16473#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 16474#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 18054#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 16901#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16902#L1495-3 assume !(1 == ~M_E~0); 17517#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17945#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18038#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17131#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17094#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17095#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17752#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17975#L1530-3 assume !(1 == ~T8_E~0); 16940#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16941#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 16978#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 18235#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 18344#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 17384#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 17385#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18000#L1570-3 assume !(1 == ~E_2~0); 17951#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17952#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18307#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18351#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18397#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 17774#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17775#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 18250#L1610-3 assume !(1 == ~E_10~0); 17137#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 17138#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 17742#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 17743#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 17647#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 17078#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 16683#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 17421#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 17977#L2036 assume !(0 == start_simulation_~tmp~3#1); 17978#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 18130#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 17290#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 18308#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 17690#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 17691#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18411#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 18412#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 17245#L2017-2 [2022-07-13 04:23:39,490 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:39,490 INFO L85 PathProgramCache]: Analyzing trace with hash -723156570, now seen corresponding path program 1 times [2022-07-13 04:23:39,490 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:39,490 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [644590599] [2022-07-13 04:23:39,490 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:39,490 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:39,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:39,513 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:39,513 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:39,514 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [644590599] [2022-07-13 04:23:39,514 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [644590599] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:39,514 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:39,514 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-13 04:23:39,514 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [654015606] [2022-07-13 04:23:39,514 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:39,514 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-13 04:23:39,515 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:39,515 INFO L85 PathProgramCache]: Analyzing trace with hash 1006606669, now seen corresponding path program 1 times [2022-07-13 04:23:39,515 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:39,515 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [304229359] [2022-07-13 04:23:39,515 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:39,515 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:39,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:39,546 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:39,547 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:39,547 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [304229359] [2022-07-13 04:23:39,547 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [304229359] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:39,547 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:39,547 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-13 04:23:39,547 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [36152077] [2022-07-13 04:23:39,547 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:39,548 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-13 04:23:39,548 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-13 04:23:39,548 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-13 04:23:39,548 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-13 04:23:39,548 INFO L87 Difference]: Start difference. First operand 2047 states and 3031 transitions. cyclomatic complexity: 985 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:39,572 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-13 04:23:39,572 INFO L93 Difference]: Finished difference Result 2047 states and 3030 transitions. [2022-07-13 04:23:39,572 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-13 04:23:39,573 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3030 transitions. [2022-07-13 04:23:39,582 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-07-13 04:23:39,589 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3030 transitions. [2022-07-13 04:23:39,589 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2022-07-13 04:23:39,590 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2022-07-13 04:23:39,590 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3030 transitions. [2022-07-13 04:23:39,592 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-13 04:23:39,592 INFO L369 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3030 transitions. [2022-07-13 04:23:39,594 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3030 transitions. [2022-07-13 04:23:39,611 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2022-07-13 04:23:39,613 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4802149487054226) internal successors, (3030), 2046 states have internal predecessors, (3030), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:39,618 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3030 transitions. [2022-07-13 04:23:39,618 INFO L392 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3030 transitions. [2022-07-13 04:23:39,619 INFO L374 stractBuchiCegarLoop]: Abstraction has 2047 states and 3030 transitions. [2022-07-13 04:23:39,619 INFO L287 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-07-13 04:23:39,619 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3030 transitions. [2022-07-13 04:23:39,624 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-07-13 04:23:39,624 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-13 04:23:39,624 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-13 04:23:39,627 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:39,627 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:39,627 INFO L752 eck$LassoCheckResult]: Stem: 21444#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 21445#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 22047#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21164#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21165#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 21410#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21411#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21138#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21139#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22362#L959-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 21714#L964-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 21715#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 22232#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 21624#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21625#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21045#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21046#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 21377#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 21575#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 20622#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20623#L1342 assume !(0 == ~M_E~0); 20788#L1342-2 assume !(0 == ~T1_E~0); 21344#L1347-1 assume !(0 == ~T2_E~0); 22345#L1352-1 assume !(0 == ~T3_E~0); 22141#L1357-1 assume !(0 == ~T4_E~0); 21369#L1362-1 assume !(0 == ~T5_E~0); 21370#L1367-1 assume !(0 == ~T6_E~0); 20967#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20968#L1377-1 assume !(0 == ~T8_E~0); 21298#L1382-1 assume !(0 == ~T9_E~0); 21299#L1387-1 assume !(0 == ~T10_E~0); 22026#L1392-1 assume !(0 == ~T11_E~0); 21330#L1397-1 assume !(0 == ~T12_E~0); 21331#L1402-1 assume !(0 == ~T13_E~0); 20983#L1407-1 assume !(0 == ~T14_E~0); 20984#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 22262#L1417-1 assume !(0 == ~E_2~0); 22263#L1422-1 assume !(0 == ~E_3~0); 22504#L1427-1 assume !(0 == ~E_4~0); 21171#L1432-1 assume !(0 == ~E_5~0); 21172#L1437-1 assume !(0 == ~E_6~0); 22180#L1442-1 assume !(0 == ~E_7~0); 22181#L1447-1 assume !(0 == ~E_8~0); 22023#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 20758#L1457-1 assume !(0 == ~E_10~0); 20759#L1462-1 assume !(0 == ~E_11~0); 22215#L1467-1 assume !(0 == ~E_12~0); 22227#L1472-1 assume !(0 == ~E_13~0); 22228#L1477-1 assume !(0 == ~E_14~0); 21970#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20957#L646 assume 1 == ~m_pc~0; 20958#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 21634#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21649#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21047#L1666 assume !(0 != activate_threads_~tmp~1#1); 21048#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22525#L665 assume !(1 == ~t1_pc~0); 21523#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 21524#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21056#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21057#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 21847#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21848#L684 assume 1 == ~t2_pc~0; 21965#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21889#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21954#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22349#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 22350#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22538#L703 assume !(1 == ~t3_pc~0); 21193#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21194#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21840#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20592#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 20593#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21078#L722 assume 1 == ~t4_pc~0; 21816#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21259#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21604#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22164#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 21671#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20789#L741 assume 1 == ~t5_pc~0; 20790#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 21100#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21254#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21255#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 21934#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21345#L760 assume !(1 == ~t6_pc~0); 21192#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 21191#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21049#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21050#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 21771#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21772#L779 assume 1 == ~t7_pc~0; 20834#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20680#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20681#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21089#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 21112#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21113#L798 assume !(1 == ~t8_pc~0); 22394#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22317#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20836#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20837#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 22527#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20657#L817 assume 1 == ~t9_pc~0; 20658#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21452#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21453#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21975#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 21063#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21064#L836 assume !(1 == ~t10_pc~0); 21080#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 21011#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21012#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21260#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 21261#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22327#L855 assume 1 == ~t11_pc~0; 21645#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 21646#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 22210#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 22019#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 21854#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20953#L874 assume !(1 == ~t12_pc~0); 20954#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 21121#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21122#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 21262#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 20630#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20631#L893 assume 1 == ~t13_pc~0; 22461#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 20986#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 21297#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 22388#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 22396#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 22397#L912 assume 1 == ~t14_pc~0; 22187#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 22188#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 20956#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 20888#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 20889#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21664#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 22080#L1495-2 assume !(1 == ~T1_E~0); 22081#L1500-1 assume !(1 == ~T2_E~0); 21767#L1505-1 assume !(1 == ~T3_E~0); 21768#L1510-1 assume !(1 == ~T4_E~0); 21825#L1515-1 assume !(1 == ~T5_E~0); 21826#L1520-1 assume !(1 == ~T6_E~0); 22395#L1525-1 assume !(1 == ~T7_E~0); 22105#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 21058#L1535-1 assume !(1 == ~T9_E~0); 21059#L1540-1 assume !(1 == ~T10_E~0); 20551#L1545-1 assume !(1 == ~T11_E~0); 20552#L1550-1 assume !(1 == ~T12_E~0); 20800#L1555-1 assume !(1 == ~T13_E~0); 20801#L1560-1 assume !(1 == ~T14_E~0); 21101#L1565-1 assume !(1 == ~E_1~0); 22514#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 21992#L1575-1 assume !(1 == ~E_3~0); 21371#L1580-1 assume !(1 == ~E_4~0); 21372#L1585-1 assume !(1 == ~E_5~0); 21842#L1590-1 assume !(1 == ~E_6~0); 21406#L1595-1 assume !(1 == ~E_7~0); 21407#L1600-1 assume !(1 == ~E_8~0); 21779#L1605-1 assume !(1 == ~E_9~0); 21780#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 22297#L1615-1 assume !(1 == ~E_11~0); 21236#L1620-1 assume !(1 == ~E_12~0); 21237#L1625-1 assume !(1 == ~E_13~0); 22024#L1630-1 assume !(1 == ~E_14~0); 21405#L1635-1 assume { :end_inline_reset_delta_events } true; 21346#L2017-2 [2022-07-13 04:23:39,628 INFO L754 eck$LassoCheckResult]: Loop: 21346#L2017-2 assume !false; 20626#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20627#L1316 assume !false; 21955#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 22017#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 20564#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 20706#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 20707#L1115 assume !(0 != eval_~tmp~0#1); 22040#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21461#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21462#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21644#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22145#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21814#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21815#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 22377#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22552#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22547#L1372-3 assume !(0 == ~T7_E~0); 20608#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20609#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21278#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21279#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 22190#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 22500#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 21758#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 20914#L1412-3 assume !(0 == ~E_1~0); 20915#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21679#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21680#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22374#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22061#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21773#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 21774#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20674#L1452-3 assume !(0 == ~E_9~0); 20675#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 22313#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22314#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 22118#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 22119#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 20912#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20913#L646-42 assume 1 == ~m_pc~0; 21498#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 22346#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22347#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22485#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22486#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22278#L665-42 assume !(1 == ~t1_pc~0); 22240#L665-44 is_transmit1_triggered_~__retres1~1#1 := 0; 22241#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22427#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21081#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21082#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22551#L684-42 assume 1 == ~t2_pc~0; 21930#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21931#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22541#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21710#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21711#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21833#L703-42 assume !(1 == ~t3_pc~0); 22033#L703-44 is_transmit3_triggered_~__retres1~3#1 := 0; 22032#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21350#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21351#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22125#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21745#L722-42 assume 1 == ~t4_pc~0; 21746#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22156#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21399#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21226#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 21227#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22521#L741-42 assume !(1 == ~t5_pc~0); 22138#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 21608#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21609#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22554#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21516#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21517#L760-42 assume !(1 == ~t6_pc~0); 21651#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 21786#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21787#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22175#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 21468#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21469#L779-42 assume !(1 == ~t7_pc~0); 22245#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 22246#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21153#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21154#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21009#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21010#L798-42 assume 1 == ~t8_pc~0; 21460#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 20621#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22364#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21810#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20840#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20841#L817-42 assume 1 == ~t9_pc~0; 21614#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21124#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21125#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21251#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 22056#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22057#L836-42 assume 1 == ~t10_pc~0; 22149#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21162#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21163#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 22464#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 22465#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22506#L855-42 assume 1 == ~t11_pc~0; 22519#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 20713#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20714#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 21463#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 22226#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 21327#L874-42 assume 1 == ~t12_pc~0; 21328#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 21567#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 20628#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 20629#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 20882#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20883#L893-42 assume 1 == ~t13_pc~0; 22085#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 21867#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 21882#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 21784#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 21256#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 21257#L912-42 assume !(1 == ~t14_pc~0); 22066#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 20574#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 20575#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 22155#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 21002#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21003#L1495-3 assume !(1 == ~M_E~0); 21618#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22046#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22139#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21232#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21195#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 21196#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21853#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22076#L1530-3 assume !(1 == ~T8_E~0); 21041#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21042#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 21079#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 22336#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 22445#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 21485#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 21486#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22101#L1570-3 assume !(1 == ~E_2~0); 22052#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22053#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22408#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22452#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22498#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21875#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21876#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 22351#L1610-3 assume !(1 == ~E_10~0); 21238#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 21239#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 21843#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 21844#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 21748#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 21179#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 20784#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 21522#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 22078#L2036 assume !(0 == start_simulation_~tmp~3#1); 22079#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 22231#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 21391#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 22409#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 21791#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 21792#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22512#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 22513#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 21346#L2017-2 [2022-07-13 04:23:39,628 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:39,629 INFO L85 PathProgramCache]: Analyzing trace with hash -1293428376, now seen corresponding path program 1 times [2022-07-13 04:23:39,629 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:39,629 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [144267300] [2022-07-13 04:23:39,629 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:39,629 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:39,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:39,656 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:39,657 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:39,657 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [144267300] [2022-07-13 04:23:39,657 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [144267300] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:39,657 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:39,657 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-13 04:23:39,660 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [316515954] [2022-07-13 04:23:39,660 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:39,661 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-13 04:23:39,661 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:39,662 INFO L85 PathProgramCache]: Analyzing trace with hash 721372171, now seen corresponding path program 1 times [2022-07-13 04:23:39,663 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:39,663 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1237686978] [2022-07-13 04:23:39,663 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:39,663 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:39,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:39,717 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:39,717 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:39,717 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1237686978] [2022-07-13 04:23:39,719 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1237686978] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:39,720 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:39,720 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-13 04:23:39,720 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1868084046] [2022-07-13 04:23:39,720 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:39,721 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-13 04:23:39,721 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-13 04:23:39,721 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-13 04:23:39,721 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-13 04:23:39,722 INFO L87 Difference]: Start difference. First operand 2047 states and 3030 transitions. cyclomatic complexity: 984 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:39,746 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-13 04:23:39,746 INFO L93 Difference]: Finished difference Result 2047 states and 3029 transitions. [2022-07-13 04:23:39,747 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-13 04:23:39,748 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3029 transitions. [2022-07-13 04:23:39,779 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-07-13 04:23:39,787 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3029 transitions. [2022-07-13 04:23:39,787 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2022-07-13 04:23:39,788 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2022-07-13 04:23:39,788 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3029 transitions. [2022-07-13 04:23:39,790 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-13 04:23:39,790 INFO L369 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3029 transitions. [2022-07-13 04:23:39,792 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3029 transitions. [2022-07-13 04:23:39,808 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2022-07-13 04:23:39,810 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4797264289203713) internal successors, (3029), 2046 states have internal predecessors, (3029), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:39,815 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3029 transitions. [2022-07-13 04:23:39,816 INFO L392 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3029 transitions. [2022-07-13 04:23:39,816 INFO L374 stractBuchiCegarLoop]: Abstraction has 2047 states and 3029 transitions. [2022-07-13 04:23:39,816 INFO L287 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-07-13 04:23:39,816 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3029 transitions. [2022-07-13 04:23:39,821 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-07-13 04:23:39,821 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-13 04:23:39,821 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-13 04:23:39,823 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:39,823 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:39,823 INFO L752 eck$LassoCheckResult]: Stem: 25545#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 25546#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 26148#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25265#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25266#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 25511#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25512#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25239#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25240#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26463#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25815#L964-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 25816#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 26333#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 25725#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25726#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 25146#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 25147#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 25478#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 25676#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 24723#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24724#L1342 assume !(0 == ~M_E~0); 24889#L1342-2 assume !(0 == ~T1_E~0); 25445#L1347-1 assume !(0 == ~T2_E~0); 26446#L1352-1 assume !(0 == ~T3_E~0); 26242#L1357-1 assume !(0 == ~T4_E~0); 25470#L1362-1 assume !(0 == ~T5_E~0); 25471#L1367-1 assume !(0 == ~T6_E~0); 25068#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 25069#L1377-1 assume !(0 == ~T8_E~0); 25399#L1382-1 assume !(0 == ~T9_E~0); 25400#L1387-1 assume !(0 == ~T10_E~0); 26127#L1392-1 assume !(0 == ~T11_E~0); 25431#L1397-1 assume !(0 == ~T12_E~0); 25432#L1402-1 assume !(0 == ~T13_E~0); 25084#L1407-1 assume !(0 == ~T14_E~0); 25085#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 26363#L1417-1 assume !(0 == ~E_2~0); 26364#L1422-1 assume !(0 == ~E_3~0); 26605#L1427-1 assume !(0 == ~E_4~0); 25272#L1432-1 assume !(0 == ~E_5~0); 25273#L1437-1 assume !(0 == ~E_6~0); 26281#L1442-1 assume !(0 == ~E_7~0); 26282#L1447-1 assume !(0 == ~E_8~0); 26124#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 24859#L1457-1 assume !(0 == ~E_10~0); 24860#L1462-1 assume !(0 == ~E_11~0); 26316#L1467-1 assume !(0 == ~E_12~0); 26328#L1472-1 assume !(0 == ~E_13~0); 26329#L1477-1 assume !(0 == ~E_14~0); 26071#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25058#L646 assume 1 == ~m_pc~0; 25059#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 25735#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25750#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25148#L1666 assume !(0 != activate_threads_~tmp~1#1); 25149#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26626#L665 assume !(1 == ~t1_pc~0); 25624#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25625#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25157#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25158#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 25948#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25949#L684 assume 1 == ~t2_pc~0; 26066#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25990#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26055#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26450#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 26451#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26639#L703 assume !(1 == ~t3_pc~0); 25294#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 25295#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25941#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24693#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 24694#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25179#L722 assume 1 == ~t4_pc~0; 25917#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25360#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25705#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26265#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 25772#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24890#L741 assume 1 == ~t5_pc~0; 24891#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25201#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25355#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25356#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 26035#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25446#L760 assume !(1 == ~t6_pc~0); 25293#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 25292#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25150#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25151#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25872#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25873#L779 assume 1 == ~t7_pc~0; 24935#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24781#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24782#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25190#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 25213#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25214#L798 assume !(1 == ~t8_pc~0); 26495#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 26418#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24937#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 24938#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 26628#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24758#L817 assume 1 == ~t9_pc~0; 24759#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25553#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25554#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26076#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 25164#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25165#L836 assume !(1 == ~t10_pc~0); 25181#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25112#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25113#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25361#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 25362#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26428#L855 assume 1 == ~t11_pc~0; 25746#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25747#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 26311#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 26120#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 25955#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25054#L874 assume !(1 == ~t12_pc~0); 25055#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 25222#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 25223#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 25363#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 24731#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 24732#L893 assume 1 == ~t13_pc~0; 26562#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 25087#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 25398#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 26489#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 26497#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 26498#L912 assume 1 == ~t14_pc~0; 26288#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 26289#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 25057#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 24989#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 24990#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25765#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 26181#L1495-2 assume !(1 == ~T1_E~0); 26182#L1500-1 assume !(1 == ~T2_E~0); 25868#L1505-1 assume !(1 == ~T3_E~0); 25869#L1510-1 assume !(1 == ~T4_E~0); 25926#L1515-1 assume !(1 == ~T5_E~0); 25927#L1520-1 assume !(1 == ~T6_E~0); 26496#L1525-1 assume !(1 == ~T7_E~0); 26206#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25159#L1535-1 assume !(1 == ~T9_E~0); 25160#L1540-1 assume !(1 == ~T10_E~0); 24652#L1545-1 assume !(1 == ~T11_E~0); 24653#L1550-1 assume !(1 == ~T12_E~0); 24901#L1555-1 assume !(1 == ~T13_E~0); 24902#L1560-1 assume !(1 == ~T14_E~0); 25202#L1565-1 assume !(1 == ~E_1~0); 26615#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 26093#L1575-1 assume !(1 == ~E_3~0); 25472#L1580-1 assume !(1 == ~E_4~0); 25473#L1585-1 assume !(1 == ~E_5~0); 25943#L1590-1 assume !(1 == ~E_6~0); 25507#L1595-1 assume !(1 == ~E_7~0); 25508#L1600-1 assume !(1 == ~E_8~0); 25880#L1605-1 assume !(1 == ~E_9~0); 25881#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 26398#L1615-1 assume !(1 == ~E_11~0); 25337#L1620-1 assume !(1 == ~E_12~0); 25338#L1625-1 assume !(1 == ~E_13~0); 26125#L1630-1 assume !(1 == ~E_14~0); 25506#L1635-1 assume { :end_inline_reset_delta_events } true; 25447#L2017-2 [2022-07-13 04:23:39,824 INFO L754 eck$LassoCheckResult]: Loop: 25447#L2017-2 assume !false; 24727#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24728#L1316 assume !false; 26056#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 26118#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 24665#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 24807#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 24808#L1115 assume !(0 != eval_~tmp~0#1); 26141#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25562#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25563#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25745#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26246#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25915#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25916#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26478#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 26653#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 26648#L1372-3 assume !(0 == ~T7_E~0); 24709#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24710#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25379#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25380#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 26291#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 26601#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 25859#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 25015#L1412-3 assume !(0 == ~E_1~0); 25016#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25780#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25781#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26475#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26162#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25874#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 25875#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 24775#L1452-3 assume !(0 == ~E_9~0); 24776#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 26414#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 26415#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 26219#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 26220#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 25013#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25014#L646-42 assume !(1 == ~m_pc~0); 25600#L646-44 is_master_triggered_~__retres1~0#1 := 0; 26447#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26448#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26586#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 26587#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26379#L665-42 assume 1 == ~t1_pc~0; 26340#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 26342#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26528#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25182#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25183#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26652#L684-42 assume !(1 == ~t2_pc~0); 26033#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 26032#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26642#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25811#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25812#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25934#L703-42 assume 1 == ~t3_pc~0; 26132#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26133#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25451#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25452#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26226#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25846#L722-42 assume 1 == ~t4_pc~0; 25847#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 26257#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25500#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25327#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25328#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26622#L741-42 assume 1 == ~t5_pc~0; 26564#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25709#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25710#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26655#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25617#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25618#L760-42 assume !(1 == ~t6_pc~0); 25752#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 25887#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25888#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26276#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 25569#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25570#L779-42 assume !(1 == ~t7_pc~0); 26346#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 26347#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25256#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25257#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25110#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25111#L798-42 assume !(1 == ~t8_pc~0); 24721#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 24722#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26465#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25911#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24941#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24942#L817-42 assume 1 == ~t9_pc~0; 25715#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25225#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25226#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25352#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 26157#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 26158#L836-42 assume 1 == ~t10_pc~0; 26250#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 25263#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25264#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 26565#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 26566#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26607#L855-42 assume 1 == ~t11_pc~0; 26620#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 24814#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24815#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25564#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 26327#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25428#L874-42 assume 1 == ~t12_pc~0; 25429#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 25668#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 24729#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 24730#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 24983#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 24984#L893-42 assume 1 == ~t13_pc~0; 26186#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 25968#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 25983#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 25885#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 25357#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 25358#L912-42 assume !(1 == ~t14_pc~0); 26167#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 24675#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 24676#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 26256#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 25103#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25104#L1495-3 assume !(1 == ~M_E~0); 25719#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26147#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26240#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25333#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25296#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25297#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 25954#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26177#L1530-3 assume !(1 == ~T8_E~0); 25142#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25143#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25180#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 26437#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 26546#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 25586#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 25587#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 26202#L1570-3 assume !(1 == ~E_2~0); 26153#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26154#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 26509#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 26553#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 26599#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25976#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25977#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 26452#L1610-3 assume !(1 == ~E_10~0); 25339#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 25340#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 25944#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 25945#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 25849#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 25280#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 24885#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 25623#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 26179#L2036 assume !(0 == start_simulation_~tmp~3#1); 26180#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 26332#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 25492#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 26510#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 25892#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 25893#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26613#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 26614#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 25447#L2017-2 [2022-07-13 04:23:39,824 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:39,824 INFO L85 PathProgramCache]: Analyzing trace with hash 1597669734, now seen corresponding path program 1 times [2022-07-13 04:23:39,825 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:39,825 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2098077546] [2022-07-13 04:23:39,825 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:39,825 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:39,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:39,849 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:39,849 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:39,849 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2098077546] [2022-07-13 04:23:39,850 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2098077546] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:39,850 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:39,850 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-13 04:23:39,850 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1226356384] [2022-07-13 04:23:39,850 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:39,850 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-13 04:23:39,851 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:39,851 INFO L85 PathProgramCache]: Analyzing trace with hash -1842591925, now seen corresponding path program 1 times [2022-07-13 04:23:39,851 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:39,851 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1394488727] [2022-07-13 04:23:39,851 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:39,851 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:39,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:39,881 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:39,882 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:39,882 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1394488727] [2022-07-13 04:23:39,882 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1394488727] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:39,882 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:39,882 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-13 04:23:39,882 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [419075498] [2022-07-13 04:23:39,882 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:39,883 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-13 04:23:39,883 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-13 04:23:39,883 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-13 04:23:39,883 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-13 04:23:39,883 INFO L87 Difference]: Start difference. First operand 2047 states and 3029 transitions. cyclomatic complexity: 983 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:39,907 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-13 04:23:39,908 INFO L93 Difference]: Finished difference Result 2047 states and 3028 transitions. [2022-07-13 04:23:39,908 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-13 04:23:39,909 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3028 transitions. [2022-07-13 04:23:39,916 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-07-13 04:23:39,922 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3028 transitions. [2022-07-13 04:23:39,923 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2022-07-13 04:23:39,924 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2022-07-13 04:23:39,924 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3028 transitions. [2022-07-13 04:23:39,926 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-13 04:23:39,926 INFO L369 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3028 transitions. [2022-07-13 04:23:39,928 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3028 transitions. [2022-07-13 04:23:39,942 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2022-07-13 04:23:39,945 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.47923790913532) internal successors, (3028), 2046 states have internal predecessors, (3028), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:39,954 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3028 transitions. [2022-07-13 04:23:39,956 INFO L392 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3028 transitions. [2022-07-13 04:23:39,956 INFO L374 stractBuchiCegarLoop]: Abstraction has 2047 states and 3028 transitions. [2022-07-13 04:23:39,956 INFO L287 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-07-13 04:23:39,956 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3028 transitions. [2022-07-13 04:23:39,961 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-07-13 04:23:39,961 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-13 04:23:39,961 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-13 04:23:39,963 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:39,963 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:39,963 INFO L752 eck$LassoCheckResult]: Stem: 29646#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 29647#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 30249#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29366#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29367#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 29612#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29613#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29340#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29341#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30564#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29916#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29917#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 30434#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 29826#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29827#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 29247#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 29248#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 29579#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 29777#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 28824#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28825#L1342 assume !(0 == ~M_E~0); 28990#L1342-2 assume !(0 == ~T1_E~0); 29546#L1347-1 assume !(0 == ~T2_E~0); 30547#L1352-1 assume !(0 == ~T3_E~0); 30343#L1357-1 assume !(0 == ~T4_E~0); 29571#L1362-1 assume !(0 == ~T5_E~0); 29572#L1367-1 assume !(0 == ~T6_E~0); 29169#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29170#L1377-1 assume !(0 == ~T8_E~0); 29500#L1382-1 assume !(0 == ~T9_E~0); 29501#L1387-1 assume !(0 == ~T10_E~0); 30228#L1392-1 assume !(0 == ~T11_E~0); 29532#L1397-1 assume !(0 == ~T12_E~0); 29533#L1402-1 assume !(0 == ~T13_E~0); 29185#L1407-1 assume !(0 == ~T14_E~0); 29186#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 30464#L1417-1 assume !(0 == ~E_2~0); 30465#L1422-1 assume !(0 == ~E_3~0); 30706#L1427-1 assume !(0 == ~E_4~0); 29373#L1432-1 assume !(0 == ~E_5~0); 29374#L1437-1 assume !(0 == ~E_6~0); 30382#L1442-1 assume !(0 == ~E_7~0); 30383#L1447-1 assume !(0 == ~E_8~0); 30225#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 28960#L1457-1 assume !(0 == ~E_10~0); 28961#L1462-1 assume !(0 == ~E_11~0); 30417#L1467-1 assume !(0 == ~E_12~0); 30429#L1472-1 assume !(0 == ~E_13~0); 30430#L1477-1 assume !(0 == ~E_14~0); 30172#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29159#L646 assume 1 == ~m_pc~0; 29160#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 29836#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29851#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29249#L1666 assume !(0 != activate_threads_~tmp~1#1); 29250#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30727#L665 assume !(1 == ~t1_pc~0); 29725#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 29726#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29258#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29259#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 30049#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30050#L684 assume 1 == ~t2_pc~0; 30167#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 30091#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30156#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30551#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 30552#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30740#L703 assume !(1 == ~t3_pc~0); 29395#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29396#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30042#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28794#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 28795#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29280#L722 assume 1 == ~t4_pc~0; 30018#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29461#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29806#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30366#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 29873#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28991#L741 assume 1 == ~t5_pc~0; 28992#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 29302#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29456#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29457#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 30136#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29547#L760 assume !(1 == ~t6_pc~0); 29394#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 29393#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29251#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29252#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29973#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29974#L779 assume 1 == ~t7_pc~0; 29036#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28882#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28883#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29291#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 29314#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29315#L798 assume !(1 == ~t8_pc~0); 30596#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 30519#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29038#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29039#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 30729#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28859#L817 assume 1 == ~t9_pc~0; 28860#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29654#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29655#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 30177#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 29265#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29266#L836 assume !(1 == ~t10_pc~0); 29282#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 29213#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29214#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29462#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 29463#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30529#L855 assume 1 == ~t11_pc~0; 29847#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29848#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30412#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 30221#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 30056#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29155#L874 assume !(1 == ~t12_pc~0); 29156#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 29323#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 29324#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 29464#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 28832#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 28833#L893 assume 1 == ~t13_pc~0; 30663#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 29188#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 29499#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 30590#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 30598#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 30599#L912 assume 1 == ~t14_pc~0; 30389#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 30390#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 29158#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 29090#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 29091#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29866#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 30282#L1495-2 assume !(1 == ~T1_E~0); 30283#L1500-1 assume !(1 == ~T2_E~0); 29969#L1505-1 assume !(1 == ~T3_E~0); 29970#L1510-1 assume !(1 == ~T4_E~0); 30027#L1515-1 assume !(1 == ~T5_E~0); 30028#L1520-1 assume !(1 == ~T6_E~0); 30597#L1525-1 assume !(1 == ~T7_E~0); 30307#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 29260#L1535-1 assume !(1 == ~T9_E~0); 29261#L1540-1 assume !(1 == ~T10_E~0); 28753#L1545-1 assume !(1 == ~T11_E~0); 28754#L1550-1 assume !(1 == ~T12_E~0); 29002#L1555-1 assume !(1 == ~T13_E~0); 29003#L1560-1 assume !(1 == ~T14_E~0); 29303#L1565-1 assume !(1 == ~E_1~0); 30716#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 30194#L1575-1 assume !(1 == ~E_3~0); 29573#L1580-1 assume !(1 == ~E_4~0); 29574#L1585-1 assume !(1 == ~E_5~0); 30044#L1590-1 assume !(1 == ~E_6~0); 29608#L1595-1 assume !(1 == ~E_7~0); 29609#L1600-1 assume !(1 == ~E_8~0); 29981#L1605-1 assume !(1 == ~E_9~0); 29982#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 30499#L1615-1 assume !(1 == ~E_11~0); 29438#L1620-1 assume !(1 == ~E_12~0); 29439#L1625-1 assume !(1 == ~E_13~0); 30226#L1630-1 assume !(1 == ~E_14~0); 29607#L1635-1 assume { :end_inline_reset_delta_events } true; 29548#L2017-2 [2022-07-13 04:23:39,964 INFO L754 eck$LassoCheckResult]: Loop: 29548#L2017-2 assume !false; 28828#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28829#L1316 assume !false; 30157#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 30219#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 28766#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 28908#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 28909#L1115 assume !(0 != eval_~tmp~0#1); 30242#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29663#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29664#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 29846#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30347#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30016#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30017#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 30579#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30754#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 30749#L1372-3 assume !(0 == ~T7_E~0); 28810#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28811#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29480#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 29481#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 30392#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 30702#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 29960#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 29116#L1412-3 assume !(0 == ~E_1~0); 29117#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29881#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29882#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30576#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30263#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 29975#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 29976#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 28876#L1452-3 assume !(0 == ~E_9~0); 28877#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 30515#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 30516#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 30320#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 30321#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 29114#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29115#L646-42 assume 1 == ~m_pc~0; 29700#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 30548#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30549#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30687#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30688#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30480#L665-42 assume 1 == ~t1_pc~0; 30441#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30443#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30629#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29283#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29284#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30753#L684-42 assume 1 == ~t2_pc~0; 30132#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 30133#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30743#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29912#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29913#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30035#L703-42 assume 1 == ~t3_pc~0; 30233#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30234#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29552#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29553#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30327#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29947#L722-42 assume 1 == ~t4_pc~0; 29948#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30358#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29601#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29428#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29429#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30723#L741-42 assume !(1 == ~t5_pc~0); 30340#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 29810#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29811#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30756#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29718#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29719#L760-42 assume !(1 == ~t6_pc~0); 29853#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 29988#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29989#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30377#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 29670#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29671#L779-42 assume 1 == ~t7_pc~0; 30500#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30448#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29357#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29358#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29211#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29212#L798-42 assume !(1 == ~t8_pc~0); 28822#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 28823#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30566#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30012#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29042#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29043#L817-42 assume 1 == ~t9_pc~0; 29816#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29326#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29327#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29453#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 30258#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 30259#L836-42 assume !(1 == ~t10_pc~0); 30352#L836-44 is_transmit10_triggered_~__retres1~10#1 := 0; 29364#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29365#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 30666#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 30667#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30708#L855-42 assume 1 == ~t11_pc~0; 30721#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 28915#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28916#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 29665#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 30428#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29529#L874-42 assume 1 == ~t12_pc~0; 29530#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 29769#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28830#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 28831#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 29084#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 29085#L893-42 assume 1 == ~t13_pc~0; 30288#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 30069#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 30084#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 29986#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 29458#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 29459#L912-42 assume !(1 == ~t14_pc~0); 30268#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 28776#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 28777#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 30357#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 29204#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29205#L1495-3 assume !(1 == ~M_E~0); 29820#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30248#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30341#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29434#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29397#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 29398#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30055#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30278#L1530-3 assume !(1 == ~T8_E~0); 29243#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 29244#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29281#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 30538#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 30647#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 29687#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 29688#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30303#L1570-3 assume !(1 == ~E_2~0); 30254#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30255#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30610#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30654#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30700#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 30077#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 30078#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 30553#L1610-3 assume !(1 == ~E_10~0); 29440#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 29441#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 30045#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 30046#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 29950#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 29381#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 28986#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 29724#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 30280#L2036 assume !(0 == start_simulation_~tmp~3#1); 30281#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 30433#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 29593#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 30611#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 29993#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 29994#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30714#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 30715#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 29548#L2017-2 [2022-07-13 04:23:39,964 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:39,964 INFO L85 PathProgramCache]: Analyzing trace with hash -1911299672, now seen corresponding path program 1 times [2022-07-13 04:23:39,964 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:39,965 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1213072476] [2022-07-13 04:23:39,965 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:39,966 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:39,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:39,995 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:39,996 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:39,996 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1213072476] [2022-07-13 04:23:39,999 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1213072476] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:40,000 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:40,000 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-13 04:23:40,000 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1363158416] [2022-07-13 04:23:40,000 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:40,001 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-13 04:23:40,001 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:40,001 INFO L85 PathProgramCache]: Analyzing trace with hash 1991472556, now seen corresponding path program 1 times [2022-07-13 04:23:40,002 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:40,003 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1585508986] [2022-07-13 04:23:40,004 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:40,004 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:40,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:40,037 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:40,037 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:40,037 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1585508986] [2022-07-13 04:23:40,039 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1585508986] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:40,039 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:40,039 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-13 04:23:40,040 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1025753348] [2022-07-13 04:23:40,040 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:40,040 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-13 04:23:40,040 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-13 04:23:40,041 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-13 04:23:40,041 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-13 04:23:40,041 INFO L87 Difference]: Start difference. First operand 2047 states and 3028 transitions. cyclomatic complexity: 982 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:40,063 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-13 04:23:40,064 INFO L93 Difference]: Finished difference Result 2047 states and 3027 transitions. [2022-07-13 04:23:40,064 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-13 04:23:40,066 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3027 transitions. [2022-07-13 04:23:40,073 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-07-13 04:23:40,080 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3027 transitions. [2022-07-13 04:23:40,080 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2022-07-13 04:23:40,081 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2022-07-13 04:23:40,081 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3027 transitions. [2022-07-13 04:23:40,083 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-13 04:23:40,083 INFO L369 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3027 transitions. [2022-07-13 04:23:40,085 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3027 transitions. [2022-07-13 04:23:40,130 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2022-07-13 04:23:40,133 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4787493893502688) internal successors, (3027), 2046 states have internal predecessors, (3027), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:40,137 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3027 transitions. [2022-07-13 04:23:40,137 INFO L392 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3027 transitions. [2022-07-13 04:23:40,137 INFO L374 stractBuchiCegarLoop]: Abstraction has 2047 states and 3027 transitions. [2022-07-13 04:23:40,138 INFO L287 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-07-13 04:23:40,138 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3027 transitions. [2022-07-13 04:23:40,143 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-07-13 04:23:40,143 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-13 04:23:40,143 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-13 04:23:40,144 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:40,145 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:40,145 INFO L752 eck$LassoCheckResult]: Stem: 33747#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 33748#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 34350#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33467#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 33468#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 33713#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33714#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33441#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33442#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34665#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 34017#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 34018#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 34535#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 33927#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33928#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 33348#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 33349#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 33680#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 33878#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 32925#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32926#L1342 assume !(0 == ~M_E~0); 33091#L1342-2 assume !(0 == ~T1_E~0); 33647#L1347-1 assume !(0 == ~T2_E~0); 34648#L1352-1 assume !(0 == ~T3_E~0); 34444#L1357-1 assume !(0 == ~T4_E~0); 33672#L1362-1 assume !(0 == ~T5_E~0); 33673#L1367-1 assume !(0 == ~T6_E~0); 33270#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 33271#L1377-1 assume !(0 == ~T8_E~0); 33601#L1382-1 assume !(0 == ~T9_E~0); 33602#L1387-1 assume !(0 == ~T10_E~0); 34329#L1392-1 assume !(0 == ~T11_E~0); 33633#L1397-1 assume !(0 == ~T12_E~0); 33634#L1402-1 assume !(0 == ~T13_E~0); 33286#L1407-1 assume !(0 == ~T14_E~0); 33287#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 34565#L1417-1 assume !(0 == ~E_2~0); 34566#L1422-1 assume !(0 == ~E_3~0); 34807#L1427-1 assume !(0 == ~E_4~0); 33474#L1432-1 assume !(0 == ~E_5~0); 33475#L1437-1 assume !(0 == ~E_6~0); 34483#L1442-1 assume !(0 == ~E_7~0); 34484#L1447-1 assume !(0 == ~E_8~0); 34326#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 33061#L1457-1 assume !(0 == ~E_10~0); 33062#L1462-1 assume !(0 == ~E_11~0); 34518#L1467-1 assume !(0 == ~E_12~0); 34530#L1472-1 assume !(0 == ~E_13~0); 34531#L1477-1 assume !(0 == ~E_14~0); 34273#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33260#L646 assume 1 == ~m_pc~0; 33261#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 33937#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33952#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33350#L1666 assume !(0 != activate_threads_~tmp~1#1); 33351#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34828#L665 assume !(1 == ~t1_pc~0); 33826#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 33827#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33359#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33360#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 34150#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34151#L684 assume 1 == ~t2_pc~0; 34268#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 34192#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34257#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34652#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 34653#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34841#L703 assume !(1 == ~t3_pc~0); 33496#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33497#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34143#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32895#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 32896#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33381#L722 assume 1 == ~t4_pc~0; 34119#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33562#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33907#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34467#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 33974#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33092#L741 assume 1 == ~t5_pc~0; 33093#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33403#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33557#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33558#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 34237#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33648#L760 assume !(1 == ~t6_pc~0); 33495#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 33494#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33352#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33353#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 34074#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 34075#L779 assume 1 == ~t7_pc~0; 33137#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 32983#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32984#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33392#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 33415#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33416#L798 assume !(1 == ~t8_pc~0); 34697#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 34620#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33139#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33140#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 34830#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32960#L817 assume 1 == ~t9_pc~0; 32961#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33755#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33756#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 34278#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 33366#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33367#L836 assume !(1 == ~t10_pc~0); 33383#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 33314#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33315#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33563#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 33564#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34630#L855 assume 1 == ~t11_pc~0; 33948#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 33949#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 34513#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 34322#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 34157#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33256#L874 assume !(1 == ~t12_pc~0); 33257#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 33424#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 33425#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 33565#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 32933#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 32934#L893 assume 1 == ~t13_pc~0; 34764#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 33289#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 33600#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 34691#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 34699#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 34700#L912 assume 1 == ~t14_pc~0; 34490#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 34491#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 33259#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 33191#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 33192#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33967#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 34383#L1495-2 assume !(1 == ~T1_E~0); 34384#L1500-1 assume !(1 == ~T2_E~0); 34070#L1505-1 assume !(1 == ~T3_E~0); 34071#L1510-1 assume !(1 == ~T4_E~0); 34128#L1515-1 assume !(1 == ~T5_E~0); 34129#L1520-1 assume !(1 == ~T6_E~0); 34698#L1525-1 assume !(1 == ~T7_E~0); 34408#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 33361#L1535-1 assume !(1 == ~T9_E~0); 33362#L1540-1 assume !(1 == ~T10_E~0); 32854#L1545-1 assume !(1 == ~T11_E~0); 32855#L1550-1 assume !(1 == ~T12_E~0); 33103#L1555-1 assume !(1 == ~T13_E~0); 33104#L1560-1 assume !(1 == ~T14_E~0); 33404#L1565-1 assume !(1 == ~E_1~0); 34817#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 34295#L1575-1 assume !(1 == ~E_3~0); 33674#L1580-1 assume !(1 == ~E_4~0); 33675#L1585-1 assume !(1 == ~E_5~0); 34145#L1590-1 assume !(1 == ~E_6~0); 33709#L1595-1 assume !(1 == ~E_7~0); 33710#L1600-1 assume !(1 == ~E_8~0); 34082#L1605-1 assume !(1 == ~E_9~0); 34083#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 34600#L1615-1 assume !(1 == ~E_11~0); 33539#L1620-1 assume !(1 == ~E_12~0); 33540#L1625-1 assume !(1 == ~E_13~0); 34327#L1630-1 assume !(1 == ~E_14~0); 33708#L1635-1 assume { :end_inline_reset_delta_events } true; 33649#L2017-2 [2022-07-13 04:23:40,145 INFO L754 eck$LassoCheckResult]: Loop: 33649#L2017-2 assume !false; 32929#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32930#L1316 assume !false; 34258#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 34320#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 32867#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 33009#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 33010#L1115 assume !(0 != eval_~tmp~0#1); 34343#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33764#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33765#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 33947#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 34448#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34117#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 34118#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 34680#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 34855#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 34850#L1372-3 assume !(0 == ~T7_E~0); 32911#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32912#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 33581#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 33582#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 34493#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 34803#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 34061#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 33217#L1412-3 assume !(0 == ~E_1~0); 33218#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33982#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33983#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 34677#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 34364#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 34076#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 34077#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 32977#L1452-3 assume !(0 == ~E_9~0); 32978#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 34616#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 34617#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 34421#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 34422#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 33215#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33216#L646-42 assume 1 == ~m_pc~0; 33801#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 34649#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34650#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 34788#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 34789#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34581#L665-42 assume 1 == ~t1_pc~0; 34542#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 34544#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34730#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33384#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33385#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34854#L684-42 assume 1 == ~t2_pc~0; 34233#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 34234#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34844#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34013#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34014#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34136#L703-42 assume !(1 == ~t3_pc~0); 34336#L703-44 is_transmit3_triggered_~__retres1~3#1 := 0; 34335#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33653#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33654#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 34428#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34048#L722-42 assume 1 == ~t4_pc~0; 34049#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 34459#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33702#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33529#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33530#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34824#L741-42 assume !(1 == ~t5_pc~0); 34441#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 33911#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33912#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34857#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 33819#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33820#L760-42 assume !(1 == ~t6_pc~0); 33954#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 34089#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34090#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34478#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 33771#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33772#L779-42 assume !(1 == ~t7_pc~0); 34548#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 34549#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33458#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33459#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 33312#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33313#L798-42 assume 1 == ~t8_pc~0; 33763#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 32924#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34667#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34113#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 33143#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33144#L817-42 assume 1 == ~t9_pc~0; 33917#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33427#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33428#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33554#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 34359#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 34360#L836-42 assume 1 == ~t10_pc~0; 34452#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 33465#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33466#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 34767#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 34768#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34809#L855-42 assume 1 == ~t11_pc~0; 34822#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 33016#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33017#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 33766#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 34529#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33630#L874-42 assume !(1 == ~t12_pc~0); 33632#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 33873#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32931#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 32932#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 33185#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 33186#L893-42 assume 1 == ~t13_pc~0; 34389#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 34170#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 34185#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 34087#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 33559#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 33560#L912-42 assume !(1 == ~t14_pc~0); 34369#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 32877#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 32878#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 34458#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 33305#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33306#L1495-3 assume !(1 == ~M_E~0); 33921#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34349#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34442#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33535#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33498#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 33499#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34156#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34379#L1530-3 assume !(1 == ~T8_E~0); 33344#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 33345#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 33382#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 34639#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 34748#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 33788#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 33789#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 34404#L1570-3 assume !(1 == ~E_2~0); 34355#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34356#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 34711#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 34755#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 34801#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 34178#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 34179#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 34654#L1610-3 assume !(1 == ~E_10~0); 33541#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 33542#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 34146#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 34147#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 34051#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 33482#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 33087#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 33825#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 34381#L2036 assume !(0 == start_simulation_~tmp~3#1); 34382#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 34534#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 33694#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 34712#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 34094#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 34095#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34815#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 34816#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 33649#L2017-2 [2022-07-13 04:23:40,146 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:40,146 INFO L85 PathProgramCache]: Analyzing trace with hash 1716285734, now seen corresponding path program 1 times [2022-07-13 04:23:40,146 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:40,147 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [416460797] [2022-07-13 04:23:40,147 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:40,147 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:40,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:40,167 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:40,167 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:40,167 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [416460797] [2022-07-13 04:23:40,168 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [416460797] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:40,168 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:40,168 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-13 04:23:40,168 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1214531540] [2022-07-13 04:23:40,168 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:40,169 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-13 04:23:40,169 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:40,169 INFO L85 PathProgramCache]: Analyzing trace with hash -1856485429, now seen corresponding path program 1 times [2022-07-13 04:23:40,169 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:40,169 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1335383411] [2022-07-13 04:23:40,169 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:40,169 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:40,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:40,203 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:40,203 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:40,203 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1335383411] [2022-07-13 04:23:40,204 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1335383411] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:40,204 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:40,204 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-13 04:23:40,204 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [470139199] [2022-07-13 04:23:40,204 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:40,204 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-13 04:23:40,204 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-13 04:23:40,205 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-13 04:23:40,205 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-13 04:23:40,205 INFO L87 Difference]: Start difference. First operand 2047 states and 3027 transitions. cyclomatic complexity: 981 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:40,227 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-13 04:23:40,227 INFO L93 Difference]: Finished difference Result 2047 states and 3026 transitions. [2022-07-13 04:23:40,228 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-13 04:23:40,229 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3026 transitions. [2022-07-13 04:23:40,236 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-07-13 04:23:40,249 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3026 transitions. [2022-07-13 04:23:40,249 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2022-07-13 04:23:40,250 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2022-07-13 04:23:40,250 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3026 transitions. [2022-07-13 04:23:40,253 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-13 04:23:40,253 INFO L369 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3026 transitions. [2022-07-13 04:23:40,255 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3026 transitions. [2022-07-13 04:23:40,274 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2022-07-13 04:23:40,287 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4782608695652173) internal successors, (3026), 2046 states have internal predecessors, (3026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:40,293 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3026 transitions. [2022-07-13 04:23:40,293 INFO L392 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3026 transitions. [2022-07-13 04:23:40,293 INFO L374 stractBuchiCegarLoop]: Abstraction has 2047 states and 3026 transitions. [2022-07-13 04:23:40,293 INFO L287 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-07-13 04:23:40,293 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3026 transitions. [2022-07-13 04:23:40,298 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-07-13 04:23:40,299 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-13 04:23:40,299 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-13 04:23:40,300 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:40,300 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:40,301 INFO L752 eck$LassoCheckResult]: Stem: 37848#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 37849#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 38451#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37568#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 37569#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 37814#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37815#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 37542#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37543#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 38766#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 38118#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 38119#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 38636#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 38028#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 38029#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 37449#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 37450#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 37781#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 37979#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 37026#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37027#L1342 assume !(0 == ~M_E~0); 37192#L1342-2 assume !(0 == ~T1_E~0); 37748#L1347-1 assume !(0 == ~T2_E~0); 38749#L1352-1 assume !(0 == ~T3_E~0); 38545#L1357-1 assume !(0 == ~T4_E~0); 37773#L1362-1 assume !(0 == ~T5_E~0); 37774#L1367-1 assume !(0 == ~T6_E~0); 37371#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 37372#L1377-1 assume !(0 == ~T8_E~0); 37702#L1382-1 assume !(0 == ~T9_E~0); 37703#L1387-1 assume !(0 == ~T10_E~0); 38430#L1392-1 assume !(0 == ~T11_E~0); 37734#L1397-1 assume !(0 == ~T12_E~0); 37735#L1402-1 assume !(0 == ~T13_E~0); 37387#L1407-1 assume !(0 == ~T14_E~0); 37388#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 38666#L1417-1 assume !(0 == ~E_2~0); 38667#L1422-1 assume !(0 == ~E_3~0); 38908#L1427-1 assume !(0 == ~E_4~0); 37575#L1432-1 assume !(0 == ~E_5~0); 37576#L1437-1 assume !(0 == ~E_6~0); 38584#L1442-1 assume !(0 == ~E_7~0); 38585#L1447-1 assume !(0 == ~E_8~0); 38427#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 37162#L1457-1 assume !(0 == ~E_10~0); 37163#L1462-1 assume !(0 == ~E_11~0); 38619#L1467-1 assume !(0 == ~E_12~0); 38631#L1472-1 assume !(0 == ~E_13~0); 38632#L1477-1 assume !(0 == ~E_14~0); 38374#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37361#L646 assume 1 == ~m_pc~0; 37362#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 38038#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38053#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37451#L1666 assume !(0 != activate_threads_~tmp~1#1); 37452#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38929#L665 assume !(1 == ~t1_pc~0); 37927#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 37928#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37460#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37461#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 38251#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38252#L684 assume 1 == ~t2_pc~0; 38369#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38293#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38358#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38753#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 38754#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38942#L703 assume !(1 == ~t3_pc~0); 37597#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 37598#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38244#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36996#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 36997#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37482#L722 assume 1 == ~t4_pc~0; 38220#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37663#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38008#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 38568#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 38075#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37193#L741 assume 1 == ~t5_pc~0; 37194#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37504#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37658#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37659#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 38338#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37749#L760 assume !(1 == ~t6_pc~0); 37596#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 37595#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37453#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37454#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 38175#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38176#L779 assume 1 == ~t7_pc~0; 37238#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 37084#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37085#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37493#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 37516#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37517#L798 assume !(1 == ~t8_pc~0); 38798#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 38721#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37240#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37241#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 38931#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37061#L817 assume 1 == ~t9_pc~0; 37062#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 37856#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37857#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 38379#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 37467#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37468#L836 assume !(1 == ~t10_pc~0); 37484#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 37415#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37416#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37664#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 37665#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 38731#L855 assume 1 == ~t11_pc~0; 38049#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 38050#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 38614#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 38423#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 38258#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37357#L874 assume !(1 == ~t12_pc~0); 37358#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 37525#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 37526#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 37666#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 37034#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 37035#L893 assume 1 == ~t13_pc~0; 38865#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 37390#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 37701#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 38792#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 38800#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 38801#L912 assume 1 == ~t14_pc~0; 38591#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 38592#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 37360#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 37292#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 37293#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38068#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 38484#L1495-2 assume !(1 == ~T1_E~0); 38485#L1500-1 assume !(1 == ~T2_E~0); 38171#L1505-1 assume !(1 == ~T3_E~0); 38172#L1510-1 assume !(1 == ~T4_E~0); 38229#L1515-1 assume !(1 == ~T5_E~0); 38230#L1520-1 assume !(1 == ~T6_E~0); 38799#L1525-1 assume !(1 == ~T7_E~0); 38509#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 37462#L1535-1 assume !(1 == ~T9_E~0); 37463#L1540-1 assume !(1 == ~T10_E~0); 36955#L1545-1 assume !(1 == ~T11_E~0); 36956#L1550-1 assume !(1 == ~T12_E~0); 37204#L1555-1 assume !(1 == ~T13_E~0); 37205#L1560-1 assume !(1 == ~T14_E~0); 37505#L1565-1 assume !(1 == ~E_1~0); 38918#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 38396#L1575-1 assume !(1 == ~E_3~0); 37775#L1580-1 assume !(1 == ~E_4~0); 37776#L1585-1 assume !(1 == ~E_5~0); 38246#L1590-1 assume !(1 == ~E_6~0); 37810#L1595-1 assume !(1 == ~E_7~0); 37811#L1600-1 assume !(1 == ~E_8~0); 38183#L1605-1 assume !(1 == ~E_9~0); 38184#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 38701#L1615-1 assume !(1 == ~E_11~0); 37640#L1620-1 assume !(1 == ~E_12~0); 37641#L1625-1 assume !(1 == ~E_13~0); 38428#L1630-1 assume !(1 == ~E_14~0); 37809#L1635-1 assume { :end_inline_reset_delta_events } true; 37750#L2017-2 [2022-07-13 04:23:40,301 INFO L754 eck$LassoCheckResult]: Loop: 37750#L2017-2 assume !false; 37030#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37031#L1316 assume !false; 38359#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 38421#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 36968#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 37110#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 37111#L1115 assume !(0 != eval_~tmp~0#1); 38444#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37865#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37866#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 38048#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 38549#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38218#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 38219#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 38781#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 38956#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 38951#L1372-3 assume !(0 == ~T7_E~0); 37012#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37013#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37682#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 37683#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 38594#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 38904#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 38162#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 37318#L1412-3 assume !(0 == ~E_1~0); 37319#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 38083#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 38084#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 38778#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38465#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 38177#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 38178#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37078#L1452-3 assume !(0 == ~E_9~0); 37079#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 38717#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 38718#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 38522#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 38523#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 37316#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37317#L646-42 assume 1 == ~m_pc~0; 37902#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 38750#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38751#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 38889#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 38890#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38682#L665-42 assume 1 == ~t1_pc~0; 38643#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 38645#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38831#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37485#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 37486#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38955#L684-42 assume !(1 == ~t2_pc~0); 38336#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 38335#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38945#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38114#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38115#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38237#L703-42 assume 1 == ~t3_pc~0; 38435#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 38436#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37754#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37755#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 38529#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38149#L722-42 assume 1 == ~t4_pc~0; 38150#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 38560#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37803#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37630#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37631#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38925#L741-42 assume 1 == ~t5_pc~0; 38867#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 38012#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38013#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 38958#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 37920#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37921#L760-42 assume !(1 == ~t6_pc~0); 38055#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 38190#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38191#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38579#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 37872#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37873#L779-42 assume !(1 == ~t7_pc~0); 38649#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 38650#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37559#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37560#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 37413#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37414#L798-42 assume !(1 == ~t8_pc~0); 37024#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 37025#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38768#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 38214#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 37244#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37245#L817-42 assume 1 == ~t9_pc~0; 38018#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 37528#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37529#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37655#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 38460#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38461#L836-42 assume 1 == ~t10_pc~0; 38553#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 37566#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37567#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 38868#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 38869#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 38910#L855-42 assume 1 == ~t11_pc~0; 38923#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 37117#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 37118#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 37867#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 38630#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37731#L874-42 assume 1 == ~t12_pc~0; 37732#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 37974#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 37032#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 37033#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 37286#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 37287#L893-42 assume 1 == ~t13_pc~0; 38490#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 38271#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 38286#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 38188#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 37660#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 37661#L912-42 assume !(1 == ~t14_pc~0); 38470#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 36978#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 36979#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 38559#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 37406#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37407#L1495-3 assume !(1 == ~M_E~0); 38022#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 38450#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 38543#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37636#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37599#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37600#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 38257#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38480#L1530-3 assume !(1 == ~T8_E~0); 37445#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 37446#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 37483#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 38740#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 38849#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 37889#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 37890#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 38505#L1570-3 assume !(1 == ~E_2~0); 38456#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 38457#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 38812#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 38856#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 38902#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 38279#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 38280#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 38755#L1610-3 assume !(1 == ~E_10~0); 37642#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 37643#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 38247#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 38248#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 38152#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 37583#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 37188#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 37926#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 38482#L2036 assume !(0 == start_simulation_~tmp~3#1); 38483#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 38635#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 37795#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 38813#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 38195#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 38196#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 38916#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 38917#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 37750#L2017-2 [2022-07-13 04:23:40,302 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:40,302 INFO L85 PathProgramCache]: Analyzing trace with hash -383452696, now seen corresponding path program 1 times [2022-07-13 04:23:40,302 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:40,302 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [909899337] [2022-07-13 04:23:40,302 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:40,302 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:40,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:40,330 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:40,331 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:40,331 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [909899337] [2022-07-13 04:23:40,331 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [909899337] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:40,331 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:40,331 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-13 04:23:40,331 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1906680886] [2022-07-13 04:23:40,332 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:40,333 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-13 04:23:40,333 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:40,333 INFO L85 PathProgramCache]: Analyzing trace with hash -1218842068, now seen corresponding path program 1 times [2022-07-13 04:23:40,333 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:40,334 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1842843288] [2022-07-13 04:23:40,334 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:40,334 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:40,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:40,370 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:40,370 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:40,370 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1842843288] [2022-07-13 04:23:40,370 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1842843288] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:40,370 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:40,370 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-13 04:23:40,371 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2146494854] [2022-07-13 04:23:40,371 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:40,371 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-13 04:23:40,371 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-13 04:23:40,372 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-13 04:23:40,372 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-13 04:23:40,373 INFO L87 Difference]: Start difference. First operand 2047 states and 3026 transitions. cyclomatic complexity: 980 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:40,395 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-13 04:23:40,395 INFO L93 Difference]: Finished difference Result 2047 states and 3025 transitions. [2022-07-13 04:23:40,395 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-13 04:23:40,396 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3025 transitions. [2022-07-13 04:23:40,403 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-07-13 04:23:40,408 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3025 transitions. [2022-07-13 04:23:40,408 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2022-07-13 04:23:40,409 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2022-07-13 04:23:40,410 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3025 transitions. [2022-07-13 04:23:40,412 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-13 04:23:40,412 INFO L369 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3025 transitions. [2022-07-13 04:23:40,414 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3025 transitions. [2022-07-13 04:23:40,432 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2022-07-13 04:23:40,434 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.477772349780166) internal successors, (3025), 2046 states have internal predecessors, (3025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:40,439 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3025 transitions. [2022-07-13 04:23:40,439 INFO L392 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3025 transitions. [2022-07-13 04:23:40,439 INFO L374 stractBuchiCegarLoop]: Abstraction has 2047 states and 3025 transitions. [2022-07-13 04:23:40,439 INFO L287 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-07-13 04:23:40,439 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3025 transitions. [2022-07-13 04:23:40,444 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-07-13 04:23:40,444 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-13 04:23:40,445 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-13 04:23:40,446 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:40,446 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:40,446 INFO L752 eck$LassoCheckResult]: Stem: 41949#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 41950#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 42552#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41669#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41670#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 41915#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41916#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41643#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41644#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 42867#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 42219#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 42220#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 42737#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 42129#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 42130#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 41550#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 41551#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 41882#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 42080#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 41127#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41128#L1342 assume !(0 == ~M_E~0); 41293#L1342-2 assume !(0 == ~T1_E~0); 41849#L1347-1 assume !(0 == ~T2_E~0); 42850#L1352-1 assume !(0 == ~T3_E~0); 42646#L1357-1 assume !(0 == ~T4_E~0); 41874#L1362-1 assume !(0 == ~T5_E~0); 41875#L1367-1 assume !(0 == ~T6_E~0); 41472#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 41473#L1377-1 assume !(0 == ~T8_E~0); 41803#L1382-1 assume !(0 == ~T9_E~0); 41804#L1387-1 assume !(0 == ~T10_E~0); 42531#L1392-1 assume !(0 == ~T11_E~0); 41835#L1397-1 assume !(0 == ~T12_E~0); 41836#L1402-1 assume !(0 == ~T13_E~0); 41488#L1407-1 assume !(0 == ~T14_E~0); 41489#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 42767#L1417-1 assume !(0 == ~E_2~0); 42768#L1422-1 assume !(0 == ~E_3~0); 43009#L1427-1 assume !(0 == ~E_4~0); 41676#L1432-1 assume !(0 == ~E_5~0); 41677#L1437-1 assume !(0 == ~E_6~0); 42685#L1442-1 assume !(0 == ~E_7~0); 42686#L1447-1 assume !(0 == ~E_8~0); 42528#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 41263#L1457-1 assume !(0 == ~E_10~0); 41264#L1462-1 assume !(0 == ~E_11~0); 42720#L1467-1 assume !(0 == ~E_12~0); 42732#L1472-1 assume !(0 == ~E_13~0); 42733#L1477-1 assume !(0 == ~E_14~0); 42475#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41462#L646 assume 1 == ~m_pc~0; 41463#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 42139#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42154#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41552#L1666 assume !(0 != activate_threads_~tmp~1#1); 41553#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43030#L665 assume !(1 == ~t1_pc~0); 42028#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 42029#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41561#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41562#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 42352#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42353#L684 assume 1 == ~t2_pc~0; 42470#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 42394#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42459#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42854#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 42855#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43043#L703 assume !(1 == ~t3_pc~0); 41698#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 41699#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42345#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41097#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 41098#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41583#L722 assume 1 == ~t4_pc~0; 42321#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41764#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 42109#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 42669#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 42176#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41294#L741 assume 1 == ~t5_pc~0; 41295#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 41605#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41759#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41760#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 42439#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41850#L760 assume !(1 == ~t6_pc~0); 41697#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 41696#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41554#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 41555#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 42276#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42277#L779 assume 1 == ~t7_pc~0; 41339#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41185#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41186#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41594#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 41617#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41618#L798 assume !(1 == ~t8_pc~0); 42899#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 42822#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41341#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 41342#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 43032#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41162#L817 assume 1 == ~t9_pc~0; 41163#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41957#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41958#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 42480#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 41568#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41569#L836 assume !(1 == ~t10_pc~0); 41585#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 41516#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41517#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41765#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 41766#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 42832#L855 assume 1 == ~t11_pc~0; 42150#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 42151#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 42715#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 42524#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 42359#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41458#L874 assume !(1 == ~t12_pc~0); 41459#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 41626#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 41627#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 41767#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 41135#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 41136#L893 assume 1 == ~t13_pc~0; 42966#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 41491#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 41802#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 42893#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 42901#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 42902#L912 assume 1 == ~t14_pc~0; 42692#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 42693#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 41461#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 41393#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 41394#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42169#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 42585#L1495-2 assume !(1 == ~T1_E~0); 42586#L1500-1 assume !(1 == ~T2_E~0); 42272#L1505-1 assume !(1 == ~T3_E~0); 42273#L1510-1 assume !(1 == ~T4_E~0); 42330#L1515-1 assume !(1 == ~T5_E~0); 42331#L1520-1 assume !(1 == ~T6_E~0); 42900#L1525-1 assume !(1 == ~T7_E~0); 42610#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 41563#L1535-1 assume !(1 == ~T9_E~0); 41564#L1540-1 assume !(1 == ~T10_E~0); 41056#L1545-1 assume !(1 == ~T11_E~0); 41057#L1550-1 assume !(1 == ~T12_E~0); 41305#L1555-1 assume !(1 == ~T13_E~0); 41306#L1560-1 assume !(1 == ~T14_E~0); 41606#L1565-1 assume !(1 == ~E_1~0); 43019#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 42497#L1575-1 assume !(1 == ~E_3~0); 41876#L1580-1 assume !(1 == ~E_4~0); 41877#L1585-1 assume !(1 == ~E_5~0); 42347#L1590-1 assume !(1 == ~E_6~0); 41911#L1595-1 assume !(1 == ~E_7~0); 41912#L1600-1 assume !(1 == ~E_8~0); 42284#L1605-1 assume !(1 == ~E_9~0); 42285#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 42802#L1615-1 assume !(1 == ~E_11~0); 41741#L1620-1 assume !(1 == ~E_12~0); 41742#L1625-1 assume !(1 == ~E_13~0); 42529#L1630-1 assume !(1 == ~E_14~0); 41910#L1635-1 assume { :end_inline_reset_delta_events } true; 41851#L2017-2 [2022-07-13 04:23:40,447 INFO L754 eck$LassoCheckResult]: Loop: 41851#L2017-2 assume !false; 41131#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 41132#L1316 assume !false; 42460#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 42522#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 41069#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 41211#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 41212#L1115 assume !(0 != eval_~tmp~0#1); 42545#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 41966#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 41967#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 42149#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 42650#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42319#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 42320#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 42882#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 43057#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 43052#L1372-3 assume !(0 == ~T7_E~0); 41113#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 41114#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 41783#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 41784#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 42695#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 43005#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 42263#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 41419#L1412-3 assume !(0 == ~E_1~0); 41420#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 42184#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 42185#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 42879#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42566#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 42278#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 42279#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 41179#L1452-3 assume !(0 == ~E_9~0); 41180#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 42818#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 42819#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 42623#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 42624#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 41417#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41418#L646-42 assume 1 == ~m_pc~0; 42003#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 42851#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42852#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 42990#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 42991#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42783#L665-42 assume 1 == ~t1_pc~0; 42744#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 42746#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42932#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41586#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 41587#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43056#L684-42 assume 1 == ~t2_pc~0; 42435#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 42436#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43046#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42215#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42216#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42338#L703-42 assume 1 == ~t3_pc~0; 42536#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 42537#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41855#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41856#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 42630#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42250#L722-42 assume 1 == ~t4_pc~0; 42251#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 42661#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41904#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41731#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 41732#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43026#L741-42 assume !(1 == ~t5_pc~0); 42643#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 42113#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42114#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 43059#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 42021#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42022#L760-42 assume !(1 == ~t6_pc~0); 42156#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 42291#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42292#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 42680#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 41973#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41974#L779-42 assume 1 == ~t7_pc~0; 42803#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 42751#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41660#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41661#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 41514#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41515#L798-42 assume !(1 == ~t8_pc~0); 41125#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 41126#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 42869#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42315#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 41345#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41346#L817-42 assume 1 == ~t9_pc~0; 42119#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41629#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41630#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41756#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 42561#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42562#L836-42 assume 1 == ~t10_pc~0; 42654#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 41667#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41668#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 42969#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 42970#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43011#L855-42 assume 1 == ~t11_pc~0; 43024#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 41218#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41219#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 41968#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 42731#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41832#L874-42 assume 1 == ~t12_pc~0; 41833#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 42075#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 41133#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 41134#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 41387#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 41388#L893-42 assume !(1 == ~t13_pc~0); 42371#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 42372#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 42387#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 42289#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 41761#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 41762#L912-42 assume !(1 == ~t14_pc~0); 42571#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 41079#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 41080#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 42660#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 41507#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41508#L1495-3 assume !(1 == ~M_E~0); 42123#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42551#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42644#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41737#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41700#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 41701#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 42358#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 42581#L1530-3 assume !(1 == ~T8_E~0); 41546#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 41547#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 41584#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 42841#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 42950#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 41990#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 41991#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 42606#L1570-3 assume !(1 == ~E_2~0); 42557#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 42558#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 42913#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 42958#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 43003#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 42380#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 42381#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 42856#L1610-3 assume !(1 == ~E_10~0); 41743#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 41744#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 42348#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 42349#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 42253#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 41684#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 41289#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 42027#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 42583#L2036 assume !(0 == start_simulation_~tmp~3#1); 42584#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 42736#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 41896#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 42914#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 42296#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 42297#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 43017#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 43018#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 41851#L2017-2 [2022-07-13 04:23:40,447 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:40,448 INFO L85 PathProgramCache]: Analyzing trace with hash -1364407510, now seen corresponding path program 1 times [2022-07-13 04:23:40,448 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:40,448 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [858751251] [2022-07-13 04:23:40,448 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:40,448 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:40,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:40,472 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:40,473 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:40,473 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [858751251] [2022-07-13 04:23:40,473 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [858751251] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:40,473 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:40,473 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-13 04:23:40,473 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [463085296] [2022-07-13 04:23:40,473 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:40,474 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-13 04:23:40,474 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:40,474 INFO L85 PathProgramCache]: Analyzing trace with hash -1715277972, now seen corresponding path program 2 times [2022-07-13 04:23:40,474 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:40,474 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1665402370] [2022-07-13 04:23:40,475 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:40,475 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:40,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:40,538 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:40,538 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:40,538 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1665402370] [2022-07-13 04:23:40,539 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1665402370] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:40,539 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:40,539 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-13 04:23:40,539 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1641784880] [2022-07-13 04:23:40,539 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:40,539 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-13 04:23:40,540 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-13 04:23:40,540 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-13 04:23:40,540 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-13 04:23:40,540 INFO L87 Difference]: Start difference. First operand 2047 states and 3025 transitions. cyclomatic complexity: 979 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:40,559 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-13 04:23:40,559 INFO L93 Difference]: Finished difference Result 2047 states and 3024 transitions. [2022-07-13 04:23:40,559 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-13 04:23:40,560 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3024 transitions. [2022-07-13 04:23:40,565 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-07-13 04:23:40,570 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3024 transitions. [2022-07-13 04:23:40,570 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2022-07-13 04:23:40,571 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2022-07-13 04:23:40,571 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3024 transitions. [2022-07-13 04:23:40,573 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-13 04:23:40,573 INFO L369 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3024 transitions. [2022-07-13 04:23:40,575 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3024 transitions. [2022-07-13 04:23:40,588 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2022-07-13 04:23:40,590 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4772838299951148) internal successors, (3024), 2046 states have internal predecessors, (3024), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:40,594 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3024 transitions. [2022-07-13 04:23:40,594 INFO L392 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3024 transitions. [2022-07-13 04:23:40,594 INFO L374 stractBuchiCegarLoop]: Abstraction has 2047 states and 3024 transitions. [2022-07-13 04:23:40,594 INFO L287 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-07-13 04:23:40,594 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3024 transitions. [2022-07-13 04:23:40,598 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-07-13 04:23:40,599 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-13 04:23:40,599 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-13 04:23:40,600 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:40,600 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:40,600 INFO L752 eck$LassoCheckResult]: Stem: 46050#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 46051#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 46653#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 45770#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 45771#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 46016#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 46017#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45744#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 45745#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46968#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46320#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 46321#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 46838#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 46230#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 46231#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 45651#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 45652#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 45983#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 46181#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 45228#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 45229#L1342 assume !(0 == ~M_E~0); 45394#L1342-2 assume !(0 == ~T1_E~0); 45950#L1347-1 assume !(0 == ~T2_E~0); 46951#L1352-1 assume !(0 == ~T3_E~0); 46747#L1357-1 assume !(0 == ~T4_E~0); 45975#L1362-1 assume !(0 == ~T5_E~0); 45976#L1367-1 assume !(0 == ~T6_E~0); 45573#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 45574#L1377-1 assume !(0 == ~T8_E~0); 45904#L1382-1 assume !(0 == ~T9_E~0); 45905#L1387-1 assume !(0 == ~T10_E~0); 46632#L1392-1 assume !(0 == ~T11_E~0); 45936#L1397-1 assume !(0 == ~T12_E~0); 45937#L1402-1 assume !(0 == ~T13_E~0); 45589#L1407-1 assume !(0 == ~T14_E~0); 45590#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 46868#L1417-1 assume !(0 == ~E_2~0); 46869#L1422-1 assume !(0 == ~E_3~0); 47110#L1427-1 assume !(0 == ~E_4~0); 45777#L1432-1 assume !(0 == ~E_5~0); 45778#L1437-1 assume !(0 == ~E_6~0); 46786#L1442-1 assume !(0 == ~E_7~0); 46787#L1447-1 assume !(0 == ~E_8~0); 46629#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 45364#L1457-1 assume !(0 == ~E_10~0); 45365#L1462-1 assume !(0 == ~E_11~0); 46821#L1467-1 assume !(0 == ~E_12~0); 46833#L1472-1 assume !(0 == ~E_13~0); 46834#L1477-1 assume !(0 == ~E_14~0); 46576#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45563#L646 assume 1 == ~m_pc~0; 45564#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 46240#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46255#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 45653#L1666 assume !(0 != activate_threads_~tmp~1#1); 45654#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47131#L665 assume !(1 == ~t1_pc~0); 46129#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 46130#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45662#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 45663#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 46453#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46454#L684 assume 1 == ~t2_pc~0; 46571#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46495#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46560#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46955#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 46956#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47144#L703 assume !(1 == ~t3_pc~0); 45799#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 45800#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46446#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45198#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 45199#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45684#L722 assume 1 == ~t4_pc~0; 46422#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45865#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46210#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 46770#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 46277#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45395#L741 assume 1 == ~t5_pc~0; 45396#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 45706#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45860#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45861#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 46540#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45951#L760 assume !(1 == ~t6_pc~0); 45798#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 45797#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45655#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 45656#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 46377#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46378#L779 assume 1 == ~t7_pc~0; 45440#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 45286#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45287#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45695#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 45718#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45719#L798 assume !(1 == ~t8_pc~0); 47000#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 46923#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 45442#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 45443#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 47133#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45263#L817 assume 1 == ~t9_pc~0; 45264#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46058#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46059#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 46581#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 45669#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 45670#L836 assume !(1 == ~t10_pc~0); 45686#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 45617#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45618#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 45866#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 45867#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 46933#L855 assume 1 == ~t11_pc~0; 46251#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 46252#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 46816#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46625#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 46460#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 45559#L874 assume !(1 == ~t12_pc~0); 45560#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 45727#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 45728#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 45868#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 45236#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 45237#L893 assume 1 == ~t13_pc~0; 47067#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 45592#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 45903#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 46994#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 47002#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 47003#L912 assume 1 == ~t14_pc~0; 46793#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 46794#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 45562#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 45494#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 45495#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46270#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 46686#L1495-2 assume !(1 == ~T1_E~0); 46687#L1500-1 assume !(1 == ~T2_E~0); 46373#L1505-1 assume !(1 == ~T3_E~0); 46374#L1510-1 assume !(1 == ~T4_E~0); 46431#L1515-1 assume !(1 == ~T5_E~0); 46432#L1520-1 assume !(1 == ~T6_E~0); 47001#L1525-1 assume !(1 == ~T7_E~0); 46711#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 45664#L1535-1 assume !(1 == ~T9_E~0); 45665#L1540-1 assume !(1 == ~T10_E~0); 45157#L1545-1 assume !(1 == ~T11_E~0); 45158#L1550-1 assume !(1 == ~T12_E~0); 45406#L1555-1 assume !(1 == ~T13_E~0); 45407#L1560-1 assume !(1 == ~T14_E~0); 45707#L1565-1 assume !(1 == ~E_1~0); 47120#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 46598#L1575-1 assume !(1 == ~E_3~0); 45977#L1580-1 assume !(1 == ~E_4~0); 45978#L1585-1 assume !(1 == ~E_5~0); 46448#L1590-1 assume !(1 == ~E_6~0); 46012#L1595-1 assume !(1 == ~E_7~0); 46013#L1600-1 assume !(1 == ~E_8~0); 46385#L1605-1 assume !(1 == ~E_9~0); 46386#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 46903#L1615-1 assume !(1 == ~E_11~0); 45842#L1620-1 assume !(1 == ~E_12~0); 45843#L1625-1 assume !(1 == ~E_13~0); 46630#L1630-1 assume !(1 == ~E_14~0); 46011#L1635-1 assume { :end_inline_reset_delta_events } true; 45952#L2017-2 [2022-07-13 04:23:40,601 INFO L754 eck$LassoCheckResult]: Loop: 45952#L2017-2 assume !false; 45232#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 45233#L1316 assume !false; 46561#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 46623#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 45170#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 45312#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 45313#L1115 assume !(0 != eval_~tmp~0#1); 46646#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 46067#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 46068#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 46250#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 46751#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 46420#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46421#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 46983#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 47158#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 47153#L1372-3 assume !(0 == ~T7_E~0); 45214#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 45215#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 45884#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 45885#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 46796#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 47106#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 46364#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 45520#L1412-3 assume !(0 == ~E_1~0); 45521#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 46285#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 46286#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 46980#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 46667#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 46379#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 46380#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 45280#L1452-3 assume !(0 == ~E_9~0); 45281#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 46919#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 46920#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 46724#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 46725#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 45518#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45519#L646-42 assume 1 == ~m_pc~0; 46104#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 46952#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46953#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47091#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 47092#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46884#L665-42 assume 1 == ~t1_pc~0; 46845#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 46847#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47033#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 45687#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 45688#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47157#L684-42 assume 1 == ~t2_pc~0; 46536#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46537#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47147#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46316#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46317#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46439#L703-42 assume 1 == ~t3_pc~0; 46637#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 46638#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45956#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45957#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 46731#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46351#L722-42 assume 1 == ~t4_pc~0; 46352#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 46762#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46005#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 45832#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 45833#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47127#L741-42 assume !(1 == ~t5_pc~0); 46744#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 46214#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46215#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47160#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 46122#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46123#L760-42 assume !(1 == ~t6_pc~0); 46257#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 46392#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46393#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46781#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 46074#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46075#L779-42 assume !(1 == ~t7_pc~0); 46851#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 46852#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45761#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45762#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 45615#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45616#L798-42 assume 1 == ~t8_pc~0; 46066#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 45227#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 46970#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46416#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 45446#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45447#L817-42 assume 1 == ~t9_pc~0; 46220#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 45730#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 45731#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 45857#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 46662#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46663#L836-42 assume 1 == ~t10_pc~0; 46755#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 45768#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45769#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 47070#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 47071#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47112#L855-42 assume 1 == ~t11_pc~0; 47125#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 45319#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 45320#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46069#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 46832#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 45933#L874-42 assume 1 == ~t12_pc~0; 45934#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 46176#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 45234#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 45235#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 45488#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 45489#L893-42 assume 1 == ~t13_pc~0; 46692#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 46473#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 46488#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 46390#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 45862#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 45863#L912-42 assume !(1 == ~t14_pc~0); 46672#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 45180#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 45181#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 46761#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 45608#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45609#L1495-3 assume !(1 == ~M_E~0); 46224#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46652#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46745#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45838#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 45801#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 45802#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 46459#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 46682#L1530-3 assume !(1 == ~T8_E~0); 45647#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 45648#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 45685#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 46942#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 47051#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 46091#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 46092#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 46707#L1570-3 assume !(1 == ~E_2~0); 46658#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 46659#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 47014#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 47059#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 47104#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 46481#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 46482#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 46957#L1610-3 assume !(1 == ~E_10~0); 45844#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 45845#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 46449#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 46450#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 46354#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 45785#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 45390#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 46128#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 46684#L2036 assume !(0 == start_simulation_~tmp~3#1); 46685#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 46837#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 45997#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 47015#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 46397#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 46398#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 47118#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 47119#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 45952#L2017-2 [2022-07-13 04:23:40,601 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:40,602 INFO L85 PathProgramCache]: Analyzing trace with hash 405064104, now seen corresponding path program 1 times [2022-07-13 04:23:40,602 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:40,602 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [425147896] [2022-07-13 04:23:40,602 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:40,602 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:40,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:40,621 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:40,621 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:40,622 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [425147896] [2022-07-13 04:23:40,622 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [425147896] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:40,622 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:40,622 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-13 04:23:40,622 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1321538324] [2022-07-13 04:23:40,622 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:40,623 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-13 04:23:40,623 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:40,623 INFO L85 PathProgramCache]: Analyzing trace with hash -1400619827, now seen corresponding path program 1 times [2022-07-13 04:23:40,623 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:40,623 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [442772770] [2022-07-13 04:23:40,623 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:40,624 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:40,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:40,650 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:40,650 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:40,650 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [442772770] [2022-07-13 04:23:40,650 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [442772770] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:40,650 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:40,650 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-13 04:23:40,651 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1749685841] [2022-07-13 04:23:40,651 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:40,651 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-13 04:23:40,651 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-13 04:23:40,651 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-13 04:23:40,652 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-13 04:23:40,652 INFO L87 Difference]: Start difference. First operand 2047 states and 3024 transitions. cyclomatic complexity: 978 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:40,671 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-13 04:23:40,671 INFO L93 Difference]: Finished difference Result 2047 states and 3023 transitions. [2022-07-13 04:23:40,671 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-13 04:23:40,672 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3023 transitions. [2022-07-13 04:23:40,677 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-07-13 04:23:40,682 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3023 transitions. [2022-07-13 04:23:40,682 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2022-07-13 04:23:40,683 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2022-07-13 04:23:40,683 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3023 transitions. [2022-07-13 04:23:40,685 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-13 04:23:40,685 INFO L369 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3023 transitions. [2022-07-13 04:23:40,687 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3023 transitions. [2022-07-13 04:23:40,701 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2022-07-13 04:23:40,703 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4767953102100635) internal successors, (3023), 2046 states have internal predecessors, (3023), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:40,707 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3023 transitions. [2022-07-13 04:23:40,707 INFO L392 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3023 transitions. [2022-07-13 04:23:40,707 INFO L374 stractBuchiCegarLoop]: Abstraction has 2047 states and 3023 transitions. [2022-07-13 04:23:40,707 INFO L287 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-07-13 04:23:40,707 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3023 transitions. [2022-07-13 04:23:40,712 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-07-13 04:23:40,712 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-13 04:23:40,712 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-13 04:23:40,714 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:40,714 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:40,714 INFO L752 eck$LassoCheckResult]: Stem: 50151#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 50152#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 50754#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 49871#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 49872#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 50117#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 50118#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49845#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49846#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 51069#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 50421#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 50422#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 50939#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 50331#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 50332#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 49752#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 49753#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 50084#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 50282#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 49329#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49330#L1342 assume !(0 == ~M_E~0); 49495#L1342-2 assume !(0 == ~T1_E~0); 50051#L1347-1 assume !(0 == ~T2_E~0); 51052#L1352-1 assume !(0 == ~T3_E~0); 50848#L1357-1 assume !(0 == ~T4_E~0); 50076#L1362-1 assume !(0 == ~T5_E~0); 50077#L1367-1 assume !(0 == ~T6_E~0); 49674#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 49675#L1377-1 assume !(0 == ~T8_E~0); 50005#L1382-1 assume !(0 == ~T9_E~0); 50006#L1387-1 assume !(0 == ~T10_E~0); 50733#L1392-1 assume !(0 == ~T11_E~0); 50037#L1397-1 assume !(0 == ~T12_E~0); 50038#L1402-1 assume !(0 == ~T13_E~0); 49690#L1407-1 assume !(0 == ~T14_E~0); 49691#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 50969#L1417-1 assume !(0 == ~E_2~0); 50970#L1422-1 assume !(0 == ~E_3~0); 51211#L1427-1 assume !(0 == ~E_4~0); 49878#L1432-1 assume !(0 == ~E_5~0); 49879#L1437-1 assume !(0 == ~E_6~0); 50887#L1442-1 assume !(0 == ~E_7~0); 50888#L1447-1 assume !(0 == ~E_8~0); 50730#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 49465#L1457-1 assume !(0 == ~E_10~0); 49466#L1462-1 assume !(0 == ~E_11~0); 50922#L1467-1 assume !(0 == ~E_12~0); 50934#L1472-1 assume !(0 == ~E_13~0); 50935#L1477-1 assume !(0 == ~E_14~0); 50677#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49664#L646 assume 1 == ~m_pc~0; 49665#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 50341#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50356#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49754#L1666 assume !(0 != activate_threads_~tmp~1#1); 49755#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51232#L665 assume !(1 == ~t1_pc~0); 50230#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 50231#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49763#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49764#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 50554#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50555#L684 assume 1 == ~t2_pc~0; 50672#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50596#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50661#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 51056#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 51057#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51245#L703 assume !(1 == ~t3_pc~0); 49900#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 49901#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50547#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49299#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 49300#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49785#L722 assume 1 == ~t4_pc~0; 50523#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 49966#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50311#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50871#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 50378#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49496#L741 assume 1 == ~t5_pc~0; 49497#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49807#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49961#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49962#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 50641#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50052#L760 assume !(1 == ~t6_pc~0); 49899#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 49898#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49756#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49757#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 50478#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50479#L779 assume 1 == ~t7_pc~0; 49541#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49387#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49388#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49796#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 49819#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49820#L798 assume !(1 == ~t8_pc~0); 51101#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 51024#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49543#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 49544#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 51234#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49364#L817 assume 1 == ~t9_pc~0; 49365#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50159#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50160#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 50682#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 49770#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49771#L836 assume !(1 == ~t10_pc~0); 49787#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 49718#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 49719#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 49967#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 49968#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51034#L855 assume 1 == ~t11_pc~0; 50352#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 50353#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 50917#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 50726#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 50561#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 49660#L874 assume !(1 == ~t12_pc~0); 49661#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 49828#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 49829#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 49969#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 49337#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 49338#L893 assume 1 == ~t13_pc~0; 51168#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 49693#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50004#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 51095#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 51103#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 51104#L912 assume 1 == ~t14_pc~0; 50894#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 50895#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 49663#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 49595#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 49596#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50371#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 50787#L1495-2 assume !(1 == ~T1_E~0); 50788#L1500-1 assume !(1 == ~T2_E~0); 50474#L1505-1 assume !(1 == ~T3_E~0); 50475#L1510-1 assume !(1 == ~T4_E~0); 50532#L1515-1 assume !(1 == ~T5_E~0); 50533#L1520-1 assume !(1 == ~T6_E~0); 51102#L1525-1 assume !(1 == ~T7_E~0); 50812#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 49765#L1535-1 assume !(1 == ~T9_E~0); 49766#L1540-1 assume !(1 == ~T10_E~0); 49258#L1545-1 assume !(1 == ~T11_E~0); 49259#L1550-1 assume !(1 == ~T12_E~0); 49507#L1555-1 assume !(1 == ~T13_E~0); 49508#L1560-1 assume !(1 == ~T14_E~0); 49808#L1565-1 assume !(1 == ~E_1~0); 51221#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 50699#L1575-1 assume !(1 == ~E_3~0); 50078#L1580-1 assume !(1 == ~E_4~0); 50079#L1585-1 assume !(1 == ~E_5~0); 50549#L1590-1 assume !(1 == ~E_6~0); 50113#L1595-1 assume !(1 == ~E_7~0); 50114#L1600-1 assume !(1 == ~E_8~0); 50486#L1605-1 assume !(1 == ~E_9~0); 50487#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 51004#L1615-1 assume !(1 == ~E_11~0); 49943#L1620-1 assume !(1 == ~E_12~0); 49944#L1625-1 assume !(1 == ~E_13~0); 50731#L1630-1 assume !(1 == ~E_14~0); 50112#L1635-1 assume { :end_inline_reset_delta_events } true; 50053#L2017-2 [2022-07-13 04:23:40,715 INFO L754 eck$LassoCheckResult]: Loop: 50053#L2017-2 assume !false; 49333#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49334#L1316 assume !false; 50662#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 50724#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 49271#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 49413#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 49414#L1115 assume !(0 != eval_~tmp~0#1); 50747#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50168#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50169#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 50351#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 50852#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50521#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 50522#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 51084#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 51259#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 51254#L1372-3 assume !(0 == ~T7_E~0); 49315#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 49316#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 49985#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 49986#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 50897#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 51207#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 50465#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 49621#L1412-3 assume !(0 == ~E_1~0); 49622#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 50386#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50387#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 51081#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 50768#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 50480#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 50481#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 49381#L1452-3 assume !(0 == ~E_9~0); 49382#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 51020#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 51021#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 50825#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 50826#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 49619#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49620#L646-42 assume 1 == ~m_pc~0; 50205#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 51053#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51054#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 51192#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 51193#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50985#L665-42 assume 1 == ~t1_pc~0; 50946#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 50948#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 51134#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49788#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 49789#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 51258#L684-42 assume 1 == ~t2_pc~0; 50637#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50638#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51248#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50417#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50418#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50540#L703-42 assume 1 == ~t3_pc~0; 50738#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 50739#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50057#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50058#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 50832#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50452#L722-42 assume 1 == ~t4_pc~0; 50453#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 50863#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50106#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49933#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 49934#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 51228#L741-42 assume 1 == ~t5_pc~0; 51170#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50315#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50316#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 51261#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 50223#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50224#L760-42 assume !(1 == ~t6_pc~0); 50358#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 50493#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50494#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50882#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 50175#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50176#L779-42 assume !(1 == ~t7_pc~0); 50952#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 50953#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49862#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49863#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 49716#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49717#L798-42 assume 1 == ~t8_pc~0; 50167#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 49328#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 51071#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50517#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 49547#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49548#L817-42 assume 1 == ~t9_pc~0; 50323#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 49831#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49832#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 49958#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 50763#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50764#L836-42 assume 1 == ~t10_pc~0; 50856#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 49869#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 49870#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 51171#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 51172#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51213#L855-42 assume 1 == ~t11_pc~0; 51226#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 49420#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49421#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 50170#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 50933#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 50034#L874-42 assume 1 == ~t12_pc~0; 50035#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 50277#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 49335#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 49336#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 49589#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 49590#L893-42 assume 1 == ~t13_pc~0; 50793#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 50574#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50589#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 50491#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 49963#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 49964#L912-42 assume !(1 == ~t14_pc~0); 50773#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 49281#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 49282#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 50862#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 49709#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49710#L1495-3 assume !(1 == ~M_E~0); 50325#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 50753#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50846#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 49939#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 49902#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 49903#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 50560#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50783#L1530-3 assume !(1 == ~T8_E~0); 49748#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 49749#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 49786#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 51043#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 51152#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 50192#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 50193#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 50808#L1570-3 assume !(1 == ~E_2~0); 50759#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 50760#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 51115#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 51160#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 51205#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 50582#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 50583#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 51058#L1610-3 assume !(1 == ~E_10~0); 49945#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 49946#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 50550#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 50551#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 50455#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 49886#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 49491#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 50229#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 50785#L2036 assume !(0 == start_simulation_~tmp~3#1); 50786#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 50938#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 50098#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 51116#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 50498#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 50499#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 51219#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 51220#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 50053#L2017-2 [2022-07-13 04:23:40,715 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:40,715 INFO L85 PathProgramCache]: Analyzing trace with hash 1016333162, now seen corresponding path program 1 times [2022-07-13 04:23:40,715 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:40,715 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1717070661] [2022-07-13 04:23:40,716 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:40,716 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:40,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:40,737 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:40,737 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:40,737 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1717070661] [2022-07-13 04:23:40,737 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1717070661] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:40,737 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:40,737 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-13 04:23:40,738 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2047661468] [2022-07-13 04:23:40,738 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:40,738 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-13 04:23:40,738 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:40,739 INFO L85 PathProgramCache]: Analyzing trace with hash 464353134, now seen corresponding path program 1 times [2022-07-13 04:23:40,739 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:40,739 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1331243570] [2022-07-13 04:23:40,739 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:40,739 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:40,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:40,768 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:40,769 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:40,769 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1331243570] [2022-07-13 04:23:40,769 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1331243570] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:40,769 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:40,769 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-13 04:23:40,769 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [921302998] [2022-07-13 04:23:40,770 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:40,770 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-13 04:23:40,770 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-13 04:23:40,770 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-13 04:23:40,770 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-13 04:23:40,771 INFO L87 Difference]: Start difference. First operand 2047 states and 3023 transitions. cyclomatic complexity: 977 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:40,792 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-13 04:23:40,793 INFO L93 Difference]: Finished difference Result 2047 states and 3022 transitions. [2022-07-13 04:23:40,793 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-13 04:23:40,793 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3022 transitions. [2022-07-13 04:23:40,799 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-07-13 04:23:40,803 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3022 transitions. [2022-07-13 04:23:40,803 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2022-07-13 04:23:40,805 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2022-07-13 04:23:40,805 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3022 transitions. [2022-07-13 04:23:40,807 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-13 04:23:40,807 INFO L369 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3022 transitions. [2022-07-13 04:23:40,809 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3022 transitions. [2022-07-13 04:23:40,825 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2022-07-13 04:23:40,827 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4763067904250122) internal successors, (3022), 2046 states have internal predecessors, (3022), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:40,831 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3022 transitions. [2022-07-13 04:23:40,831 INFO L392 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3022 transitions. [2022-07-13 04:23:40,831 INFO L374 stractBuchiCegarLoop]: Abstraction has 2047 states and 3022 transitions. [2022-07-13 04:23:40,831 INFO L287 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-07-13 04:23:40,831 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3022 transitions. [2022-07-13 04:23:40,836 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-07-13 04:23:40,836 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-13 04:23:40,836 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-13 04:23:40,837 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:40,837 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:40,838 INFO L752 eck$LassoCheckResult]: Stem: 54252#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 54253#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 54855#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 53972#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 53973#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 54218#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 54219#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53946#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53947#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 55170#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 54522#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 54523#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 55040#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 54432#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 54433#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 53853#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 53854#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 54185#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 54383#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 53430#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 53431#L1342 assume !(0 == ~M_E~0); 53596#L1342-2 assume !(0 == ~T1_E~0); 54152#L1347-1 assume !(0 == ~T2_E~0); 55153#L1352-1 assume !(0 == ~T3_E~0); 54949#L1357-1 assume !(0 == ~T4_E~0); 54177#L1362-1 assume !(0 == ~T5_E~0); 54178#L1367-1 assume !(0 == ~T6_E~0); 53775#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 53776#L1377-1 assume !(0 == ~T8_E~0); 54106#L1382-1 assume !(0 == ~T9_E~0); 54107#L1387-1 assume !(0 == ~T10_E~0); 54834#L1392-1 assume !(0 == ~T11_E~0); 54138#L1397-1 assume !(0 == ~T12_E~0); 54139#L1402-1 assume !(0 == ~T13_E~0); 53791#L1407-1 assume !(0 == ~T14_E~0); 53792#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 55070#L1417-1 assume !(0 == ~E_2~0); 55071#L1422-1 assume !(0 == ~E_3~0); 55312#L1427-1 assume !(0 == ~E_4~0); 53979#L1432-1 assume !(0 == ~E_5~0); 53980#L1437-1 assume !(0 == ~E_6~0); 54988#L1442-1 assume !(0 == ~E_7~0); 54989#L1447-1 assume !(0 == ~E_8~0); 54831#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 53566#L1457-1 assume !(0 == ~E_10~0); 53567#L1462-1 assume !(0 == ~E_11~0); 55023#L1467-1 assume !(0 == ~E_12~0); 55035#L1472-1 assume !(0 == ~E_13~0); 55036#L1477-1 assume !(0 == ~E_14~0); 54778#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53765#L646 assume 1 == ~m_pc~0; 53766#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 54442#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54457#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 53855#L1666 assume !(0 != activate_threads_~tmp~1#1); 53856#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55333#L665 assume !(1 == ~t1_pc~0); 54331#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 54332#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53864#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53865#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 54655#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54656#L684 assume 1 == ~t2_pc~0; 54773#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 54697#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54762#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 55157#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 55158#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55346#L703 assume !(1 == ~t3_pc~0); 54001#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 54002#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54648#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53400#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 53401#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53886#L722 assume 1 == ~t4_pc~0; 54624#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 54067#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54412#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54972#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 54479#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53597#L741 assume 1 == ~t5_pc~0; 53598#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 53908#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54062#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 54063#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 54742#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54153#L760 assume !(1 == ~t6_pc~0); 54000#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 53999#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53857#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 53858#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 54579#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54580#L779 assume 1 == ~t7_pc~0; 53642#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 53488#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53489#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53897#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 53920#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 53921#L798 assume !(1 == ~t8_pc~0); 55202#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 55125#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53644#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 53645#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 55335#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53465#L817 assume 1 == ~t9_pc~0; 53466#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 54260#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 54261#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 54783#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 53871#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 53872#L836 assume !(1 == ~t10_pc~0); 53888#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 53819#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 53820#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 54068#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 54069#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 55135#L855 assume 1 == ~t11_pc~0; 54453#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 54454#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 55018#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 54827#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 54662#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 53761#L874 assume !(1 == ~t12_pc~0); 53762#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 53929#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 53930#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 54070#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 53438#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 53439#L893 assume 1 == ~t13_pc~0; 55269#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 53794#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 54105#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 55196#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 55204#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 55205#L912 assume 1 == ~t14_pc~0; 54995#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 54996#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 53764#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 53696#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 53697#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54472#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 54888#L1495-2 assume !(1 == ~T1_E~0); 54889#L1500-1 assume !(1 == ~T2_E~0); 54575#L1505-1 assume !(1 == ~T3_E~0); 54576#L1510-1 assume !(1 == ~T4_E~0); 54633#L1515-1 assume !(1 == ~T5_E~0); 54634#L1520-1 assume !(1 == ~T6_E~0); 55203#L1525-1 assume !(1 == ~T7_E~0); 54913#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 53866#L1535-1 assume !(1 == ~T9_E~0); 53867#L1540-1 assume !(1 == ~T10_E~0); 53359#L1545-1 assume !(1 == ~T11_E~0); 53360#L1550-1 assume !(1 == ~T12_E~0); 53608#L1555-1 assume !(1 == ~T13_E~0); 53609#L1560-1 assume !(1 == ~T14_E~0); 53909#L1565-1 assume !(1 == ~E_1~0); 55322#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 54800#L1575-1 assume !(1 == ~E_3~0); 54179#L1580-1 assume !(1 == ~E_4~0); 54180#L1585-1 assume !(1 == ~E_5~0); 54650#L1590-1 assume !(1 == ~E_6~0); 54214#L1595-1 assume !(1 == ~E_7~0); 54215#L1600-1 assume !(1 == ~E_8~0); 54587#L1605-1 assume !(1 == ~E_9~0); 54588#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 55105#L1615-1 assume !(1 == ~E_11~0); 54044#L1620-1 assume !(1 == ~E_12~0); 54045#L1625-1 assume !(1 == ~E_13~0); 54832#L1630-1 assume !(1 == ~E_14~0); 54213#L1635-1 assume { :end_inline_reset_delta_events } true; 54154#L2017-2 [2022-07-13 04:23:40,838 INFO L754 eck$LassoCheckResult]: Loop: 54154#L2017-2 assume !false; 53434#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 53435#L1316 assume !false; 54763#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 54825#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 53372#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 53514#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 53515#L1115 assume !(0 != eval_~tmp~0#1); 54848#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 54269#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 54270#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 54452#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 54953#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 54622#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 54623#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 55185#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 55360#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 55355#L1372-3 assume !(0 == ~T7_E~0); 53416#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 53417#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 54086#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 54087#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 54998#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 55308#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 54566#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 53722#L1412-3 assume !(0 == ~E_1~0); 53723#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 54487#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 54488#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 55182#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 54869#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 54581#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 54582#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 53482#L1452-3 assume !(0 == ~E_9~0); 53483#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 55121#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 55122#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 54926#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 54927#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 53720#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53721#L646-42 assume 1 == ~m_pc~0; 54306#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 55154#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 55155#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 55293#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 55294#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55086#L665-42 assume 1 == ~t1_pc~0; 55047#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 55049#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55235#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53889#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 53890#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55359#L684-42 assume 1 == ~t2_pc~0; 54738#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 54739#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 55349#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 54518#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 54519#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54641#L703-42 assume 1 == ~t3_pc~0; 54839#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 54840#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54158#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 54159#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 54933#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54553#L722-42 assume 1 == ~t4_pc~0; 54554#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 54964#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54207#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54034#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 54035#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 55329#L741-42 assume !(1 == ~t5_pc~0); 54946#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 54416#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54417#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 55362#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 54324#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54325#L760-42 assume !(1 == ~t6_pc~0); 54459#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 54594#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54595#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 54983#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 54276#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54277#L779-42 assume 1 == ~t7_pc~0; 55106#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 55054#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53963#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53964#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 53817#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 53818#L798-42 assume !(1 == ~t8_pc~0); 53428#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 53429#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 55172#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54618#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 53648#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53649#L817-42 assume 1 == ~t9_pc~0; 54424#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 53932#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 53933#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 54059#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 54864#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 54865#L836-42 assume 1 == ~t10_pc~0; 54957#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 53970#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 53971#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 55272#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 55273#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 55314#L855-42 assume !(1 == ~t11_pc~0); 55328#L855-44 is_transmit11_triggered_~__retres1~11#1 := 0; 53521#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 53522#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 54271#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 55034#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 54135#L874-42 assume 1 == ~t12_pc~0; 54136#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 54378#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 53436#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 53437#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 53690#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 53691#L893-42 assume !(1 == ~t13_pc~0); 54674#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 54675#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 54690#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 54592#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 54064#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 54065#L912-42 assume !(1 == ~t14_pc~0); 54874#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 53382#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 53383#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 54963#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 53810#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53811#L1495-3 assume !(1 == ~M_E~0); 54426#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 54854#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 54947#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 54040#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 54003#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 54004#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 54661#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 54884#L1530-3 assume !(1 == ~T8_E~0); 53849#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 53850#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 53887#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 55144#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 55253#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 54293#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 54294#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 54909#L1570-3 assume !(1 == ~E_2~0); 54860#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 54861#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 55216#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 55261#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 55306#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 54683#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 54684#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 55159#L1610-3 assume !(1 == ~E_10~0); 54046#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 54047#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 54651#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 54652#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 54556#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 53987#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 53592#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 54330#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 54886#L2036 assume !(0 == start_simulation_~tmp~3#1); 54887#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 55039#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 54199#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 55217#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 54599#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 54600#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 55320#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 55321#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 54154#L2017-2 [2022-07-13 04:23:40,839 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:40,839 INFO L85 PathProgramCache]: Analyzing trace with hash -1873442456, now seen corresponding path program 1 times [2022-07-13 04:23:40,839 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:40,839 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [497727692] [2022-07-13 04:23:40,840 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:40,840 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:40,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:40,881 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:40,881 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:40,881 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [497727692] [2022-07-13 04:23:40,881 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [497727692] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:40,882 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:40,882 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-13 04:23:40,882 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [223477826] [2022-07-13 04:23:40,882 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:40,882 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-13 04:23:40,883 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:40,883 INFO L85 PathProgramCache]: Analyzing trace with hash 1401714763, now seen corresponding path program 1 times [2022-07-13 04:23:40,883 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:40,883 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1517755344] [2022-07-13 04:23:40,883 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:40,883 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:40,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:40,914 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:40,915 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:40,915 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1517755344] [2022-07-13 04:23:40,915 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1517755344] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:40,915 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:40,915 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-13 04:23:40,916 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1457635102] [2022-07-13 04:23:40,916 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:40,916 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-13 04:23:40,916 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-13 04:23:40,917 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-13 04:23:40,917 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-13 04:23:40,917 INFO L87 Difference]: Start difference. First operand 2047 states and 3022 transitions. cyclomatic complexity: 976 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:40,940 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-13 04:23:40,941 INFO L93 Difference]: Finished difference Result 2047 states and 3021 transitions. [2022-07-13 04:23:40,941 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-13 04:23:40,941 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3021 transitions. [2022-07-13 04:23:40,948 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-07-13 04:23:40,951 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3021 transitions. [2022-07-13 04:23:40,952 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2022-07-13 04:23:40,953 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2022-07-13 04:23:40,953 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3021 transitions. [2022-07-13 04:23:40,955 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-13 04:23:40,955 INFO L369 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3021 transitions. [2022-07-13 04:23:40,957 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3021 transitions. [2022-07-13 04:23:40,974 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2022-07-13 04:23:40,976 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.475818270639961) internal successors, (3021), 2046 states have internal predecessors, (3021), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:40,980 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3021 transitions. [2022-07-13 04:23:40,980 INFO L392 hiAutomatonCegarLoop]: Abstraction has 2047 states and 3021 transitions. [2022-07-13 04:23:40,980 INFO L374 stractBuchiCegarLoop]: Abstraction has 2047 states and 3021 transitions. [2022-07-13 04:23:40,981 INFO L287 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-07-13 04:23:40,981 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3021 transitions. [2022-07-13 04:23:40,985 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2022-07-13 04:23:40,985 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-13 04:23:40,985 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-13 04:23:40,987 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:40,987 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:40,988 INFO L752 eck$LassoCheckResult]: Stem: 58353#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 58354#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 58956#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 58073#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 58074#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 58319#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 58320#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 58047#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 58048#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 59271#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 58623#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 58624#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 59141#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 58533#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 58534#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 57954#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 57955#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 58286#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 58484#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 57531#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 57532#L1342 assume !(0 == ~M_E~0); 57697#L1342-2 assume !(0 == ~T1_E~0); 58253#L1347-1 assume !(0 == ~T2_E~0); 59254#L1352-1 assume !(0 == ~T3_E~0); 59050#L1357-1 assume !(0 == ~T4_E~0); 58278#L1362-1 assume !(0 == ~T5_E~0); 58279#L1367-1 assume !(0 == ~T6_E~0); 57876#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 57877#L1377-1 assume !(0 == ~T8_E~0); 58207#L1382-1 assume !(0 == ~T9_E~0); 58208#L1387-1 assume !(0 == ~T10_E~0); 58935#L1392-1 assume !(0 == ~T11_E~0); 58239#L1397-1 assume !(0 == ~T12_E~0); 58240#L1402-1 assume !(0 == ~T13_E~0); 57892#L1407-1 assume !(0 == ~T14_E~0); 57893#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 59171#L1417-1 assume !(0 == ~E_2~0); 59172#L1422-1 assume !(0 == ~E_3~0); 59413#L1427-1 assume !(0 == ~E_4~0); 58080#L1432-1 assume !(0 == ~E_5~0); 58081#L1437-1 assume !(0 == ~E_6~0); 59089#L1442-1 assume !(0 == ~E_7~0); 59090#L1447-1 assume !(0 == ~E_8~0); 58932#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 57667#L1457-1 assume !(0 == ~E_10~0); 57668#L1462-1 assume !(0 == ~E_11~0); 59124#L1467-1 assume !(0 == ~E_12~0); 59136#L1472-1 assume !(0 == ~E_13~0); 59137#L1477-1 assume !(0 == ~E_14~0); 58879#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 57868#L646 assume 1 == ~m_pc~0; 57869#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 58543#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 58558#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 57956#L1666 assume !(0 != activate_threads_~tmp~1#1); 57957#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59434#L665 assume !(1 == ~t1_pc~0); 58432#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 58433#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 57965#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 57966#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 58756#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 58757#L684 assume 1 == ~t2_pc~0; 58874#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 58798#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 58863#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 59258#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 59259#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 59447#L703 assume !(1 == ~t3_pc~0); 58102#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 58103#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 58749#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 57501#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 57502#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 57987#L722 assume 1 == ~t4_pc~0; 58725#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 58168#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58513#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 59073#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 58580#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 57698#L741 assume 1 == ~t5_pc~0; 57699#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 58009#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 58163#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 58164#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 58843#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 58254#L760 assume !(1 == ~t6_pc~0); 58101#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 58100#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 57958#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 57959#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 58680#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 58681#L779 assume 1 == ~t7_pc~0; 57743#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 57589#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 57590#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 57998#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 58021#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 58022#L798 assume !(1 == ~t8_pc~0); 59303#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 59226#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 57745#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 57746#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 59436#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 57566#L817 assume 1 == ~t9_pc~0; 57567#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 58361#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 58362#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 58884#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 57972#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 57973#L836 assume !(1 == ~t10_pc~0); 57989#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 57920#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 57921#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 58169#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 58170#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 59236#L855 assume 1 == ~t11_pc~0; 58554#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 58555#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 59119#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 58928#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 58763#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 57862#L874 assume !(1 == ~t12_pc~0); 57863#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 58030#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 58031#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 58171#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 57539#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 57540#L893 assume 1 == ~t13_pc~0; 59370#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 57895#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 58206#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 59297#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 59305#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 59306#L912 assume 1 == ~t14_pc~0; 59096#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 59097#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 57865#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 57797#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 57798#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 58573#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 58989#L1495-2 assume !(1 == ~T1_E~0); 58990#L1500-1 assume !(1 == ~T2_E~0); 58676#L1505-1 assume !(1 == ~T3_E~0); 58677#L1510-1 assume !(1 == ~T4_E~0); 58734#L1515-1 assume !(1 == ~T5_E~0); 58735#L1520-1 assume !(1 == ~T6_E~0); 59304#L1525-1 assume !(1 == ~T7_E~0); 59014#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 57967#L1535-1 assume !(1 == ~T9_E~0); 57968#L1540-1 assume !(1 == ~T10_E~0); 57460#L1545-1 assume !(1 == ~T11_E~0); 57461#L1550-1 assume !(1 == ~T12_E~0); 57709#L1555-1 assume !(1 == ~T13_E~0); 57710#L1560-1 assume !(1 == ~T14_E~0); 58010#L1565-1 assume !(1 == ~E_1~0); 59423#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 58901#L1575-1 assume !(1 == ~E_3~0); 58280#L1580-1 assume !(1 == ~E_4~0); 58281#L1585-1 assume !(1 == ~E_5~0); 58751#L1590-1 assume !(1 == ~E_6~0); 58315#L1595-1 assume !(1 == ~E_7~0); 58316#L1600-1 assume !(1 == ~E_8~0); 58688#L1605-1 assume !(1 == ~E_9~0); 58689#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 59206#L1615-1 assume !(1 == ~E_11~0); 58145#L1620-1 assume !(1 == ~E_12~0); 58146#L1625-1 assume !(1 == ~E_13~0); 58933#L1630-1 assume !(1 == ~E_14~0); 58314#L1635-1 assume { :end_inline_reset_delta_events } true; 58255#L2017-2 [2022-07-13 04:23:40,988 INFO L754 eck$LassoCheckResult]: Loop: 58255#L2017-2 assume !false; 57535#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 57536#L1316 assume !false; 58864#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 58926#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 57473#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 57615#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 57616#L1115 assume !(0 != eval_~tmp~0#1); 58949#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 58370#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 58371#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 58553#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 59054#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 58723#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 58724#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 59286#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 59461#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 59456#L1372-3 assume !(0 == ~T7_E~0); 57517#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 57518#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 58187#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 58188#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 59099#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 59409#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 58667#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 57823#L1412-3 assume !(0 == ~E_1~0); 57824#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 58588#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 58589#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 59283#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 58970#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 58682#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 58683#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 57583#L1452-3 assume !(0 == ~E_9~0); 57584#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 59222#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 59223#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 59027#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 59028#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 57821#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 57822#L646-42 assume 1 == ~m_pc~0; 58407#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 59255#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59256#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 59394#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 59395#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59187#L665-42 assume 1 == ~t1_pc~0; 59148#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 59150#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 59336#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 57990#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 57991#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 59460#L684-42 assume 1 == ~t2_pc~0; 58839#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 58840#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 59450#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 58619#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 58620#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 58742#L703-42 assume 1 == ~t3_pc~0; 58940#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 58941#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 58259#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 58260#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 59034#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 58654#L722-42 assume !(1 == ~t4_pc~0); 58656#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 59065#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58308#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 58135#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 58136#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 59430#L741-42 assume !(1 == ~t5_pc~0); 59047#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 58517#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 58518#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 59463#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 58425#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 58426#L760-42 assume !(1 == ~t6_pc~0); 58560#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 58695#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 58696#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 59084#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 58377#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 58378#L779-42 assume !(1 == ~t7_pc~0); 59154#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 59155#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 58064#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 58065#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 57918#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 57919#L798-42 assume 1 == ~t8_pc~0; 58369#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 57530#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 59273#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 58719#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 57749#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 57750#L817-42 assume 1 == ~t9_pc~0; 58525#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 58033#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 58034#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 58160#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 58965#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 58966#L836-42 assume 1 == ~t10_pc~0; 59058#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 58071#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 58072#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 59373#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 59374#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 59415#L855-42 assume 1 == ~t11_pc~0; 59428#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 57622#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 57623#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 58372#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 59135#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 58236#L874-42 assume 1 == ~t12_pc~0; 58237#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 58479#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 57537#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 57538#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 57791#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 57792#L893-42 assume 1 == ~t13_pc~0; 58995#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 58776#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 58791#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 58693#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 58165#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 58166#L912-42 assume 1 == ~t14_pc~0; 59410#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 57483#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 57484#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 59064#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 57911#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57912#L1495-3 assume !(1 == ~M_E~0); 58527#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 58955#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 59048#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 58141#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 58104#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 58105#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 58762#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 58985#L1530-3 assume !(1 == ~T8_E~0); 57950#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 57951#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 57988#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 59245#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 59354#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 58394#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 58395#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 59010#L1570-3 assume !(1 == ~E_2~0); 58961#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 58962#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 59317#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 59362#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 59407#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 58784#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 58785#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 59260#L1610-3 assume !(1 == ~E_10~0); 58147#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 58148#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 58752#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 58753#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 58657#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 58088#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 57693#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 58431#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 58987#L2036 assume !(0 == start_simulation_~tmp~3#1); 58988#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 59140#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 58300#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 59318#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 58700#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 58701#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 59421#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 59422#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 58255#L2017-2 [2022-07-13 04:23:40,989 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:40,989 INFO L85 PathProgramCache]: Analyzing trace with hash 527190954, now seen corresponding path program 1 times [2022-07-13 04:23:40,989 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:40,989 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1986925405] [2022-07-13 04:23:40,989 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:40,990 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:41,000 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:41,020 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:41,020 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:41,020 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1986925405] [2022-07-13 04:23:41,020 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1986925405] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:41,020 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:41,020 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-13 04:23:41,021 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [395899992] [2022-07-13 04:23:41,021 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:41,021 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-13 04:23:41,021 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:41,022 INFO L85 PathProgramCache]: Analyzing trace with hash 1014754381, now seen corresponding path program 1 times [2022-07-13 04:23:41,022 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:41,022 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1079242222] [2022-07-13 04:23:41,022 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:41,022 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:41,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:41,052 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:41,052 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:41,052 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1079242222] [2022-07-13 04:23:41,052 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1079242222] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:41,052 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:41,053 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-13 04:23:41,053 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1029196905] [2022-07-13 04:23:41,053 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:41,053 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-13 04:23:41,053 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-13 04:23:41,054 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-13 04:23:41,054 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-13 04:23:41,054 INFO L87 Difference]: Start difference. First operand 2047 states and 3021 transitions. cyclomatic complexity: 975 Second operand has 4 states, 4 states have (on average 42.5) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:41,189 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-13 04:23:41,189 INFO L93 Difference]: Finished difference Result 3936 states and 5800 transitions. [2022-07-13 04:23:41,189 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-13 04:23:41,190 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3936 states and 5800 transitions. [2022-07-13 04:23:41,201 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3724 [2022-07-13 04:23:41,209 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3936 states to 3936 states and 5800 transitions. [2022-07-13 04:23:41,209 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3936 [2022-07-13 04:23:41,211 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3936 [2022-07-13 04:23:41,211 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3936 states and 5800 transitions. [2022-07-13 04:23:41,216 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-13 04:23:41,216 INFO L369 hiAutomatonCegarLoop]: Abstraction has 3936 states and 5800 transitions. [2022-07-13 04:23:41,219 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3936 states and 5800 transitions. [2022-07-13 04:23:41,262 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3936 to 3936. [2022-07-13 04:23:41,267 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3936 states, 3936 states have (on average 1.4735772357723578) internal successors, (5800), 3935 states have internal predecessors, (5800), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:41,275 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3936 states to 3936 states and 5800 transitions. [2022-07-13 04:23:41,275 INFO L392 hiAutomatonCegarLoop]: Abstraction has 3936 states and 5800 transitions. [2022-07-13 04:23:41,275 INFO L374 stractBuchiCegarLoop]: Abstraction has 3936 states and 5800 transitions. [2022-07-13 04:23:41,275 INFO L287 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-07-13 04:23:41,275 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3936 states and 5800 transitions. [2022-07-13 04:23:41,284 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3724 [2022-07-13 04:23:41,284 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-13 04:23:41,284 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-13 04:23:41,286 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:41,286 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:41,287 INFO L752 eck$LassoCheckResult]: Stem: 64347#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 64348#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 64968#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 64067#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 64068#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 64313#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 64314#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 64041#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 64042#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 65321#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 64623#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 64624#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 65178#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 64530#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 64531#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 63948#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 63949#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 64280#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 64480#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 63524#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 63525#L1342 assume !(0 == ~M_E~0); 63690#L1342-2 assume !(0 == ~T1_E~0); 64247#L1347-1 assume !(0 == ~T2_E~0); 65303#L1352-1 assume !(0 == ~T3_E~0); 65072#L1357-1 assume !(0 == ~T4_E~0); 64272#L1362-1 assume !(0 == ~T5_E~0); 64273#L1367-1 assume !(0 == ~T6_E~0); 63869#L1372-1 assume !(0 == ~T7_E~0); 63870#L1377-1 assume !(0 == ~T8_E~0); 64201#L1382-1 assume !(0 == ~T9_E~0); 64202#L1387-1 assume !(0 == ~T10_E~0); 64946#L1392-1 assume !(0 == ~T11_E~0); 64233#L1397-1 assume !(0 == ~T12_E~0); 64234#L1402-1 assume !(0 == ~T13_E~0); 63885#L1407-1 assume !(0 == ~T14_E~0); 63886#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 65211#L1417-1 assume !(0 == ~E_2~0); 65212#L1422-1 assume !(0 == ~E_3~0); 65490#L1427-1 assume !(0 == ~E_4~0); 64074#L1432-1 assume !(0 == ~E_5~0); 64075#L1437-1 assume !(0 == ~E_6~0); 65118#L1442-1 assume !(0 == ~E_7~0); 65119#L1447-1 assume !(0 == ~E_8~0); 64942#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 63660#L1457-1 assume !(0 == ~E_10~0); 63661#L1462-1 assume !(0 == ~E_11~0); 65157#L1467-1 assume !(0 == ~E_12~0); 65173#L1472-1 assume !(0 == ~E_13~0); 65174#L1477-1 assume !(0 == ~E_14~0); 64887#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 63859#L646 assume 1 == ~m_pc~0; 63860#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 64541#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 64556#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 63950#L1666 assume !(0 != activate_threads_~tmp~1#1); 63951#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65520#L665 assume !(1 == ~t1_pc~0); 64428#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 64429#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 63959#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 63960#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 64757#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 64758#L684 assume 1 == ~t2_pc~0; 64882#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 64800#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 64869#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 65307#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 65308#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 65538#L703 assume !(1 == ~t3_pc~0); 64096#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 64097#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 64749#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 63494#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 63495#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 63981#L722 assume 1 == ~t4_pc~0; 64725#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 64162#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64510#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 65101#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 64580#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 63691#L741 assume 1 == ~t5_pc~0; 63692#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 64003#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 64157#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 64158#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 64847#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 64248#L760 assume !(1 == ~t6_pc~0); 64095#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 64094#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 63952#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 63953#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 64680#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 64681#L779 assume 1 == ~t7_pc~0; 63736#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 63582#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 63583#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 63992#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 64015#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 64016#L798 assume !(1 == ~t8_pc~0); 65360#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 65270#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 63738#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 63739#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 65522#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 63559#L817 assume 1 == ~t9_pc~0; 63560#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 64356#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 64357#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 64892#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 63966#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 63967#L836 assume !(1 == ~t10_pc~0); 63983#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 63913#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 63914#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 64163#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 64164#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 65284#L855 assume 1 == ~t11_pc~0; 64552#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 64553#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 65152#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 64938#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 64764#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 63855#L874 assume !(1 == ~t12_pc~0); 63856#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 64024#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 64025#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 64165#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 63532#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 63533#L893 assume 1 == ~t13_pc~0; 65437#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 63888#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 64200#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 65354#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 65363#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 65364#L912 assume 1 == ~t14_pc~0; 65125#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 65126#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 63858#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 63790#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 63791#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64573#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 65004#L1495-2 assume !(1 == ~T1_E~0); 65005#L1500-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 65486#L1505-1 assume !(1 == ~T3_E~0); 66391#L1510-1 assume !(1 == ~T4_E~0); 66390#L1515-1 assume !(1 == ~T5_E~0); 66389#L1520-1 assume !(1 == ~T6_E~0); 66388#L1525-1 assume !(1 == ~T7_E~0); 65362#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 66387#L1535-1 assume !(1 == ~T9_E~0); 66385#L1540-1 assume !(1 == ~T10_E~0); 66382#L1545-1 assume !(1 == ~T11_E~0); 65668#L1550-1 assume !(1 == ~T12_E~0); 65667#L1555-1 assume !(1 == ~T13_E~0); 65666#L1560-1 assume !(1 == ~T14_E~0); 65665#L1565-1 assume !(1 == ~E_1~0); 65664#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 65663#L1575-1 assume !(1 == ~E_3~0); 65662#L1580-1 assume !(1 == ~E_4~0); 65661#L1585-1 assume !(1 == ~E_5~0); 65660#L1590-1 assume !(1 == ~E_6~0); 65659#L1595-1 assume !(1 == ~E_7~0); 65658#L1600-1 assume !(1 == ~E_8~0); 65657#L1605-1 assume !(1 == ~E_9~0); 65480#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 65250#L1615-1 assume !(1 == ~E_11~0); 64139#L1620-1 assume !(1 == ~E_12~0); 64140#L1625-1 assume !(1 == ~E_13~0); 64943#L1630-1 assume !(1 == ~E_14~0); 64944#L1635-1 assume { :end_inline_reset_delta_events } true; 65608#L2017-2 [2022-07-13 04:23:41,287 INFO L754 eck$LassoCheckResult]: Loop: 65608#L2017-2 assume !false; 65606#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 64870#L1316 assume !false; 64871#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 65599#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 65588#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 65587#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 65586#L1115 assume !(0 != eval_~tmp~0#1); 65277#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 65278#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 65585#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 65077#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 65078#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 64723#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 64724#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 65340#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 65557#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 65551#L1372-3 assume !(0 == ~T7_E~0); 63510#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 63511#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 64181#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 64182#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 65128#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 65484#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 64667#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 63816#L1412-3 assume !(0 == ~E_1~0); 63817#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 64588#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 64589#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 65335#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 64982#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 64682#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 64683#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 63576#L1452-3 assume !(0 == ~E_9~0); 63577#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 65266#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 65267#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 65048#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 65049#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 63814#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 63815#L646-42 assume 1 == ~m_pc~0; 64402#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 66942#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 66941#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 66940#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 66939#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 66938#L665-42 assume 1 == ~t1_pc~0; 66937#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 66935#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 66934#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 66933#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 66932#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 66931#L684-42 assume 1 == ~t2_pc~0; 66929#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 66928#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 66927#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 66926#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 66925#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 66924#L703-42 assume 1 == ~t3_pc~0; 66923#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 66921#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 66920#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 66919#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 66918#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 66917#L722-42 assume 1 == ~t4_pc~0; 66915#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 66914#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66913#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 66912#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 66911#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 66910#L741-42 assume 1 == ~t5_pc~0; 66909#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 66907#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 66906#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 66905#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 66904#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 66903#L760-42 assume !(1 == ~t6_pc~0); 64849#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 64695#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 64696#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 65113#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 64372#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 64373#L779-42 assume 1 == ~t7_pc~0; 65251#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 65194#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 64056#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 64057#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 63911#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 63912#L798-42 assume !(1 == ~t8_pc~0); 63522#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 63523#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 65323#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 64719#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 63742#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 63743#L817-42 assume 1 == ~t9_pc~0; 64520#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 64027#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 64028#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 64154#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 64977#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 64978#L836-42 assume 1 == ~t10_pc~0; 65082#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 64065#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 64066#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 65440#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 65441#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 65493#L855-42 assume 1 == ~t11_pc~0; 65509#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 63615#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 63616#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 64367#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 65172#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 64230#L874-42 assume 1 == ~t12_pc~0; 64231#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 64472#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 63530#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 63531#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 63784#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 63785#L893-42 assume 1 == ~t13_pc~0; 65011#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 64777#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 64792#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 64693#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 64159#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 64160#L912-42 assume !(1 == ~t14_pc~0); 64987#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 63476#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 63477#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 65088#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 66801#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 66799#L1495-3 assume !(1 == ~M_E~0); 66796#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 66794#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 65453#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 66791#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 66790#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 66789#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 66788#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 64999#L1530-3 assume !(1 == ~T8_E~0); 66787#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 66785#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 66782#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 66780#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 66778#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 66776#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 66774#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 66772#L1570-3 assume !(1 == ~E_2~0); 66769#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 66767#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 66765#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 66763#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 66761#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 66759#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 66756#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 66754#L1610-3 assume !(1 == ~E_10~0); 66752#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 66750#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 66748#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 66746#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 66743#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 66720#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 66704#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 65576#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 65577#L2036 assume !(0 == start_simulation_~tmp~3#1); 65787#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 65473#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 64294#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 65379#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 64700#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 64701#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 65499#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 65500#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 65608#L2017-2 [2022-07-13 04:23:41,288 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:41,288 INFO L85 PathProgramCache]: Analyzing trace with hash 1463218542, now seen corresponding path program 1 times [2022-07-13 04:23:41,288 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:41,288 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [724386886] [2022-07-13 04:23:41,288 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:41,288 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:41,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:41,315 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:41,315 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:41,316 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [724386886] [2022-07-13 04:23:41,316 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [724386886] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:41,316 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:41,316 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-13 04:23:41,316 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1491915199] [2022-07-13 04:23:41,316 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:41,317 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-13 04:23:41,317 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:41,317 INFO L85 PathProgramCache]: Analyzing trace with hash 46893742, now seen corresponding path program 1 times [2022-07-13 04:23:41,317 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:41,317 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1823137002] [2022-07-13 04:23:41,318 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:41,318 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:41,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:41,346 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:41,347 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:41,347 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1823137002] [2022-07-13 04:23:41,347 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1823137002] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:41,347 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:41,347 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-13 04:23:41,347 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [337846001] [2022-07-13 04:23:41,348 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:41,348 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-13 04:23:41,348 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-13 04:23:41,348 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-13 04:23:41,348 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-13 04:23:41,349 INFO L87 Difference]: Start difference. First operand 3936 states and 5800 transitions. cyclomatic complexity: 1866 Second operand has 4 states, 4 states have (on average 42.5) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:41,501 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-13 04:23:41,501 INFO L93 Difference]: Finished difference Result 7484 states and 11021 transitions. [2022-07-13 04:23:41,502 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-13 04:23:41,502 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7484 states and 11021 transitions. [2022-07-13 04:23:41,530 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7232 [2022-07-13 04:23:41,546 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7484 states to 7484 states and 11021 transitions. [2022-07-13 04:23:41,547 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7484 [2022-07-13 04:23:41,551 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7484 [2022-07-13 04:23:41,551 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7484 states and 11021 transitions. [2022-07-13 04:23:41,559 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-13 04:23:41,559 INFO L369 hiAutomatonCegarLoop]: Abstraction has 7484 states and 11021 transitions. [2022-07-13 04:23:41,563 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7484 states and 11021 transitions. [2022-07-13 04:23:41,625 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7484 to 7480. [2022-07-13 04:23:41,637 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7480 states, 7480 states have (on average 1.472860962566845) internal successors, (11017), 7479 states have internal predecessors, (11017), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:41,651 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7480 states to 7480 states and 11017 transitions. [2022-07-13 04:23:41,651 INFO L392 hiAutomatonCegarLoop]: Abstraction has 7480 states and 11017 transitions. [2022-07-13 04:23:41,652 INFO L374 stractBuchiCegarLoop]: Abstraction has 7480 states and 11017 transitions. [2022-07-13 04:23:41,652 INFO L287 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-07-13 04:23:41,652 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7480 states and 11017 transitions. [2022-07-13 04:23:41,670 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7232 [2022-07-13 04:23:41,670 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-13 04:23:41,670 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-13 04:23:41,672 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:41,672 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:41,672 INFO L752 eck$LassoCheckResult]: Stem: 75793#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 75794#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 76417#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 75509#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 75510#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 75759#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 75760#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 75483#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 75484#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 76767#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 76073#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 76074#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 76623#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 75983#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 75984#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 75385#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 75386#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 75723#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 75932#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 74954#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 74955#L1342 assume !(0 == ~M_E~0); 75120#L1342-2 assume !(0 == ~T1_E~0); 75690#L1347-1 assume !(0 == ~T2_E~0); 76750#L1352-1 assume !(0 == ~T3_E~0); 76521#L1357-1 assume !(0 == ~T4_E~0); 75715#L1362-1 assume !(0 == ~T5_E~0); 75716#L1367-1 assume !(0 == ~T6_E~0); 75303#L1372-1 assume !(0 == ~T7_E~0); 75304#L1377-1 assume !(0 == ~T8_E~0); 75643#L1382-1 assume !(0 == ~T9_E~0); 75644#L1387-1 assume !(0 == ~T10_E~0); 76395#L1392-1 assume !(0 == ~T11_E~0); 75676#L1397-1 assume !(0 == ~T12_E~0); 75677#L1402-1 assume !(0 == ~T13_E~0); 75320#L1407-1 assume !(0 == ~T14_E~0); 75321#L1412-1 assume !(0 == ~E_1~0); 76653#L1417-1 assume !(0 == ~E_2~0); 76654#L1422-1 assume !(0 == ~E_3~0); 76950#L1427-1 assume !(0 == ~E_4~0); 75516#L1432-1 assume !(0 == ~E_5~0); 75517#L1437-1 assume !(0 == ~E_6~0); 76561#L1442-1 assume !(0 == ~E_7~0); 76562#L1447-1 assume !(0 == ~E_8~0); 76392#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 75090#L1457-1 assume !(0 == ~E_10~0); 75091#L1462-1 assume !(0 == ~E_11~0); 76600#L1467-1 assume !(0 == ~E_12~0); 76618#L1472-1 assume !(0 == ~E_13~0); 76619#L1477-1 assume !(0 == ~E_14~0); 76336#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 75293#L646 assume 1 == ~m_pc~0; 75294#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 75993#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76008#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 75387#L1666 assume !(0 != activate_threads_~tmp~1#1); 75388#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76979#L665 assume !(1 == ~t1_pc~0); 75876#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 75877#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 75396#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 75397#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 76211#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 76212#L684 assume 1 == ~t2_pc~0; 76331#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 76253#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 76320#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 76754#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 76755#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 76994#L703 assume !(1 == ~t3_pc~0); 75538#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 75539#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 76204#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 74924#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 74925#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 75419#L722 assume 1 == ~t4_pc~0; 76178#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 75604#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 75963#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 76544#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 76030#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 75121#L741 assume 1 == ~t5_pc~0; 75122#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 75441#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 75599#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 75600#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 76298#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 75691#L760 assume !(1 == ~t6_pc~0); 75537#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 75536#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 75389#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 75390#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 76130#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 76131#L779 assume 1 == ~t7_pc~0; 75166#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 75012#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 75013#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 75430#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 75455#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 75456#L798 assume !(1 == ~t8_pc~0); 76809#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 76718#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 75168#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 75169#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 76981#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 74989#L817 assume 1 == ~t9_pc~0; 74990#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 75801#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 75802#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 76341#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 75403#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 75404#L836 assume !(1 == ~t10_pc~0); 75421#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 75349#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 75350#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 75605#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 75606#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 76730#L855 assume 1 == ~t11_pc~0; 76004#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 76005#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 76593#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 76388#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 76218#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 75289#L874 assume !(1 == ~t12_pc~0); 75290#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 75464#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 75465#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 75607#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 74962#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 74963#L893 assume 1 == ~t13_pc~0; 76892#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 75323#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 75642#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 76802#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 76812#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 76813#L912 assume 1 == ~t14_pc~0; 76568#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 76569#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 75292#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 75221#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 75222#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76023#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 76455#L1495-2 assume !(1 == ~T1_E~0); 76456#L1500-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 76944#L1505-1 assume !(1 == ~T3_E~0); 77460#L1510-1 assume !(1 == ~T4_E~0); 76188#L1515-1 assume !(1 == ~T5_E~0); 76189#L1520-1 assume !(1 == ~T6_E~0); 76810#L1525-1 assume !(1 == ~T7_E~0); 76811#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 77415#L1535-1 assume !(1 == ~T9_E~0); 77414#L1540-1 assume !(1 == ~T10_E~0); 77379#L1545-1 assume !(1 == ~T11_E~0); 77377#L1550-1 assume !(1 == ~T12_E~0); 77375#L1555-1 assume !(1 == ~T13_E~0); 75442#L1560-1 assume !(1 == ~T14_E~0); 75443#L1565-1 assume !(1 == ~E_1~0); 77305#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 77303#L1575-1 assume !(1 == ~E_3~0); 77263#L1580-1 assume !(1 == ~E_4~0); 77239#L1585-1 assume !(1 == ~E_5~0); 77219#L1590-1 assume !(1 == ~E_6~0); 77203#L1595-1 assume !(1 == ~E_7~0); 77196#L1600-1 assume !(1 == ~E_8~0); 77191#L1605-1 assume !(1 == ~E_9~0); 77175#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 77141#L1615-1 assume !(1 == ~E_11~0); 77123#L1620-1 assume !(1 == ~E_12~0); 77114#L1625-1 assume !(1 == ~E_13~0); 77106#L1630-1 assume !(1 == ~E_14~0); 77098#L1635-1 assume { :end_inline_reset_delta_events } true; 77091#L2017-2 [2022-07-13 04:23:41,673 INFO L754 eck$LassoCheckResult]: Loop: 77091#L2017-2 assume !false; 77088#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 77084#L1316 assume !false; 77083#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 77078#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 77067#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 77066#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 77064#L1115 assume !(0 != eval_~tmp~0#1); 77063#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 77062#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 77061#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 77060#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 77059#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 76176#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 76177#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 76787#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 77018#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 77010#L1372-3 assume !(0 == ~T7_E~0); 74940#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 74941#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 75623#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 75624#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 76571#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 76942#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 76117#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 75248#L1412-3 assume !(0 == ~E_1~0); 75249#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 76038#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 76039#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 76780#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 76431#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 76132#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 76133#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 75006#L1452-3 assume !(0 == ~E_9~0); 75007#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 76714#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 76715#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 76498#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 76499#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 75246#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 75247#L646-42 assume 1 == ~m_pc~0; 75851#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 76751#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76752#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 76923#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 76924#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76673#L665-42 assume !(1 == ~t1_pc~0); 76631#L665-44 is_transmit1_triggered_~__retres1~1#1 := 0; 76632#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 76848#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 75422#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 75423#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77017#L684-42 assume 1 == ~t2_pc~0; 76294#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 76295#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 76997#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 76069#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 76070#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 76197#L703-42 assume 1 == ~t3_pc~0; 76401#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 76402#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 75696#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 75697#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 76505#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 76104#L722-42 assume 1 == ~t4_pc~0; 76105#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 76536#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 75748#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 75571#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 75572#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 76974#L741-42 assume !(1 == ~t5_pc~0); 76518#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 75967#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 75968#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 77025#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 75869#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 75870#L760-42 assume 1 == ~t6_pc~0; 76011#L761-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 76145#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 76146#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 76555#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 75820#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 75821#L779-42 assume 1 == ~t7_pc~0; 76697#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 76637#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 75498#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 75499#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 75347#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 75348#L798-42 assume 1 == ~t8_pc~0; 75810#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 74953#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 76769#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 76171#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 75172#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 75173#L817-42 assume 1 == ~t9_pc~0; 75973#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 75469#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 75470#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 75596#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 76426#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 76427#L836-42 assume 1 == ~t10_pc~0; 76529#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 75507#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 75508#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 76896#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 76897#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 76953#L855-42 assume !(1 == ~t11_pc~0); 76973#L855-44 is_transmit11_triggered_~__retres1~11#1 := 0; 75045#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 75046#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 75815#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 76617#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 75672#L874-42 assume 1 == ~t12_pc~0; 75673#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 75924#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 74960#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 74961#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 75215#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 75216#L893-42 assume !(1 == ~t13_pc~0); 77047#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 78090#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 78087#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 78085#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 78083#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 78081#L912-42 assume 1 == ~t14_pc~0; 78077#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 78074#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 78072#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 78009#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 78007#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 78005#L1495-3 assume !(1 == ~M_E~0); 78003#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 78001#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 76908#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 77998#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 77996#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 77994#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 77993#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 77989#L1530-3 assume !(1 == ~T8_E~0); 77987#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 77985#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 77983#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 77981#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 77920#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 77917#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 77914#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 76478#L1570-3 assume !(1 == ~E_2~0); 77505#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 77503#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 77501#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 77461#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 77459#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 77413#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 77378#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 77376#L1610-3 assume !(1 == ~E_10~0); 77374#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 77373#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 77371#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 77369#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 77334#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 77295#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 77257#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 77255#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 77228#L2036 assume !(0 == start_simulation_~tmp~3#1); 77188#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 77159#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 77157#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 77140#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 77122#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 77113#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 77105#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 77097#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 77091#L2017-2 [2022-07-13 04:23:41,673 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:41,673 INFO L85 PathProgramCache]: Analyzing trace with hash -1432795152, now seen corresponding path program 1 times [2022-07-13 04:23:41,673 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:41,674 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [669200100] [2022-07-13 04:23:41,674 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:41,674 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:41,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:41,719 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:41,719 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:41,719 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [669200100] [2022-07-13 04:23:41,719 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [669200100] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:41,720 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:41,720 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-13 04:23:41,720 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1526527556] [2022-07-13 04:23:41,720 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:41,720 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-13 04:23:41,721 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:41,721 INFO L85 PathProgramCache]: Analyzing trace with hash 739563085, now seen corresponding path program 1 times [2022-07-13 04:23:41,721 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:41,721 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [781248165] [2022-07-13 04:23:41,721 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:41,721 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:41,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:41,746 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:41,746 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:41,746 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [781248165] [2022-07-13 04:23:41,746 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [781248165] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:41,746 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:41,747 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-13 04:23:41,747 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [664285403] [2022-07-13 04:23:41,747 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:41,747 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-13 04:23:41,747 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-13 04:23:41,747 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-13 04:23:41,748 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-13 04:23:41,748 INFO L87 Difference]: Start difference. First operand 7480 states and 11017 transitions. cyclomatic complexity: 3541 Second operand has 4 states, 4 states have (on average 42.5) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:41,899 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-13 04:23:41,899 INFO L93 Difference]: Finished difference Result 14320 states and 21070 transitions. [2022-07-13 04:23:41,899 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-13 04:23:41,899 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14320 states and 21070 transitions. [2022-07-13 04:23:41,967 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 14036 [2022-07-13 04:23:42,028 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14320 states to 14320 states and 21070 transitions. [2022-07-13 04:23:42,028 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14320 [2022-07-13 04:23:42,044 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14320 [2022-07-13 04:23:42,044 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14320 states and 21070 transitions. [2022-07-13 04:23:42,057 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-13 04:23:42,057 INFO L369 hiAutomatonCegarLoop]: Abstraction has 14320 states and 21070 transitions. [2022-07-13 04:23:42,067 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14320 states and 21070 transitions. [2022-07-13 04:23:42,215 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14320 to 14316. [2022-07-13 04:23:42,239 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14316 states, 14316 states have (on average 1.4715004191114835) internal successors, (21066), 14315 states have internal predecessors, (21066), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:42,278 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14316 states to 14316 states and 21066 transitions. [2022-07-13 04:23:42,278 INFO L392 hiAutomatonCegarLoop]: Abstraction has 14316 states and 21066 transitions. [2022-07-13 04:23:42,278 INFO L374 stractBuchiCegarLoop]: Abstraction has 14316 states and 21066 transitions. [2022-07-13 04:23:42,278 INFO L287 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-07-13 04:23:42,278 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14316 states and 21066 transitions. [2022-07-13 04:23:42,329 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 14036 [2022-07-13 04:23:42,329 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-13 04:23:42,329 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-13 04:23:42,330 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:42,330 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:42,331 INFO L752 eck$LassoCheckResult]: Stem: 97593#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 97594#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 98215#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 97310#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 97311#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 97559#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 97560#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 97284#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 97285#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 98556#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 97870#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 97871#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 98414#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 97777#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 97778#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 97190#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 97191#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 97526#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 97728#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 96764#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 96765#L1342 assume !(0 == ~M_E~0); 96931#L1342-2 assume !(0 == ~T1_E~0); 97493#L1347-1 assume !(0 == ~T2_E~0); 98539#L1352-1 assume !(0 == ~T3_E~0); 98315#L1357-1 assume !(0 == ~T4_E~0); 97518#L1362-1 assume !(0 == ~T5_E~0); 97519#L1367-1 assume !(0 == ~T6_E~0); 97111#L1372-1 assume !(0 == ~T7_E~0); 97112#L1377-1 assume !(0 == ~T8_E~0); 97446#L1382-1 assume !(0 == ~T9_E~0); 97447#L1387-1 assume !(0 == ~T10_E~0); 98193#L1392-1 assume !(0 == ~T11_E~0); 97479#L1397-1 assume !(0 == ~T12_E~0); 97480#L1402-1 assume !(0 == ~T13_E~0); 97128#L1407-1 assume !(0 == ~T14_E~0); 97129#L1412-1 assume !(0 == ~E_1~0); 98447#L1417-1 assume !(0 == ~E_2~0); 98448#L1422-1 assume !(0 == ~E_3~0); 98727#L1427-1 assume !(0 == ~E_4~0); 97317#L1432-1 assume !(0 == ~E_5~0); 97318#L1437-1 assume !(0 == ~E_6~0); 98355#L1442-1 assume !(0 == ~E_7~0); 98356#L1447-1 assume !(0 == ~E_8~0); 98190#L1452-1 assume !(0 == ~E_9~0); 96901#L1457-1 assume !(0 == ~E_10~0); 96902#L1462-1 assume !(0 == ~E_11~0); 98393#L1467-1 assume !(0 == ~E_12~0); 98408#L1472-1 assume !(0 == ~E_13~0); 98409#L1477-1 assume !(0 == ~E_14~0); 98136#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 97101#L646 assume 1 == ~m_pc~0; 97102#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 97788#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 97803#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 97192#L1666 assume !(0 != activate_threads_~tmp~1#1); 97193#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 98756#L665 assume !(1 == ~t1_pc~0); 97673#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 97674#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 97201#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 97202#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 98009#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 98010#L684 assume 1 == ~t2_pc~0; 98131#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 98052#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 98120#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 98543#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 98544#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 98771#L703 assume !(1 == ~t3_pc~0); 97339#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 97340#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 98001#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 96734#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 96735#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 97223#L722 assume 1 == ~t4_pc~0; 97977#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 97406#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 97757#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 98339#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 97825#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 96932#L741 assume 1 == ~t5_pc~0; 96933#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 97245#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 97401#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 97402#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 98097#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 97494#L760 assume !(1 == ~t6_pc~0); 97338#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 97337#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 97194#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 97195#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 97929#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 97930#L779 assume 1 == ~t7_pc~0; 96978#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 96822#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 96823#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 97234#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 97258#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 97259#L798 assume !(1 == ~t8_pc~0); 98593#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 98504#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 96980#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 96981#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 98758#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 96799#L817 assume 1 == ~t9_pc~0; 96800#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 97601#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 97602#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 98141#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 97208#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 97209#L836 assume !(1 == ~t10_pc~0); 97225#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 97156#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 97157#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 97407#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 97408#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 98517#L855 assume 1 == ~t11_pc~0; 97799#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 97800#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 98388#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 98186#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 98016#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 97097#L874 assume !(1 == ~t12_pc~0); 97098#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 97267#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 97268#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 97409#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 96772#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 96773#L893 assume 1 == ~t13_pc~0; 98672#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 97131#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 97445#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 98587#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 98595#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 98596#L912 assume 1 == ~t14_pc~0; 98362#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 98363#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 97100#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 97032#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 97033#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 97818#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 98250#L1495-2 assume !(1 == ~T1_E~0); 98251#L1500-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 97925#L1505-1 assume !(1 == ~T3_E~0); 97926#L1510-1 assume !(1 == ~T4_E~0); 97986#L1515-1 assume !(1 == ~T5_E~0); 97987#L1520-1 assume !(1 == ~T6_E~0); 98594#L1525-1 assume !(1 == ~T7_E~0); 98275#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 98276#L1535-1 assume !(1 == ~T9_E~0); 98787#L1540-1 assume !(1 == ~T10_E~0); 98788#L1545-1 assume !(1 == ~T11_E~0); 98818#L1550-1 assume !(1 == ~T12_E~0); 98819#L1555-1 assume !(1 == ~T13_E~0); 97246#L1560-1 assume !(1 == ~T14_E~0); 97247#L1565-1 assume !(1 == ~E_1~0); 99006#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 99002#L1575-1 assume !(1 == ~E_3~0); 98997#L1580-1 assume !(1 == ~E_4~0); 98993#L1585-1 assume !(1 == ~E_5~0); 98989#L1590-1 assume !(1 == ~E_6~0); 98985#L1595-1 assume !(1 == ~E_7~0); 98980#L1600-1 assume !(1 == ~E_8~0); 98936#L1605-1 assume !(1 == ~E_9~0); 98932#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 98931#L1615-1 assume !(1 == ~E_11~0); 98893#L1620-1 assume !(1 == ~E_12~0); 98884#L1625-1 assume !(1 == ~E_13~0); 98876#L1630-1 assume !(1 == ~E_14~0); 98868#L1635-1 assume { :end_inline_reset_delta_events } true; 98861#L2017-2 [2022-07-13 04:23:42,331 INFO L754 eck$LassoCheckResult]: Loop: 98861#L2017-2 assume !false; 98858#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 98854#L1316 assume !false; 98853#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 98848#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 98837#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 98836#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 98834#L1115 assume !(0 != eval_~tmp~0#1); 98833#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 98832#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 98831#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 98830#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 98828#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 98829#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 101659#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 101656#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 101654#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 101652#L1372-3 assume !(0 == ~T7_E~0); 101650#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 101648#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 101646#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 101643#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 101641#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 101639#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 101637#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 101635#L1412-3 assume !(0 == ~E_1~0); 101633#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 101632#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 101629#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 101627#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 101625#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 101623#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 101621#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 101619#L1452-3 assume !(0 == ~E_9~0); 101616#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 101614#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 101438#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 101430#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 101422#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 101414#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 101406#L646-42 assume 1 == ~m_pc~0; 101397#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 101390#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 101382#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 101374#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 101366#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 101359#L665-42 assume !(1 == ~t1_pc~0); 101351#L665-44 is_transmit1_triggered_~__retres1~1#1 := 0; 101345#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 101338#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 101333#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 101327#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 101322#L684-42 assume 1 == ~t2_pc~0; 101315#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 101309#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 101303#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 101297#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 101290#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 101283#L703-42 assume !(1 == ~t3_pc~0); 101277#L703-44 is_transmit3_triggered_~__retres1~3#1 := 0; 101272#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 101266#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 101259#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 101252#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 101244#L722-42 assume 1 == ~t4_pc~0; 101237#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 101232#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 101227#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 101221#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 101215#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 101209#L741-42 assume 1 == ~t5_pc~0; 101203#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 101197#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 101192#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 101191#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 101190#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 101189#L760-42 assume 1 == ~t6_pc~0; 101187#L761-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 101186#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 101185#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 101184#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 101183#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 101182#L779-42 assume !(1 == ~t7_pc~0); 101181#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 101179#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 101178#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 101177#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 101176#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 101175#L798-42 assume !(1 == ~t8_pc~0); 101173#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 101172#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 101171#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 101170#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 101169#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 101168#L817-42 assume !(1 == ~t9_pc~0); 101167#L817-44 is_transmit9_triggered_~__retres1~9#1 := 0; 101165#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 101164#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 101163#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 101162#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 101161#L836-42 assume !(1 == ~t10_pc~0); 101159#L836-44 is_transmit10_triggered_~__retres1~10#1 := 0; 101157#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 101155#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 101153#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 101151#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 101149#L855-42 assume !(1 == ~t11_pc~0); 101147#L855-44 is_transmit11_triggered_~__retres1~11#1 := 0; 101144#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 101143#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 101141#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 101139#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 101137#L874-42 assume 1 == ~t12_pc~0; 101135#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 101132#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 101131#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 101115#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 101113#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 101111#L893-42 assume 1 == ~t13_pc~0; 101107#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 101105#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 101103#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 101100#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 101098#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 101096#L912-42 assume 1 == ~t14_pc~0; 101093#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 101091#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 101089#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 101086#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 101084#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 101082#L1495-3 assume !(1 == ~M_E~0); 101080#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 101078#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 98687#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 101074#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 101072#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 101070#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 100504#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 100501#L1530-3 assume !(1 == ~T8_E~0); 100499#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 100497#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 100010#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 99684#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 99430#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 99428#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 99425#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 99421#L1570-3 assume !(1 == ~E_2~0); 99419#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 99417#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 99415#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 99413#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 99410#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 99408#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 99406#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 99402#L1610-3 assume !(1 == ~E_10~0); 99400#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 99398#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 99395#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 99393#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 99391#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 99182#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 99166#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 99114#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 99111#L2036 assume !(0 == start_simulation_~tmp~3#1); 98969#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 98915#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 98913#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 98911#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 98892#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 98883#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 98875#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 98867#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 98861#L2017-2 [2022-07-13 04:23:42,331 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:42,331 INFO L85 PathProgramCache]: Analyzing trace with hash -1867300750, now seen corresponding path program 1 times [2022-07-13 04:23:42,331 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:42,331 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1866356652] [2022-07-13 04:23:42,331 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:42,332 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:42,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:42,358 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:42,358 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:42,358 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1866356652] [2022-07-13 04:23:42,358 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1866356652] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:42,358 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:42,358 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-13 04:23:42,358 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1828310026] [2022-07-13 04:23:42,358 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:42,359 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-13 04:23:42,359 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:42,359 INFO L85 PathProgramCache]: Analyzing trace with hash 1697432426, now seen corresponding path program 1 times [2022-07-13 04:23:42,359 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:42,359 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1937363601] [2022-07-13 04:23:42,360 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:42,360 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:42,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:42,385 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:42,385 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:42,385 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1937363601] [2022-07-13 04:23:42,385 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1937363601] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:42,385 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:42,385 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-13 04:23:42,385 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2019944269] [2022-07-13 04:23:42,385 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:42,386 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-13 04:23:42,386 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-13 04:23:42,386 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-13 04:23:42,386 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-13 04:23:42,386 INFO L87 Difference]: Start difference. First operand 14316 states and 21066 transitions. cyclomatic complexity: 6758 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 2 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:42,535 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-13 04:23:42,535 INFO L93 Difference]: Finished difference Result 21413 states and 31292 transitions. [2022-07-13 04:23:42,535 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-13 04:23:42,536 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21413 states and 31292 transitions. [2022-07-13 04:23:42,691 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 21126 [2022-07-13 04:23:42,743 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21413 states to 21413 states and 31292 transitions. [2022-07-13 04:23:42,743 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21413 [2022-07-13 04:23:42,769 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21413 [2022-07-13 04:23:42,770 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21413 states and 31292 transitions. [2022-07-13 04:23:42,785 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-13 04:23:42,785 INFO L369 hiAutomatonCegarLoop]: Abstraction has 21413 states and 31292 transitions. [2022-07-13 04:23:42,797 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21413 states and 31292 transitions. [2022-07-13 04:23:42,966 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21413 to 20985. [2022-07-13 04:23:42,990 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20985 states, 20985 states have (on average 1.46256850131046) internal successors, (30692), 20984 states have internal predecessors, (30692), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:43,024 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20985 states to 20985 states and 30692 transitions. [2022-07-13 04:23:43,024 INFO L392 hiAutomatonCegarLoop]: Abstraction has 20985 states and 30692 transitions. [2022-07-13 04:23:43,024 INFO L374 stractBuchiCegarLoop]: Abstraction has 20985 states and 30692 transitions. [2022-07-13 04:23:43,024 INFO L287 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-07-13 04:23:43,025 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20985 states and 30692 transitions. [2022-07-13 04:23:43,080 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 20702 [2022-07-13 04:23:43,081 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-13 04:23:43,081 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-13 04:23:43,082 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:43,082 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:43,083 INFO L752 eck$LassoCheckResult]: Stem: 133326#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 133327#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 133958#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 133044#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 133045#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 133292#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 133293#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 133018#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 133019#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 134310#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 133604#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 133605#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 134170#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 133509#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 133510#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 132922#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 132923#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 133259#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 133459#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 132500#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 132501#L1342 assume !(0 == ~M_E~0); 132666#L1342-2 assume !(0 == ~T1_E~0); 133225#L1347-1 assume !(0 == ~T2_E~0); 134289#L1352-1 assume !(0 == ~T3_E~0); 134064#L1357-1 assume !(0 == ~T4_E~0); 133251#L1362-1 assume !(0 == ~T5_E~0); 133252#L1367-1 assume !(0 == ~T6_E~0); 132842#L1372-1 assume !(0 == ~T7_E~0); 132843#L1377-1 assume !(0 == ~T8_E~0); 133179#L1382-1 assume !(0 == ~T9_E~0); 133180#L1387-1 assume !(0 == ~T10_E~0); 133937#L1392-1 assume !(0 == ~T11_E~0); 133213#L1397-1 assume !(0 == ~T12_E~0); 133214#L1402-1 assume !(0 == ~T13_E~0); 132859#L1407-1 assume !(0 == ~T14_E~0); 132860#L1412-1 assume !(0 == ~E_1~0); 134201#L1417-1 assume !(0 == ~E_2~0); 134202#L1422-1 assume !(0 == ~E_3~0); 134503#L1427-1 assume !(0 == ~E_4~0); 133051#L1432-1 assume !(0 == ~E_5~0); 133052#L1437-1 assume !(0 == ~E_6~0); 134110#L1442-1 assume !(0 == ~E_7~0); 134111#L1447-1 assume !(0 == ~E_8~0); 133934#L1452-1 assume !(0 == ~E_9~0); 132636#L1457-1 assume !(0 == ~E_10~0); 132637#L1462-1 assume !(0 == ~E_11~0); 134152#L1467-1 assume !(0 == ~E_12~0); 134165#L1472-1 assume !(0 == ~E_13~0); 134166#L1477-1 assume !(0 == ~E_14~0); 133878#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 132835#L646 assume !(1 == ~m_pc~0); 132836#L646-2 is_master_triggered_~__retres1~0#1 := 0; 133537#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 133538#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 132924#L1666 assume !(0 != activate_threads_~tmp~1#1); 132925#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 134538#L665 assume !(1 == ~t1_pc~0); 133406#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 133407#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 132933#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 132934#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 133745#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 133746#L684 assume 1 == ~t2_pc~0; 133873#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 133790#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 133861#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 134293#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 134294#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 134553#L703 assume !(1 == ~t3_pc~0); 133073#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 133074#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 133737#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 132470#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 132471#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 132956#L722 assume 1 == ~t4_pc~0; 133711#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 133140#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 133488#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 134093#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 133562#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 132667#L741 assume 1 == ~t5_pc~0; 132668#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 132978#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 133137#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 133138#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 133840#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 133226#L760 assume !(1 == ~t6_pc~0); 133072#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 133071#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 132926#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 132927#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 133662#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 133663#L779 assume 1 == ~t7_pc~0; 132711#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 132558#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 132559#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 132967#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 132991#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 132992#L798 assume !(1 == ~t8_pc~0); 134347#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 134260#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 132713#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 132714#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 134540#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 132535#L817 assume 1 == ~t9_pc~0; 132536#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 133334#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 133335#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 133883#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 132940#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 132941#L836 assume !(1 == ~t10_pc~0); 132958#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 132888#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 132889#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 133141#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 133142#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 134270#L855 assume 1 == ~t11_pc~0; 133533#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 133534#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 134145#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 133930#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 133753#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 132829#L874 assume !(1 == ~t12_pc~0); 132830#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 133000#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 133001#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 133143#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 132508#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 132509#L893 assume 1 == ~t13_pc~0; 134445#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 132862#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 133178#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 134340#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 134350#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 134351#L912 assume 1 == ~t14_pc~0; 134117#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 134118#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 132832#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 132764#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 132765#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 133553#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 133995#L1495-2 assume !(1 == ~T1_E~0); 133996#L1500-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 133657#L1505-1 assume !(1 == ~T3_E~0); 133658#L1510-1 assume !(1 == ~T4_E~0); 133720#L1515-1 assume !(1 == ~T5_E~0); 133721#L1520-1 assume !(1 == ~T6_E~0); 134348#L1525-1 assume !(1 == ~T7_E~0); 134024#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 134025#L1535-1 assume !(1 == ~T9_E~0); 134564#L1540-1 assume !(1 == ~T10_E~0); 134565#L1545-1 assume !(1 == ~T11_E~0); 134604#L1550-1 assume !(1 == ~T12_E~0); 134605#L1555-1 assume !(1 == ~T13_E~0); 132979#L1560-1 assume !(1 == ~T14_E~0); 132980#L1565-1 assume !(1 == ~E_1~0); 134590#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 133902#L1575-1 assume !(1 == ~E_3~0); 133253#L1580-1 assume !(1 == ~E_4~0); 133254#L1585-1 assume !(1 == ~E_5~0); 133739#L1590-1 assume !(1 == ~E_6~0); 133288#L1595-1 assume !(1 == ~E_7~0); 133289#L1600-1 assume !(1 == ~E_8~0); 133670#L1605-1 assume !(1 == ~E_9~0); 133671#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 146028#L1615-1 assume !(1 == ~E_11~0); 146027#L1620-1 assume !(1 == ~E_12~0); 146026#L1625-1 assume !(1 == ~E_13~0); 146025#L1630-1 assume !(1 == ~E_14~0); 145075#L1635-1 assume { :end_inline_reset_delta_events } true; 145074#L2017-2 [2022-07-13 04:23:43,083 INFO L754 eck$LassoCheckResult]: Loop: 145074#L2017-2 assume !false; 145058#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 145055#L1316 assume !false; 145047#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 145048#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 145027#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 145028#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 145020#L1115 assume !(0 != eval_~tmp~0#1); 145022#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 145528#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 145529#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 146006#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 146004#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 146005#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 151705#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 151703#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 151701#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 151698#L1372-3 assume !(0 == ~T7_E~0); 151696#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 151694#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 151692#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 151690#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 151689#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 151688#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 151687#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 151686#L1412-3 assume !(0 == ~E_1~0); 151685#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 151684#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 151683#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 151682#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 151681#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 151680#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 151679#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 151678#L1452-3 assume !(0 == ~E_9~0); 151677#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 151676#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 151675#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 151674#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 151673#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 151672#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 151671#L646-42 assume !(1 == ~m_pc~0); 151670#L646-44 is_master_triggered_~__retres1~0#1 := 0; 151669#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 151668#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 151667#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 151666#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 151665#L665-42 assume 1 == ~t1_pc~0; 151664#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 151662#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 151661#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 151660#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 151659#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 151658#L684-42 assume 1 == ~t2_pc~0; 151656#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 151655#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 151654#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 151653#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 151652#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 151651#L703-42 assume 1 == ~t3_pc~0; 151650#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 151648#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 151647#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 151646#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 151645#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 151644#L722-42 assume 1 == ~t4_pc~0; 151642#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 151641#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 151640#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 151639#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 151638#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 151637#L741-42 assume !(1 == ~t5_pc~0); 151635#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 151634#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 151633#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 151632#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 151631#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 151630#L760-42 assume 1 == ~t6_pc~0; 151628#L761-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 151627#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 151626#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 151625#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 151624#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 151623#L779-42 assume !(1 == ~t7_pc~0); 151622#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 151620#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 151619#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 151618#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 151617#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 151616#L798-42 assume !(1 == ~t8_pc~0); 151614#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 151613#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 151612#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 151611#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 151610#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 151609#L817-42 assume 1 == ~t9_pc~0; 151607#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 151606#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 151605#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 151604#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 151603#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 151602#L836-42 assume !(1 == ~t10_pc~0); 151600#L836-44 is_transmit10_triggered_~__retres1~10#1 := 0; 151599#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 151598#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 151597#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 151596#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 151595#L855-42 assume !(1 == ~t11_pc~0); 151594#L855-44 is_transmit11_triggered_~__retres1~11#1 := 0; 151592#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 151591#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 151590#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 151589#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 151588#L874-42 assume !(1 == ~t12_pc~0); 151586#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 151585#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 151584#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 151583#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 151582#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 151581#L893-42 assume 1 == ~t13_pc~0; 151579#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 151578#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 151577#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 151576#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 151575#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 151574#L912-42 assume 1 == ~t14_pc~0; 151572#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 151571#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 151570#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 151569#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 151568#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 151567#L1495-3 assume !(1 == ~M_E~0); 151566#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 151565#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 134460#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 151564#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 151563#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 151562#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 151561#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 147055#L1530-3 assume !(1 == ~T8_E~0); 151560#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 151559#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 151558#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 151557#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 151556#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 151555#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 151554#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 134017#L1570-3 assume !(1 == ~E_2~0); 151553#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 151552#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 151551#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 151550#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 151549#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 151548#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 151547#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 147543#L1610-3 assume !(1 == ~E_10~0); 151546#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 151545#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 151544#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 151543#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 151542#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 145187#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 145170#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 145171#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 146206#L2036 assume !(0 == start_simulation_~tmp~3#1); 145159#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 145160#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 146051#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 146050#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 146049#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 146048#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 146047#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 145073#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 145074#L2017-2 [2022-07-13 04:23:43,083 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:43,084 INFO L85 PathProgramCache]: Analyzing trace with hash 1199377425, now seen corresponding path program 1 times [2022-07-13 04:23:43,084 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:43,084 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2119682204] [2022-07-13 04:23:43,084 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:43,084 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:43,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:43,109 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:43,109 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:43,109 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2119682204] [2022-07-13 04:23:43,109 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2119682204] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:43,109 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:43,109 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-13 04:23:43,109 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1116185240] [2022-07-13 04:23:43,110 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:43,110 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-13 04:23:43,110 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:43,110 INFO L85 PathProgramCache]: Analyzing trace with hash 752353386, now seen corresponding path program 1 times [2022-07-13 04:23:43,110 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:43,111 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1485258917] [2022-07-13 04:23:43,111 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:43,111 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:43,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:43,135 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:43,135 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:43,135 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1485258917] [2022-07-13 04:23:43,135 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1485258917] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:43,135 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:43,135 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-13 04:23:43,136 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [305270271] [2022-07-13 04:23:43,136 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:43,136 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-13 04:23:43,136 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-13 04:23:43,136 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-13 04:23:43,137 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-13 04:23:43,137 INFO L87 Difference]: Start difference. First operand 20985 states and 30692 transitions. cyclomatic complexity: 9719 Second operand has 4 states, 4 states have (on average 42.5) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:43,525 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-13 04:23:43,525 INFO L93 Difference]: Finished difference Result 54264 states and 78850 transitions. [2022-07-13 04:23:43,525 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-13 04:23:43,526 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 54264 states and 78850 transitions. [2022-07-13 04:23:43,750 INFO L131 ngComponentsAnalysis]: Automaton has 20 accepting balls. 53510 [2022-07-13 04:23:44,058 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 54264 states to 54264 states and 78850 transitions. [2022-07-13 04:23:44,059 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 54264 [2022-07-13 04:23:44,087 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 54264 [2022-07-13 04:23:44,087 INFO L73 IsDeterministic]: Start isDeterministic. Operand 54264 states and 78850 transitions. [2022-07-13 04:23:44,108 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-13 04:23:44,108 INFO L369 hiAutomatonCegarLoop]: Abstraction has 54264 states and 78850 transitions. [2022-07-13 04:23:44,136 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54264 states and 78850 transitions. [2022-07-13 04:23:44,572 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54264 to 40224. [2022-07-13 04:23:44,619 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40224 states, 40224 states have (on average 1.4569659904534606) internal successors, (58605), 40223 states have internal predecessors, (58605), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:44,882 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40224 states to 40224 states and 58605 transitions. [2022-07-13 04:23:44,883 INFO L392 hiAutomatonCegarLoop]: Abstraction has 40224 states and 58605 transitions. [2022-07-13 04:23:44,883 INFO L374 stractBuchiCegarLoop]: Abstraction has 40224 states and 58605 transitions. [2022-07-13 04:23:44,883 INFO L287 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-07-13 04:23:44,883 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40224 states and 58605 transitions. [2022-07-13 04:23:44,983 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 39938 [2022-07-13 04:23:44,983 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-13 04:23:44,983 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-13 04:23:44,985 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:44,985 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:44,985 INFO L752 eck$LassoCheckResult]: Stem: 208586#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 208587#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 209217#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 208301#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 208302#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 208551#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 208552#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 208275#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 208276#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 209579#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 208862#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 208863#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 209443#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 208768#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 208769#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 208180#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 208181#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 208516#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 208719#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 207759#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 207760#L1342 assume !(0 == ~M_E~0); 207925#L1342-2 assume !(0 == ~T1_E~0); 208483#L1347-1 assume !(0 == ~T2_E~0); 209561#L1352-1 assume !(0 == ~T3_E~0); 209326#L1357-1 assume !(0 == ~T4_E~0); 208508#L1362-1 assume !(0 == ~T5_E~0); 208509#L1367-1 assume !(0 == ~T6_E~0); 208101#L1372-1 assume !(0 == ~T7_E~0); 208102#L1377-1 assume !(0 == ~T8_E~0); 208436#L1382-1 assume !(0 == ~T9_E~0); 208437#L1387-1 assume !(0 == ~T10_E~0); 209195#L1392-1 assume !(0 == ~T11_E~0); 208469#L1397-1 assume !(0 == ~T12_E~0); 208470#L1402-1 assume !(0 == ~T13_E~0); 208118#L1407-1 assume !(0 == ~T14_E~0); 208119#L1412-1 assume !(0 == ~E_1~0); 209473#L1417-1 assume !(0 == ~E_2~0); 209474#L1422-1 assume !(0 == ~E_3~0); 209758#L1427-1 assume !(0 == ~E_4~0); 208308#L1432-1 assume !(0 == ~E_5~0); 208309#L1437-1 assume !(0 == ~E_6~0); 209378#L1442-1 assume !(0 == ~E_7~0); 209379#L1447-1 assume !(0 == ~E_8~0); 209191#L1452-1 assume !(0 == ~E_9~0); 207894#L1457-1 assume !(0 == ~E_10~0); 207895#L1462-1 assume !(0 == ~E_11~0); 209421#L1467-1 assume !(0 == ~E_12~0); 209438#L1472-1 assume !(0 == ~E_13~0); 209439#L1477-1 assume !(0 == ~E_14~0); 209135#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 208092#L646 assume !(1 == ~m_pc~0); 208093#L646-2 is_master_triggered_~__retres1~0#1 := 0; 208795#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 208796#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 208182#L1666 assume !(0 != activate_threads_~tmp~1#1); 208183#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 209792#L665 assume !(1 == ~t1_pc~0); 208666#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 208667#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 208191#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 208192#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 209005#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 209006#L684 assume !(1 == ~t2_pc~0); 209046#L684-2 is_transmit2_triggered_~__retres1~2#1 := 0; 209047#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 209120#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 209565#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 209566#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 209809#L703 assume !(1 == ~t3_pc~0); 208330#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 208331#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 208994#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 207729#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 207730#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 208214#L722 assume 1 == ~t4_pc~0; 208969#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 208397#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 208748#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 209360#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 208819#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 207926#L741 assume 1 == ~t5_pc~0; 207927#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 208236#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 208392#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 208393#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 209097#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 208484#L760 assume !(1 == ~t6_pc~0); 208329#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 208328#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 208184#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 208185#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 208922#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 208923#L779 assume 1 == ~t7_pc~0; 207970#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 207817#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 207818#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 208225#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 208249#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 208250#L798 assume !(1 == ~t8_pc~0); 209617#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 209530#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 207972#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 207973#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 209794#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 207794#L817 assume 1 == ~t9_pc~0; 207795#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 208594#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 208595#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 209140#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 208198#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 208199#L836 assume !(1 == ~t10_pc~0); 208216#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 208146#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 208147#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 208398#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 208399#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 209542#L855 assume 1 == ~t11_pc~0; 208791#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 208792#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 209414#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 209187#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 209012#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 208088#L874 assume !(1 == ~t12_pc~0); 208089#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 208258#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 208259#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 208400#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 207767#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 207768#L893 assume 1 == ~t13_pc~0; 209697#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 208121#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 208435#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 209611#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 209619#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 209620#L912 assume 1 == ~t14_pc~0; 209386#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 209387#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 208091#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 208024#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 208025#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 208812#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 209257#L1495-2 assume !(1 == ~T1_E~0); 209258#L1500-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 208918#L1505-1 assume !(1 == ~T3_E~0); 208919#L1510-1 assume !(1 == ~T4_E~0); 208979#L1515-1 assume !(1 == ~T5_E~0); 208980#L1520-1 assume !(1 == ~T6_E~0); 209618#L1525-1 assume !(1 == ~T7_E~0); 209284#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 209285#L1535-1 assume !(1 == ~T9_E~0); 209826#L1540-1 assume !(1 == ~T10_E~0); 209827#L1545-1 assume !(1 == ~T11_E~0); 209863#L1550-1 assume !(1 == ~T12_E~0); 209864#L1555-1 assume !(1 == ~T13_E~0); 208237#L1560-1 assume !(1 == ~T14_E~0); 208238#L1565-1 assume !(1 == ~E_1~0); 236582#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 236581#L1575-1 assume !(1 == ~E_3~0); 236580#L1580-1 assume !(1 == ~E_4~0); 236579#L1585-1 assume !(1 == ~E_5~0); 236578#L1590-1 assume !(1 == ~E_6~0); 236577#L1595-1 assume !(1 == ~E_7~0); 236576#L1600-1 assume !(1 == ~E_8~0); 208930#L1605-1 assume !(1 == ~E_9~0); 208931#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 209511#L1615-1 assume !(1 == ~E_11~0); 208373#L1620-1 assume !(1 == ~E_12~0); 208374#L1625-1 assume !(1 == ~E_13~0); 209359#L1630-1 assume !(1 == ~E_14~0); 236504#L1635-1 assume { :end_inline_reset_delta_events } true; 236503#L2017-2 [2022-07-13 04:23:44,985 INFO L754 eck$LassoCheckResult]: Loop: 236503#L2017-2 assume !false; 236111#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 236108#L1316 assume !false; 236056#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 236057#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 239371#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 236003#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 235999#L1115 assume !(0 != eval_~tmp~0#1); 236001#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 247768#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 247766#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 247763#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 247761#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 247759#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 247757#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 247755#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 247753#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 247750#L1372-3 assume !(0 == ~T7_E~0); 247748#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 247746#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 247744#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 247742#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 247740#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 247737#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 247735#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 247733#L1412-3 assume !(0 == ~E_1~0); 247731#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 247729#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 247727#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 247724#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 247722#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 247721#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 247720#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 247719#L1452-3 assume !(0 == ~E_9~0); 247718#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 247672#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 247671#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 247669#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 247667#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 247666#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 247665#L646-42 assume !(1 == ~m_pc~0); 247662#L646-44 is_master_triggered_~__retres1~0#1 := 0; 247660#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 247658#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 247656#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 247654#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 247652#L665-42 assume 1 == ~t1_pc~0; 247649#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 247646#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 247644#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 247642#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 247640#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 247638#L684-42 assume !(1 == ~t2_pc~0); 230293#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 247634#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 247632#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 247630#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 247628#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 247626#L703-42 assume 1 == ~t3_pc~0; 247623#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 247620#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 247618#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 247616#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 247614#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 247612#L722-42 assume !(1 == ~t4_pc~0); 247610#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 247607#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 247604#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 247602#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 247600#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 247598#L741-42 assume 1 == ~t5_pc~0; 247595#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 247591#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 247589#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 209847#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 208659#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 208660#L760-42 assume !(1 == ~t6_pc~0); 247575#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 247573#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 209372#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 209373#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 209741#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 246991#L779-42 assume !(1 == ~t7_pc~0); 246990#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 246988#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 246987#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 246986#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 246985#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 246007#L798-42 assume !(1 == ~t8_pc~0); 244851#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 244492#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 244491#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 244490#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 244489#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 244488#L817-42 assume !(1 == ~t9_pc~0); 244487#L817-44 is_transmit9_triggered_~__retres1~9#1 := 0; 244484#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 244482#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 244480#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 244478#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 244476#L836-42 assume 1 == ~t10_pc~0; 244474#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 244472#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 244471#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 244470#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 244469#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 244468#L855-42 assume !(1 == ~t11_pc~0); 244467#L855-44 is_transmit11_triggered_~__retres1~11#1 := 0; 244465#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 244464#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 244463#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 244462#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 244461#L874-42 assume 1 == ~t12_pc~0; 244459#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 244456#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 244454#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 244452#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 244450#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 244448#L893-42 assume !(1 == ~t13_pc~0); 244446#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 244442#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 244440#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 244438#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 244436#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 244434#L912-42 assume !(1 == ~t14_pc~0); 244432#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 244430#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 244428#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 244426#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 244424#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 244422#L1495-3 assume !(1 == ~M_E~0); 244420#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 244417#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 209715#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 244414#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 244412#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 244410#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 244408#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 244170#L1530-3 assume !(1 == ~T8_E~0); 244404#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 244402#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 244400#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 244398#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 244396#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 244393#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 244391#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 239931#L1570-3 assume !(1 == ~E_2~0); 244388#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 244386#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 244384#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 244381#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 244379#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 244377#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 244375#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 244371#L1610-3 assume !(1 == ~E_10~0); 244369#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 244366#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 242696#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 242495#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 242491#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 242485#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 242469#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 242467#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 242465#L2036 assume !(0 == start_simulation_~tmp~3#1); 242463#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 242417#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 242411#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 242405#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 241472#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 241471#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 241470#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 236502#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 236503#L2017-2 [2022-07-13 04:23:44,986 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:44,986 INFO L85 PathProgramCache]: Analyzing trace with hash 752619056, now seen corresponding path program 1 times [2022-07-13 04:23:44,986 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:44,986 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1348905962] [2022-07-13 04:23:44,986 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:44,986 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:44,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:45,026 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:45,026 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:45,026 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1348905962] [2022-07-13 04:23:45,026 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1348905962] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:45,026 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:45,026 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-13 04:23:45,027 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [220905735] [2022-07-13 04:23:45,027 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:45,027 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-13 04:23:45,027 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:45,027 INFO L85 PathProgramCache]: Analyzing trace with hash -346708985, now seen corresponding path program 1 times [2022-07-13 04:23:45,027 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:45,027 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [152741953] [2022-07-13 04:23:45,027 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:45,027 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:45,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:45,067 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:45,067 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:45,067 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [152741953] [2022-07-13 04:23:45,067 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [152741953] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:45,067 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:45,068 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-13 04:23:45,068 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2108781458] [2022-07-13 04:23:45,068 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:45,068 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-13 04:23:45,069 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-13 04:23:45,069 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-13 04:23:45,069 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-13 04:23:45,069 INFO L87 Difference]: Start difference. First operand 40224 states and 58605 transitions. cyclomatic complexity: 18393 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 2 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:45,510 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-13 04:23:45,510 INFO L93 Difference]: Finished difference Result 77309 states and 112244 transitions. [2022-07-13 04:23:45,511 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-13 04:23:45,511 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 77309 states and 112244 transitions. [2022-07-13 04:23:45,780 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 76968 [2022-07-13 04:23:46,246 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 77309 states to 77309 states and 112244 transitions. [2022-07-13 04:23:46,247 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 77309 [2022-07-13 04:23:46,296 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 77309 [2022-07-13 04:23:46,296 INFO L73 IsDeterministic]: Start isDeterministic. Operand 77309 states and 112244 transitions. [2022-07-13 04:23:46,358 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-13 04:23:46,358 INFO L369 hiAutomatonCegarLoop]: Abstraction has 77309 states and 112244 transitions. [2022-07-13 04:23:46,404 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77309 states and 112244 transitions. [2022-07-13 04:23:47,045 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77309 to 77261. [2022-07-13 04:23:47,115 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 77261 states, 77261 states have (on average 1.452168623238115) internal successors, (112196), 77260 states have internal predecessors, (112196), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:47,451 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77261 states to 77261 states and 112196 transitions. [2022-07-13 04:23:47,451 INFO L392 hiAutomatonCegarLoop]: Abstraction has 77261 states and 112196 transitions. [2022-07-13 04:23:47,451 INFO L374 stractBuchiCegarLoop]: Abstraction has 77261 states and 112196 transitions. [2022-07-13 04:23:47,451 INFO L287 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-07-13 04:23:47,451 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 77261 states and 112196 transitions. [2022-07-13 04:23:47,607 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 76920 [2022-07-13 04:23:47,607 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-13 04:23:47,607 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-13 04:23:47,609 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:47,609 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:47,609 INFO L752 eck$LassoCheckResult]: Stem: 326130#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 326131#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 326775#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 325844#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 325845#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 326098#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 326099#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 325818#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 325819#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 327146#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 326411#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 326412#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 326996#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 326315#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 326316#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 325721#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 325722#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 326061#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 326267#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 325299#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 325300#L1342 assume !(0 == ~M_E~0); 325465#L1342-2 assume !(0 == ~T1_E~0); 326027#L1347-1 assume !(0 == ~T2_E~0); 327128#L1352-1 assume !(0 == ~T3_E~0); 326887#L1357-1 assume !(0 == ~T4_E~0); 326052#L1362-1 assume !(0 == ~T5_E~0); 326053#L1367-1 assume !(0 == ~T6_E~0); 325641#L1372-1 assume !(0 == ~T7_E~0); 325642#L1377-1 assume !(0 == ~T8_E~0); 325979#L1382-1 assume !(0 == ~T9_E~0); 325980#L1387-1 assume !(0 == ~T10_E~0); 326756#L1392-1 assume !(0 == ~T11_E~0); 326015#L1397-1 assume !(0 == ~T12_E~0); 326016#L1402-1 assume !(0 == ~T13_E~0); 325656#L1407-1 assume !(0 == ~T14_E~0); 325657#L1412-1 assume !(0 == ~E_1~0); 327031#L1417-1 assume !(0 == ~E_2~0); 327032#L1422-1 assume !(0 == ~E_3~0); 327356#L1427-1 assume !(0 == ~E_4~0); 325850#L1432-1 assume !(0 == ~E_5~0); 325851#L1437-1 assume !(0 == ~E_6~0); 326935#L1442-1 assume !(0 == ~E_7~0); 326936#L1447-1 assume !(0 == ~E_8~0); 326751#L1452-1 assume !(0 == ~E_9~0); 325437#L1457-1 assume !(0 == ~E_10~0); 325438#L1462-1 assume !(0 == ~E_11~0); 326975#L1467-1 assume !(0 == ~E_12~0); 326991#L1472-1 assume !(0 == ~E_13~0); 326992#L1477-1 assume !(0 == ~E_14~0); 326690#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 325635#L646 assume !(1 == ~m_pc~0); 325636#L646-2 is_master_triggered_~__retres1~0#1 := 0; 326344#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 326345#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 325723#L1666 assume !(0 != activate_threads_~tmp~1#1); 325724#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 327389#L665 assume !(1 == ~t1_pc~0); 326213#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 326214#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 325730#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 325731#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 326558#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 326559#L684 assume !(1 == ~t2_pc~0); 326602#L684-2 is_transmit2_triggered_~__retres1~2#1 := 0; 326603#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 326675#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 327132#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 327133#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 327409#L703 assume !(1 == ~t3_pc~0); 325872#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 325873#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 326549#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 325269#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 325270#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 325751#L722 assume !(1 == ~t4_pc~0); 325939#L722-2 is_transmit4_triggered_~__retres1~4#1 := 0; 325940#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 326294#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 326919#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 326367#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 325466#L741 assume 1 == ~t5_pc~0; 325467#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 325773#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 325937#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 325938#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 326653#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 326028#L760 assume !(1 == ~t6_pc~0); 325871#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 325870#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 325725#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 325726#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 326474#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 326475#L779 assume 1 == ~t7_pc~0; 325510#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 325357#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 325358#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 325762#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 325787#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 325788#L798 assume !(1 == ~t8_pc~0); 327193#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 327094#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 325512#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 325513#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 327391#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 325334#L817 assume 1 == ~t9_pc~0; 325335#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 326140#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 326141#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 326696#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 325736#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 325737#L836 assume !(1 == ~t10_pc~0); 325753#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 325685#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 325686#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 325941#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 325942#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 327106#L855 assume 1 == ~t11_pc~0; 326340#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 326341#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 326968#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 326746#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 326565#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 325627#L874 assume !(1 == ~t12_pc~0); 325628#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 325797#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 325798#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 325943#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 325309#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 325310#L893 assume 1 == ~t13_pc~0; 327288#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 325659#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 325978#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 327187#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 327195#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 327196#L912 assume 1 == ~t14_pc~0; 326944#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 326945#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 325630#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 325563#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 325564#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 326361#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 326811#L1495-2 assume !(1 == ~T1_E~0); 326812#L1500-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 326470#L1505-1 assume !(1 == ~T3_E~0); 326471#L1510-1 assume !(1 == ~T4_E~0); 326533#L1515-1 assume !(1 == ~T5_E~0); 326534#L1520-1 assume !(1 == ~T6_E~0); 327194#L1525-1 assume !(1 == ~T7_E~0); 326839#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 326840#L1535-1 assume !(1 == ~T9_E~0); 327428#L1540-1 assume !(1 == ~T10_E~0); 327429#L1545-1 assume !(1 == ~T11_E~0); 327468#L1550-1 assume !(1 == ~T12_E~0); 327469#L1555-1 assume !(1 == ~T13_E~0); 325776#L1560-1 assume !(1 == ~T14_E~0); 325777#L1565-1 assume !(1 == ~E_1~0); 363723#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 363722#L1575-1 assume !(1 == ~E_3~0); 363721#L1580-1 assume !(1 == ~E_4~0); 363720#L1585-1 assume !(1 == ~E_5~0); 326854#L1590-1 assume !(1 == ~E_6~0); 326092#L1595-1 assume !(1 == ~E_7~0); 326093#L1600-1 assume !(1 == ~E_8~0); 326483#L1605-1 assume !(1 == ~E_9~0); 326484#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 327070#L1615-1 assume !(1 == ~E_11~0); 325916#L1620-1 assume !(1 == ~E_12~0); 325917#L1625-1 assume !(1 == ~E_13~0); 326752#L1630-1 assume !(1 == ~E_14~0); 326090#L1635-1 assume { :end_inline_reset_delta_events } true; 326091#L2017-2 [2022-07-13 04:23:47,609 INFO L754 eck$LassoCheckResult]: Loop: 326091#L2017-2 assume !false; 378381#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 378375#L1316 assume !false; 364626#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 364627#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 382533#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 382532#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 382530#L1115 assume !(0 != eval_~tmp~0#1); 382531#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 386449#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 386448#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 386447#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 386446#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 386445#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 386444#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 386443#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 386442#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 386441#L1372-3 assume !(0 == ~T7_E~0); 386440#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 386439#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 386438#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 386437#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 386436#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 386435#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 386434#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 386433#L1412-3 assume !(0 == ~E_1~0); 386432#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 386431#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 386430#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 386429#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 386428#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 386427#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 386426#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 386425#L1452-3 assume !(0 == ~E_9~0); 386424#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 386423#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 386422#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 386421#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 386420#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 386419#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 386418#L646-42 assume !(1 == ~m_pc~0); 386417#L646-44 is_master_triggered_~__retres1~0#1 := 0; 386416#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 386415#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 386414#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 386413#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 386412#L665-42 assume 1 == ~t1_pc~0; 386411#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 386409#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 386408#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 386407#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 386406#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 386405#L684-42 assume !(1 == ~t2_pc~0); 373110#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 386404#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 386403#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 386402#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 386401#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 386400#L703-42 assume 1 == ~t3_pc~0; 386399#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 386397#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 386396#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 386395#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 386394#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 386393#L722-42 assume !(1 == ~t4_pc~0); 386392#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 386391#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 386390#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 386389#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 386388#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 386387#L741-42 assume !(1 == ~t5_pc~0); 386385#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 386384#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 386383#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 386382#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 386381#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 386380#L760-42 assume !(1 == ~t6_pc~0); 386379#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 386377#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 386376#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 386375#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 386374#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 386373#L779-42 assume !(1 == ~t7_pc~0); 386372#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 386370#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 386369#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 386368#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 386367#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 386366#L798-42 assume 1 == ~t8_pc~0; 386365#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 386363#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 386362#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 386361#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 386360#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 386359#L817-42 assume 1 == ~t9_pc~0; 386357#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 386356#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 386355#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 386354#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 386353#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 386352#L836-42 assume 1 == ~t10_pc~0; 386351#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 386349#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 386348#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 386347#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 386346#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 386345#L855-42 assume 1 == ~t11_pc~0; 386343#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 386342#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 386341#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 386340#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 386339#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 386338#L874-42 assume 1 == ~t12_pc~0; 386337#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 386335#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 386334#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 386333#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 386332#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 386331#L893-42 assume 1 == ~t13_pc~0; 386329#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 386328#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 386327#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 386326#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 386325#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 386324#L912-42 assume !(1 == ~t14_pc~0); 386323#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 386321#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 386320#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 386319#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 386318#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 386317#L1495-3 assume !(1 == ~M_E~0); 386316#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 386315#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 362537#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 386314#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 386313#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 386312#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 379431#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 362524#L1530-3 assume !(1 == ~T8_E~0); 379429#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 379427#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 379425#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 379423#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 379422#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 379420#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 379418#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 379416#L1570-3 assume !(1 == ~E_2~0); 379414#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 379412#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 379410#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 379408#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 379406#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 379404#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 379402#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 366275#L1610-3 assume !(1 == ~E_10~0); 379399#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 379397#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 379395#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 379390#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 379389#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 379386#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 379369#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 379366#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 379364#L2036 assume !(0 == start_simulation_~tmp~3#1); 379362#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 379330#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 379328#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 379325#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 379323#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 379321#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 379319#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 379317#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 326091#L2017-2 [2022-07-13 04:23:47,610 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:47,610 INFO L85 PathProgramCache]: Analyzing trace with hash 1108215503, now seen corresponding path program 1 times [2022-07-13 04:23:47,610 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:47,610 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [286795265] [2022-07-13 04:23:47,610 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:47,610 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:47,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:47,638 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:47,639 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:47,639 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [286795265] [2022-07-13 04:23:47,639 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [286795265] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:47,639 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:47,639 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-13 04:23:47,639 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [253411118] [2022-07-13 04:23:47,639 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:47,640 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-13 04:23:47,640 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:47,640 INFO L85 PathProgramCache]: Analyzing trace with hash 595550122, now seen corresponding path program 1 times [2022-07-13 04:23:47,640 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:47,640 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1996848875] [2022-07-13 04:23:47,640 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:47,641 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:47,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:47,665 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:47,665 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:47,665 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1996848875] [2022-07-13 04:23:47,665 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1996848875] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:47,666 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:47,666 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-13 04:23:47,666 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [810930094] [2022-07-13 04:23:47,666 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:47,666 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-13 04:23:47,667 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-13 04:23:47,667 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-13 04:23:47,667 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-13 04:23:47,667 INFO L87 Difference]: Start difference. First operand 77261 states and 112196 transitions. cyclomatic complexity: 34959 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 2 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:48,365 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-13 04:23:48,367 INFO L93 Difference]: Finished difference Result 148572 states and 215073 transitions. [2022-07-13 04:23:48,368 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-13 04:23:48,369 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 148572 states and 215073 transitions. [2022-07-13 04:23:48,904 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 148072 [2022-07-13 04:23:49,496 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 148572 states to 148572 states and 215073 transitions. [2022-07-13 04:23:49,496 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 148572 [2022-07-13 04:23:49,590 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 148572 [2022-07-13 04:23:49,590 INFO L73 IsDeterministic]: Start isDeterministic. Operand 148572 states and 215073 transitions. [2022-07-13 04:23:49,669 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-13 04:23:49,669 INFO L369 hiAutomatonCegarLoop]: Abstraction has 148572 states and 215073 transitions. [2022-07-13 04:23:49,749 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 148572 states and 215073 transitions. [2022-07-13 04:23:51,238 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 148572 to 148476. [2022-07-13 04:23:51,330 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 148476 states, 148476 states have (on average 1.447890568172634) internal successors, (214977), 148475 states have internal predecessors, (214977), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:51,579 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 148476 states to 148476 states and 214977 transitions. [2022-07-13 04:23:51,579 INFO L392 hiAutomatonCegarLoop]: Abstraction has 148476 states and 214977 transitions. [2022-07-13 04:23:51,579 INFO L374 stractBuchiCegarLoop]: Abstraction has 148476 states and 214977 transitions. [2022-07-13 04:23:51,579 INFO L287 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-07-13 04:23:51,579 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 148476 states and 214977 transitions. [2022-07-13 04:23:51,963 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 147976 [2022-07-13 04:23:51,965 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-13 04:23:51,965 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-13 04:23:51,966 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:51,967 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:51,967 INFO L752 eck$LassoCheckResult]: Stem: 551968#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 551969#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 552618#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 551678#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 551679#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 551933#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 551934#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 551652#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 551653#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 553012#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 552255#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 552256#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 552862#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 552159#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 552160#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 551559#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 551560#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 551898#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 552108#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 551140#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 551141#L1342 assume !(0 == ~M_E~0); 551305#L1342-2 assume !(0 == ~T1_E~0); 551864#L1347-1 assume !(0 == ~T2_E~0); 552992#L1352-1 assume !(0 == ~T3_E~0); 552741#L1357-1 assume !(0 == ~T4_E~0); 551890#L1362-1 assume !(0 == ~T5_E~0); 551891#L1367-1 assume !(0 == ~T6_E~0); 551481#L1372-1 assume !(0 == ~T7_E~0); 551482#L1377-1 assume !(0 == ~T8_E~0); 551816#L1382-1 assume !(0 == ~T9_E~0); 551817#L1387-1 assume !(0 == ~T10_E~0); 552596#L1392-1 assume !(0 == ~T11_E~0); 551850#L1397-1 assume !(0 == ~T12_E~0); 551851#L1402-1 assume !(0 == ~T13_E~0); 551496#L1407-1 assume !(0 == ~T14_E~0); 551497#L1412-1 assume !(0 == ~E_1~0); 552897#L1417-1 assume !(0 == ~E_2~0); 552898#L1422-1 assume !(0 == ~E_3~0); 553225#L1427-1 assume !(0 == ~E_4~0); 551685#L1432-1 assume !(0 == ~E_5~0); 551686#L1437-1 assume !(0 == ~E_6~0); 552798#L1442-1 assume !(0 == ~E_7~0); 552799#L1447-1 assume !(0 == ~E_8~0); 552593#L1452-1 assume !(0 == ~E_9~0); 551275#L1457-1 assume !(0 == ~E_10~0); 551276#L1462-1 assume !(0 == ~E_11~0); 552839#L1467-1 assume !(0 == ~E_12~0); 552856#L1472-1 assume !(0 == ~E_13~0); 552857#L1477-1 assume !(0 == ~E_14~0); 552537#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 551472#L646 assume !(1 == ~m_pc~0); 551473#L646-2 is_master_triggered_~__retres1~0#1 := 0; 552187#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 552188#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 551561#L1666 assume !(0 != activate_threads_~tmp~1#1); 551562#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 553268#L665 assume !(1 == ~t1_pc~0); 552052#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 552053#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 551570#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 551571#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 552397#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 552398#L684 assume !(1 == ~t2_pc~0); 552446#L684-2 is_transmit2_triggered_~__retres1~2#1 := 0; 552447#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 552522#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 552998#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 552999#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 553291#L703 assume !(1 == ~t3_pc~0); 551708#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 551709#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 552390#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 551110#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 551111#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 551591#L722 assume !(1 == ~t4_pc~0); 551776#L722-2 is_transmit4_triggered_~__retres1~4#1 := 0; 551777#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 552138#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 552776#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 552212#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 551306#L741 assume !(1 == ~t5_pc~0); 551307#L741-2 is_transmit5_triggered_~__retres1~5#1 := 0; 552436#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 551774#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 551775#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 552500#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 551865#L760 assume !(1 == ~t6_pc~0); 551707#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 551706#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 551563#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 551564#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 552318#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 552319#L779 assume 1 == ~t7_pc~0; 551349#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 551198#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 551199#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 551602#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 551625#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 551626#L798 assume !(1 == ~t8_pc~0); 553063#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 552954#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 551351#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 551352#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 553270#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 551175#L817 assume 1 == ~t9_pc~0; 551176#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 551978#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 551979#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 552542#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 551576#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 551577#L836 assume !(1 == ~t10_pc~0); 551593#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 551525#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 551526#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 551778#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 551779#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 552970#L855 assume 1 == ~t11_pc~0; 552180#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 552181#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 552833#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 552589#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 552405#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 551466#L874 assume !(1 == ~t12_pc~0); 551467#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 551634#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 551635#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 551780#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 551148#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 551149#L893 assume 1 == ~t13_pc~0; 553153#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 551499#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 551815#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 553057#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 553065#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 553066#L912 assume 1 == ~t14_pc~0; 552805#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 552806#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 551469#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 551401#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 551402#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 552205#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 552659#L1495-2 assume !(1 == ~T1_E~0); 552660#L1500-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 552314#L1505-1 assume !(1 == ~T3_E~0); 552315#L1510-1 assume !(1 == ~T4_E~0); 552375#L1515-1 assume !(1 == ~T5_E~0); 552376#L1520-1 assume !(1 == ~T6_E~0); 553064#L1525-1 assume !(1 == ~T7_E~0); 552696#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 552697#L1535-1 assume !(1 == ~T9_E~0); 553317#L1540-1 assume !(1 == ~T10_E~0); 553318#L1545-1 assume !(1 == ~T11_E~0); 553365#L1550-1 assume !(1 == ~T12_E~0); 553366#L1555-1 assume !(1 == ~T13_E~0); 551613#L1560-1 assume !(1 == ~T14_E~0); 551614#L1565-1 assume !(1 == ~E_1~0); 576134#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 576133#L1575-1 assume !(1 == ~E_3~0); 576132#L1580-1 assume !(1 == ~E_4~0); 576131#L1585-1 assume !(1 == ~E_5~0); 576130#L1590-1 assume !(1 == ~E_6~0); 576129#L1595-1 assume !(1 == ~E_7~0); 576128#L1600-1 assume !(1 == ~E_8~0); 576127#L1605-1 assume !(1 == ~E_9~0); 552327#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 575215#L1615-1 assume !(1 == ~E_11~0); 575216#L1620-1 assume !(1 == ~E_12~0); 575187#L1625-1 assume !(1 == ~E_13~0); 575188#L1630-1 assume !(1 == ~E_14~0); 575136#L1635-1 assume { :end_inline_reset_delta_events } true; 575135#L2017-2 [2022-07-13 04:23:51,967 INFO L754 eck$LassoCheckResult]: Loop: 575135#L2017-2 assume !false; 575115#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 575112#L1316 assume !false; 592526#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 575004#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 574984#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 574976#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 574966#L1115 assume !(0 != eval_~tmp~0#1); 574967#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 596102#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 596100#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 596098#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 596096#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 596093#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 596091#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 596089#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 596087#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 596085#L1372-3 assume !(0 == ~T7_E~0); 596083#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 596080#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 596078#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 596076#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 596074#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 596072#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 596070#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 596067#L1412-3 assume !(0 == ~E_1~0); 593642#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 593640#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 593638#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 593637#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 593636#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 593635#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 593634#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 593633#L1452-3 assume !(0 == ~E_9~0); 593632#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 593631#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 593629#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 593627#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 593625#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 593623#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 593621#L646-42 assume !(1 == ~m_pc~0); 593619#L646-44 is_master_triggered_~__retres1~0#1 := 0; 593617#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 593616#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 593615#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 593613#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 592434#L665-42 assume !(1 == ~t1_pc~0); 592435#L665-44 is_transmit1_triggered_~__retres1~1#1 := 0; 592422#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 592423#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 592416#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 592417#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 579627#L684-42 assume !(1 == ~t2_pc~0); 579628#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 579621#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 579622#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 579600#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 579601#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 579558#L703-42 assume 1 == ~t3_pc~0; 579560#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 579410#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 579411#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 579404#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 579405#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 579398#L722-42 assume !(1 == ~t4_pc~0); 579399#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 579392#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 579393#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 579386#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 579387#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 579380#L741-42 assume !(1 == ~t5_pc~0); 579381#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 579265#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 579266#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 579261#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 579262#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 579256#L760-42 assume !(1 == ~t6_pc~0); 579257#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 579251#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 579252#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 579247#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 579248#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 579242#L779-42 assume 1 == ~t7_pc~0; 579243#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 579234#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 579235#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 579228#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 579229#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 579221#L798-42 assume !(1 == ~t8_pc~0); 579222#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 579213#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 579214#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 579207#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 579208#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 579200#L817-42 assume 1 == ~t9_pc~0; 579201#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 579192#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 579193#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 579186#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 579187#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 579179#L836-42 assume !(1 == ~t10_pc~0); 579180#L836-44 is_transmit10_triggered_~__retres1~10#1 := 0; 579172#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 579173#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 579168#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 579169#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 579163#L855-42 assume 1 == ~t11_pc~0; 579164#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 579158#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 579159#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 579152#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 579153#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 579145#L874-42 assume 1 == ~t12_pc~0; 579146#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 579118#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 579119#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 579112#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 579113#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 579105#L893-42 assume !(1 == ~t13_pc~0); 579106#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 579098#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 579099#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 579091#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 579092#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 579084#L912-42 assume 1 == ~t14_pc~0; 579085#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 579077#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 579078#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 579071#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 579072#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 579065#L1495-3 assume !(1 == ~M_E~0); 579066#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 579060#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 572316#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 579052#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 579053#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 579046#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 579047#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 572304#L1530-3 assume !(1 == ~T8_E~0); 579041#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 579037#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 579038#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 579032#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 579033#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 579026#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 579027#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 579020#L1570-3 assume !(1 == ~E_2~0); 579021#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 579014#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 579015#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 576666#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 576667#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 576628#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 576629#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 576443#L1610-3 assume !(1 == ~E_10~0); 576444#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 576427#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 576428#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 576409#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 576410#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 575549#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 575533#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 575531#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 575528#L2036 assume !(0 == start_simulation_~tmp~3#1); 575524#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 575525#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 592546#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 592545#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 592544#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 592543#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 592542#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 575134#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 575135#L2017-2 [2022-07-13 04:23:51,968 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:51,968 INFO L85 PathProgramCache]: Analyzing trace with hash 1070768814, now seen corresponding path program 1 times [2022-07-13 04:23:51,968 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:51,968 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1182294807] [2022-07-13 04:23:51,968 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:51,968 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:51,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:52,003 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:52,004 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:52,004 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1182294807] [2022-07-13 04:23:52,005 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1182294807] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:52,006 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:52,006 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-13 04:23:52,006 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [189380187] [2022-07-13 04:23:52,006 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:52,007 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-13 04:23:52,007 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:52,007 INFO L85 PathProgramCache]: Analyzing trace with hash -965984856, now seen corresponding path program 1 times [2022-07-13 04:23:52,007 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:52,007 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1798591948] [2022-07-13 04:23:52,007 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:52,008 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:52,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:52,034 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:52,034 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:52,034 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1798591948] [2022-07-13 04:23:52,035 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1798591948] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:52,035 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:52,035 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-13 04:23:52,035 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1575076850] [2022-07-13 04:23:52,035 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:52,035 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-13 04:23:52,036 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-13 04:23:52,036 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-07-13 04:23:52,036 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-07-13 04:23:52,036 INFO L87 Difference]: Start difference. First operand 148476 states and 214977 transitions. cyclomatic complexity: 66549 Second operand has 5 states, 5 states have (on average 34.0) internal successors, (170), 5 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:53,701 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-13 04:23:53,701 INFO L93 Difference]: Finished difference Result 387299 states and 563250 transitions. [2022-07-13 04:23:53,703 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-07-13 04:23:53,703 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 387299 states and 563250 transitions. [2022-07-13 04:23:55,380 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 385984 [2022-07-13 04:23:56,299 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 387299 states to 387299 states and 563250 transitions. [2022-07-13 04:23:56,299 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 387299 [2022-07-13 04:23:56,491 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 387299 [2022-07-13 04:23:56,491 INFO L73 IsDeterministic]: Start isDeterministic. Operand 387299 states and 563250 transitions. [2022-07-13 04:23:56,665 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-13 04:23:56,665 INFO L369 hiAutomatonCegarLoop]: Abstraction has 387299 states and 563250 transitions. [2022-07-13 04:23:56,848 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 387299 states and 563250 transitions. [2022-07-13 04:23:58,886 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 387299 to 152031. [2022-07-13 04:23:58,991 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 152031 states, 152031 states have (on average 1.4374173688260947) internal successors, (218532), 152030 states have internal predecessors, (218532), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:23:59,226 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 152031 states to 152031 states and 218532 transitions. [2022-07-13 04:23:59,226 INFO L392 hiAutomatonCegarLoop]: Abstraction has 152031 states and 218532 transitions. [2022-07-13 04:23:59,226 INFO L374 stractBuchiCegarLoop]: Abstraction has 152031 states and 218532 transitions. [2022-07-13 04:23:59,226 INFO L287 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-07-13 04:23:59,226 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 152031 states and 218532 transitions. [2022-07-13 04:23:59,623 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 151528 [2022-07-13 04:23:59,623 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-13 04:23:59,623 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-13 04:23:59,625 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:59,625 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:23:59,626 INFO L752 eck$LassoCheckResult]: Stem: 1087778#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 1087779#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 1088533#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1087475#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1087476#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 1087740#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1087741#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1087447#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1087448#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1089010#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1088088#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1088089#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1088827#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1087982#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1087983#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1087352#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1087353#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1087703#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1087927#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 1086927#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1086928#L1342 assume !(0 == ~M_E~0); 1087095#L1342-2 assume !(0 == ~T1_E~0); 1087668#L1347-1 assume !(0 == ~T2_E~0); 1088986#L1352-1 assume !(0 == ~T3_E~0); 1088686#L1357-1 assume !(0 == ~T4_E~0); 1087694#L1362-1 assume !(0 == ~T5_E~0); 1087695#L1367-1 assume !(0 == ~T6_E~0); 1087272#L1372-1 assume !(0 == ~T7_E~0); 1087273#L1377-1 assume !(0 == ~T8_E~0); 1087618#L1382-1 assume !(0 == ~T9_E~0); 1087619#L1387-1 assume !(0 == ~T10_E~0); 1088506#L1392-1 assume !(0 == ~T11_E~0); 1087656#L1397-1 assume !(0 == ~T12_E~0); 1087657#L1402-1 assume !(0 == ~T13_E~0); 1087289#L1407-1 assume !(0 == ~T14_E~0); 1087290#L1412-1 assume !(0 == ~E_1~0); 1088864#L1417-1 assume !(0 == ~E_2~0); 1088865#L1422-1 assume !(0 == ~E_3~0); 1089348#L1427-1 assume !(0 == ~E_4~0); 1087482#L1432-1 assume !(0 == ~E_5~0); 1087483#L1437-1 assume !(0 == ~E_6~0); 1088747#L1442-1 assume !(0 == ~E_7~0); 1088748#L1447-1 assume !(0 == ~E_8~0); 1088503#L1452-1 assume !(0 == ~E_9~0); 1087063#L1457-1 assume !(0 == ~E_10~0); 1087064#L1462-1 assume !(0 == ~E_11~0); 1088800#L1467-1 assume !(0 == ~E_12~0); 1088821#L1472-1 assume !(0 == ~E_13~0); 1088822#L1477-1 assume !(0 == ~E_14~0); 1088428#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1087265#L646 assume !(1 == ~m_pc~0); 1087266#L646-2 is_master_triggered_~__retres1~0#1 := 0; 1088013#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1088014#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1087354#L1666 assume !(0 != activate_threads_~tmp~1#1); 1087355#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1089409#L665 assume !(1 == ~t1_pc~0); 1087865#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1087866#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1087363#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1087364#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 1088259#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1088260#L684 assume !(1 == ~t2_pc~0); 1088318#L684-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1088319#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1088411#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1088992#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 1088993#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1089444#L703 assume !(1 == ~t3_pc~0); 1087505#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1087506#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1088248#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1086897#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 1086898#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1087384#L722 assume !(1 == ~t4_pc~0); 1087575#L722-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1087576#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1087962#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1088724#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 1088042#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1087096#L741 assume !(1 == ~t5_pc~0); 1087097#L741-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1088306#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1087573#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1087574#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 1088382#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1087669#L760 assume !(1 == ~t6_pc~0); 1087504#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1088198#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1088562#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1089324#L1714 assume !(0 != activate_threads_~tmp___5~0#1); 1088162#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1088163#L779 assume 1 == ~t7_pc~0; 1087140#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1086985#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1086986#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1087395#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 1087419#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1087420#L798 assume !(1 == ~t8_pc~0); 1089076#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1088942#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1087142#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1087143#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 1089411#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1086962#L817 assume 1 == ~t9_pc~0; 1086963#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1087786#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1087787#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1088436#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 1087369#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1087370#L836 assume !(1 == ~t10_pc~0); 1087386#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1087317#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1087318#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1087577#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 1087578#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1088957#L855 assume 1 == ~t11_pc~0; 1088008#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1088009#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1088795#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1088499#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 1088268#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1087259#L874 assume !(1 == ~t12_pc~0); 1087260#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 1087428#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1087429#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1087579#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 1086935#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1086936#L893 assume 1 == ~t13_pc~0; 1089218#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1087292#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1087617#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1089067#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 1089081#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 1089082#L912 assume 1 == ~t14_pc~0; 1088758#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 1088759#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 1087262#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1087193#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 1087194#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1088033#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 1088578#L1495-2 assume !(1 == ~T1_E~0); 1088579#L1500-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1089338#L1505-1 assume !(1 == ~T3_E~0); 1089522#L1510-1 assume !(1 == ~T4_E~0); 1089523#L1515-1 assume !(1 == ~T5_E~0); 1089391#L1520-1 assume !(1 == ~T6_E~0); 1089392#L1525-1 assume !(1 == ~T7_E~0); 1115650#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1115649#L1535-1 assume !(1 == ~T9_E~0); 1115648#L1540-1 assume !(1 == ~T10_E~0); 1115647#L1545-1 assume !(1 == ~T11_E~0); 1115646#L1550-1 assume !(1 == ~T12_E~0); 1115645#L1555-1 assume !(1 == ~T13_E~0); 1115644#L1560-1 assume !(1 == ~T14_E~0); 1115643#L1565-1 assume !(1 == ~E_1~0); 1115642#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1115641#L1575-1 assume !(1 == ~E_3~0); 1115640#L1580-1 assume !(1 == ~E_4~0); 1115639#L1585-1 assume !(1 == ~E_5~0); 1115638#L1590-1 assume !(1 == ~E_6~0); 1115637#L1595-1 assume !(1 == ~E_7~0); 1115636#L1600-1 assume !(1 == ~E_8~0); 1115635#L1605-1 assume !(1 == ~E_9~0); 1115633#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 1115632#L1615-1 assume !(1 == ~E_11~0); 1115631#L1620-1 assume !(1 == ~E_12~0); 1115628#L1625-1 assume !(1 == ~E_13~0); 1115625#L1630-1 assume !(1 == ~E_14~0); 1115623#L1635-1 assume { :end_inline_reset_delta_events } true; 1115621#L2017-2 [2022-07-13 04:23:59,626 INFO L754 eck$LassoCheckResult]: Loop: 1115621#L2017-2 assume !false; 1115619#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1115615#L1316 assume !false; 1115613#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 1115614#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 1115508#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 1115509#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1115487#L1115 assume !(0 != eval_~tmp~0#1); 1115489#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1147048#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1147047#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1147046#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1147045#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1147044#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1147043#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1147042#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1147041#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1147040#L1372-3 assume !(0 == ~T7_E~0); 1147039#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1147038#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1147037#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1147036#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1147035#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1147034#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 1147033#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 1147032#L1412-3 assume !(0 == ~E_1~0); 1147031#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1147030#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1147029#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1147028#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1147027#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1147026#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1147025#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1147024#L1452-3 assume !(0 == ~E_9~0); 1147023#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1147022#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1147021#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 1147020#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 1147019#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 1147018#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1138931#L646-42 assume !(1 == ~m_pc~0); 1138932#L646-44 is_master_triggered_~__retres1~0#1 := 0; 1138919#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1138920#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1138907#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1138908#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1138893#L665-42 assume 1 == ~t1_pc~0; 1138895#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1138877#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1138878#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1138865#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1138866#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1119845#L684-42 assume !(1 == ~t2_pc~0); 1119846#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 1119841#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1119842#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1119837#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1119838#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1119832#L703-42 assume !(1 == ~t3_pc~0); 1119833#L703-44 is_transmit3_triggered_~__retres1~3#1 := 0; 1119827#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1119828#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1119823#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1119824#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1119819#L722-42 assume !(1 == ~t4_pc~0); 1119820#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 1119815#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1119816#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1119811#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1119812#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1119807#L741-42 assume !(1 == ~t5_pc~0); 1119808#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 1119803#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1119804#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1119799#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1119800#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1119794#L760-42 assume !(1 == ~t6_pc~0); 1119795#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 1119786#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1119787#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1119780#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 1119773#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1119766#L779-42 assume !(1 == ~t7_pc~0); 1119759#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 1119750#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1119642#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1119640#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1119638#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1119635#L798-42 assume 1 == ~t8_pc~0; 1119633#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1119630#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1119628#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1119626#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1119624#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1119621#L817-42 assume !(1 == ~t9_pc~0); 1119619#L817-44 is_transmit9_triggered_~__retres1~9#1 := 0; 1119616#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1119614#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1119612#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1119610#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1119609#L836-42 assume !(1 == ~t10_pc~0); 1119607#L836-44 is_transmit10_triggered_~__retres1~10#1 := 0; 1119606#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1119605#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1119604#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1119599#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1119597#L855-42 assume 1 == ~t11_pc~0; 1119593#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1119590#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1119588#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1119585#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1119583#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1119581#L874-42 assume 1 == ~t12_pc~0; 1119579#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1119576#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1119574#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1119571#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1119569#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1119567#L893-42 assume !(1 == ~t13_pc~0); 1119565#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 1119562#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1119558#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1119555#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 1119553#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 1119551#L912-42 assume !(1 == ~t14_pc~0); 1119549#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 1119546#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 1119544#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1119541#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 1119539#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1119537#L1495-3 assume !(1 == ~M_E~0); 1119535#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1119468#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1119464#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1119462#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1119460#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1119458#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1119456#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1119450#L1530-3 assume !(1 == ~T8_E~0); 1119448#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1119446#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1119444#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1119275#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1119271#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 1119269#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 1119267#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1119265#L1570-3 assume !(1 == ~E_2~0); 1119263#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1119261#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1119259#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1119257#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1119254#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1119252#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1119250#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1119246#L1610-3 assume !(1 == ~E_10~0); 1119244#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1119242#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1119240#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 1119225#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 1119212#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 1116637#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 1116616#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 1116609#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 1116601#L2036 assume !(0 == start_simulation_~tmp~3#1); 1116595#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 1115782#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 1115780#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 1115778#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 1115776#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1115774#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1115772#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 1115622#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 1115621#L2017-2 [2022-07-13 04:23:59,626 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:59,627 INFO L85 PathProgramCache]: Analyzing trace with hash -71733652, now seen corresponding path program 1 times [2022-07-13 04:23:59,627 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:59,627 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1193802574] [2022-07-13 04:23:59,627 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:59,627 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:59,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:59,650 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:59,651 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:59,651 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1193802574] [2022-07-13 04:23:59,651 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1193802574] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:59,651 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:59,651 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-13 04:23:59,651 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [803495103] [2022-07-13 04:23:59,652 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:59,652 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-13 04:23:59,652 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:23:59,652 INFO L85 PathProgramCache]: Analyzing trace with hash 386401766, now seen corresponding path program 1 times [2022-07-13 04:23:59,652 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:23:59,652 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [566053479] [2022-07-13 04:23:59,653 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:23:59,653 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:23:59,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:23:59,673 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:23:59,673 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:23:59,673 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [566053479] [2022-07-13 04:23:59,673 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [566053479] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:23:59,674 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:23:59,674 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-13 04:23:59,674 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1787147321] [2022-07-13 04:23:59,674 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:23:59,674 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-13 04:23:59,674 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-13 04:23:59,675 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-13 04:23:59,675 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-13 04:23:59,675 INFO L87 Difference]: Start difference. First operand 152031 states and 218532 transitions. cyclomatic complexity: 66549 Second operand has 4 states, 4 states have (on average 42.5) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:24:01,302 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-13 04:24:01,302 INFO L93 Difference]: Finished difference Result 391798 states and 560497 transitions. [2022-07-13 04:24:01,303 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-13 04:24:01,303 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 391798 states and 560497 transitions. [2022-07-13 04:24:03,092 INFO L131 ngComponentsAnalysis]: Automaton has 80 accepting balls. 387152 [2022-07-13 04:24:04,413 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 391798 states to 391798 states and 560497 transitions. [2022-07-13 04:24:04,414 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 391798 [2022-07-13 04:24:04,583 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 391798 [2022-07-13 04:24:04,583 INFO L73 IsDeterministic]: Start isDeterministic. Operand 391798 states and 560497 transitions. [2022-07-13 04:24:04,722 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-13 04:24:04,722 INFO L369 hiAutomatonCegarLoop]: Abstraction has 391798 states and 560497 transitions. [2022-07-13 04:24:04,892 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 391798 states and 560497 transitions. [2022-07-13 04:24:08,002 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 391798 to 292054. [2022-07-13 04:24:08,196 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 292054 states, 292054 states have (on average 1.4336287124983735) internal successors, (418697), 292053 states have internal predecessors, (418697), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:24:08,745 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 292054 states to 292054 states and 418697 transitions. [2022-07-13 04:24:08,745 INFO L392 hiAutomatonCegarLoop]: Abstraction has 292054 states and 418697 transitions. [2022-07-13 04:24:08,745 INFO L374 stractBuchiCegarLoop]: Abstraction has 292054 states and 418697 transitions. [2022-07-13 04:24:08,745 INFO L287 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2022-07-13 04:24:08,745 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 292054 states and 418697 transitions. [2022-07-13 04:24:10,003 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 291328 [2022-07-13 04:24:10,004 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-13 04:24:10,004 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-13 04:24:10,007 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:24:10,008 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-13 04:24:10,008 INFO L752 eck$LassoCheckResult]: Stem: 1631585#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 1631586#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 1632221#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1631302#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1631303#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 1631551#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1631552#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1631275#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1631276#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1632577#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1631865#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1631866#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1632428#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1631772#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1631773#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1631182#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1631183#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1631517#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1631722#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 1630766#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1630767#L1342 assume !(0 == ~M_E~0); 1630932#L1342-2 assume !(0 == ~T1_E~0); 1631484#L1347-1 assume !(0 == ~T2_E~0); 1632554#L1352-1 assume !(0 == ~T3_E~0); 1632326#L1357-1 assume !(0 == ~T4_E~0); 1631509#L1362-1 assume !(0 == ~T5_E~0); 1631510#L1367-1 assume !(0 == ~T6_E~0); 1631104#L1372-1 assume !(0 == ~T7_E~0); 1631105#L1377-1 assume !(0 == ~T8_E~0); 1631437#L1382-1 assume !(0 == ~T9_E~0); 1631438#L1387-1 assume !(0 == ~T10_E~0); 1632198#L1392-1 assume !(0 == ~T11_E~0); 1631472#L1397-1 assume !(0 == ~T12_E~0); 1631473#L1402-1 assume !(0 == ~T13_E~0); 1631119#L1407-1 assume !(0 == ~T14_E~0); 1631120#L1412-1 assume !(0 == ~E_1~0); 1632461#L1417-1 assume !(0 == ~E_2~0); 1632462#L1422-1 assume !(0 == ~E_3~0); 1632780#L1427-1 assume !(0 == ~E_4~0); 1631308#L1432-1 assume !(0 == ~E_5~0); 1631309#L1437-1 assume !(0 == ~E_6~0); 1632371#L1442-1 assume !(0 == ~E_7~0); 1632372#L1447-1 assume !(0 == ~E_8~0); 1632195#L1452-1 assume !(0 == ~E_9~0); 1630902#L1457-1 assume !(0 == ~E_10~0); 1630903#L1462-1 assume !(0 == ~E_11~0); 1632410#L1467-1 assume !(0 == ~E_12~0); 1632423#L1472-1 assume !(0 == ~E_13~0); 1632424#L1477-1 assume !(0 == ~E_14~0); 1632137#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1631096#L646 assume !(1 == ~m_pc~0); 1631097#L646-2 is_master_triggered_~__retres1~0#1 := 0; 1631800#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1631801#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1631184#L1666 assume !(0 != activate_threads_~tmp~1#1); 1631185#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1632814#L665 assume !(1 == ~t1_pc~0); 1631668#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1631669#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1631193#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1631194#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 1632004#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1632005#L684 assume !(1 == ~t2_pc~0); 1632047#L684-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1632048#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1632122#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1632560#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 1632561#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1632830#L703 assume !(1 == ~t3_pc~0); 1631330#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1631331#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1631996#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1630736#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 1630737#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1631215#L722 assume !(1 == ~t4_pc~0); 1631397#L722-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1631398#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1631752#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1632355#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 1631825#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1630933#L741 assume !(1 == ~t5_pc~0); 1630934#L741-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1632038#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1631395#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1631396#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 1632100#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1631485#L760 assume !(1 == ~t6_pc~0); 1631329#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1631953#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1632905#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1632767#L1714 assume !(0 != activate_threads_~tmp___5~0#1); 1631924#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1631925#L779 assume !(1 == ~t7_pc~0); 1632624#L779-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1630824#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1630825#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1631226#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 1631249#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1631250#L798 assume !(1 == ~t8_pc~0); 1632617#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1632520#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1630976#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1630977#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 1632816#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1630801#L817 assume 1 == ~t9_pc~0; 1630802#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1631593#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1631594#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1632143#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 1631200#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1631201#L836 assume !(1 == ~t10_pc~0); 1631217#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1631148#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1631149#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1631400#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 1631401#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1632536#L855 assume 1 == ~t11_pc~0; 1631795#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1631796#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1632404#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1632191#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 1632011#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1631090#L874 assume !(1 == ~t12_pc~0); 1631091#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 1631258#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1631259#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1631399#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 1630774#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1630775#L893 assume 1 == ~t13_pc~0; 1632714#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1631122#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1631436#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1632611#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 1632621#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 1632622#L912 assume 1 == ~t14_pc~0; 1632378#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 1632379#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 1631093#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1631026#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 1631027#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1631817#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 1632258#L1495-2 assume !(1 == ~T1_E~0); 1632259#L1500-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1631920#L1505-1 assume !(1 == ~T3_E~0); 1631921#L1510-1 assume !(1 == ~T4_E~0); 1631980#L1515-1 assume !(1 == ~T5_E~0); 1631981#L1520-1 assume !(1 == ~T6_E~0); 1632619#L1525-1 assume !(1 == ~T7_E~0); 1632620#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1631195#L1535-1 assume !(1 == ~T9_E~0); 1631196#L1540-1 assume !(1 == ~T10_E~0); 1630695#L1545-1 assume !(1 == ~T11_E~0); 1630696#L1550-1 assume !(1 == ~T12_E~0); 1630942#L1555-1 assume !(1 == ~T13_E~0); 1630943#L1560-1 assume !(1 == ~T14_E~0); 1632794#L1565-1 assume !(1 == ~E_1~0); 1632795#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1728416#L1575-1 assume !(1 == ~E_3~0); 1631511#L1580-1 assume !(1 == ~E_4~0); 1631512#L1585-1 assume !(1 == ~E_5~0); 1632297#L1590-1 assume !(1 == ~E_6~0); 1631547#L1595-1 assume !(1 == ~E_7~0); 1631548#L1600-1 assume !(1 == ~E_8~0); 1728414#L1605-1 assume !(1 == ~E_9~0); 1722921#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 1728413#L1615-1 assume !(1 == ~E_11~0); 1728412#L1620-1 assume !(1 == ~E_12~0); 1728411#L1625-1 assume !(1 == ~E_13~0); 1728410#L1630-1 assume !(1 == ~E_14~0); 1728409#L1635-1 assume { :end_inline_reset_delta_events } true; 1728406#L2017-2 [2022-07-13 04:24:10,016 INFO L754 eck$LassoCheckResult]: Loop: 1728406#L2017-2 assume !false; 1728259#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1728254#L1316 assume !false; 1728252#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 1717400#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 1717374#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 1717371#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1717372#L1115 assume !(0 != eval_~tmp~0#1); 1724384#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1759762#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1759761#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1759759#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1756048#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1756045#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1756042#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1756039#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1756036#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1756033#L1372-3 assume !(0 == ~T7_E~0); 1756030#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1756027#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1756023#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1756019#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1756016#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1756013#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 1756010#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 1756007#L1412-3 assume !(0 == ~E_1~0); 1755930#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1755927#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1755925#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1755923#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1755922#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1755920#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1755918#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1755916#L1452-3 assume !(0 == ~E_9~0); 1755914#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1755912#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1755909#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 1755707#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 1755258#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 1745318#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1745317#L646-42 assume !(1 == ~m_pc~0); 1745315#L646-44 is_master_triggered_~__retres1~0#1 := 0; 1745314#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1745311#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1745309#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1745307#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1745305#L665-42 assume !(1 == ~t1_pc~0); 1745302#L665-44 is_transmit1_triggered_~__retres1~1#1 := 0; 1745300#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1745297#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1745295#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1745293#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1745291#L684-42 assume !(1 == ~t2_pc~0); 1731498#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 1745288#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1745286#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1745284#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1745282#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1745280#L703-42 assume 1 == ~t3_pc~0; 1745278#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1745275#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1745274#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1745273#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1745271#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1745269#L722-42 assume !(1 == ~t4_pc~0); 1745268#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 1745267#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1745266#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1745265#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1745263#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1745261#L741-42 assume !(1 == ~t5_pc~0); 1745259#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 1745257#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1745255#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1745253#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1745251#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1745249#L760-42 assume 1 == ~t6_pc~0; 1745246#L761-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1745245#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1745242#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1745240#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 1744675#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1744658#L779-42 assume !(1 == ~t7_pc~0); 1686483#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 1744650#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1744648#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1744646#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1744644#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1744642#L798-42 assume !(1 == ~t8_pc~0); 1744639#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 1744636#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1744634#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1744632#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1744630#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1744628#L817-42 assume !(1 == ~t9_pc~0); 1744626#L817-44 is_transmit9_triggered_~__retres1~9#1 := 0; 1744622#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1744620#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1744618#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1744616#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1744614#L836-42 assume 1 == ~t10_pc~0; 1744610#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1744607#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1744605#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1744604#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1744603#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1744595#L855-42 assume !(1 == ~t11_pc~0); 1744590#L855-44 is_transmit11_triggered_~__retres1~11#1 := 0; 1744579#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1744548#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1744407#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1736849#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1729660#L874-42 assume 1 == ~t12_pc~0; 1729654#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1729646#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1729638#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1729628#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1729621#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1729613#L893-42 assume !(1 == ~t13_pc~0); 1729606#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 1729597#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1729589#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1729580#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 1729572#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 1729564#L912-42 assume 1 == ~t14_pc~0; 1729556#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 1729549#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 1729541#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1729532#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 1729525#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1729515#L1495-3 assume !(1 == ~M_E~0); 1729507#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1729500#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1721857#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1728528#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1728524#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1728523#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1728521#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1728517#L1530-3 assume !(1 == ~T8_E~0); 1728515#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1728511#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1728509#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1728507#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1728505#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 1728503#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 1728501#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1726273#L1570-3 assume !(1 == ~E_2~0); 1728498#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1728496#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1728495#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1728493#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1728491#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1728489#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1728487#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1723562#L1610-3 assume !(1 == ~E_10~0); 1728484#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1728482#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1728481#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 1728479#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 1728477#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 1728474#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 1728459#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 1728458#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 1728455#L2036 assume !(0 == start_simulation_~tmp~3#1); 1728452#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 1728425#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 1728424#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 1728422#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 1728420#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1728418#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1728417#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 1728408#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 1728406#L2017-2 [2022-07-13 04:24:10,017 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:24:10,017 INFO L85 PathProgramCache]: Analyzing trace with hash -1348886325, now seen corresponding path program 1 times [2022-07-13 04:24:10,017 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:24:10,017 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1230491053] [2022-07-13 04:24:10,017 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:24:10,018 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:24:10,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:24:10,051 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:24:10,051 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:24:10,051 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1230491053] [2022-07-13 04:24:10,052 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1230491053] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:24:10,052 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:24:10,052 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-13 04:24:10,052 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [289364215] [2022-07-13 04:24:10,052 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:24:10,052 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-13 04:24:10,053 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-13 04:24:10,053 INFO L85 PathProgramCache]: Analyzing trace with hash 966227591, now seen corresponding path program 1 times [2022-07-13 04:24:10,053 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-13 04:24:10,053 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [702230295] [2022-07-13 04:24:10,053 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-13 04:24:10,053 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-13 04:24:10,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-13 04:24:10,076 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-13 04:24:10,076 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-13 04:24:10,076 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [702230295] [2022-07-13 04:24:10,076 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [702230295] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-13 04:24:10,076 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-13 04:24:10,076 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-13 04:24:10,077 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1631238588] [2022-07-13 04:24:10,077 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-13 04:24:10,077 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-13 04:24:10,077 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-13 04:24:10,077 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-13 04:24:10,077 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-13 04:24:10,078 INFO L87 Difference]: Start difference. First operand 292054 states and 418697 transitions. cyclomatic complexity: 126691 Second operand has 4 states, 4 states have (on average 42.5) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-13 04:24:12,726 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-13 04:24:12,728 INFO L93 Difference]: Finished difference Result 749685 states and 1069942 transitions. [2022-07-13 04:24:12,728 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-13 04:24:12,729 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 749685 states and 1069942 transitions. [2022-07-13 04:24:16,352 INFO L131 ngComponentsAnalysis]: Automaton has 80 accepting balls. 740704