./Ultimate.py --spec ../sv-benchmarks/c/properties/valid-memsafety.prp --file ../sv-benchmarks/c/memsafety-ext/skiplist_3lvl.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for memory safety (deref-memtrack) Using default analysis Version 6c24879c Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerMemDerefMemtrack.xml -i ../sv-benchmarks/c/memsafety-ext/skiplist_3lvl.i -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-DerefFreeMemtrack-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash a92c386f0a3e93e7f4997075243ca49a5a9660dc1b84c645c53a036868e1508d --- Real Ultimate output --- This is Ultimate 0.2.2-?-6c24879 [2022-07-12 18:39:38,435 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-07-12 18:39:38,436 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-07-12 18:39:38,459 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-07-12 18:39:38,460 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-07-12 18:39:38,460 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-07-12 18:39:38,461 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-07-12 18:39:38,463 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-07-12 18:39:38,464 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-07-12 18:39:38,464 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-07-12 18:39:38,465 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-07-12 18:39:38,466 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-07-12 18:39:38,466 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-07-12 18:39:38,467 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-07-12 18:39:38,468 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-07-12 18:39:38,469 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-07-12 18:39:38,469 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-07-12 18:39:38,470 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-07-12 18:39:38,472 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-07-12 18:39:38,474 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-07-12 18:39:38,475 INFO L181 SettingsManager]: Resetting HornVerifier preferences to default values [2022-07-12 18:39:38,476 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-07-12 18:39:38,477 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-07-12 18:39:38,478 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-07-12 18:39:38,478 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-07-12 18:39:38,482 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-07-12 18:39:38,487 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-07-12 18:39:38,487 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-07-12 18:39:38,488 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-07-12 18:39:38,488 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-07-12 18:39:38,489 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-07-12 18:39:38,489 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-07-12 18:39:38,490 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-07-12 18:39:38,490 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-07-12 18:39:38,491 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-07-12 18:39:38,492 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-07-12 18:39:38,495 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-07-12 18:39:38,495 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-07-12 18:39:38,496 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-07-12 18:39:38,496 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-07-12 18:39:38,496 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-07-12 18:39:38,498 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-07-12 18:39:38,498 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-DerefFreeMemtrack-32bit-Automizer_Default.epf [2022-07-12 18:39:38,514 INFO L113 SettingsManager]: Loading preferences was successful [2022-07-12 18:39:38,514 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-07-12 18:39:38,515 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-07-12 18:39:38,515 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-07-12 18:39:38,516 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-07-12 18:39:38,516 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-07-12 18:39:38,517 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-07-12 18:39:38,517 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-07-12 18:39:38,517 INFO L138 SettingsManager]: * Use SBE=true [2022-07-12 18:39:38,517 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-07-12 18:39:38,517 INFO L138 SettingsManager]: * sizeof long=4 [2022-07-12 18:39:38,517 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-07-12 18:39:38,517 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-07-12 18:39:38,518 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-07-12 18:39:38,518 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-07-12 18:39:38,518 INFO L138 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2022-07-12 18:39:38,518 INFO L138 SettingsManager]: * Bitprecise bitfields=true [2022-07-12 18:39:38,518 INFO L138 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2022-07-12 18:39:38,518 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-07-12 18:39:38,518 INFO L138 SettingsManager]: * Adapt memory model on pointer casts if necessary=true [2022-07-12 18:39:38,518 INFO L138 SettingsManager]: * sizeof long double=12 [2022-07-12 18:39:38,519 INFO L138 SettingsManager]: * Use constant arrays=true [2022-07-12 18:39:38,519 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-07-12 18:39:38,519 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-07-12 18:39:38,523 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-07-12 18:39:38,523 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-07-12 18:39:38,523 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-07-12 18:39:38,524 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-07-12 18:39:38,524 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-07-12 18:39:38,524 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-07-12 18:39:38,524 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G valid-free) ) CHECK( init(main()), LTL(G valid-deref) ) CHECK( init(main()), LTL(G valid-memtrack) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> a92c386f0a3e93e7f4997075243ca49a5a9660dc1b84c645c53a036868e1508d [2022-07-12 18:39:38,732 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-07-12 18:39:38,750 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-07-12 18:39:38,752 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-07-12 18:39:38,753 INFO L271 PluginConnector]: Initializing CDTParser... [2022-07-12 18:39:38,754 INFO L275 PluginConnector]: CDTParser initialized [2022-07-12 18:39:38,755 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/memsafety-ext/skiplist_3lvl.i [2022-07-12 18:39:38,805 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/197a2a1d0/c1860d973e6d49a089c3eadb3f089bac/FLAG1d1979015 [2022-07-12 18:39:39,202 INFO L306 CDTParser]: Found 1 translation units. [2022-07-12 18:39:39,206 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/memsafety-ext/skiplist_3lvl.i [2022-07-12 18:39:39,220 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/197a2a1d0/c1860d973e6d49a089c3eadb3f089bac/FLAG1d1979015 [2022-07-12 18:39:39,231 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/197a2a1d0/c1860d973e6d49a089c3eadb3f089bac [2022-07-12 18:39:39,233 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-07-12 18:39:39,234 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-07-12 18:39:39,236 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-07-12 18:39:39,236 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-07-12 18:39:39,238 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-07-12 18:39:39,239 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.07 06:39:39" (1/1) ... [2022-07-12 18:39:39,240 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@184e89de and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.07 06:39:39, skipping insertion in model container [2022-07-12 18:39:39,240 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.07 06:39:39" (1/1) ... [2022-07-12 18:39:39,245 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-07-12 18:39:39,276 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-07-12 18:39:39,494 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-12 18:39:39,501 INFO L203 MainTranslator]: Completed pre-run [2022-07-12 18:39:39,529 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-12 18:39:39,549 INFO L208 MainTranslator]: Completed translation [2022-07-12 18:39:39,550 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.07 06:39:39 WrapperNode [2022-07-12 18:39:39,550 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-07-12 18:39:39,550 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-07-12 18:39:39,551 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-07-12 18:39:39,551 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-07-12 18:39:39,555 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.07 06:39:39" (1/1) ... [2022-07-12 18:39:39,564 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.07 06:39:39" (1/1) ... [2022-07-12 18:39:39,581 INFO L137 Inliner]: procedures = 127, calls = 55, calls flagged for inlining = 5, calls inlined = 5, statements flattened = 175 [2022-07-12 18:39:39,585 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-07-12 18:39:39,586 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-07-12 18:39:39,586 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-07-12 18:39:39,586 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-07-12 18:39:39,592 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.07 06:39:39" (1/1) ... [2022-07-12 18:39:39,592 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.07 06:39:39" (1/1) ... [2022-07-12 18:39:39,604 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.07 06:39:39" (1/1) ... [2022-07-12 18:39:39,605 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.07 06:39:39" (1/1) ... [2022-07-12 18:39:39,624 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.07 06:39:39" (1/1) ... [2022-07-12 18:39:39,635 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.07 06:39:39" (1/1) ... [2022-07-12 18:39:39,636 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.07 06:39:39" (1/1) ... [2022-07-12 18:39:39,638 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-07-12 18:39:39,639 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-07-12 18:39:39,639 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-07-12 18:39:39,639 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-07-12 18:39:39,640 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.07 06:39:39" (1/1) ... [2022-07-12 18:39:39,648 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-07-12 18:39:39,657 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-12 18:39:39,666 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-07-12 18:39:39,671 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-07-12 18:39:39,698 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2022-07-12 18:39:39,698 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-07-12 18:39:39,700 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2022-07-12 18:39:39,700 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2022-07-12 18:39:39,700 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-07-12 18:39:39,700 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-07-12 18:39:39,701 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-07-12 18:39:39,701 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-07-12 18:39:39,822 INFO L234 CfgBuilder]: Building ICFG [2022-07-12 18:39:39,823 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-07-12 18:39:40,158 INFO L275 CfgBuilder]: Performing block encoding [2022-07-12 18:39:40,165 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-07-12 18:39:40,166 INFO L299 CfgBuilder]: Removed 5 assume(true) statements. [2022-07-12 18:39:40,168 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.07 06:39:40 BoogieIcfgContainer [2022-07-12 18:39:40,168 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-07-12 18:39:40,170 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-07-12 18:39:40,170 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-07-12 18:39:40,172 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-07-12 18:39:40,172 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 12.07 06:39:39" (1/3) ... [2022-07-12 18:39:40,173 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@38a7b793 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 12.07 06:39:40, skipping insertion in model container [2022-07-12 18:39:40,173 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.07 06:39:39" (2/3) ... [2022-07-12 18:39:40,173 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@38a7b793 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 12.07 06:39:40, skipping insertion in model container [2022-07-12 18:39:40,174 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.07 06:39:40" (3/3) ... [2022-07-12 18:39:40,175 INFO L111 eAbstractionObserver]: Analyzing ICFG skiplist_3lvl.i [2022-07-12 18:39:40,184 INFO L201 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-07-12 18:39:40,184 INFO L160 ceAbstractionStarter]: Applying trace abstraction to program that has 85 error locations. [2022-07-12 18:39:40,220 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-07-12 18:39:40,225 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=false, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=All, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings@2ad34ca3, mLbeIndependenceSettings=de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings@482b457a [2022-07-12 18:39:40,225 INFO L358 AbstractCegarLoop]: Starting to check reachability of 85 error locations. [2022-07-12 18:39:40,228 INFO L276 IsEmpty]: Start isEmpty. Operand has 171 states, 85 states have (on average 2.176470588235294) internal successors, (185), 170 states have internal predecessors, (185), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:40,233 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2022-07-12 18:39:40,233 INFO L187 NwaCegarLoop]: Found error trace [2022-07-12 18:39:40,233 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1] [2022-07-12 18:39:40,234 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 82 more)] === [2022-07-12 18:39:40,237 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-12 18:39:40,237 INFO L85 PathProgramCache]: Analyzing trace with hash 29857, now seen corresponding path program 1 times [2022-07-12 18:39:40,243 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-12 18:39:40,244 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1319682735] [2022-07-12 18:39:40,244 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-12 18:39:40,245 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-12 18:39:40,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-12 18:39:40,368 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-12 18:39:40,369 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-12 18:39:40,369 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1319682735] [2022-07-12 18:39:40,369 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1319682735] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-12 18:39:40,370 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-12 18:39:40,370 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-12 18:39:40,371 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1639301893] [2022-07-12 18:39:40,371 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-12 18:39:40,374 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-07-12 18:39:40,375 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-12 18:39:40,399 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-12 18:39:40,400 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-12 18:39:40,402 INFO L87 Difference]: Start difference. First operand has 171 states, 85 states have (on average 2.176470588235294) internal successors, (185), 170 states have internal predecessors, (185), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 2 states have (on average 1.5) internal successors, (3), 3 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:40,589 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-12 18:39:40,589 INFO L93 Difference]: Finished difference Result 192 states and 202 transitions. [2022-07-12 18:39:40,590 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-12 18:39:40,591 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 2 states have (on average 1.5) internal successors, (3), 3 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 3 [2022-07-12 18:39:40,591 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-07-12 18:39:40,597 INFO L225 Difference]: With dead ends: 192 [2022-07-12 18:39:40,597 INFO L226 Difference]: Without dead ends: 190 [2022-07-12 18:39:40,601 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-12 18:39:40,603 INFO L413 NwaCegarLoop]: 86 mSDtfsCounter, 161 mSDsluCounter, 19 mSDsCounter, 0 mSdLazyCounter, 102 mSolverCounterSat, 10 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 161 SdHoareTripleChecker+Valid, 105 SdHoareTripleChecker+Invalid, 112 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 10 IncrementalHoareTripleChecker+Valid, 102 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-07-12 18:39:40,604 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [161 Valid, 105 Invalid, 112 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [10 Valid, 102 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-07-12 18:39:40,615 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 190 states. [2022-07-12 18:39:40,631 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 190 to 160. [2022-07-12 18:39:40,632 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 160 states, 84 states have (on average 2.011904761904762) internal successors, (169), 159 states have internal predecessors, (169), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:40,634 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 160 states to 160 states and 169 transitions. [2022-07-12 18:39:40,635 INFO L78 Accepts]: Start accepts. Automaton has 160 states and 169 transitions. Word has length 3 [2022-07-12 18:39:40,635 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-07-12 18:39:40,635 INFO L495 AbstractCegarLoop]: Abstraction has 160 states and 169 transitions. [2022-07-12 18:39:40,635 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 2 states have (on average 1.5) internal successors, (3), 3 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:40,635 INFO L276 IsEmpty]: Start isEmpty. Operand 160 states and 169 transitions. [2022-07-12 18:39:40,636 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2022-07-12 18:39:40,636 INFO L187 NwaCegarLoop]: Found error trace [2022-07-12 18:39:40,636 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1] [2022-07-12 18:39:40,636 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-07-12 18:39:40,636 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr1REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 82 more)] === [2022-07-12 18:39:40,637 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-12 18:39:40,637 INFO L85 PathProgramCache]: Analyzing trace with hash 29858, now seen corresponding path program 1 times [2022-07-12 18:39:40,637 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-12 18:39:40,637 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1716206930] [2022-07-12 18:39:40,637 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-12 18:39:40,638 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-12 18:39:40,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-12 18:39:40,673 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-12 18:39:40,673 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-12 18:39:40,674 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1716206930] [2022-07-12 18:39:40,674 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1716206930] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-12 18:39:40,675 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-12 18:39:40,675 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-12 18:39:40,675 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [184728995] [2022-07-12 18:39:40,675 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-12 18:39:40,677 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-07-12 18:39:40,677 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-12 18:39:40,677 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-12 18:39:40,678 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-12 18:39:40,678 INFO L87 Difference]: Start difference. First operand 160 states and 169 transitions. Second operand has 3 states, 2 states have (on average 1.5) internal successors, (3), 3 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:40,777 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-12 18:39:40,778 INFO L93 Difference]: Finished difference Result 159 states and 168 transitions. [2022-07-12 18:39:40,778 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-12 18:39:40,778 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 2 states have (on average 1.5) internal successors, (3), 3 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 3 [2022-07-12 18:39:40,778 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-07-12 18:39:40,781 INFO L225 Difference]: With dead ends: 159 [2022-07-12 18:39:40,781 INFO L226 Difference]: Without dead ends: 159 [2022-07-12 18:39:40,782 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-12 18:39:40,782 INFO L413 NwaCegarLoop]: 166 mSDtfsCounter, 1 mSDsluCounter, 86 mSDsCounter, 0 mSdLazyCounter, 82 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 252 SdHoareTripleChecker+Invalid, 82 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 82 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-07-12 18:39:40,783 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 252 Invalid, 82 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 82 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-07-12 18:39:40,784 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 159 states. [2022-07-12 18:39:40,787 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 159 to 159. [2022-07-12 18:39:40,787 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 159 states, 84 states have (on average 2.0) internal successors, (168), 158 states have internal predecessors, (168), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:40,788 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 159 states to 159 states and 168 transitions. [2022-07-12 18:39:40,789 INFO L78 Accepts]: Start accepts. Automaton has 159 states and 168 transitions. Word has length 3 [2022-07-12 18:39:40,789 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-07-12 18:39:40,789 INFO L495 AbstractCegarLoop]: Abstraction has 159 states and 168 transitions. [2022-07-12 18:39:40,789 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 2 states have (on average 1.5) internal successors, (3), 3 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:40,789 INFO L276 IsEmpty]: Start isEmpty. Operand 159 states and 168 transitions. [2022-07-12 18:39:40,790 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2022-07-12 18:39:40,790 INFO L187 NwaCegarLoop]: Found error trace [2022-07-12 18:39:40,790 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2022-07-12 18:39:40,790 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2022-07-12 18:39:40,791 INFO L420 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr3REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 82 more)] === [2022-07-12 18:39:40,791 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-12 18:39:40,791 INFO L85 PathProgramCache]: Analyzing trace with hash 28691811, now seen corresponding path program 1 times [2022-07-12 18:39:40,791 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-12 18:39:40,792 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [186804104] [2022-07-12 18:39:40,792 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-12 18:39:40,792 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-12 18:39:40,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-12 18:39:40,858 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-12 18:39:40,862 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-12 18:39:40,862 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [186804104] [2022-07-12 18:39:40,863 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [186804104] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-12 18:39:40,863 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-12 18:39:40,863 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-07-12 18:39:40,864 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2058499393] [2022-07-12 18:39:40,864 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-12 18:39:40,864 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-07-12 18:39:40,864 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-12 18:39:40,865 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-07-12 18:39:40,865 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-07-12 18:39:40,865 INFO L87 Difference]: Start difference. First operand 159 states and 168 transitions. Second operand has 5 states, 4 states have (on average 1.25) internal successors, (5), 5 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:41,068 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-12 18:39:41,068 INFO L93 Difference]: Finished difference Result 181 states and 191 transitions. [2022-07-12 18:39:41,069 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-07-12 18:39:41,069 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 4 states have (on average 1.25) internal successors, (5), 5 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 5 [2022-07-12 18:39:41,069 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-07-12 18:39:41,071 INFO L225 Difference]: With dead ends: 181 [2022-07-12 18:39:41,071 INFO L226 Difference]: Without dead ends: 181 [2022-07-12 18:39:41,071 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=14, Invalid=16, Unknown=0, NotChecked=0, Total=30 [2022-07-12 18:39:41,076 INFO L413 NwaCegarLoop]: 54 mSDtfsCounter, 185 mSDsluCounter, 65 mSDsCounter, 0 mSdLazyCounter, 234 mSolverCounterSat, 12 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 185 SdHoareTripleChecker+Valid, 119 SdHoareTripleChecker+Invalid, 246 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 12 IncrementalHoareTripleChecker+Valid, 234 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-07-12 18:39:41,077 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [185 Valid, 119 Invalid, 246 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [12 Valid, 234 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-07-12 18:39:41,079 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 181 states. [2022-07-12 18:39:41,086 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 181 to 151. [2022-07-12 18:39:41,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 151 states, 84 states have (on average 1.9047619047619047) internal successors, (160), 150 states have internal predecessors, (160), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:41,092 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 151 states to 151 states and 160 transitions. [2022-07-12 18:39:41,094 INFO L78 Accepts]: Start accepts. Automaton has 151 states and 160 transitions. Word has length 5 [2022-07-12 18:39:41,095 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-07-12 18:39:41,095 INFO L495 AbstractCegarLoop]: Abstraction has 151 states and 160 transitions. [2022-07-12 18:39:41,095 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 4 states have (on average 1.25) internal successors, (5), 5 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:41,095 INFO L276 IsEmpty]: Start isEmpty. Operand 151 states and 160 transitions. [2022-07-12 18:39:41,096 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2022-07-12 18:39:41,096 INFO L187 NwaCegarLoop]: Found error trace [2022-07-12 18:39:41,096 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-12 18:39:41,096 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2 [2022-07-12 18:39:41,096 INFO L420 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr12REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 82 more)] === [2022-07-12 18:39:41,097 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-12 18:39:41,101 INFO L85 PathProgramCache]: Analyzing trace with hash -1604937495, now seen corresponding path program 1 times [2022-07-12 18:39:41,101 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-12 18:39:41,102 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [729469435] [2022-07-12 18:39:41,102 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-12 18:39:41,102 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-12 18:39:41,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-12 18:39:41,153 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-12 18:39:41,154 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-12 18:39:41,154 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [729469435] [2022-07-12 18:39:41,154 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [729469435] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-12 18:39:41,154 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-12 18:39:41,154 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-07-12 18:39:41,154 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [405306629] [2022-07-12 18:39:41,154 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-12 18:39:41,155 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-07-12 18:39:41,155 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-12 18:39:41,155 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-07-12 18:39:41,155 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-07-12 18:39:41,155 INFO L87 Difference]: Start difference. First operand 151 states and 160 transitions. Second operand has 5 states, 4 states have (on average 2.75) internal successors, (11), 5 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:41,282 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-12 18:39:41,282 INFO L93 Difference]: Finished difference Result 150 states and 159 transitions. [2022-07-12 18:39:41,282 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-07-12 18:39:41,283 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 4 states have (on average 2.75) internal successors, (11), 5 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 11 [2022-07-12 18:39:41,283 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-07-12 18:39:41,283 INFO L225 Difference]: With dead ends: 150 [2022-07-12 18:39:41,283 INFO L226 Difference]: Without dead ends: 150 [2022-07-12 18:39:41,284 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2022-07-12 18:39:41,284 INFO L413 NwaCegarLoop]: 146 mSDtfsCounter, 11 mSDsluCounter, 238 mSDsCounter, 0 mSdLazyCounter, 231 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 11 SdHoareTripleChecker+Valid, 384 SdHoareTripleChecker+Invalid, 232 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 231 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-07-12 18:39:41,285 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [11 Valid, 384 Invalid, 232 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 231 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-07-12 18:39:41,285 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 150 states. [2022-07-12 18:39:41,288 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 150 to 150. [2022-07-12 18:39:41,288 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 150 states, 84 states have (on average 1.8928571428571428) internal successors, (159), 149 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:41,289 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 150 states to 150 states and 159 transitions. [2022-07-12 18:39:41,289 INFO L78 Accepts]: Start accepts. Automaton has 150 states and 159 transitions. Word has length 11 [2022-07-12 18:39:41,289 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-07-12 18:39:41,289 INFO L495 AbstractCegarLoop]: Abstraction has 150 states and 159 transitions. [2022-07-12 18:39:41,289 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 4 states have (on average 2.75) internal successors, (11), 5 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:41,289 INFO L276 IsEmpty]: Start isEmpty. Operand 150 states and 159 transitions. [2022-07-12 18:39:41,290 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2022-07-12 18:39:41,290 INFO L187 NwaCegarLoop]: Found error trace [2022-07-12 18:39:41,290 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-12 18:39:41,290 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3 [2022-07-12 18:39:41,290 INFO L420 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr13REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 82 more)] === [2022-07-12 18:39:41,291 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-12 18:39:41,291 INFO L85 PathProgramCache]: Analyzing trace with hash -1604937494, now seen corresponding path program 1 times [2022-07-12 18:39:41,291 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-12 18:39:41,291 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1802589950] [2022-07-12 18:39:41,291 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-12 18:39:41,291 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-12 18:39:41,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-12 18:39:41,370 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-12 18:39:41,371 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-12 18:39:41,371 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1802589950] [2022-07-12 18:39:41,371 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1802589950] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-12 18:39:41,371 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-12 18:39:41,371 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-12 18:39:41,371 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [946383762] [2022-07-12 18:39:41,371 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-12 18:39:41,372 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-07-12 18:39:41,372 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-12 18:39:41,372 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-07-12 18:39:41,372 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2022-07-12 18:39:41,372 INFO L87 Difference]: Start difference. First operand 150 states and 159 transitions. Second operand has 6 states, 5 states have (on average 2.2) internal successors, (11), 6 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:41,543 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-12 18:39:41,543 INFO L93 Difference]: Finished difference Result 149 states and 158 transitions. [2022-07-12 18:39:41,543 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-07-12 18:39:41,544 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 2.2) internal successors, (11), 6 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 11 [2022-07-12 18:39:41,544 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-07-12 18:39:41,544 INFO L225 Difference]: With dead ends: 149 [2022-07-12 18:39:41,544 INFO L226 Difference]: Without dead ends: 149 [2022-07-12 18:39:41,544 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2022-07-12 18:39:41,545 INFO L413 NwaCegarLoop]: 146 mSDtfsCounter, 14 mSDsluCounter, 219 mSDsCounter, 0 mSdLazyCounter, 248 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 14 SdHoareTripleChecker+Valid, 365 SdHoareTripleChecker+Invalid, 252 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 248 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-07-12 18:39:41,545 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [14 Valid, 365 Invalid, 252 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 248 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-07-12 18:39:41,546 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 149 states. [2022-07-12 18:39:41,548 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 149 to 149. [2022-07-12 18:39:41,548 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 149 states, 84 states have (on average 1.880952380952381) internal successors, (158), 148 states have internal predecessors, (158), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:41,549 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149 states to 149 states and 158 transitions. [2022-07-12 18:39:41,549 INFO L78 Accepts]: Start accepts. Automaton has 149 states and 158 transitions. Word has length 11 [2022-07-12 18:39:41,549 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-07-12 18:39:41,549 INFO L495 AbstractCegarLoop]: Abstraction has 149 states and 158 transitions. [2022-07-12 18:39:41,549 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 2.2) internal successors, (11), 6 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:41,549 INFO L276 IsEmpty]: Start isEmpty. Operand 149 states and 158 transitions. [2022-07-12 18:39:41,550 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2022-07-12 18:39:41,550 INFO L187 NwaCegarLoop]: Found error trace [2022-07-12 18:39:41,550 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-12 18:39:41,550 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4 [2022-07-12 18:39:41,550 INFO L420 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr14REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 82 more)] === [2022-07-12 18:39:41,551 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-12 18:39:41,551 INFO L85 PathProgramCache]: Analyzing trace with hash 1786545203, now seen corresponding path program 1 times [2022-07-12 18:39:41,551 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-12 18:39:41,551 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [912630466] [2022-07-12 18:39:41,551 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-12 18:39:41,551 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-12 18:39:41,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-12 18:39:41,613 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-12 18:39:41,614 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-12 18:39:41,614 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [912630466] [2022-07-12 18:39:41,614 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [912630466] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-12 18:39:41,614 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-12 18:39:41,614 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-07-12 18:39:41,614 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1589309478] [2022-07-12 18:39:41,614 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-12 18:39:41,614 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-07-12 18:39:41,614 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-12 18:39:41,615 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-07-12 18:39:41,615 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-07-12 18:39:41,615 INFO L87 Difference]: Start difference. First operand 149 states and 158 transitions. Second operand has 5 states, 4 states have (on average 3.0) internal successors, (12), 5 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:41,703 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-12 18:39:41,703 INFO L93 Difference]: Finished difference Result 148 states and 157 transitions. [2022-07-12 18:39:41,704 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-07-12 18:39:41,704 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 4 states have (on average 3.0) internal successors, (12), 5 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 12 [2022-07-12 18:39:41,704 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-07-12 18:39:41,704 INFO L225 Difference]: With dead ends: 148 [2022-07-12 18:39:41,705 INFO L226 Difference]: Without dead ends: 148 [2022-07-12 18:39:41,705 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2022-07-12 18:39:41,705 INFO L413 NwaCegarLoop]: 150 mSDtfsCounter, 12 mSDsluCounter, 337 mSDsCounter, 0 mSdLazyCounter, 124 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 12 SdHoareTripleChecker+Valid, 487 SdHoareTripleChecker+Invalid, 125 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 124 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-07-12 18:39:41,706 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [12 Valid, 487 Invalid, 125 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 124 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-07-12 18:39:41,706 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 148 states. [2022-07-12 18:39:41,708 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 148 to 148. [2022-07-12 18:39:41,708 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 148 states, 84 states have (on average 1.869047619047619) internal successors, (157), 147 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:41,709 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 148 states to 148 states and 157 transitions. [2022-07-12 18:39:41,709 INFO L78 Accepts]: Start accepts. Automaton has 148 states and 157 transitions. Word has length 12 [2022-07-12 18:39:41,709 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-07-12 18:39:41,709 INFO L495 AbstractCegarLoop]: Abstraction has 148 states and 157 transitions. [2022-07-12 18:39:41,709 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 4 states have (on average 3.0) internal successors, (12), 5 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:41,709 INFO L276 IsEmpty]: Start isEmpty. Operand 148 states and 157 transitions. [2022-07-12 18:39:41,709 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2022-07-12 18:39:41,710 INFO L187 NwaCegarLoop]: Found error trace [2022-07-12 18:39:41,710 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-12 18:39:41,710 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5 [2022-07-12 18:39:41,710 INFO L420 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr15REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 82 more)] === [2022-07-12 18:39:41,710 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-12 18:39:41,710 INFO L85 PathProgramCache]: Analyzing trace with hash 1786545204, now seen corresponding path program 1 times [2022-07-12 18:39:41,711 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-12 18:39:41,711 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [379587083] [2022-07-12 18:39:41,711 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-12 18:39:41,711 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-12 18:39:41,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-12 18:39:41,846 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-12 18:39:41,846 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-12 18:39:41,847 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [379587083] [2022-07-12 18:39:41,847 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [379587083] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-12 18:39:41,847 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-12 18:39:41,847 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2022-07-12 18:39:41,847 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1902017587] [2022-07-12 18:39:41,847 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-12 18:39:41,848 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-07-12 18:39:41,848 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-12 18:39:41,848 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-07-12 18:39:41,848 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2022-07-12 18:39:41,848 INFO L87 Difference]: Start difference. First operand 148 states and 157 transitions. Second operand has 7 states, 6 states have (on average 2.0) internal successors, (12), 7 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:42,018 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-12 18:39:42,018 INFO L93 Difference]: Finished difference Result 147 states and 156 transitions. [2022-07-12 18:39:42,019 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-07-12 18:39:42,019 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 6 states have (on average 2.0) internal successors, (12), 7 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 12 [2022-07-12 18:39:42,019 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-07-12 18:39:42,019 INFO L225 Difference]: With dead ends: 147 [2022-07-12 18:39:42,019 INFO L226 Difference]: Without dead ends: 147 [2022-07-12 18:39:42,020 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=29, Invalid=61, Unknown=0, NotChecked=0, Total=90 [2022-07-12 18:39:42,020 INFO L413 NwaCegarLoop]: 145 mSDtfsCounter, 12 mSDsluCounter, 335 mSDsCounter, 0 mSdLazyCounter, 280 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 12 SdHoareTripleChecker+Valid, 480 SdHoareTripleChecker+Invalid, 282 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 280 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-07-12 18:39:42,021 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [12 Valid, 480 Invalid, 282 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 280 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-07-12 18:39:42,021 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 147 states. [2022-07-12 18:39:42,022 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 147 to 147. [2022-07-12 18:39:42,023 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 147 states, 84 states have (on average 1.8571428571428572) internal successors, (156), 146 states have internal predecessors, (156), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:42,023 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 147 states to 147 states and 156 transitions. [2022-07-12 18:39:42,023 INFO L78 Accepts]: Start accepts. Automaton has 147 states and 156 transitions. Word has length 12 [2022-07-12 18:39:42,023 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-07-12 18:39:42,024 INFO L495 AbstractCegarLoop]: Abstraction has 147 states and 156 transitions. [2022-07-12 18:39:42,024 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 6 states have (on average 2.0) internal successors, (12), 7 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:42,024 INFO L276 IsEmpty]: Start isEmpty. Operand 147 states and 156 transitions. [2022-07-12 18:39:42,024 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2022-07-12 18:39:42,024 INFO L187 NwaCegarLoop]: Found error trace [2022-07-12 18:39:42,024 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-12 18:39:42,024 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6 [2022-07-12 18:39:42,025 INFO L420 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr16REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 82 more)] === [2022-07-12 18:39:42,025 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-12 18:39:42,025 INFO L85 PathProgramCache]: Analyzing trace with hash -451673556, now seen corresponding path program 1 times [2022-07-12 18:39:42,025 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-12 18:39:42,025 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [545274080] [2022-07-12 18:39:42,025 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-12 18:39:42,026 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-12 18:39:42,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-12 18:39:42,071 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-12 18:39:42,071 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-12 18:39:42,071 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [545274080] [2022-07-12 18:39:42,072 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [545274080] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-12 18:39:42,072 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-12 18:39:42,072 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-07-12 18:39:42,072 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [286620509] [2022-07-12 18:39:42,072 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-12 18:39:42,072 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-07-12 18:39:42,073 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-12 18:39:42,073 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-07-12 18:39:42,073 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-07-12 18:39:42,073 INFO L87 Difference]: Start difference. First operand 147 states and 156 transitions. Second operand has 5 states, 4 states have (on average 3.25) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:42,165 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-12 18:39:42,165 INFO L93 Difference]: Finished difference Result 146 states and 155 transitions. [2022-07-12 18:39:42,165 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-07-12 18:39:42,165 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 4 states have (on average 3.25) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 13 [2022-07-12 18:39:42,166 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-07-12 18:39:42,166 INFO L225 Difference]: With dead ends: 146 [2022-07-12 18:39:42,166 INFO L226 Difference]: Without dead ends: 146 [2022-07-12 18:39:42,166 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2022-07-12 18:39:42,167 INFO L413 NwaCegarLoop]: 148 mSDtfsCounter, 8 mSDsluCounter, 335 mSDsCounter, 0 mSdLazyCounter, 123 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 8 SdHoareTripleChecker+Valid, 483 SdHoareTripleChecker+Invalid, 123 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 123 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-07-12 18:39:42,167 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [8 Valid, 483 Invalid, 123 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 123 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-07-12 18:39:42,167 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146 states. [2022-07-12 18:39:42,168 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146 to 146. [2022-07-12 18:39:42,169 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 146 states, 84 states have (on average 1.8452380952380953) internal successors, (155), 145 states have internal predecessors, (155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:42,169 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 146 states to 146 states and 155 transitions. [2022-07-12 18:39:42,169 INFO L78 Accepts]: Start accepts. Automaton has 146 states and 155 transitions. Word has length 13 [2022-07-12 18:39:42,170 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-07-12 18:39:42,170 INFO L495 AbstractCegarLoop]: Abstraction has 146 states and 155 transitions. [2022-07-12 18:39:42,170 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 4 states have (on average 3.25) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:42,170 INFO L276 IsEmpty]: Start isEmpty. Operand 146 states and 155 transitions. [2022-07-12 18:39:42,170 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2022-07-12 18:39:42,170 INFO L187 NwaCegarLoop]: Found error trace [2022-07-12 18:39:42,170 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-12 18:39:42,171 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7 [2022-07-12 18:39:42,171 INFO L420 AbstractCegarLoop]: === Iteration 9 === Targeting ULTIMATE.startErr17REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 82 more)] === [2022-07-12 18:39:42,171 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-12 18:39:42,171 INFO L85 PathProgramCache]: Analyzing trace with hash -451673555, now seen corresponding path program 1 times [2022-07-12 18:39:42,171 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-12 18:39:42,171 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [706580834] [2022-07-12 18:39:42,171 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-12 18:39:42,172 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-12 18:39:42,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-12 18:39:42,283 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-12 18:39:42,283 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-12 18:39:42,283 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [706580834] [2022-07-12 18:39:42,283 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [706580834] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-12 18:39:42,283 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-12 18:39:42,283 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2022-07-12 18:39:42,283 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1811619315] [2022-07-12 18:39:42,284 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-12 18:39:42,284 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-07-12 18:39:42,284 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-12 18:39:42,284 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-07-12 18:39:42,284 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2022-07-12 18:39:42,284 INFO L87 Difference]: Start difference. First operand 146 states and 155 transitions. Second operand has 7 states, 6 states have (on average 2.1666666666666665) internal successors, (13), 7 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:42,440 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-12 18:39:42,440 INFO L93 Difference]: Finished difference Result 145 states and 154 transitions. [2022-07-12 18:39:42,441 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-07-12 18:39:42,441 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 6 states have (on average 2.1666666666666665) internal successors, (13), 7 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 13 [2022-07-12 18:39:42,441 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-07-12 18:39:42,441 INFO L225 Difference]: With dead ends: 145 [2022-07-12 18:39:42,441 INFO L226 Difference]: Without dead ends: 145 [2022-07-12 18:39:42,442 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=29, Invalid=61, Unknown=0, NotChecked=0, Total=90 [2022-07-12 18:39:42,442 INFO L413 NwaCegarLoop]: 144 mSDtfsCounter, 13 mSDsluCounter, 332 mSDsCounter, 0 mSdLazyCounter, 274 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 13 SdHoareTripleChecker+Valid, 476 SdHoareTripleChecker+Invalid, 276 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 274 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-07-12 18:39:42,442 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [13 Valid, 476 Invalid, 276 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 274 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-07-12 18:39:42,443 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 145 states. [2022-07-12 18:39:42,444 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 145 to 145. [2022-07-12 18:39:42,444 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 145 states, 84 states have (on average 1.8333333333333333) internal successors, (154), 144 states have internal predecessors, (154), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:42,444 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 145 states to 145 states and 154 transitions. [2022-07-12 18:39:42,444 INFO L78 Accepts]: Start accepts. Automaton has 145 states and 154 transitions. Word has length 13 [2022-07-12 18:39:42,444 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-07-12 18:39:42,444 INFO L495 AbstractCegarLoop]: Abstraction has 145 states and 154 transitions. [2022-07-12 18:39:42,444 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 6 states have (on average 2.1666666666666665) internal successors, (13), 7 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:42,445 INFO L276 IsEmpty]: Start isEmpty. Operand 145 states and 154 transitions. [2022-07-12 18:39:42,445 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2022-07-12 18:39:42,445 INFO L187 NwaCegarLoop]: Found error trace [2022-07-12 18:39:42,445 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-12 18:39:42,445 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8 [2022-07-12 18:39:42,445 INFO L420 AbstractCegarLoop]: === Iteration 10 === Targeting ULTIMATE.startErr24REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 82 more)] === [2022-07-12 18:39:42,445 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-12 18:39:42,445 INFO L85 PathProgramCache]: Analyzing trace with hash -598729444, now seen corresponding path program 1 times [2022-07-12 18:39:42,445 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-12 18:39:42,446 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1356153187] [2022-07-12 18:39:42,446 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-12 18:39:42,446 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-12 18:39:42,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-12 18:39:42,575 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-12 18:39:42,575 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-12 18:39:42,575 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1356153187] [2022-07-12 18:39:42,576 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1356153187] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-12 18:39:42,576 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-12 18:39:42,576 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2022-07-12 18:39:42,576 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [919395070] [2022-07-12 18:39:42,576 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-12 18:39:42,576 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 13 states [2022-07-12 18:39:42,576 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-12 18:39:42,576 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2022-07-12 18:39:42,576 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=42, Invalid=114, Unknown=0, NotChecked=0, Total=156 [2022-07-12 18:39:42,576 INFO L87 Difference]: Start difference. First operand 145 states and 154 transitions. Second operand has 13 states, 12 states have (on average 1.5) internal successors, (18), 13 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:42,807 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-12 18:39:42,807 INFO L93 Difference]: Finished difference Result 144 states and 153 transitions. [2022-07-12 18:39:42,807 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-07-12 18:39:42,807 INFO L78 Accepts]: Start accepts. Automaton has has 13 states, 12 states have (on average 1.5) internal successors, (18), 13 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 18 [2022-07-12 18:39:42,807 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-07-12 18:39:42,808 INFO L225 Difference]: With dead ends: 144 [2022-07-12 18:39:42,808 INFO L226 Difference]: Without dead ends: 144 [2022-07-12 18:39:42,808 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 36 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=68, Invalid=204, Unknown=0, NotChecked=0, Total=272 [2022-07-12 18:39:42,809 INFO L413 NwaCegarLoop]: 135 mSDtfsCounter, 27 mSDsluCounter, 617 mSDsCounter, 0 mSdLazyCounter, 427 mSolverCounterSat, 18 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 27 SdHoareTripleChecker+Valid, 752 SdHoareTripleChecker+Invalid, 445 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 18 IncrementalHoareTripleChecker+Valid, 427 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-07-12 18:39:42,809 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [27 Valid, 752 Invalid, 445 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [18 Valid, 427 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-07-12 18:39:42,809 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144 states. [2022-07-12 18:39:42,810 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144 to 144. [2022-07-12 18:39:42,811 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 144 states, 84 states have (on average 1.8214285714285714) internal successors, (153), 143 states have internal predecessors, (153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:42,811 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 144 states to 144 states and 153 transitions. [2022-07-12 18:39:42,811 INFO L78 Accepts]: Start accepts. Automaton has 144 states and 153 transitions. Word has length 18 [2022-07-12 18:39:42,811 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-07-12 18:39:42,811 INFO L495 AbstractCegarLoop]: Abstraction has 144 states and 153 transitions. [2022-07-12 18:39:42,811 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 13 states, 12 states have (on average 1.5) internal successors, (18), 13 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:42,811 INFO L276 IsEmpty]: Start isEmpty. Operand 144 states and 153 transitions. [2022-07-12 18:39:42,812 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2022-07-12 18:39:42,812 INFO L187 NwaCegarLoop]: Found error trace [2022-07-12 18:39:42,812 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-12 18:39:42,812 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable9 [2022-07-12 18:39:42,812 INFO L420 AbstractCegarLoop]: === Iteration 11 === Targeting ULTIMATE.startErr25REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 82 more)] === [2022-07-12 18:39:42,812 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-12 18:39:42,812 INFO L85 PathProgramCache]: Analyzing trace with hash -598729443, now seen corresponding path program 1 times [2022-07-12 18:39:42,812 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-12 18:39:42,812 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [641979679] [2022-07-12 18:39:42,812 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-12 18:39:42,813 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-12 18:39:42,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-12 18:39:42,998 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-12 18:39:42,998 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-12 18:39:42,999 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [641979679] [2022-07-12 18:39:43,000 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [641979679] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-12 18:39:43,000 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-12 18:39:43,000 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2022-07-12 18:39:43,000 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1360244646] [2022-07-12 18:39:43,000 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-12 18:39:43,000 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 13 states [2022-07-12 18:39:43,001 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-12 18:39:43,001 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2022-07-12 18:39:43,001 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=42, Invalid=114, Unknown=0, NotChecked=0, Total=156 [2022-07-12 18:39:43,002 INFO L87 Difference]: Start difference. First operand 144 states and 153 transitions. Second operand has 13 states, 12 states have (on average 1.5) internal successors, (18), 13 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:43,272 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-12 18:39:43,272 INFO L93 Difference]: Finished difference Result 143 states and 152 transitions. [2022-07-12 18:39:43,272 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-07-12 18:39:43,272 INFO L78 Accepts]: Start accepts. Automaton has has 13 states, 12 states have (on average 1.5) internal successors, (18), 13 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 18 [2022-07-12 18:39:43,272 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-07-12 18:39:43,273 INFO L225 Difference]: With dead ends: 143 [2022-07-12 18:39:43,273 INFO L226 Difference]: Without dead ends: 143 [2022-07-12 18:39:43,273 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 36 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=68, Invalid=204, Unknown=0, NotChecked=0, Total=272 [2022-07-12 18:39:43,273 INFO L413 NwaCegarLoop]: 135 mSDtfsCounter, 23 mSDsluCounter, 802 mSDsCounter, 0 mSdLazyCounter, 512 mSolverCounterSat, 14 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 23 SdHoareTripleChecker+Valid, 937 SdHoareTripleChecker+Invalid, 526 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 14 IncrementalHoareTripleChecker+Valid, 512 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-07-12 18:39:43,274 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [23 Valid, 937 Invalid, 526 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [14 Valid, 512 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-07-12 18:39:43,274 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 143 states. [2022-07-12 18:39:43,275 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 143 to 143. [2022-07-12 18:39:43,275 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 143 states, 84 states have (on average 1.8095238095238095) internal successors, (152), 142 states have internal predecessors, (152), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:43,275 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 143 states to 143 states and 152 transitions. [2022-07-12 18:39:43,276 INFO L78 Accepts]: Start accepts. Automaton has 143 states and 152 transitions. Word has length 18 [2022-07-12 18:39:43,276 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-07-12 18:39:43,276 INFO L495 AbstractCegarLoop]: Abstraction has 143 states and 152 transitions. [2022-07-12 18:39:43,276 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 13 states, 12 states have (on average 1.5) internal successors, (18), 13 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:43,276 INFO L276 IsEmpty]: Start isEmpty. Operand 143 states and 152 transitions. [2022-07-12 18:39:43,276 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2022-07-12 18:39:43,276 INFO L187 NwaCegarLoop]: Found error trace [2022-07-12 18:39:43,276 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-12 18:39:43,276 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable10 [2022-07-12 18:39:43,276 INFO L420 AbstractCegarLoop]: === Iteration 12 === Targeting ULTIMATE.startErr26REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 82 more)] === [2022-07-12 18:39:43,276 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-12 18:39:43,277 INFO L85 PathProgramCache]: Analyzing trace with hash -1380743565, now seen corresponding path program 1 times [2022-07-12 18:39:43,277 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-12 18:39:43,277 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1959056979] [2022-07-12 18:39:43,277 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-12 18:39:43,277 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-12 18:39:43,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-12 18:39:43,327 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-12 18:39:43,327 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-12 18:39:43,327 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1959056979] [2022-07-12 18:39:43,327 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1959056979] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-12 18:39:43,327 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-12 18:39:43,327 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-07-12 18:39:43,328 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2072338037] [2022-07-12 18:39:43,328 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-12 18:39:43,328 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-07-12 18:39:43,328 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-12 18:39:43,328 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-07-12 18:39:43,328 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-07-12 18:39:43,329 INFO L87 Difference]: Start difference. First operand 143 states and 152 transitions. Second operand has 5 states, 4 states have (on average 4.75) internal successors, (19), 5 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:43,410 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-12 18:39:43,410 INFO L93 Difference]: Finished difference Result 142 states and 151 transitions. [2022-07-12 18:39:43,410 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-07-12 18:39:43,411 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 4 states have (on average 4.75) internal successors, (19), 5 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 19 [2022-07-12 18:39:43,412 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-07-12 18:39:43,412 INFO L225 Difference]: With dead ends: 142 [2022-07-12 18:39:43,412 INFO L226 Difference]: Without dead ends: 142 [2022-07-12 18:39:43,413 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2022-07-12 18:39:43,413 INFO L413 NwaCegarLoop]: 145 mSDtfsCounter, 11 mSDsluCounter, 324 mSDsCounter, 0 mSdLazyCounter, 120 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 11 SdHoareTripleChecker+Valid, 469 SdHoareTripleChecker+Invalid, 121 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 120 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-07-12 18:39:43,414 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [11 Valid, 469 Invalid, 121 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 120 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-07-12 18:39:43,414 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 142 states. [2022-07-12 18:39:43,415 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 142 to 142. [2022-07-12 18:39:43,415 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 142 states, 84 states have (on average 1.7976190476190477) internal successors, (151), 141 states have internal predecessors, (151), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:43,416 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 142 states to 142 states and 151 transitions. [2022-07-12 18:39:43,416 INFO L78 Accepts]: Start accepts. Automaton has 142 states and 151 transitions. Word has length 19 [2022-07-12 18:39:43,416 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-07-12 18:39:43,416 INFO L495 AbstractCegarLoop]: Abstraction has 142 states and 151 transitions. [2022-07-12 18:39:43,417 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 4 states have (on average 4.75) internal successors, (19), 5 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:43,417 INFO L276 IsEmpty]: Start isEmpty. Operand 142 states and 151 transitions. [2022-07-12 18:39:43,417 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2022-07-12 18:39:43,417 INFO L187 NwaCegarLoop]: Found error trace [2022-07-12 18:39:43,417 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-12 18:39:43,417 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable11 [2022-07-12 18:39:43,418 INFO L420 AbstractCegarLoop]: === Iteration 13 === Targeting ULTIMATE.startErr27REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 82 more)] === [2022-07-12 18:39:43,418 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-12 18:39:43,418 INFO L85 PathProgramCache]: Analyzing trace with hash -1380743564, now seen corresponding path program 1 times [2022-07-12 18:39:43,418 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-12 18:39:43,418 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1101533541] [2022-07-12 18:39:43,418 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-12 18:39:43,418 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-12 18:39:43,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-12 18:39:43,664 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-12 18:39:43,664 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-12 18:39:43,664 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1101533541] [2022-07-12 18:39:43,664 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1101533541] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-12 18:39:43,664 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-12 18:39:43,664 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [14] imperfect sequences [] total 14 [2022-07-12 18:39:43,664 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [993447032] [2022-07-12 18:39:43,665 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-12 18:39:43,665 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 15 states [2022-07-12 18:39:43,665 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-12 18:39:43,665 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2022-07-12 18:39:43,665 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=162, Unknown=0, NotChecked=0, Total=210 [2022-07-12 18:39:43,665 INFO L87 Difference]: Start difference. First operand 142 states and 151 transitions. Second operand has 15 states, 14 states have (on average 1.3571428571428572) internal successors, (19), 15 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:43,885 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-12 18:39:43,885 INFO L93 Difference]: Finished difference Result 141 states and 150 transitions. [2022-07-12 18:39:43,886 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-07-12 18:39:43,886 INFO L78 Accepts]: Start accepts. Automaton has has 15 states, 14 states have (on average 1.3571428571428572) internal successors, (19), 15 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 19 [2022-07-12 18:39:43,886 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-07-12 18:39:43,886 INFO L225 Difference]: With dead ends: 141 [2022-07-12 18:39:43,886 INFO L226 Difference]: Without dead ends: 141 [2022-07-12 18:39:43,887 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 54 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=84, Invalid=296, Unknown=0, NotChecked=0, Total=380 [2022-07-12 18:39:43,887 INFO L413 NwaCegarLoop]: 134 mSDtfsCounter, 34 mSDsluCounter, 477 mSDsCounter, 0 mSdLazyCounter, 270 mSolverCounterSat, 18 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 34 SdHoareTripleChecker+Valid, 611 SdHoareTripleChecker+Invalid, 288 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 18 IncrementalHoareTripleChecker+Valid, 270 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-07-12 18:39:43,887 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [34 Valid, 611 Invalid, 288 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [18 Valid, 270 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-07-12 18:39:43,887 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 141 states. [2022-07-12 18:39:43,888 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 141 to 141. [2022-07-12 18:39:43,889 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 141 states, 84 states have (on average 1.7857142857142858) internal successors, (150), 140 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:43,889 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 150 transitions. [2022-07-12 18:39:43,889 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 150 transitions. Word has length 19 [2022-07-12 18:39:43,889 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-07-12 18:39:43,889 INFO L495 AbstractCegarLoop]: Abstraction has 141 states and 150 transitions. [2022-07-12 18:39:43,889 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 15 states, 14 states have (on average 1.3571428571428572) internal successors, (19), 15 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:43,889 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 150 transitions. [2022-07-12 18:39:43,889 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2022-07-12 18:39:43,889 INFO L187 NwaCegarLoop]: Found error trace [2022-07-12 18:39:43,889 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-12 18:39:43,890 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable12 [2022-07-12 18:39:43,890 INFO L420 AbstractCegarLoop]: === Iteration 14 === Targeting ULTIMATE.startErr28REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 82 more)] === [2022-07-12 18:39:43,890 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-12 18:39:43,890 INFO L85 PathProgramCache]: Analyzing trace with hash 146622463, now seen corresponding path program 1 times [2022-07-12 18:39:43,890 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-12 18:39:43,890 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [800870407] [2022-07-12 18:39:43,890 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-12 18:39:43,890 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-12 18:39:43,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-12 18:39:43,923 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-12 18:39:43,923 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-12 18:39:43,923 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [800870407] [2022-07-12 18:39:43,924 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [800870407] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-12 18:39:43,924 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-12 18:39:43,924 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-07-12 18:39:43,924 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1699397122] [2022-07-12 18:39:43,924 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-12 18:39:43,924 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-07-12 18:39:43,924 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-12 18:39:43,925 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-07-12 18:39:43,925 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-07-12 18:39:43,925 INFO L87 Difference]: Start difference. First operand 141 states and 150 transitions. Second operand has 5 states, 4 states have (on average 5.0) internal successors, (20), 5 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:44,006 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-12 18:39:44,006 INFO L93 Difference]: Finished difference Result 140 states and 149 transitions. [2022-07-12 18:39:44,006 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-07-12 18:39:44,006 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 4 states have (on average 5.0) internal successors, (20), 5 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 20 [2022-07-12 18:39:44,007 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-07-12 18:39:44,007 INFO L225 Difference]: With dead ends: 140 [2022-07-12 18:39:44,007 INFO L226 Difference]: Without dead ends: 140 [2022-07-12 18:39:44,007 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2022-07-12 18:39:44,008 INFO L413 NwaCegarLoop]: 143 mSDtfsCounter, 7 mSDsluCounter, 322 mSDsCounter, 0 mSdLazyCounter, 119 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 7 SdHoareTripleChecker+Valid, 465 SdHoareTripleChecker+Invalid, 119 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 119 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-07-12 18:39:44,008 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [7 Valid, 465 Invalid, 119 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 119 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-07-12 18:39:44,009 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 140 states. [2022-07-12 18:39:44,010 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 140 to 140. [2022-07-12 18:39:44,010 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 140 states, 84 states have (on average 1.7738095238095237) internal successors, (149), 139 states have internal predecessors, (149), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:44,010 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 140 states to 140 states and 149 transitions. [2022-07-12 18:39:44,010 INFO L78 Accepts]: Start accepts. Automaton has 140 states and 149 transitions. Word has length 20 [2022-07-12 18:39:44,010 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-07-12 18:39:44,011 INFO L495 AbstractCegarLoop]: Abstraction has 140 states and 149 transitions. [2022-07-12 18:39:44,011 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 4 states have (on average 5.0) internal successors, (20), 5 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:44,011 INFO L276 IsEmpty]: Start isEmpty. Operand 140 states and 149 transitions. [2022-07-12 18:39:44,011 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2022-07-12 18:39:44,011 INFO L187 NwaCegarLoop]: Found error trace [2022-07-12 18:39:44,011 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-12 18:39:44,011 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable13 [2022-07-12 18:39:44,012 INFO L420 AbstractCegarLoop]: === Iteration 15 === Targeting ULTIMATE.startErr29REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 82 more)] === [2022-07-12 18:39:44,012 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-12 18:39:44,012 INFO L85 PathProgramCache]: Analyzing trace with hash 146622464, now seen corresponding path program 1 times [2022-07-12 18:39:44,012 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-12 18:39:44,012 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1487656022] [2022-07-12 18:39:44,012 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-12 18:39:44,012 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-12 18:39:44,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-12 18:39:44,195 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-12 18:39:44,195 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-12 18:39:44,195 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1487656022] [2022-07-12 18:39:44,195 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1487656022] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-12 18:39:44,195 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-12 18:39:44,195 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [14] imperfect sequences [] total 14 [2022-07-12 18:39:44,195 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [829107925] [2022-07-12 18:39:44,195 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-12 18:39:44,195 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 15 states [2022-07-12 18:39:44,195 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-12 18:39:44,196 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2022-07-12 18:39:44,196 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=162, Unknown=0, NotChecked=0, Total=210 [2022-07-12 18:39:44,196 INFO L87 Difference]: Start difference. First operand 140 states and 149 transitions. Second operand has 15 states, 14 states have (on average 1.4285714285714286) internal successors, (20), 15 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:44,427 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-12 18:39:44,427 INFO L93 Difference]: Finished difference Result 139 states and 148 transitions. [2022-07-12 18:39:44,427 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-07-12 18:39:44,427 INFO L78 Accepts]: Start accepts. Automaton has has 15 states, 14 states have (on average 1.4285714285714286) internal successors, (20), 15 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 20 [2022-07-12 18:39:44,428 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-07-12 18:39:44,428 INFO L225 Difference]: With dead ends: 139 [2022-07-12 18:39:44,428 INFO L226 Difference]: Without dead ends: 139 [2022-07-12 18:39:44,428 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 54 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=84, Invalid=296, Unknown=0, NotChecked=0, Total=380 [2022-07-12 18:39:44,429 INFO L413 NwaCegarLoop]: 133 mSDtfsCounter, 31 mSDsluCounter, 708 mSDsCounter, 0 mSdLazyCounter, 438 mSolverCounterSat, 17 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 31 SdHoareTripleChecker+Valid, 841 SdHoareTripleChecker+Invalid, 455 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 17 IncrementalHoareTripleChecker+Valid, 438 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-07-12 18:39:44,429 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [31 Valid, 841 Invalid, 455 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [17 Valid, 438 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-07-12 18:39:44,429 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 139 states. [2022-07-12 18:39:44,430 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 139 to 139. [2022-07-12 18:39:44,430 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 139 states, 84 states have (on average 1.7619047619047619) internal successors, (148), 138 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:44,431 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139 states to 139 states and 148 transitions. [2022-07-12 18:39:44,431 INFO L78 Accepts]: Start accepts. Automaton has 139 states and 148 transitions. Word has length 20 [2022-07-12 18:39:44,431 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-07-12 18:39:44,431 INFO L495 AbstractCegarLoop]: Abstraction has 139 states and 148 transitions. [2022-07-12 18:39:44,431 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 15 states, 14 states have (on average 1.4285714285714286) internal successors, (20), 15 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:44,431 INFO L276 IsEmpty]: Start isEmpty. Operand 139 states and 148 transitions. [2022-07-12 18:39:44,431 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2022-07-12 18:39:44,431 INFO L187 NwaCegarLoop]: Found error trace [2022-07-12 18:39:44,431 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-12 18:39:44,431 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable14 [2022-07-12 18:39:44,431 INFO L420 AbstractCegarLoop]: === Iteration 16 === Targeting ULTIMATE.startErr30REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 82 more)] === [2022-07-12 18:39:44,432 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-12 18:39:44,432 INFO L85 PathProgramCache]: Analyzing trace with hash -1043484996, now seen corresponding path program 1 times [2022-07-12 18:39:44,432 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-12 18:39:44,432 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1582266726] [2022-07-12 18:39:44,432 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-12 18:39:44,432 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-12 18:39:44,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-12 18:39:44,491 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-12 18:39:44,492 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-12 18:39:44,492 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1582266726] [2022-07-12 18:39:44,492 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1582266726] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-12 18:39:44,494 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-12 18:39:44,494 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-12 18:39:44,494 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [59694438] [2022-07-12 18:39:44,494 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-12 18:39:44,495 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-07-12 18:39:44,495 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-12 18:39:44,495 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-07-12 18:39:44,495 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2022-07-12 18:39:44,495 INFO L87 Difference]: Start difference. First operand 139 states and 148 transitions. Second operand has 6 states, 5 states have (on average 5.0) internal successors, (25), 6 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:44,620 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-12 18:39:44,620 INFO L93 Difference]: Finished difference Result 200 states and 212 transitions. [2022-07-12 18:39:44,621 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-07-12 18:39:44,621 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 5.0) internal successors, (25), 6 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 25 [2022-07-12 18:39:44,621 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-07-12 18:39:44,622 INFO L225 Difference]: With dead ends: 200 [2022-07-12 18:39:44,622 INFO L226 Difference]: Without dead ends: 200 [2022-07-12 18:39:44,622 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2022-07-12 18:39:44,622 INFO L413 NwaCegarLoop]: 92 mSDtfsCounter, 478 mSDsluCounter, 80 mSDsCounter, 0 mSdLazyCounter, 216 mSolverCounterSat, 7 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 478 SdHoareTripleChecker+Valid, 172 SdHoareTripleChecker+Invalid, 223 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 7 IncrementalHoareTripleChecker+Valid, 216 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-07-12 18:39:44,623 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [478 Valid, 172 Invalid, 223 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [7 Valid, 216 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-07-12 18:39:44,623 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 200 states. [2022-07-12 18:39:44,624 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 200 to 137. [2022-07-12 18:39:44,624 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 137 states, 84 states have (on average 1.7380952380952381) internal successors, (146), 136 states have internal predecessors, (146), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:44,625 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 137 states to 137 states and 146 transitions. [2022-07-12 18:39:44,625 INFO L78 Accepts]: Start accepts. Automaton has 137 states and 146 transitions. Word has length 25 [2022-07-12 18:39:44,625 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-07-12 18:39:44,625 INFO L495 AbstractCegarLoop]: Abstraction has 137 states and 146 transitions. [2022-07-12 18:39:44,625 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 5.0) internal successors, (25), 6 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:44,625 INFO L276 IsEmpty]: Start isEmpty. Operand 137 states and 146 transitions. [2022-07-12 18:39:44,625 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2022-07-12 18:39:44,625 INFO L187 NwaCegarLoop]: Found error trace [2022-07-12 18:39:44,625 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-12 18:39:44,625 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable15 [2022-07-12 18:39:44,626 INFO L420 AbstractCegarLoop]: === Iteration 17 === Targeting ULTIMATE.startErr31REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 82 more)] === [2022-07-12 18:39:44,626 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-12 18:39:44,626 INFO L85 PathProgramCache]: Analyzing trace with hash -1043484995, now seen corresponding path program 1 times [2022-07-12 18:39:44,626 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-12 18:39:44,626 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [925202151] [2022-07-12 18:39:44,626 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-12 18:39:44,626 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-12 18:39:44,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-12 18:39:44,707 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-12 18:39:44,707 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-12 18:39:44,707 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [925202151] [2022-07-12 18:39:44,708 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [925202151] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-12 18:39:44,708 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-12 18:39:44,708 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2022-07-12 18:39:44,708 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [507177178] [2022-07-12 18:39:44,708 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-12 18:39:44,708 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-07-12 18:39:44,709 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-12 18:39:44,709 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-07-12 18:39:44,709 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2022-07-12 18:39:44,709 INFO L87 Difference]: Start difference. First operand 137 states and 146 transitions. Second operand has 7 states, 6 states have (on average 4.166666666666667) internal successors, (25), 7 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:44,825 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-12 18:39:44,825 INFO L93 Difference]: Finished difference Result 171 states and 181 transitions. [2022-07-12 18:39:44,826 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-07-12 18:39:44,826 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 6 states have (on average 4.166666666666667) internal successors, (25), 7 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 25 [2022-07-12 18:39:44,826 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-07-12 18:39:44,826 INFO L225 Difference]: With dead ends: 171 [2022-07-12 18:39:44,826 INFO L226 Difference]: Without dead ends: 171 [2022-07-12 18:39:44,827 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=57, Unknown=0, NotChecked=0, Total=90 [2022-07-12 18:39:44,827 INFO L413 NwaCegarLoop]: 102 mSDtfsCounter, 625 mSDsluCounter, 32 mSDsCounter, 0 mSdLazyCounter, 147 mSolverCounterSat, 8 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 625 SdHoareTripleChecker+Valid, 134 SdHoareTripleChecker+Invalid, 155 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 8 IncrementalHoareTripleChecker+Valid, 147 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-07-12 18:39:44,827 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [625 Valid, 134 Invalid, 155 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [8 Valid, 147 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-07-12 18:39:44,828 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 171 states. [2022-07-12 18:39:44,829 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 171 to 135. [2022-07-12 18:39:44,829 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 135 states, 84 states have (on average 1.7142857142857142) internal successors, (144), 134 states have internal predecessors, (144), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:44,829 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 135 states to 135 states and 144 transitions. [2022-07-12 18:39:44,829 INFO L78 Accepts]: Start accepts. Automaton has 135 states and 144 transitions. Word has length 25 [2022-07-12 18:39:44,829 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-07-12 18:39:44,829 INFO L495 AbstractCegarLoop]: Abstraction has 135 states and 144 transitions. [2022-07-12 18:39:44,829 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 6 states have (on average 4.166666666666667) internal successors, (25), 7 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:44,829 INFO L276 IsEmpty]: Start isEmpty. Operand 135 states and 144 transitions. [2022-07-12 18:39:44,830 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2022-07-12 18:39:44,830 INFO L187 NwaCegarLoop]: Found error trace [2022-07-12 18:39:44,830 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-12 18:39:44,830 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable16 [2022-07-12 18:39:44,830 INFO L420 AbstractCegarLoop]: === Iteration 18 === Targeting ULTIMATE.startErr68REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 82 more)] === [2022-07-12 18:39:44,830 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-12 18:39:44,830 INFO L85 PathProgramCache]: Analyzing trace with hash 2011706153, now seen corresponding path program 1 times [2022-07-12 18:39:44,830 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-12 18:39:44,830 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [745328500] [2022-07-12 18:39:44,830 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-12 18:39:44,830 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-12 18:39:44,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-12 18:39:44,865 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-12 18:39:44,865 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-12 18:39:44,865 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [745328500] [2022-07-12 18:39:44,865 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [745328500] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-12 18:39:44,865 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-12 18:39:44,865 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-12 18:39:44,865 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [882984107] [2022-07-12 18:39:44,866 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-12 18:39:44,866 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-07-12 18:39:44,866 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-12 18:39:44,866 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-07-12 18:39:44,866 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2022-07-12 18:39:44,866 INFO L87 Difference]: Start difference. First operand 135 states and 144 transitions. Second operand has 6 states, 5 states have (on average 5.2) internal successors, (26), 6 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:44,988 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-12 18:39:44,988 INFO L93 Difference]: Finished difference Result 156 states and 166 transitions. [2022-07-12 18:39:44,988 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-07-12 18:39:44,989 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 5.2) internal successors, (26), 6 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 26 [2022-07-12 18:39:44,989 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-07-12 18:39:44,989 INFO L225 Difference]: With dead ends: 156 [2022-07-12 18:39:44,989 INFO L226 Difference]: Without dead ends: 156 [2022-07-12 18:39:44,989 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2022-07-12 18:39:44,990 INFO L413 NwaCegarLoop]: 68 mSDtfsCounter, 384 mSDsluCounter, 96 mSDsCounter, 0 mSdLazyCounter, 221 mSolverCounterSat, 14 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 384 SdHoareTripleChecker+Valid, 164 SdHoareTripleChecker+Invalid, 235 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 14 IncrementalHoareTripleChecker+Valid, 221 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-07-12 18:39:44,990 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [384 Valid, 164 Invalid, 235 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [14 Valid, 221 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-07-12 18:39:44,990 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 156 states. [2022-07-12 18:39:44,992 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 156 to 132. [2022-07-12 18:39:44,992 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 132 states, 85 states have (on average 1.6705882352941177) internal successors, (142), 131 states have internal predecessors, (142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:44,992 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 132 states to 132 states and 142 transitions. [2022-07-12 18:39:44,992 INFO L78 Accepts]: Start accepts. Automaton has 132 states and 142 transitions. Word has length 26 [2022-07-12 18:39:44,992 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-07-12 18:39:44,992 INFO L495 AbstractCegarLoop]: Abstraction has 132 states and 142 transitions. [2022-07-12 18:39:44,992 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 5.2) internal successors, (26), 6 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:44,992 INFO L276 IsEmpty]: Start isEmpty. Operand 132 states and 142 transitions. [2022-07-12 18:39:44,993 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2022-07-12 18:39:44,993 INFO L187 NwaCegarLoop]: Found error trace [2022-07-12 18:39:44,993 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-12 18:39:44,993 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable17 [2022-07-12 18:39:44,993 INFO L420 AbstractCegarLoop]: === Iteration 19 === Targeting ULTIMATE.startErr69REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 82 more)] === [2022-07-12 18:39:44,993 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-12 18:39:44,993 INFO L85 PathProgramCache]: Analyzing trace with hash 2011706154, now seen corresponding path program 1 times [2022-07-12 18:39:44,993 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-12 18:39:44,993 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1469942676] [2022-07-12 18:39:44,993 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-12 18:39:44,993 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-12 18:39:45,009 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-12 18:39:45,067 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-12 18:39:45,067 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-12 18:39:45,067 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1469942676] [2022-07-12 18:39:45,067 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1469942676] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-12 18:39:45,067 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-12 18:39:45,067 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2022-07-12 18:39:45,068 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1080684681] [2022-07-12 18:39:45,068 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-12 18:39:45,069 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-07-12 18:39:45,069 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-12 18:39:45,069 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-07-12 18:39:45,069 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2022-07-12 18:39:45,070 INFO L87 Difference]: Start difference. First operand 132 states and 142 transitions. Second operand has 7 states, 6 states have (on average 4.333333333333333) internal successors, (26), 7 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:45,191 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-12 18:39:45,191 INFO L93 Difference]: Finished difference Result 127 states and 136 transitions. [2022-07-12 18:39:45,191 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-07-12 18:39:45,192 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 6 states have (on average 4.333333333333333) internal successors, (26), 7 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 26 [2022-07-12 18:39:45,192 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-07-12 18:39:45,192 INFO L225 Difference]: With dead ends: 127 [2022-07-12 18:39:45,192 INFO L226 Difference]: Without dead ends: 127 [2022-07-12 18:39:45,192 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=57, Unknown=0, NotChecked=0, Total=90 [2022-07-12 18:39:45,193 INFO L413 NwaCegarLoop]: 67 mSDtfsCounter, 378 mSDsluCounter, 57 mSDsCounter, 0 mSdLazyCounter, 164 mSolverCounterSat, 9 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 378 SdHoareTripleChecker+Valid, 124 SdHoareTripleChecker+Invalid, 173 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 9 IncrementalHoareTripleChecker+Valid, 164 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-07-12 18:39:45,193 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [378 Valid, 124 Invalid, 173 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [9 Valid, 164 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-07-12 18:39:45,193 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 127 states. [2022-07-12 18:39:45,194 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 127 to 127. [2022-07-12 18:39:45,195 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 127 states, 85 states have (on average 1.6) internal successors, (136), 126 states have internal predecessors, (136), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:45,195 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 127 states to 127 states and 136 transitions. [2022-07-12 18:39:45,195 INFO L78 Accepts]: Start accepts. Automaton has 127 states and 136 transitions. Word has length 26 [2022-07-12 18:39:45,195 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-07-12 18:39:45,195 INFO L495 AbstractCegarLoop]: Abstraction has 127 states and 136 transitions. [2022-07-12 18:39:45,195 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 6 states have (on average 4.333333333333333) internal successors, (26), 7 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:45,195 INFO L276 IsEmpty]: Start isEmpty. Operand 127 states and 136 transitions. [2022-07-12 18:39:45,196 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2022-07-12 18:39:45,196 INFO L187 NwaCegarLoop]: Found error trace [2022-07-12 18:39:45,196 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-12 18:39:45,196 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable18 [2022-07-12 18:39:45,196 INFO L420 AbstractCegarLoop]: === Iteration 20 === Targeting ULTIMATE.startErr32REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 82 more)] === [2022-07-12 18:39:45,196 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-12 18:39:45,196 INFO L85 PathProgramCache]: Analyzing trace with hash -2061699999, now seen corresponding path program 1 times [2022-07-12 18:39:45,196 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-12 18:39:45,196 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1748197964] [2022-07-12 18:39:45,196 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-12 18:39:45,197 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-12 18:39:45,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-12 18:39:45,466 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-12 18:39:45,466 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-12 18:39:45,466 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1748197964] [2022-07-12 18:39:45,466 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1748197964] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-12 18:39:45,466 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-12 18:39:45,466 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [20] imperfect sequences [] total 20 [2022-07-12 18:39:45,466 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [78793877] [2022-07-12 18:39:45,466 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-12 18:39:45,467 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 21 states [2022-07-12 18:39:45,467 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-12 18:39:45,467 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2022-07-12 18:39:45,467 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=360, Unknown=0, NotChecked=0, Total=420 [2022-07-12 18:39:45,467 INFO L87 Difference]: Start difference. First operand 127 states and 136 transitions. Second operand has 21 states, 20 states have (on average 1.35) internal successors, (27), 21 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:46,143 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-12 18:39:46,144 INFO L93 Difference]: Finished difference Result 209 states and 226 transitions. [2022-07-12 18:39:46,144 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2022-07-12 18:39:46,144 INFO L78 Accepts]: Start accepts. Automaton has has 21 states, 20 states have (on average 1.35) internal successors, (27), 21 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 27 [2022-07-12 18:39:46,144 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-07-12 18:39:46,145 INFO L225 Difference]: With dead ends: 209 [2022-07-12 18:39:46,145 INFO L226 Difference]: Without dead ends: 209 [2022-07-12 18:39:46,145 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 39 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 218 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=225, Invalid=1181, Unknown=0, NotChecked=0, Total=1406 [2022-07-12 18:39:46,146 INFO L413 NwaCegarLoop]: 80 mSDtfsCounter, 562 mSDsluCounter, 996 mSDsCounter, 0 mSdLazyCounter, 1063 mSolverCounterSat, 59 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 562 SdHoareTripleChecker+Valid, 1076 SdHoareTripleChecker+Invalid, 1122 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 59 IncrementalHoareTripleChecker+Valid, 1063 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2022-07-12 18:39:46,146 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [562 Valid, 1076 Invalid, 1122 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [59 Valid, 1063 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2022-07-12 18:39:46,146 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 209 states. [2022-07-12 18:39:46,147 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 209 to 128. [2022-07-12 18:39:46,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 128 states, 90 states have (on average 1.5444444444444445) internal successors, (139), 127 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:46,148 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 139 transitions. [2022-07-12 18:39:46,148 INFO L78 Accepts]: Start accepts. Automaton has 128 states and 139 transitions. Word has length 27 [2022-07-12 18:39:46,148 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-07-12 18:39:46,148 INFO L495 AbstractCegarLoop]: Abstraction has 128 states and 139 transitions. [2022-07-12 18:39:46,148 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 21 states, 20 states have (on average 1.35) internal successors, (27), 21 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:46,148 INFO L276 IsEmpty]: Start isEmpty. Operand 128 states and 139 transitions. [2022-07-12 18:39:46,148 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2022-07-12 18:39:46,148 INFO L187 NwaCegarLoop]: Found error trace [2022-07-12 18:39:46,148 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-12 18:39:46,149 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable19 [2022-07-12 18:39:46,149 INFO L420 AbstractCegarLoop]: === Iteration 21 === Targeting ULTIMATE.startErr33REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 82 more)] === [2022-07-12 18:39:46,149 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-12 18:39:46,149 INFO L85 PathProgramCache]: Analyzing trace with hash -2061699998, now seen corresponding path program 1 times [2022-07-12 18:39:46,149 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-12 18:39:46,149 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1213035340] [2022-07-12 18:39:46,149 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-12 18:39:46,149 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-12 18:39:46,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-12 18:39:46,530 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-12 18:39:46,530 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-12 18:39:46,530 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1213035340] [2022-07-12 18:39:46,530 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1213035340] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-12 18:39:46,530 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-12 18:39:46,530 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [22] imperfect sequences [] total 22 [2022-07-12 18:39:46,530 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [801609751] [2022-07-12 18:39:46,530 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-12 18:39:46,530 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 23 states [2022-07-12 18:39:46,531 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-12 18:39:46,531 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2022-07-12 18:39:46,531 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=69, Invalid=437, Unknown=0, NotChecked=0, Total=506 [2022-07-12 18:39:46,531 INFO L87 Difference]: Start difference. First operand 128 states and 139 transitions. Second operand has 23 states, 22 states have (on average 1.2272727272727273) internal successors, (27), 23 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:47,513 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-12 18:39:47,514 INFO L93 Difference]: Finished difference Result 281 states and 306 transitions. [2022-07-12 18:39:47,514 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2022-07-12 18:39:47,514 INFO L78 Accepts]: Start accepts. Automaton has has 23 states, 22 states have (on average 1.2272727272727273) internal successors, (27), 23 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 27 [2022-07-12 18:39:47,514 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-07-12 18:39:47,524 INFO L225 Difference]: With dead ends: 281 [2022-07-12 18:39:47,524 INFO L226 Difference]: Without dead ends: 281 [2022-07-12 18:39:47,524 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 40 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 273 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=252, Invalid=1388, Unknown=0, NotChecked=0, Total=1640 [2022-07-12 18:39:47,525 INFO L413 NwaCegarLoop]: 80 mSDtfsCounter, 775 mSDsluCounter, 1215 mSDsCounter, 0 mSdLazyCounter, 1183 mSolverCounterSat, 70 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 775 SdHoareTripleChecker+Valid, 1295 SdHoareTripleChecker+Invalid, 1253 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 70 IncrementalHoareTripleChecker+Valid, 1183 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2022-07-12 18:39:47,525 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [775 Valid, 1295 Invalid, 1253 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [70 Valid, 1183 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2022-07-12 18:39:47,527 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 281 states. [2022-07-12 18:39:47,528 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 281 to 166. [2022-07-12 18:39:47,528 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 166 states, 128 states have (on average 1.625) internal successors, (208), 165 states have internal predecessors, (208), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:47,529 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 166 states to 166 states and 208 transitions. [2022-07-12 18:39:47,529 INFO L78 Accepts]: Start accepts. Automaton has 166 states and 208 transitions. Word has length 27 [2022-07-12 18:39:47,529 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-07-12 18:39:47,529 INFO L495 AbstractCegarLoop]: Abstraction has 166 states and 208 transitions. [2022-07-12 18:39:47,529 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 23 states, 22 states have (on average 1.2272727272727273) internal successors, (27), 23 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:47,530 INFO L276 IsEmpty]: Start isEmpty. Operand 166 states and 208 transitions. [2022-07-12 18:39:47,530 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2022-07-12 18:39:47,530 INFO L187 NwaCegarLoop]: Found error trace [2022-07-12 18:39:47,530 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-12 18:39:47,530 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable20 [2022-07-12 18:39:47,531 INFO L420 AbstractCegarLoop]: === Iteration 22 === Targeting ULTIMATE.startErr82ASSERT_VIOLATIONMEMORY_FREE === [ULTIMATE.startErr0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 82 more)] === [2022-07-12 18:39:47,531 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-12 18:39:47,531 INFO L85 PathProgramCache]: Analyzing trace with hash -1235458799, now seen corresponding path program 1 times [2022-07-12 18:39:47,532 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-12 18:39:47,532 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [398942121] [2022-07-12 18:39:47,532 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-12 18:39:47,532 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-12 18:39:47,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-12 18:39:47,573 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-12 18:39:47,573 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-12 18:39:47,574 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [398942121] [2022-07-12 18:39:47,574 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [398942121] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-12 18:39:47,574 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-12 18:39:47,574 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-12 18:39:47,574 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [529282804] [2022-07-12 18:39:47,574 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-12 18:39:47,574 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-07-12 18:39:47,574 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-12 18:39:47,575 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-07-12 18:39:47,575 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2022-07-12 18:39:47,575 INFO L87 Difference]: Start difference. First operand 166 states and 208 transitions. Second operand has 6 states, 5 states have (on average 5.8) internal successors, (29), 6 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:47,624 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-12 18:39:47,624 INFO L93 Difference]: Finished difference Result 165 states and 207 transitions. [2022-07-12 18:39:47,625 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-07-12 18:39:47,625 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 5.8) internal successors, (29), 6 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 29 [2022-07-12 18:39:47,625 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-07-12 18:39:47,626 INFO L225 Difference]: With dead ends: 165 [2022-07-12 18:39:47,626 INFO L226 Difference]: Without dead ends: 165 [2022-07-12 18:39:47,627 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2022-07-12 18:39:47,627 INFO L413 NwaCegarLoop]: 106 mSDtfsCounter, 345 mSDsluCounter, 106 mSDsCounter, 0 mSdLazyCounter, 66 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 345 SdHoareTripleChecker+Valid, 212 SdHoareTripleChecker+Invalid, 66 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 66 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-07-12 18:39:47,627 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [345 Valid, 212 Invalid, 66 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 66 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-07-12 18:39:47,628 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 165 states. [2022-07-12 18:39:47,630 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 165 to 165. [2022-07-12 18:39:47,630 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 165 states, 128 states have (on average 1.6171875) internal successors, (207), 164 states have internal predecessors, (207), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:47,630 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 165 states to 165 states and 207 transitions. [2022-07-12 18:39:47,630 INFO L78 Accepts]: Start accepts. Automaton has 165 states and 207 transitions. Word has length 29 [2022-07-12 18:39:47,631 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-07-12 18:39:47,631 INFO L495 AbstractCegarLoop]: Abstraction has 165 states and 207 transitions. [2022-07-12 18:39:47,631 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 5.8) internal successors, (29), 6 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:47,631 INFO L276 IsEmpty]: Start isEmpty. Operand 165 states and 207 transitions. [2022-07-12 18:39:47,631 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2022-07-12 18:39:47,631 INFO L187 NwaCegarLoop]: Found error trace [2022-07-12 18:39:47,631 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-12 18:39:47,631 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable21 [2022-07-12 18:39:47,632 INFO L420 AbstractCegarLoop]: === Iteration 23 === Targeting ULTIMATE.startErr74REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 82 more)] === [2022-07-12 18:39:47,632 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-12 18:39:47,632 INFO L85 PathProgramCache]: Analyzing trace with hash -1863814087, now seen corresponding path program 1 times [2022-07-12 18:39:47,632 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-12 18:39:47,632 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1446572136] [2022-07-12 18:39:47,632 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-12 18:39:47,632 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-12 18:39:47,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-12 18:39:47,869 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-12 18:39:47,870 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-12 18:39:47,870 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1446572136] [2022-07-12 18:39:47,870 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1446572136] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-12 18:39:47,870 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-12 18:39:47,870 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [19] imperfect sequences [] total 19 [2022-07-12 18:39:47,870 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [539142497] [2022-07-12 18:39:47,870 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-12 18:39:47,870 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 20 states [2022-07-12 18:39:47,871 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-12 18:39:47,871 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2022-07-12 18:39:47,871 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=58, Invalid=322, Unknown=0, NotChecked=0, Total=380 [2022-07-12 18:39:47,871 INFO L87 Difference]: Start difference. First operand 165 states and 207 transitions. Second operand has 20 states, 19 states have (on average 1.631578947368421) internal successors, (31), 20 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:48,395 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-12 18:39:48,395 INFO L93 Difference]: Finished difference Result 224 states and 272 transitions. [2022-07-12 18:39:48,396 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2022-07-12 18:39:48,396 INFO L78 Accepts]: Start accepts. Automaton has has 20 states, 19 states have (on average 1.631578947368421) internal successors, (31), 20 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 31 [2022-07-12 18:39:48,396 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-07-12 18:39:48,397 INFO L225 Difference]: With dead ends: 224 [2022-07-12 18:39:48,397 INFO L226 Difference]: Without dead ends: 224 [2022-07-12 18:39:48,397 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 37 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 196 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=208, Invalid=1052, Unknown=0, NotChecked=0, Total=1260 [2022-07-12 18:39:48,398 INFO L413 NwaCegarLoop]: 80 mSDtfsCounter, 359 mSDsluCounter, 874 mSDsCounter, 0 mSdLazyCounter, 784 mSolverCounterSat, 44 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 359 SdHoareTripleChecker+Valid, 954 SdHoareTripleChecker+Invalid, 828 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 44 IncrementalHoareTripleChecker+Valid, 784 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-07-12 18:39:48,398 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [359 Valid, 954 Invalid, 828 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [44 Valid, 784 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2022-07-12 18:39:48,398 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 224 states. [2022-07-12 18:39:48,400 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 224 to 172. [2022-07-12 18:39:48,400 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 172 states, 135 states have (on average 1.6) internal successors, (216), 171 states have internal predecessors, (216), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:48,401 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 172 states to 172 states and 216 transitions. [2022-07-12 18:39:48,401 INFO L78 Accepts]: Start accepts. Automaton has 172 states and 216 transitions. Word has length 31 [2022-07-12 18:39:48,401 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-07-12 18:39:48,401 INFO L495 AbstractCegarLoop]: Abstraction has 172 states and 216 transitions. [2022-07-12 18:39:48,401 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 20 states, 19 states have (on average 1.631578947368421) internal successors, (31), 20 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:48,401 INFO L276 IsEmpty]: Start isEmpty. Operand 172 states and 216 transitions. [2022-07-12 18:39:48,401 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2022-07-12 18:39:48,401 INFO L187 NwaCegarLoop]: Found error trace [2022-07-12 18:39:48,402 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-12 18:39:48,402 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable22 [2022-07-12 18:39:48,402 INFO L420 AbstractCegarLoop]: === Iteration 24 === Targeting ULTIMATE.startErr75REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 82 more)] === [2022-07-12 18:39:48,402 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-12 18:39:48,402 INFO L85 PathProgramCache]: Analyzing trace with hash -1863814086, now seen corresponding path program 1 times [2022-07-12 18:39:48,402 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-12 18:39:48,402 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [970662884] [2022-07-12 18:39:48,403 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-12 18:39:48,403 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-12 18:39:48,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-12 18:39:48,763 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-12 18:39:48,764 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-12 18:39:48,764 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [970662884] [2022-07-12 18:39:48,764 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [970662884] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-12 18:39:48,764 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-12 18:39:48,764 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [20] imperfect sequences [] total 20 [2022-07-12 18:39:48,764 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [773420791] [2022-07-12 18:39:48,764 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-12 18:39:48,764 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 21 states [2022-07-12 18:39:48,764 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-12 18:39:48,765 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2022-07-12 18:39:48,765 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=359, Unknown=0, NotChecked=0, Total=420 [2022-07-12 18:39:48,765 INFO L87 Difference]: Start difference. First operand 172 states and 216 transitions. Second operand has 21 states, 20 states have (on average 1.55) internal successors, (31), 21 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:49,518 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-12 18:39:49,518 INFO L93 Difference]: Finished difference Result 224 states and 272 transitions. [2022-07-12 18:39:49,519 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2022-07-12 18:39:49,519 INFO L78 Accepts]: Start accepts. Automaton has has 21 states, 20 states have (on average 1.55) internal successors, (31), 21 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 31 [2022-07-12 18:39:49,519 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-07-12 18:39:49,520 INFO L225 Difference]: With dead ends: 224 [2022-07-12 18:39:49,520 INFO L226 Difference]: Without dead ends: 224 [2022-07-12 18:39:49,522 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 219 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=225, Invalid=1181, Unknown=0, NotChecked=0, Total=1406 [2022-07-12 18:39:49,523 INFO L413 NwaCegarLoop]: 71 mSDtfsCounter, 429 mSDsluCounter, 835 mSDsCounter, 0 mSdLazyCounter, 953 mSolverCounterSat, 47 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 429 SdHoareTripleChecker+Valid, 906 SdHoareTripleChecker+Invalid, 1000 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 47 IncrementalHoareTripleChecker+Valid, 953 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2022-07-12 18:39:49,523 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [429 Valid, 906 Invalid, 1000 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [47 Valid, 953 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2022-07-12 18:39:49,524 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 224 states. [2022-07-12 18:39:49,525 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 224 to 172. [2022-07-12 18:39:49,526 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 172 states, 135 states have (on average 1.5925925925925926) internal successors, (215), 171 states have internal predecessors, (215), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:49,526 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 172 states to 172 states and 215 transitions. [2022-07-12 18:39:49,526 INFO L78 Accepts]: Start accepts. Automaton has 172 states and 215 transitions. Word has length 31 [2022-07-12 18:39:49,527 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-07-12 18:39:49,527 INFO L495 AbstractCegarLoop]: Abstraction has 172 states and 215 transitions. [2022-07-12 18:39:49,527 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 21 states, 20 states have (on average 1.55) internal successors, (31), 21 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:49,527 INFO L276 IsEmpty]: Start isEmpty. Operand 172 states and 215 transitions. [2022-07-12 18:39:49,528 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2022-07-12 18:39:49,528 INFO L187 NwaCegarLoop]: Found error trace [2022-07-12 18:39:49,528 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-12 18:39:49,528 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable23 [2022-07-12 18:39:49,528 INFO L420 AbstractCegarLoop]: === Iteration 25 === Targeting ULTIMATE.startErr84ASSERT_VIOLATIONMEMORY_LEAK === [ULTIMATE.startErr0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 82 more)] === [2022-07-12 18:39:49,529 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-12 18:39:49,529 INFO L85 PathProgramCache]: Analyzing trace with hash -1978046457, now seen corresponding path program 1 times [2022-07-12 18:39:49,529 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-12 18:39:49,529 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1758980512] [2022-07-12 18:39:49,529 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-12 18:39:49,530 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-12 18:39:49,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-12 18:39:49,812 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-12 18:39:49,813 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-12 18:39:49,813 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1758980512] [2022-07-12 18:39:49,813 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1758980512] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-12 18:39:49,813 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-12 18:39:49,814 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [22] imperfect sequences [] total 22 [2022-07-12 18:39:49,814 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1570660799] [2022-07-12 18:39:49,814 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-12 18:39:49,814 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 22 states [2022-07-12 18:39:49,814 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-12 18:39:49,814 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2022-07-12 18:39:49,815 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=79, Invalid=383, Unknown=0, NotChecked=0, Total=462 [2022-07-12 18:39:49,815 INFO L87 Difference]: Start difference. First operand 172 states and 215 transitions. Second operand has 22 states, 22 states have (on average 1.4545454545454546) internal successors, (32), 22 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:50,311 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-12 18:39:50,311 INFO L93 Difference]: Finished difference Result 217 states and 265 transitions. [2022-07-12 18:39:50,311 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2022-07-12 18:39:50,311 INFO L78 Accepts]: Start accepts. Automaton has has 22 states, 22 states have (on average 1.4545454545454546) internal successors, (32), 22 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 32 [2022-07-12 18:39:50,311 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-07-12 18:39:50,312 INFO L225 Difference]: With dead ends: 217 [2022-07-12 18:39:50,312 INFO L226 Difference]: Without dead ends: 217 [2022-07-12 18:39:50,312 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 36 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 185 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=218, Invalid=1042, Unknown=0, NotChecked=0, Total=1260 [2022-07-12 18:39:50,313 INFO L413 NwaCegarLoop]: 83 mSDtfsCounter, 329 mSDsluCounter, 1075 mSDsCounter, 0 mSdLazyCounter, 792 mSolverCounterSat, 46 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 329 SdHoareTripleChecker+Valid, 1158 SdHoareTripleChecker+Invalid, 838 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 46 IncrementalHoareTripleChecker+Valid, 792 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-07-12 18:39:50,313 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [329 Valid, 1158 Invalid, 838 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [46 Valid, 792 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2022-07-12 18:39:50,313 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 217 states. [2022-07-12 18:39:50,315 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 217 to 172. [2022-07-12 18:39:50,315 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 172 states, 135 states have (on average 1.5851851851851853) internal successors, (214), 171 states have internal predecessors, (214), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:50,315 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 172 states to 172 states and 214 transitions. [2022-07-12 18:39:50,316 INFO L78 Accepts]: Start accepts. Automaton has 172 states and 214 transitions. Word has length 32 [2022-07-12 18:39:50,316 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-07-12 18:39:50,316 INFO L495 AbstractCegarLoop]: Abstraction has 172 states and 214 transitions. [2022-07-12 18:39:50,316 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 22 states, 22 states have (on average 1.4545454545454546) internal successors, (32), 22 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:50,316 INFO L276 IsEmpty]: Start isEmpty. Operand 172 states and 214 transitions. [2022-07-12 18:39:50,316 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2022-07-12 18:39:50,316 INFO L187 NwaCegarLoop]: Found error trace [2022-07-12 18:39:50,317 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-12 18:39:50,317 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable24 [2022-07-12 18:39:50,317 INFO L420 AbstractCegarLoop]: === Iteration 26 === Targeting ULTIMATE.startErr38REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 82 more)] === [2022-07-12 18:39:50,317 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-12 18:39:50,317 INFO L85 PathProgramCache]: Analyzing trace with hash 190378255, now seen corresponding path program 1 times [2022-07-12 18:39:50,317 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-12 18:39:50,317 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [983929707] [2022-07-12 18:39:50,317 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-12 18:39:50,318 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-12 18:39:50,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-12 18:39:50,366 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-12 18:39:50,366 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-12 18:39:50,366 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [983929707] [2022-07-12 18:39:50,366 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [983929707] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-12 18:39:50,366 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-12 18:39:50,367 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-12 18:39:50,367 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [544952278] [2022-07-12 18:39:50,367 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-12 18:39:50,367 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-07-12 18:39:50,367 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-12 18:39:50,367 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-12 18:39:50,367 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-12 18:39:50,368 INFO L87 Difference]: Start difference. First operand 172 states and 214 transitions. Second operand has 4 states, 3 states have (on average 11.0) internal successors, (33), 4 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:50,447 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-12 18:39:50,448 INFO L93 Difference]: Finished difference Result 189 states and 229 transitions. [2022-07-12 18:39:50,448 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-12 18:39:50,448 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 3 states have (on average 11.0) internal successors, (33), 4 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 33 [2022-07-12 18:39:50,448 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-07-12 18:39:50,449 INFO L225 Difference]: With dead ends: 189 [2022-07-12 18:39:50,449 INFO L226 Difference]: Without dead ends: 189 [2022-07-12 18:39:50,449 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-07-12 18:39:50,450 INFO L413 NwaCegarLoop]: 104 mSDtfsCounter, 169 mSDsluCounter, 46 mSDsCounter, 0 mSdLazyCounter, 126 mSolverCounterSat, 7 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 169 SdHoareTripleChecker+Valid, 150 SdHoareTripleChecker+Invalid, 133 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 7 IncrementalHoareTripleChecker+Valid, 126 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-07-12 18:39:50,450 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [169 Valid, 150 Invalid, 133 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [7 Valid, 126 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-07-12 18:39:50,450 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 189 states. [2022-07-12 18:39:50,452 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 189 to 170. [2022-07-12 18:39:50,452 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 170 states, 137 states have (on average 1.532846715328467) internal successors, (210), 169 states have internal predecessors, (210), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:50,452 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 170 states to 170 states and 210 transitions. [2022-07-12 18:39:50,452 INFO L78 Accepts]: Start accepts. Automaton has 170 states and 210 transitions. Word has length 33 [2022-07-12 18:39:50,453 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-07-12 18:39:50,453 INFO L495 AbstractCegarLoop]: Abstraction has 170 states and 210 transitions. [2022-07-12 18:39:50,453 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 3 states have (on average 11.0) internal successors, (33), 4 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:50,453 INFO L276 IsEmpty]: Start isEmpty. Operand 170 states and 210 transitions. [2022-07-12 18:39:50,453 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2022-07-12 18:39:50,453 INFO L187 NwaCegarLoop]: Found error trace [2022-07-12 18:39:50,453 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-12 18:39:50,453 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable25 [2022-07-12 18:39:50,454 INFO L420 AbstractCegarLoop]: === Iteration 27 === Targeting ULTIMATE.startErr39REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 82 more)] === [2022-07-12 18:39:50,454 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-12 18:39:50,454 INFO L85 PathProgramCache]: Analyzing trace with hash 190378256, now seen corresponding path program 1 times [2022-07-12 18:39:50,454 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-12 18:39:50,454 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [117580661] [2022-07-12 18:39:50,454 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-12 18:39:50,454 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-12 18:39:50,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-12 18:39:50,786 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-12 18:39:50,786 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-12 18:39:50,786 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [117580661] [2022-07-12 18:39:50,786 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [117580661] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-12 18:39:50,786 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-12 18:39:50,787 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [24] imperfect sequences [] total 24 [2022-07-12 18:39:50,787 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1400747339] [2022-07-12 18:39:50,787 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-12 18:39:50,787 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 25 states [2022-07-12 18:39:50,787 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-12 18:39:50,787 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2022-07-12 18:39:50,787 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=86, Invalid=514, Unknown=0, NotChecked=0, Total=600 [2022-07-12 18:39:50,788 INFO L87 Difference]: Start difference. First operand 170 states and 210 transitions. Second operand has 25 states, 24 states have (on average 1.375) internal successors, (33), 25 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:51,482 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-12 18:39:51,482 INFO L93 Difference]: Finished difference Result 282 states and 313 transitions. [2022-07-12 18:39:51,483 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2022-07-12 18:39:51,483 INFO L78 Accepts]: Start accepts. Automaton has has 25 states, 24 states have (on average 1.375) internal successors, (33), 25 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 33 [2022-07-12 18:39:51,484 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-07-12 18:39:51,484 INFO L225 Difference]: With dead ends: 282 [2022-07-12 18:39:51,484 INFO L226 Difference]: Without dead ends: 282 [2022-07-12 18:39:51,485 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 41 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 266 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=273, Invalid=1449, Unknown=0, NotChecked=0, Total=1722 [2022-07-12 18:39:51,485 INFO L413 NwaCegarLoop]: 81 mSDtfsCounter, 1000 mSDsluCounter, 1197 mSDsCounter, 0 mSdLazyCounter, 1045 mSolverCounterSat, 68 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1000 SdHoareTripleChecker+Valid, 1278 SdHoareTripleChecker+Invalid, 1113 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 68 IncrementalHoareTripleChecker+Valid, 1045 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2022-07-12 18:39:51,485 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [1000 Valid, 1278 Invalid, 1113 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [68 Valid, 1045 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2022-07-12 18:39:51,486 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 282 states. [2022-07-12 18:39:51,487 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 282 to 183. [2022-07-12 18:39:51,488 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 183 states, 150 states have (on average 1.5333333333333334) internal successors, (230), 182 states have internal predecessors, (230), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:51,488 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 183 states to 183 states and 230 transitions. [2022-07-12 18:39:51,488 INFO L78 Accepts]: Start accepts. Automaton has 183 states and 230 transitions. Word has length 33 [2022-07-12 18:39:51,488 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-07-12 18:39:51,488 INFO L495 AbstractCegarLoop]: Abstraction has 183 states and 230 transitions. [2022-07-12 18:39:51,489 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 25 states, 24 states have (on average 1.375) internal successors, (33), 25 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:51,489 INFO L276 IsEmpty]: Start isEmpty. Operand 183 states and 230 transitions. [2022-07-12 18:39:51,489 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2022-07-12 18:39:51,489 INFO L187 NwaCegarLoop]: Found error trace [2022-07-12 18:39:51,489 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-12 18:39:51,489 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable26 [2022-07-12 18:39:51,489 INFO L420 AbstractCegarLoop]: === Iteration 28 === Targeting ULTIMATE.startErr78ASSERT_VIOLATIONMEMORY_FREE === [ULTIMATE.startErr0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 82 more)] === [2022-07-12 18:39:51,490 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-12 18:39:51,490 INFO L85 PathProgramCache]: Analyzing trace with hash 451934574, now seen corresponding path program 1 times [2022-07-12 18:39:51,490 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-12 18:39:51,490 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1716089773] [2022-07-12 18:39:51,490 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-12 18:39:51,490 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-12 18:39:51,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-12 18:39:51,769 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-12 18:39:51,769 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-12 18:39:51,769 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1716089773] [2022-07-12 18:39:51,769 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1716089773] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-12 18:39:51,769 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-12 18:39:51,769 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [22] imperfect sequences [] total 22 [2022-07-12 18:39:51,769 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1662852762] [2022-07-12 18:39:51,769 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-12 18:39:51,769 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 23 states [2022-07-12 18:39:51,770 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-12 18:39:51,770 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2022-07-12 18:39:51,770 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=81, Invalid=425, Unknown=0, NotChecked=0, Total=506 [2022-07-12 18:39:51,770 INFO L87 Difference]: Start difference. First operand 183 states and 230 transitions. Second operand has 23 states, 22 states have (on average 1.5454545454545454) internal successors, (34), 23 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:52,203 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-12 18:39:52,203 INFO L93 Difference]: Finished difference Result 238 states and 292 transitions. [2022-07-12 18:39:52,203 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2022-07-12 18:39:52,204 INFO L78 Accepts]: Start accepts. Automaton has has 23 states, 22 states have (on average 1.5454545454545454) internal successors, (34), 23 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 34 [2022-07-12 18:39:52,204 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-07-12 18:39:52,205 INFO L225 Difference]: With dead ends: 238 [2022-07-12 18:39:52,205 INFO L226 Difference]: Without dead ends: 238 [2022-07-12 18:39:52,205 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 37 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 207 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=234, Invalid=1172, Unknown=0, NotChecked=0, Total=1406 [2022-07-12 18:39:52,206 INFO L413 NwaCegarLoop]: 84 mSDtfsCounter, 405 mSDsluCounter, 695 mSDsCounter, 0 mSdLazyCounter, 510 mSolverCounterSat, 69 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 405 SdHoareTripleChecker+Valid, 779 SdHoareTripleChecker+Invalid, 579 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 69 IncrementalHoareTripleChecker+Valid, 510 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-07-12 18:39:52,206 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [405 Valid, 779 Invalid, 579 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [69 Valid, 510 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-07-12 18:39:52,206 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 238 states. [2022-07-12 18:39:52,209 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 238 to 186. [2022-07-12 18:39:52,209 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 186 states, 153 states have (on average 1.522875816993464) internal successors, (233), 185 states have internal predecessors, (233), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:52,209 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 233 transitions. [2022-07-12 18:39:52,209 INFO L78 Accepts]: Start accepts. Automaton has 186 states and 233 transitions. Word has length 34 [2022-07-12 18:39:52,210 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-07-12 18:39:52,210 INFO L495 AbstractCegarLoop]: Abstraction has 186 states and 233 transitions. [2022-07-12 18:39:52,210 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 23 states, 22 states have (on average 1.5454545454545454) internal successors, (34), 23 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:39:52,210 INFO L276 IsEmpty]: Start isEmpty. Operand 186 states and 233 transitions. [2022-07-12 18:39:52,210 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2022-07-12 18:39:52,210 INFO L187 NwaCegarLoop]: Found error trace [2022-07-12 18:39:52,210 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-12 18:39:52,210 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable27 [2022-07-12 18:39:52,211 INFO L420 AbstractCegarLoop]: === Iteration 29 === Targeting ULTIMATE.startErr32REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 82 more)] === [2022-07-12 18:39:52,211 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-12 18:39:52,211 INFO L85 PathProgramCache]: Analyzing trace with hash 1606811227, now seen corresponding path program 1 times [2022-07-12 18:39:52,211 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-12 18:39:52,211 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1031864125] [2022-07-12 18:39:52,211 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-12 18:39:52,211 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-12 18:39:52,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-12 18:39:52,952 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-12 18:39:52,952 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-12 18:39:52,952 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1031864125] [2022-07-12 18:39:52,952 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1031864125] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-12 18:39:52,952 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1616641861] [2022-07-12 18:39:52,952 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-12 18:39:52,952 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-12 18:39:52,952 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-12 18:39:52,964 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-12 18:39:52,967 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-07-12 18:39:53,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-12 18:39:53,102 INFO L263 TraceCheckSpWp]: Trace formula consists of 310 conjuncts, 86 conjunts are in the unsatisfiable core [2022-07-12 18:39:53,118 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-12 18:39:53,188 INFO L356 Elim1Store]: treesize reduction 15, result has 25.0 percent of original size [2022-07-12 18:39:53,189 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 19 treesize of output 18 [2022-07-12 18:39:53,229 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2022-07-12 18:39:53,300 INFO L356 Elim1Store]: treesize reduction 48, result has 36.0 percent of original size [2022-07-12 18:39:53,301 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 1 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 4 case distinctions, treesize of input 26 treesize of output 41 [2022-07-12 18:39:53,341 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-07-12 18:39:53,342 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 39 treesize of output 30 [2022-07-12 18:39:53,662 INFO L356 Elim1Store]: treesize reduction 15, result has 25.0 percent of original size [2022-07-12 18:39:53,662 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 81 [2022-07-12 18:39:53,667 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 20 [2022-07-12 18:39:53,748 INFO L356 Elim1Store]: treesize reduction 15, result has 25.0 percent of original size [2022-07-12 18:39:53,749 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 89 treesize of output 76 [2022-07-12 18:39:53,753 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 20 [2022-07-12 18:39:53,832 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-07-12 18:39:53,848 INFO L356 Elim1Store]: treesize reduction 78, result has 17.9 percent of original size [2022-07-12 18:39:53,848 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 3 new quantified variables, introduced 2 case distinctions, treesize of input 94 treesize of output 61 [2022-07-12 18:39:53,852 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 93 treesize of output 89 [2022-07-12 18:39:54,136 INFO L356 Elim1Store]: treesize reduction 36, result has 23.4 percent of original size [2022-07-12 18:39:54,136 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 4 new quantified variables, introduced 3 case distinctions, treesize of input 142 treesize of output 119 [2022-07-12 18:39:54,146 INFO L356 Elim1Store]: treesize reduction 27, result has 15.6 percent of original size [2022-07-12 18:39:54,146 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 95 treesize of output 91 [2022-07-12 18:39:54,188 INFO L356 Elim1Store]: treesize reduction 36, result has 23.4 percent of original size [2022-07-12 18:39:54,189 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 4 new quantified variables, introduced 3 case distinctions, treesize of input 133 treesize of output 112 [2022-07-12 18:39:54,199 INFO L356 Elim1Store]: treesize reduction 27, result has 15.6 percent of original size [2022-07-12 18:39:54,199 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 95 treesize of output 91 [2022-07-12 18:39:54,231 INFO L356 Elim1Store]: treesize reduction 36, result has 23.4 percent of original size [2022-07-12 18:39:54,231 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 4 new quantified variables, introduced 3 case distinctions, treesize of input 124 treesize of output 105 [2022-07-12 18:39:54,240 INFO L356 Elim1Store]: treesize reduction 27, result has 15.6 percent of original size [2022-07-12 18:39:54,240 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 95 treesize of output 91 [2022-07-12 18:39:54,427 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 88 treesize of output 68 [2022-07-12 18:39:54,644 INFO L356 Elim1Store]: treesize reduction 28, result has 3.4 percent of original size [2022-07-12 18:39:54,644 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 1 disjoint index pairs (out of 3 index pairs), introduced 4 new quantified variables, introduced 2 case distinctions, treesize of input 95 treesize of output 32 [2022-07-12 18:39:54,743 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-12 18:39:54,743 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-12 18:39:54,962 WARN L833 $PredicateComparison]: unable to prove that (forall ((v_ArrVal_1284 (Array Int Int)) (v_ArrVal_1283 (Array Int Int))) (= (select |c_#valid| (select (let ((.cse0 (store |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~mem11#1.base| v_ArrVal_1284))) (select .cse0 (select (select .cse0 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|))) (+ 8 (select (select (store |c_#memory_$Pointer$.offset| |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~mem11#1.base| v_ArrVal_1283) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|)))) 1)) is different from false [2022-07-12 18:39:55,478 WARN L833 $PredicateComparison]: unable to prove that (forall ((v_ArrVal_1284 (Array Int Int)) (v_ArrVal_1283 (Array Int Int))) (= 1 (select |c_#valid| (let ((.cse1 (select (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4)))) (select (let ((.cse0 (store |c_#memory_$Pointer$.base| .cse1 v_ArrVal_1284))) (select .cse0 (select (select .cse0 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|))) (+ 8 (select (select (store |c_#memory_$Pointer$.offset| .cse1 v_ArrVal_1283) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|))))))) is different from false [2022-07-12 18:39:55,489 WARN L833 $PredicateComparison]: unable to prove that (forall ((v_ArrVal_1278 (Array Int Int)) (v_ArrVal_1284 (Array Int Int)) (v_ArrVal_1283 (Array Int Int))) (= (select |c_#valid| (let ((.cse1 (store |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~mem7#1.base| (store (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~mem7#1.base|) (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~mem7#1.offset| 8) |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~mem10#1.base|)))) (let ((.cse2 (select (select .cse1 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4)))) (select (let ((.cse0 (store .cse1 .cse2 v_ArrVal_1284))) (select .cse0 (select (select .cse0 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|))) (+ (select (select (store (store |c_#memory_$Pointer$.offset| |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~mem7#1.base| v_ArrVal_1278) .cse2 v_ArrVal_1283) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|) 8))))) 1)) is different from false [2022-07-12 18:39:55,515 WARN L833 $PredicateComparison]: unable to prove that (forall ((v_ArrVal_1278 (Array Int Int)) (v_ArrVal_1275 (Array Int Int)) (v_ArrVal_1274 (Array Int Int)) (v_ArrVal_1284 (Array Int Int)) (v_ArrVal_1283 (Array Int Int))) (= (select |c_#valid| (let ((.cse1 (let ((.cse3 (store |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~mem8#1.base| v_ArrVal_1275))) (store .cse3 |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~mem7#1.base| (store (select .cse3 |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~mem7#1.base|) (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~mem7#1.offset| 8) |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~mem10#1.base|))))) (let ((.cse2 (select (select .cse1 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4)))) (select (let ((.cse0 (store .cse1 .cse2 v_ArrVal_1284))) (select .cse0 (select (select .cse0 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|))) (+ (select (select (store (store (store |c_#memory_$Pointer$.offset| |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~mem8#1.base| v_ArrVal_1274) |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~mem7#1.base| v_ArrVal_1278) .cse2 v_ArrVal_1283) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|) 8))))) 1)) is different from false [2022-07-12 18:39:55,524 WARN L833 $PredicateComparison]: unable to prove that (forall ((v_ArrVal_1278 (Array Int Int)) (v_ArrVal_1275 (Array Int Int)) (v_ArrVal_1274 (Array Int Int)) (v_ArrVal_1273 (Array Int Int)) (v_ArrVal_1284 (Array Int Int)) (v_ArrVal_1272 (Array Int Int)) (v_ArrVal_1283 (Array Int Int))) (= (select |c_#valid| (let ((.cse1 (let ((.cse3 (store (store |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~mem9#1.base| v_ArrVal_1272) |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~mem8#1.base| v_ArrVal_1275))) (store .cse3 |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~mem7#1.base| (store (select .cse3 |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~mem7#1.base|) (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~mem7#1.offset| 8) |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~mem10#1.base|))))) (let ((.cse2 (select (select .cse1 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4)))) (select (let ((.cse0 (store .cse1 .cse2 v_ArrVal_1284))) (select .cse0 (select (select .cse0 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|))) (+ 8 (select (select (store (store (store (store |c_#memory_$Pointer$.offset| |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~mem9#1.base| v_ArrVal_1273) |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~mem8#1.base| v_ArrVal_1274) |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~mem7#1.base| v_ArrVal_1278) .cse2 v_ArrVal_1283) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|)))))) 1)) is different from false [2022-07-12 18:39:55,533 WARN L833 $PredicateComparison]: unable to prove that (forall ((v_ArrVal_1278 (Array Int Int)) (v_ArrVal_1275 (Array Int Int)) (v_ArrVal_1274 (Array Int Int)) (v_ArrVal_1273 (Array Int Int)) (v_ArrVal_1284 (Array Int Int)) (v_ArrVal_1272 (Array Int Int)) (v_ArrVal_1283 (Array Int Int))) (= (select |c_#valid| (let ((.cse3 (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4))) (let ((.cse1 (let ((.cse4 (store (store |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~mem9#1.base| v_ArrVal_1272) |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~mem8#1.base| v_ArrVal_1275))) (store .cse4 |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~mem7#1.base| (store (select .cse4 |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~mem7#1.base|) (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~mem7#1.offset| 8) (select (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) .cse3)))))) (let ((.cse2 (select (select .cse1 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) .cse3))) (select (let ((.cse0 (store .cse1 .cse2 v_ArrVal_1284))) (select .cse0 (select (select .cse0 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|))) (+ (select (select (store (store (store (store |c_#memory_$Pointer$.offset| |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~mem9#1.base| v_ArrVal_1273) |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~mem8#1.base| v_ArrVal_1274) |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~mem7#1.base| v_ArrVal_1278) .cse2 v_ArrVal_1283) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|) 8)))))) 1)) is different from false [2022-07-12 18:39:55,564 WARN L833 $PredicateComparison]: unable to prove that (forall ((v_ArrVal_1278 (Array Int Int)) (v_ArrVal_1275 (Array Int Int)) (v_ArrVal_1274 (Array Int Int)) (v_ArrVal_1273 (Array Int Int)) (v_ArrVal_1284 (Array Int Int)) (v_ArrVal_1272 (Array Int Int)) (v_ArrVal_1283 (Array Int Int))) (= (select |c_#valid| (let ((.cse6 (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|))) (let ((.cse4 (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4)) (.cse3 (select .cse6 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|))) (let ((.cse1 (let ((.cse5 (store (store |c_#memory_$Pointer$.base| .cse3 v_ArrVal_1272) |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~mem8#1.base| v_ArrVal_1275))) (store .cse5 |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~mem7#1.base| (store (select .cse5 |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~mem7#1.base|) (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~mem7#1.offset| 8) (select .cse6 .cse4)))))) (let ((.cse2 (select (select .cse1 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) .cse4))) (select (let ((.cse0 (store .cse1 .cse2 v_ArrVal_1284))) (select .cse0 (select (select .cse0 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|))) (+ 8 (select (select (store (store (store (store |c_#memory_$Pointer$.offset| .cse3 v_ArrVal_1273) |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~mem8#1.base| v_ArrVal_1274) |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~mem7#1.base| v_ArrVal_1278) .cse2 v_ArrVal_1283) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|)))))))) 1)) is different from false [2022-07-12 18:39:55,577 WARN L833 $PredicateComparison]: unable to prove that (forall ((v_ArrVal_1278 (Array Int Int)) (v_ArrVal_1275 (Array Int Int)) (v_ArrVal_1274 (Array Int Int)) (v_ArrVal_1284 (Array Int Int)) (v_ArrVal_1283 (Array Int Int))) (= (select |c_#valid| (let ((.cse6 (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|))) (let ((.cse4 (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4)) (.cse3 (select .cse6 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|))) (let ((.cse1 (let ((.cse5 (store |c_#memory_$Pointer$.base| .cse3 v_ArrVal_1275))) (store .cse5 |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~mem7#1.base| (store (select .cse5 |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~mem7#1.base|) (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~mem7#1.offset| 8) (select .cse6 .cse4)))))) (let ((.cse2 (select (select .cse1 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) .cse4))) (select (let ((.cse0 (store .cse1 .cse2 v_ArrVal_1284))) (select .cse0 (select (select .cse0 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|))) (+ 8 (select (select (store (store (store |c_#memory_$Pointer$.offset| .cse3 v_ArrVal_1274) |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~mem7#1.base| v_ArrVal_1278) .cse2 v_ArrVal_1283) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|)))))))) 1)) is different from false [2022-07-12 18:39:55,581 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 644 treesize of output 560 [2022-07-12 18:39:55,585 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-07-12 18:39:55,585 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 560 treesize of output 354 [2022-07-12 18:39:55,588 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 170 treesize of output 168 [2022-07-12 18:39:55,592 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 338 treesize of output 334 [2022-07-12 18:39:55,758 WARN L833 $PredicateComparison]: unable to prove that (let ((.cse5 (forall ((v_arrayElimArr_1 (Array Int Int)) (v_arrayElimCell_26 Int)) (let ((.cse39 (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|)) (.cse40 (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4))) (or (not (= (select (select (store |c_#memory_$Pointer$.base| (select .cse39 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|) v_arrayElimArr_1) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) .cse40) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|)) (forall ((v_arrayElimCell_28 Int) (v_ArrVal_1284 (Array Int Int))) (= (select |c_#valid| (select (let ((.cse41 (let ((.cse42 (store |c_#memory_$Pointer$.base| (select (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|) v_arrayElimArr_1))) (store .cse42 (select (select .cse42 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4)) v_ArrVal_1284)))) (select .cse41 (select (select .cse41 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|))) (+ 8 v_arrayElimCell_28))) 1)) (not (= (select v_arrayElimArr_1 (+ 8 v_arrayElimCell_26)) (select .cse39 .cse40))))))) (.cse11 (= (select (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|))) (and (forall ((v_arrayElimArr_1 (Array Int Int)) (v_arrayElimCell_26 Int)) (let ((.cse3 (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|)) (.cse4 (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4))) (or (forall ((v_arrayElimCell_27 Int) (v_ArrVal_1284 (Array Int Int))) (let ((.cse0 (let ((.cse1 (let ((.cse2 (store |c_#memory_$Pointer$.base| (select (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|) v_arrayElimArr_1))) (store .cse2 (select (select .cse2 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4)) v_ArrVal_1284)))) (select .cse1 (select (select .cse1 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|))))) (or (= (select |c_#valid| (select .cse0 (+ 8 v_arrayElimCell_26))) 1) (= (select |c_#valid| (select .cse0 (+ 8 v_arrayElimCell_27))) 1)))) (not (= (select v_arrayElimArr_1 (+ 8 v_arrayElimCell_26)) (select .cse3 .cse4))) (= (select (select (store |c_#memory_$Pointer$.base| (select .cse3 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|) v_arrayElimArr_1) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) .cse4) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|)))) .cse5 (forall ((v_arrayElimArr_1 (Array Int Int)) (v_arrayElimCell_26 Int)) (let ((.cse6 (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|)) (.cse7 (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4))) (or (not (= (select (select (store |c_#memory_$Pointer$.base| (select .cse6 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|) v_arrayElimArr_1) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) .cse7) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|)) (not (= (select v_arrayElimArr_1 (+ 8 v_arrayElimCell_26)) (select .cse6 .cse7))) (forall ((v_arrayElimCell_28 Int) (v_ArrVal_1284 (Array Int Int))) (let ((.cse8 (let ((.cse9 (let ((.cse10 (store |c_#memory_$Pointer$.base| (select (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|) v_arrayElimArr_1))) (store .cse10 (select (select .cse10 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4)) v_ArrVal_1284)))) (select .cse9 (select (select .cse9 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|))))) (or (= (select |c_#valid| (select .cse8 (+ 8 v_arrayElimCell_28))) 1) (= (select |c_#valid| (select .cse8 (+ 8 v_arrayElimCell_26))) 1))))))) (or (not .cse11) (and (forall ((v_arrayElimArr_1 (Array Int Int)) (v_arrayElimCell_26 Int)) (let ((.cse12 (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|)) (.cse13 (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4))) (or (not (= (select v_arrayElimArr_1 (+ 8 v_arrayElimCell_26)) (select .cse12 .cse13))) (= (select (select (store |c_#memory_$Pointer$.base| (select .cse12 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|) v_arrayElimArr_1) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) .cse13) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) (forall ((v_arrayElimCell_27 Int) (v_ArrVal_1284 (Array Int Int))) (= (select |c_#valid| (select (let ((.cse14 (let ((.cse15 (store |c_#memory_$Pointer$.base| (select (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|) v_arrayElimArr_1))) (store .cse15 (select (select .cse15 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4)) v_ArrVal_1284)))) (select .cse14 (select (select .cse14 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|))) (+ 8 v_arrayElimCell_27))) 1))))) .cse5 (forall ((v_arrayElimArr_1 (Array Int Int)) (v_arrayElimCell_26 Int)) (or (not (= (select v_arrayElimArr_1 (+ 8 v_arrayElimCell_26)) (select (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4)))) (forall ((v_arrayElimCell_27 Int) (v_ArrVal_1284 (Array Int Int))) (or (forall ((v_arrayElimCell_28 Int)) (= (select |c_#valid| (select (let ((.cse16 (let ((.cse17 (store |c_#memory_$Pointer$.base| (select (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|) v_arrayElimArr_1))) (store .cse17 (select (select .cse17 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4)) v_ArrVal_1284)))) (select .cse16 (select (select .cse16 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|))) (+ 8 v_arrayElimCell_28))) 1)) (= (select |c_#valid| (select (let ((.cse18 (let ((.cse19 (store |c_#memory_$Pointer$.base| (select (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|) v_arrayElimArr_1))) (store .cse19 (select (select .cse19 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4)) v_ArrVal_1284)))) (select .cse18 (select (select .cse18 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|))) (+ 8 v_arrayElimCell_27))) 1))))))) (forall ((v_arrayElimArr_1 (Array Int Int)) (v_arrayElimCell_26 Int)) (or (forall ((v_arrayElimCell_27 Int) (v_ArrVal_1284 (Array Int Int))) (let ((.cse22 (let ((.cse23 (let ((.cse24 (store |c_#memory_$Pointer$.base| (select (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|) v_arrayElimArr_1))) (store .cse24 (select (select .cse24 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4)) v_ArrVal_1284)))) (select .cse23 (select (select .cse23 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|))))) (or (forall ((v_arrayElimCell_28 Int)) (= (select |c_#valid| (select (let ((.cse20 (let ((.cse21 (store |c_#memory_$Pointer$.base| (select (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|) v_arrayElimArr_1))) (store .cse21 (select (select .cse21 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4)) v_ArrVal_1284)))) (select .cse20 (select (select .cse20 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|))) (+ 8 v_arrayElimCell_28))) 1)) (= (select |c_#valid| (select .cse22 (+ 8 v_arrayElimCell_26))) 1) (= (select |c_#valid| (select .cse22 (+ 8 v_arrayElimCell_27))) 1)))) (not (= (select v_arrayElimArr_1 (+ 8 v_arrayElimCell_26)) (select (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4)))))) (or (and (forall ((v_arrayElimArr_1 (Array Int Int)) (v_arrayElimCell_26 Int)) (let ((.cse25 (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|)) (.cse26 (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4))) (or (not (= (select v_arrayElimArr_1 (+ 8 v_arrayElimCell_26)) (select .cse25 .cse26))) (= (select (select (store |c_#memory_$Pointer$.base| (select .cse25 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|) v_arrayElimArr_1) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) .cse26) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) (forall ((v_ArrVal_1284 (Array Int Int))) (= (select |c_#valid| (select (let ((.cse27 (let ((.cse28 (store |c_#memory_$Pointer$.base| (select (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|) v_arrayElimArr_1))) (store .cse28 (select (select .cse28 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4)) v_ArrVal_1284)))) (select .cse27 (select (select .cse27 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|))) (+ 8 v_arrayElimCell_26))) 1))))) (forall ((v_arrayElimArr_1 (Array Int Int)) (v_arrayElimCell_26 Int)) (or (not (= (select v_arrayElimArr_1 (+ 8 v_arrayElimCell_26)) (select (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4)))) (forall ((v_ArrVal_1284 (Array Int Int))) (or (forall ((v_arrayElimCell_28 Int)) (= (select |c_#valid| (select (let ((.cse29 (let ((.cse30 (store |c_#memory_$Pointer$.base| (select (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|) v_arrayElimArr_1))) (store .cse30 (select (select .cse30 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4)) v_ArrVal_1284)))) (select .cse29 (select (select .cse29 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|))) (+ 8 v_arrayElimCell_28))) 1)) (= (select |c_#valid| (select (let ((.cse31 (let ((.cse32 (store |c_#memory_$Pointer$.base| (select (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|) v_arrayElimArr_1))) (store .cse32 (select (select .cse32 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4)) v_ArrVal_1284)))) (select .cse31 (select (select .cse31 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|))) (+ 8 v_arrayElimCell_26))) 1)))))) .cse11) (forall ((v_arrayElimArr_1 (Array Int Int)) (v_arrayElimCell_26 Int)) (let ((.cse33 (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|)) (.cse34 (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4))) (or (not (= (select (select (store |c_#memory_$Pointer$.base| (select .cse33 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|) v_arrayElimArr_1) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) .cse34) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|)) (not (= (select v_arrayElimArr_1 (+ 8 v_arrayElimCell_26)) (select .cse33 .cse34))) (forall ((v_arrayElimCell_27 Int) (v_ArrVal_1284 (Array Int Int))) (or (forall ((v_arrayElimCell_28 Int)) (= (select |c_#valid| (select (let ((.cse35 (let ((.cse36 (store |c_#memory_$Pointer$.base| (select (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|) v_arrayElimArr_1))) (store .cse36 (select (select .cse36 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4)) v_ArrVal_1284)))) (select .cse35 (select (select .cse35 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|))) (+ 8 v_arrayElimCell_28))) 1)) (= (select |c_#valid| (select (let ((.cse37 (let ((.cse38 (store |c_#memory_$Pointer$.base| (select (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|) v_arrayElimArr_1))) (store .cse38 (select (select .cse38 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4)) v_ArrVal_1284)))) (select .cse37 (select (select .cse37 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|))) (+ 8 v_arrayElimCell_27))) 1)))))))) is different from false [2022-07-12 18:39:55,975 WARN L833 $PredicateComparison]: unable to prove that (let ((.cse26 (forall ((v_arrayElimArr_1 (Array Int Int)) (v_arrayElimCell_26 Int)) (or (not (= (let ((.cse64 (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4))) (select (select (let ((.cse63 (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|))) (store (store |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base| (store .cse63 .cse64 |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~malloc6#1.base|)) (select .cse63 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|) v_arrayElimArr_1)) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) .cse64)) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|)) (forall ((v_arrayElimCell_28 Int) (v_ArrVal_1284 (Array Int Int))) (= (select |c_#valid| (select (let ((.cse65 (let ((.cse67 (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4))) (let ((.cse66 (let ((.cse68 (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|))) (store (store |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base| (store .cse68 .cse67 |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~malloc6#1.base|)) (select .cse68 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|) v_arrayElimArr_1)))) (store .cse66 (select (select .cse66 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) .cse67) v_ArrVal_1284))))) (select .cse65 (select (select .cse65 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|))) (+ 8 v_arrayElimCell_28))) 1)) (not (= (select v_arrayElimArr_1 (+ 8 v_arrayElimCell_26)) |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~malloc6#1.base|))))) (.cse34 (= (select (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|))) (and (forall ((v_arrayElimArr_1 (Array Int Int)) (v_arrayElimCell_26 Int)) (or (forall ((v_arrayElimCell_27 Int) (v_ArrVal_1284 (Array Int Int))) (let ((.cse0 (let ((.cse1 (let ((.cse3 (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4))) (let ((.cse2 (let ((.cse4 (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|))) (store (store |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base| (store .cse4 .cse3 |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~malloc6#1.base|)) (select .cse4 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|) v_arrayElimArr_1)))) (store .cse2 (select (select .cse2 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) .cse3) v_ArrVal_1284))))) (select .cse1 (select (select .cse1 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|))))) (or (= (select |c_#valid| (select .cse0 (+ 8 v_arrayElimCell_27))) 1) (= (select |c_#valid| (select .cse0 (+ 8 v_arrayElimCell_26))) 1)))) (= (let ((.cse6 (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4))) (select (select (let ((.cse5 (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|))) (store (store |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base| (store .cse5 .cse6 |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~malloc6#1.base|)) (select .cse5 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|) v_arrayElimArr_1)) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) .cse6)) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) (not (= (select v_arrayElimArr_1 (+ 8 v_arrayElimCell_26)) |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~malloc6#1.base|)))) (forall ((v_arrayElimArr_1 (Array Int Int)) (v_arrayElimCell_26 Int)) (or (not (= (let ((.cse8 (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4))) (select (select (let ((.cse7 (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|))) (store (store |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base| (store .cse7 .cse8 |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~malloc6#1.base|)) (select .cse7 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|) v_arrayElimArr_1)) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) .cse8)) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|)) (forall ((v_arrayElimCell_27 Int) (v_ArrVal_1284 (Array Int Int))) (or (= (select |c_#valid| (select (let ((.cse9 (let ((.cse11 (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4))) (let ((.cse10 (let ((.cse12 (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|))) (store (store |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base| (store .cse12 .cse11 |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~malloc6#1.base|)) (select .cse12 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|) v_arrayElimArr_1)))) (store .cse10 (select (select .cse10 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) .cse11) v_ArrVal_1284))))) (select .cse9 (select (select .cse9 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|))) (+ 8 v_arrayElimCell_27))) 1) (forall ((v_arrayElimCell_28 Int)) (= (select |c_#valid| (select (let ((.cse13 (let ((.cse15 (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4))) (let ((.cse14 (let ((.cse16 (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|))) (store (store |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base| (store .cse16 .cse15 |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~malloc6#1.base|)) (select .cse16 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|) v_arrayElimArr_1)))) (store .cse14 (select (select .cse14 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) .cse15) v_ArrVal_1284))))) (select .cse13 (select (select .cse13 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|))) (+ 8 v_arrayElimCell_28))) 1)))) (not (= (select v_arrayElimArr_1 (+ 8 v_arrayElimCell_26)) |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~malloc6#1.base|)))) (forall ((v_arrayElimArr_1 (Array Int Int)) (v_arrayElimCell_26 Int)) (or (forall ((v_arrayElimCell_27 Int) (v_ArrVal_1284 (Array Int Int))) (let ((.cse17 (let ((.cse22 (let ((.cse24 (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4))) (let ((.cse23 (let ((.cse25 (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|))) (store (store |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base| (store .cse25 .cse24 |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~malloc6#1.base|)) (select .cse25 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|) v_arrayElimArr_1)))) (store .cse23 (select (select .cse23 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) .cse24) v_ArrVal_1284))))) (select .cse22 (select (select .cse22 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|))))) (or (= (select |c_#valid| (select .cse17 (+ 8 v_arrayElimCell_27))) 1) (forall ((v_arrayElimCell_28 Int)) (= (select |c_#valid| (select (let ((.cse18 (let ((.cse20 (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4))) (let ((.cse19 (let ((.cse21 (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|))) (store (store |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base| (store .cse21 .cse20 |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~malloc6#1.base|)) (select .cse21 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|) v_arrayElimArr_1)))) (store .cse19 (select (select .cse19 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) .cse20) v_ArrVal_1284))))) (select .cse18 (select (select .cse18 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|))) (+ 8 v_arrayElimCell_28))) 1)) (= (select |c_#valid| (select .cse17 (+ 8 v_arrayElimCell_26))) 1)))) (not (= (select v_arrayElimArr_1 (+ 8 v_arrayElimCell_26)) |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~malloc6#1.base|)))) .cse26 (forall ((v_arrayElimArr_1 (Array Int Int)) (v_arrayElimCell_26 Int)) (or (forall ((v_arrayElimCell_28 Int) (v_ArrVal_1284 (Array Int Int))) (let ((.cse27 (let ((.cse28 (let ((.cse30 (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4))) (let ((.cse29 (let ((.cse31 (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|))) (store (store |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base| (store .cse31 .cse30 |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~malloc6#1.base|)) (select .cse31 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|) v_arrayElimArr_1)))) (store .cse29 (select (select .cse29 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) .cse30) v_ArrVal_1284))))) (select .cse28 (select (select .cse28 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|))))) (or (= (select |c_#valid| (select .cse27 (+ 8 v_arrayElimCell_28))) 1) (= (select |c_#valid| (select .cse27 (+ 8 v_arrayElimCell_26))) 1)))) (not (= (let ((.cse33 (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4))) (select (select (let ((.cse32 (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|))) (store (store |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base| (store .cse32 .cse33 |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~malloc6#1.base|)) (select .cse32 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|) v_arrayElimArr_1)) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) .cse33)) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|)) (not (= (select v_arrayElimArr_1 (+ 8 v_arrayElimCell_26)) |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~malloc6#1.base|)))) (or .cse34 (and (forall ((v_arrayElimArr_1 (Array Int Int)) (v_arrayElimCell_26 Int)) (or (not (= (select v_arrayElimArr_1 (+ 8 v_arrayElimCell_26)) |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~malloc6#1.base|)) (forall ((v_ArrVal_1284 (Array Int Int))) (or (forall ((v_arrayElimCell_28 Int)) (= (select |c_#valid| (select (let ((.cse35 (let ((.cse37 (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4))) (let ((.cse36 (let ((.cse38 (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|))) (store (store |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base| (store .cse38 .cse37 |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~malloc6#1.base|)) (select .cse38 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|) v_arrayElimArr_1)))) (store .cse36 (select (select .cse36 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) .cse37) v_ArrVal_1284))))) (select .cse35 (select (select .cse35 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|))) (+ 8 v_arrayElimCell_28))) 1)) (= (select |c_#valid| (select (let ((.cse39 (let ((.cse41 (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4))) (let ((.cse40 (let ((.cse42 (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|))) (store (store |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base| (store .cse42 .cse41 |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~malloc6#1.base|)) (select .cse42 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|) v_arrayElimArr_1)))) (store .cse40 (select (select .cse40 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) .cse41) v_ArrVal_1284))))) (select .cse39 (select (select .cse39 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|))) (+ 8 v_arrayElimCell_26))) 1))))) (forall ((v_arrayElimArr_1 (Array Int Int)) (v_arrayElimCell_26 Int)) (or (= (let ((.cse44 (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4))) (select (select (let ((.cse43 (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|))) (store (store |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base| (store .cse43 .cse44 |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~malloc6#1.base|)) (select .cse43 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|) v_arrayElimArr_1)) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) .cse44)) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) (forall ((v_ArrVal_1284 (Array Int Int))) (= (select |c_#valid| (select (let ((.cse45 (let ((.cse47 (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4))) (let ((.cse46 (let ((.cse48 (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|))) (store (store |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base| (store .cse48 .cse47 |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~malloc6#1.base|)) (select .cse48 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|) v_arrayElimArr_1)))) (store .cse46 (select (select .cse46 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) .cse47) v_ArrVal_1284))))) (select .cse45 (select (select .cse45 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|))) (+ 8 v_arrayElimCell_26))) 1)) (not (= (select v_arrayElimArr_1 (+ 8 v_arrayElimCell_26)) |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~malloc6#1.base|)))))) (or (and .cse26 (forall ((v_arrayElimArr_1 (Array Int Int)) (v_arrayElimCell_26 Int)) (or (forall ((v_arrayElimCell_27 Int) (v_ArrVal_1284 (Array Int Int))) (= (select |c_#valid| (select (let ((.cse49 (let ((.cse51 (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4))) (let ((.cse50 (let ((.cse52 (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|))) (store (store |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base| (store .cse52 .cse51 |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~malloc6#1.base|)) (select .cse52 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|) v_arrayElimArr_1)))) (store .cse50 (select (select .cse50 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) .cse51) v_ArrVal_1284))))) (select .cse49 (select (select .cse49 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|))) (+ 8 v_arrayElimCell_27))) 1)) (= (let ((.cse54 (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4))) (select (select (let ((.cse53 (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|))) (store (store |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base| (store .cse53 .cse54 |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~malloc6#1.base|)) (select .cse53 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|) v_arrayElimArr_1)) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) .cse54)) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) (not (= (select v_arrayElimArr_1 (+ 8 v_arrayElimCell_26)) |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~malloc6#1.base|)))) (forall ((v_arrayElimArr_1 (Array Int Int)) (v_arrayElimCell_26 Int)) (or (forall ((v_arrayElimCell_27 Int) (v_ArrVal_1284 (Array Int Int))) (or (= (select |c_#valid| (select (let ((.cse55 (let ((.cse57 (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4))) (let ((.cse56 (let ((.cse58 (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|))) (store (store |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base| (store .cse58 .cse57 |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~malloc6#1.base|)) (select .cse58 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|) v_arrayElimArr_1)))) (store .cse56 (select (select .cse56 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) .cse57) v_ArrVal_1284))))) (select .cse55 (select (select .cse55 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|))) (+ 8 v_arrayElimCell_27))) 1) (forall ((v_arrayElimCell_28 Int)) (= (select |c_#valid| (select (let ((.cse59 (let ((.cse61 (+ |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset| 4))) (let ((.cse60 (let ((.cse62 (select |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|))) (store (store |c_#memory_$Pointer$.base| |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base| (store .cse62 .cse61 |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~malloc6#1.base|)) (select .cse62 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|) v_arrayElimArr_1)))) (store .cse60 (select (select .cse60 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) .cse61) v_ArrVal_1284))))) (select .cse59 (select (select .cse59 |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.base|) |c_ULTIMATE.start_create_sl_with_head_and_tail_~sl~0#1.offset|))) (+ 8 v_arrayElimCell_28))) 1)))) (not (= (select v_arrayElimArr_1 (+ 8 v_arrayElimCell_26)) |c_ULTIMATE.start_create_sl_with_head_and_tail_#t~malloc6#1.base|))))) (not .cse34)))) is different from false [2022-07-12 18:39:56,709 INFO L173 IndexEqualityManager]: detected equality via solver [2022-07-12 18:39:56,734 INFO L356 Elim1Store]: treesize reduction 25, result has 47.9 percent of original size [2022-07-12 18:39:56,734 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 150 treesize of output 87 [2022-07-12 18:39:56,737 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-07-12 18:39:56,776 INFO L356 Elim1Store]: treesize reduction 29, result has 66.7 percent of original size [2022-07-12 18:39:56,776 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 347 treesize of output 378 [2022-07-12 18:39:56,788 INFO L173 IndexEqualityManager]: detected equality via solver [2022-07-12 18:39:56,807 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-07-12 18:39:56,807 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 1 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 5 case distinctions, treesize of input 369 treesize of output 281 [2022-07-12 18:39:56,819 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-07-12 18:39:56,819 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 218 treesize of output 202 [2022-07-12 18:39:57,349 INFO L173 IndexEqualityManager]: detected equality via solver [2022-07-12 18:39:57,357 INFO L356 Elim1Store]: treesize reduction 25, result has 47.9 percent of original size [2022-07-12 18:39:57,358 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 151 treesize of output 88 [2022-07-12 18:39:57,360 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-07-12 18:39:57,407 INFO L356 Elim1Store]: treesize reduction 29, result has 66.7 percent of original size [2022-07-12 18:39:57,408 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 348 treesize of output 379 [2022-07-12 18:39:57,457 INFO L356 Elim1Store]: treesize reduction 23, result has 65.7 percent of original size [2022-07-12 18:39:57,457 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 385 treesize of output 282 [2022-07-12 18:39:57,469 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-07-12 18:39:57,469 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 107 treesize of output 93 [2022-07-12 18:39:57,533 INFO L173 IndexEqualityManager]: detected equality via solver [2022-07-12 18:39:57,541 INFO L356 Elim1Store]: treesize reduction 25, result has 47.9 percent of original size [2022-07-12 18:39:57,541 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 241 treesize of output 127 [2022-07-12 18:39:57,551 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-07-12 18:39:57,685 INFO L356 Elim1Store]: treesize reduction 64, result has 71.6 percent of original size [2022-07-12 18:39:57,686 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 6 select indices, 6 select index equivalence classes, 0 disjoint index pairs (out of 15 index pairs), introduced 6 new quantified variables, introduced 15 case distinctions, treesize of input 657 treesize of output 775 [2022-07-12 18:39:57,701 INFO L173 IndexEqualityManager]: detected equality via solver [2022-07-12 18:39:57,748 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-07-12 18:39:57,748 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 1 disjoint index pairs (out of 10 index pairs), introduced 5 new quantified variables, introduced 9 case distinctions, treesize of input 743 treesize of output 565 [2022-07-12 18:39:57,799 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-07-12 18:39:57,800 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 435 treesize of output 415 [2022-07-12 18:40:06,780 INFO L356 Elim1Store]: treesize reduction 25, result has 47.9 percent of original size [2022-07-12 18:40:06,780 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 361 treesize of output 179 [2022-07-12 18:40:07,369 INFO L356 Elim1Store]: treesize reduction 442, result has 45.4 percent of original size [2022-07-12 18:40:07,369 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 11 select indices, 11 select index equivalence classes, 0 disjoint index pairs (out of 55 index pairs), introduced 12 new quantified variables, introduced 55 case distinctions, treesize of input 8386 treesize of output 6970 [2022-07-12 18:40:07,672 INFO L173 IndexEqualityManager]: detected equality via solver [2022-07-12 18:40:07,720 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-07-12 18:40:07,720 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 1 disjoint index pairs (out of 10 index pairs), introduced 5 new quantified variables, introduced 9 case distinctions, treesize of input 7226 treesize of output 5354 [2022-07-12 18:40:07,853 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-07-12 18:40:07,855 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 5148 treesize of output 4948 [2022-07-12 18:41:04,521 INFO L356 Elim1Store]: treesize reduction 25, result has 47.9 percent of original size [2022-07-12 18:41:04,521 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 271 treesize of output 140 [2022-07-12 18:41:04,702 INFO L356 Elim1Store]: treesize reduction 272, result has 32.2 percent of original size [2022-07-12 18:41:04,703 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 8 select indices, 8 select index equivalence classes, 0 disjoint index pairs (out of 28 index pairs), introduced 9 new quantified variables, introduced 28 case distinctions, treesize of input 7189 treesize of output 6165 [2022-07-12 18:41:04,853 INFO L173 IndexEqualityManager]: detected equality via solver [2022-07-12 18:41:04,922 INFO L356 Elim1Store]: treesize reduction 23, result has 77.7 percent of original size [2022-07-12 18:41:04,922 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 1 disjoint index pairs (out of 10 index pairs), introduced 5 new quantified variables, introduced 9 case distinctions, treesize of input 6119 treesize of output 4290 [2022-07-12 18:41:04,978 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-07-12 18:41:04,979 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 1 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 4171 treesize of output 3875 [2022-07-12 18:41:10,316 INFO L356 Elim1Store]: treesize reduction 25, result has 47.9 percent of original size [2022-07-12 18:41:10,316 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 241 treesize of output 127 [2022-07-12 18:41:10,318 INFO L173 IndexEqualityManager]: detected equality via solver [2022-07-12 18:41:10,399 INFO L356 Elim1Store]: treesize reduction 142, result has 32.1 percent of original size [2022-07-12 18:41:10,399 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 6 select indices, 6 select index equivalence classes, 1 disjoint index pairs (out of 15 index pairs), introduced 7 new quantified variables, introduced 15 case distinctions, treesize of input 757 treesize of output 469 [2022-07-12 18:41:10,418 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-07-12 18:41:10,419 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 524 treesize of output 340 [2022-07-12 18:41:10,436 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-07-12 18:41:10,436 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 342 treesize of output 328 [2022-07-12 18:41:10,684 INFO L356 Elim1Store]: treesize reduction 25, result has 47.9 percent of original size [2022-07-12 18:41:10,685 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 150 treesize of output 87 [2022-07-12 18:41:10,699 INFO L173 IndexEqualityManager]: detected equality via solver [2022-07-12 18:41:10,742 INFO L356 Elim1Store]: treesize reduction 55, result has 32.1 percent of original size [2022-07-12 18:41:10,742 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 4 select indices, 4 select index equivalence classes, 1 disjoint index pairs (out of 6 index pairs), introduced 5 new quantified variables, introduced 6 case distinctions, treesize of input 795 treesize of output 452 [2022-07-12 18:41:10,753 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 458 treesize of output 290 [2022-07-12 18:41:10,761 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-07-12 18:41:10,761 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 291 treesize of output 257 [2022-07-12 18:41:10,862 INFO L356 Elim1Store]: treesize reduction 25, result has 47.9 percent of original size [2022-07-12 18:41:10,862 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 271 treesize of output 140 [2022-07-12 18:41:11,027 INFO L356 Elim1Store]: treesize reduction 282, result has 29.7 percent of original size [2022-07-12 18:41:11,027 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 8 select indices, 8 select index equivalence classes, 0 disjoint index pairs (out of 28 index pairs), introduced 9 new quantified variables, introduced 28 case distinctions, treesize of input 3133 treesize of output 2563 [2022-07-12 18:41:11,116 INFO L173 IndexEqualityManager]: detected equality via solver [2022-07-12 18:41:11,154 INFO L356 Elim1Store]: treesize reduction 13, result has 77.2 percent of original size [2022-07-12 18:41:11,154 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 1 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 5 case distinctions, treesize of input 2566 treesize of output 1869 [2022-07-12 18:41:11,196 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-07-12 18:41:11,196 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 1 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 1796 treesize of output 1732 [2022-07-12 18:41:11,804 INFO L356 Elim1Store]: treesize reduction 25, result has 47.9 percent of original size [2022-07-12 18:41:11,804 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 151 treesize of output 88 [2022-07-12 18:41:11,849 INFO L356 Elim1Store]: treesize reduction 82, result has 39.3 percent of original size [2022-07-12 18:41:11,849 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 5 select indices, 5 select index equivalence classes, 0 disjoint index pairs (out of 10 index pairs), introduced 6 new quantified variables, introduced 10 case distinctions, treesize of input 1480 treesize of output 1140 [2022-07-12 18:41:11,871 INFO L173 IndexEqualityManager]: detected equality via solver [2022-07-12 18:41:11,900 INFO L356 Elim1Store]: treesize reduction 13, result has 77.2 percent of original size [2022-07-12 18:41:11,901 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 1 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 5 case distinctions, treesize of input 1246 treesize of output 845 [2022-07-12 18:41:11,916 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-07-12 18:41:11,916 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 770 treesize of output 712 [2022-07-12 18:41:12,407 INFO L356 Elim1Store]: treesize reduction 25, result has 47.9 percent of original size [2022-07-12 18:41:12,407 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 270 treesize of output 139 [2022-07-12 18:41:12,620 INFO L356 Elim1Store]: treesize reduction 185, result has 53.9 percent of original size [2022-07-12 18:41:12,621 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 8 select indices, 8 select index equivalence classes, 0 disjoint index pairs (out of 28 index pairs), introduced 9 new quantified variables, introduced 28 case distinctions, treesize of input 2902 treesize of output 2345 [2022-07-12 18:41:12,729 INFO L173 IndexEqualityManager]: detected equality via solver [2022-07-12 18:41:12,751 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-07-12 18:41:12,752 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 1 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 5 case distinctions, treesize of input 2374 treesize of output 1640 [2022-07-12 18:41:12,805 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-07-12 18:41:12,805 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 1502 treesize of output 1418 [2022-07-12 18:41:35,840 WARN L233 SmtUtils]: Spent 17.75s on a formula simplification. DAG size of input: 964 DAG size of output: 41 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-07-12 18:41:35,843 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-12 18:41:35,843 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1616641861] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-12 18:41:35,843 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-12 18:41:35,843 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 22, 25] total 71 [2022-07-12 18:41:35,844 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1309306711] [2022-07-12 18:41:35,844 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-12 18:41:35,844 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 72 states [2022-07-12 18:41:35,844 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-12 18:41:35,845 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 72 interpolants. [2022-07-12 18:41:35,845 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=278, Invalid=3394, Unknown=150, NotChecked=1290, Total=5112 [2022-07-12 18:41:35,846 INFO L87 Difference]: Start difference. First operand 186 states and 233 transitions. Second operand has 72 states, 71 states have (on average 1.380281690140845) internal successors, (98), 72 states have internal predecessors, (98), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:41:39,482 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-12 18:41:39,482 INFO L93 Difference]: Finished difference Result 209 states and 257 transitions. [2022-07-12 18:41:39,483 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2022-07-12 18:41:39,483 INFO L78 Accepts]: Start accepts. Automaton has has 72 states, 71 states have (on average 1.380281690140845) internal successors, (98), 72 states have internal predecessors, (98), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 34 [2022-07-12 18:41:39,483 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-07-12 18:41:39,484 INFO L225 Difference]: With dead ends: 209 [2022-07-12 18:41:39,484 INFO L226 Difference]: Without dead ends: 209 [2022-07-12 18:41:39,485 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 120 GetRequests, 26 SyntacticMatches, 1 SemanticMatches, 93 ConstructedPredicates, 10 IntricatePredicates, 0 DeprecatedPredicates, 1746 ImplicationChecksByTransitivity, 25.7s TimeCoverageRelationStatistics Valid=616, Invalid=6388, Unknown=176, NotChecked=1750, Total=8930 [2022-07-12 18:41:39,486 INFO L413 NwaCegarLoop]: 83 mSDtfsCounter, 226 mSDsluCounter, 2673 mSDsCounter, 0 mSdLazyCounter, 1817 mSolverCounterSat, 34 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 226 SdHoareTripleChecker+Valid, 2756 SdHoareTripleChecker+Invalid, 3703 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 34 IncrementalHoareTripleChecker+Valid, 1817 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 1852 IncrementalHoareTripleChecker+Unchecked, 0.9s IncrementalHoareTripleChecker+Time [2022-07-12 18:41:39,486 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [226 Valid, 2756 Invalid, 3703 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [34 Valid, 1817 Invalid, 0 Unknown, 1852 Unchecked, 0.9s Time] [2022-07-12 18:41:39,486 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 209 states. [2022-07-12 18:41:39,487 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 209 to 188. [2022-07-12 18:41:39,488 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 188 states, 155 states have (on average 1.5225806451612902) internal successors, (236), 187 states have internal predecessors, (236), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:41:39,488 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 188 states to 188 states and 236 transitions. [2022-07-12 18:41:39,488 INFO L78 Accepts]: Start accepts. Automaton has 188 states and 236 transitions. Word has length 34 [2022-07-12 18:41:39,488 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-07-12 18:41:39,489 INFO L495 AbstractCegarLoop]: Abstraction has 188 states and 236 transitions. [2022-07-12 18:41:39,489 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 72 states, 71 states have (on average 1.380281690140845) internal successors, (98), 72 states have internal predecessors, (98), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-12 18:41:39,489 INFO L276 IsEmpty]: Start isEmpty. Operand 188 states and 236 transitions. [2022-07-12 18:41:39,489 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2022-07-12 18:41:39,489 INFO L187 NwaCegarLoop]: Found error trace [2022-07-12 18:41:39,489 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-12 18:41:39,513 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Forceful destruction successful, exit code 0 [2022-07-12 18:41:39,689 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable28 [2022-07-12 18:41:39,690 INFO L420 AbstractCegarLoop]: === Iteration 30 === Targeting ULTIMATE.startErr33REQUIRES_VIOLATIONMEMORY_DEREFERENCE === [ULTIMATE.startErr0REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr1REQUIRES_VIOLATIONMEMORY_DEREFERENCE, ULTIMATE.startErr2REQUIRES_VIOLATIONMEMORY_DEREFERENCE (and 82 more)] === [2022-07-12 18:41:39,690 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-12 18:41:39,690 INFO L85 PathProgramCache]: Analyzing trace with hash 1606811228, now seen corresponding path program 1 times [2022-07-12 18:41:39,690 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-12 18:41:39,690 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [680169752] [2022-07-12 18:41:39,690 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-12 18:41:39,690 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-12 18:41:39,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-12 18:41:40,408 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-12 18:41:40,408 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-12 18:41:40,408 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [680169752] [2022-07-12 18:41:40,409 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [680169752] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-12 18:41:40,409 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [388301435] [2022-07-12 18:41:40,409 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-12 18:41:40,409 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-12 18:41:40,409 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-12 18:41:40,410 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-12 18:41:40,410 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-07-12 18:41:40,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-12 18:41:40,532 INFO L263 TraceCheckSpWp]: Trace formula consists of 310 conjuncts, 105 conjunts are in the unsatisfiable core [2022-07-12 18:41:40,535 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-12 18:41:40,553 INFO L356 Elim1Store]: treesize reduction 15, result has 25.0 percent of original size [2022-07-12 18:41:40,554 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 19 treesize of output 18 [2022-07-12 18:41:40,593 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2022-07-12 18:41:40,640 INFO L356 Elim1Store]: treesize reduction 8, result has 61.9 percent of original size [2022-07-12 18:41:40,641 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 1 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 2 case distinctions, treesize of input 20 treesize of output 22 [2022-07-12 18:41:40,660 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2022-07-12 18:41:40,695 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2022-07-12 18:41:40,699 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-07-12 18:41:40,699 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 25 [2022-07-12 18:41:41,005 INFO L356 Elim1Store]: treesize reduction 15, result has 25.0 percent of original size [2022-07-12 18:41:41,005 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 76 treesize of output 65 [2022-07-12 18:41:41,008 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 34 [2022-07-12 18:41:41,091 INFO L356 Elim1Store]: treesize reduction 15, result has 25.0 percent of original size [2022-07-12 18:41:41,092 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 69 treesize of output 60 [2022-07-12 18:41:41,095 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 34 [2022-07-12 18:41:41,159 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-07-12 18:41:41,174 INFO L356 Elim1Store]: treesize reduction 78, result has 17.9 percent of original size [2022-07-12 18:41:41,174 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 3 new quantified variables, introduced 2 case distinctions, treesize of input 95 treesize of output 68 [2022-07-12 18:41:41,176 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-07-12 18:41:41,177 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 3 new quantified variables, introduced 0 case distinctions, treesize of input 104 treesize of output 87 [2022-07-12 18:41:41,466 INFO L356 Elim1Store]: treesize reduction 36, result has 23.4 percent of original size [2022-07-12 18:41:41,466 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 4 new quantified variables, introduced 3 case distinctions, treesize of input 137 treesize of output 120 [2022-07-12 18:41:41,482 INFO L356 Elim1Store]: treesize reduction 64, result has 19.0 percent of original size [2022-07-12 18:41:41,487 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 2 case distinctions, treesize of input 117 treesize of output 110 [2022-07-12 18:41:41,524 INFO L356 Elim1Store]: treesize reduction 36, result has 23.4 percent of original size [2022-07-12 18:41:41,524 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 4 new quantified variables, introduced 3 case distinctions, treesize of input 128 treesize of output 113 [2022-07-12 18:41:41,540 INFO L356 Elim1Store]: treesize reduction 64, result has 19.0 percent of original size [2022-07-12 18:41:41,540 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 2 case distinctions, treesize of input 117 treesize of output 110 [2022-07-12 18:41:41,571 INFO L356 Elim1Store]: treesize reduction 36, result has 23.4 percent of original size [2022-07-12 18:41:41,571 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 4 new quantified variables, introduced 3 case distinctions, treesize of input 138 treesize of output 123 [2022-07-12 18:41:41,586 INFO L356 Elim1Store]: treesize reduction 64, result has 19.0 percent of original size [2022-07-12 18:41:41,586 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 2 case distinctions, treesize of input 127 treesize of output 120 [2022-07-12 18:41:42,094 INFO L356 Elim1Store]: treesize reduction 36, result has 2.7 percent of original size [2022-07-12 18:41:42,094 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 1 disjoint index pairs (out of 3 index pairs), introduced 4 new quantified variables, introduced 2 case distinctions, treesize of input 140 treesize of output 63 [2022-07-12 18:41:42,106 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 4 new quantified variables, introduced 0 case distinctions, treesize of input 49 treesize of output 22 [2022-07-12 18:41:42,112 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-12 18:41:42,113 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-12 18:41:45,522 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-07-12 18:41:45,522 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 448 treesize of output 391 [2022-07-12 18:41:45,527 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-07-12 18:41:45,527 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 357 treesize of output 225 [2022-07-12 18:41:45,541 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-07-12 18:41:45,541 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 273 treesize of output 231 [2022-07-12 18:41:45,546 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-07-12 18:41:45,546 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 197 treesize of output 140 [2022-07-12 18:41:45,993 INFO L356 Elim1Store]: treesize reduction 21, result has 47.5 percent of original size [2022-07-12 18:41:45,993 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 2 new quantified variables, introduced 2 case distinctions, treesize of input 397 treesize of output 357 [2022-07-12 18:41:46,102 INFO L356 Elim1Store]: treesize reduction 18, result has 95.7 percent of original size [2022-07-12 18:41:46,102 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 5 select indices, 5 select index equivalence classes, 0 disjoint index pairs (out of 10 index pairs), introduced 6 new quantified variables, introduced 10 case distinctions, treesize of input 7666 treesize of output 7548 [2022-07-12 18:41:46,150 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-07-12 18:41:46,151 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 5 new quantified variables, introduced 6 case distinctions, treesize of input 7134 treesize of output 7072 [2022-07-12 18:41:46,173 INFO L173 IndexEqualityManager]: detected equality via solver [2022-07-12 18:41:46,230 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-07-12 18:41:46,230 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 1 disjoint index pairs (out of 10 index pairs), introduced 6 new quantified variables, introduced 9 case distinctions, treesize of input 7075 treesize of output 7095