./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.11.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 791161d1 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.11.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 940a677bfde7dbbc79e036121bd0ec6fd3518c0f58a02d336e5d42fafb098792 --- Real Ultimate output --- This is Ultimate 0.2.2-?-791161d [2022-07-23 15:32:24,057 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-07-23 15:32:24,059 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-07-23 15:32:24,097 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-07-23 15:32:24,097 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-07-23 15:32:24,098 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-07-23 15:32:24,100 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-07-23 15:32:24,102 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-07-23 15:32:24,103 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-07-23 15:32:24,107 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-07-23 15:32:24,107 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-07-23 15:32:24,109 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-07-23 15:32:24,109 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-07-23 15:32:24,111 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-07-23 15:32:24,112 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-07-23 15:32:24,115 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-07-23 15:32:24,115 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-07-23 15:32:24,116 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-07-23 15:32:24,118 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-07-23 15:32:24,122 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-07-23 15:32:24,124 INFO L181 SettingsManager]: Resetting HornVerifier preferences to default values [2022-07-23 15:32:24,124 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-07-23 15:32:24,125 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-07-23 15:32:24,126 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-07-23 15:32:24,127 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-07-23 15:32:24,132 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-07-23 15:32:24,133 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-07-23 15:32:24,133 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-07-23 15:32:24,134 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-07-23 15:32:24,134 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-07-23 15:32:24,135 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-07-23 15:32:24,135 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-07-23 15:32:24,137 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-07-23 15:32:24,137 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-07-23 15:32:24,137 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-07-23 15:32:24,138 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-07-23 15:32:24,139 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-07-23 15:32:24,140 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-07-23 15:32:24,140 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-07-23 15:32:24,140 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-07-23 15:32:24,140 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-07-23 15:32:24,142 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-07-23 15:32:24,143 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-07-23 15:32:24,167 INFO L113 SettingsManager]: Loading preferences was successful [2022-07-23 15:32:24,168 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-07-23 15:32:24,168 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-07-23 15:32:24,168 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-07-23 15:32:24,170 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-07-23 15:32:24,170 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-07-23 15:32:24,170 INFO L138 SettingsManager]: * Use SBE=true [2022-07-23 15:32:24,170 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-07-23 15:32:24,170 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-07-23 15:32:24,171 INFO L138 SettingsManager]: * Use old map elimination=false [2022-07-23 15:32:24,171 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-07-23 15:32:24,172 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-07-23 15:32:24,172 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-07-23 15:32:24,172 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-07-23 15:32:24,172 INFO L138 SettingsManager]: * sizeof long=4 [2022-07-23 15:32:24,172 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-07-23 15:32:24,174 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-07-23 15:32:24,174 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-07-23 15:32:24,174 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-07-23 15:32:24,174 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-07-23 15:32:24,174 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-07-23 15:32:24,174 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-07-23 15:32:24,174 INFO L138 SettingsManager]: * sizeof long double=12 [2022-07-23 15:32:24,175 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-07-23 15:32:24,175 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-07-23 15:32:24,175 INFO L138 SettingsManager]: * Use constant arrays=true [2022-07-23 15:32:24,175 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-07-23 15:32:24,175 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-07-23 15:32:24,176 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-07-23 15:32:24,176 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-07-23 15:32:24,176 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-07-23 15:32:24,177 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-07-23 15:32:24,177 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 940a677bfde7dbbc79e036121bd0ec6fd3518c0f58a02d336e5d42fafb098792 [2022-07-23 15:32:24,358 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-07-23 15:32:24,387 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-07-23 15:32:24,389 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-07-23 15:32:24,390 INFO L271 PluginConnector]: Initializing CDTParser... [2022-07-23 15:32:24,391 INFO L275 PluginConnector]: CDTParser initialized [2022-07-23 15:32:24,392 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.11.cil.c [2022-07-23 15:32:24,431 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/e45fa7b28/3e4dd0e094f048b186cd139a5e235533/FLAG62760bd7a [2022-07-23 15:32:24,830 INFO L306 CDTParser]: Found 1 translation units. [2022-07-23 15:32:24,830 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.11.cil.c [2022-07-23 15:32:24,840 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/e45fa7b28/3e4dd0e094f048b186cd139a5e235533/FLAG62760bd7a [2022-07-23 15:32:25,219 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/e45fa7b28/3e4dd0e094f048b186cd139a5e235533 [2022-07-23 15:32:25,221 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-07-23 15:32:25,221 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-07-23 15:32:25,235 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-07-23 15:32:25,236 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-07-23 15:32:25,238 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-07-23 15:32:25,239 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.07 03:32:25" (1/1) ... [2022-07-23 15:32:25,240 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1e7d5c0d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.07 03:32:25, skipping insertion in model container [2022-07-23 15:32:25,240 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.07 03:32:25" (1/1) ... [2022-07-23 15:32:25,244 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-07-23 15:32:25,278 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-07-23 15:32:25,381 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.11.cil.c[706,719] [2022-07-23 15:32:25,507 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-23 15:32:25,514 INFO L203 MainTranslator]: Completed pre-run [2022-07-23 15:32:25,526 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.11.cil.c[706,719] [2022-07-23 15:32:25,572 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-23 15:32:25,584 INFO L208 MainTranslator]: Completed translation [2022-07-23 15:32:25,584 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.07 03:32:25 WrapperNode [2022-07-23 15:32:25,585 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-07-23 15:32:25,585 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-07-23 15:32:25,585 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-07-23 15:32:25,585 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-07-23 15:32:25,590 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.07 03:32:25" (1/1) ... [2022-07-23 15:32:25,598 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.07 03:32:25" (1/1) ... [2022-07-23 15:32:25,665 INFO L137 Inliner]: procedures = 50, calls = 63, calls flagged for inlining = 58, calls inlined = 224, statements flattened = 3437 [2022-07-23 15:32:25,665 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-07-23 15:32:25,666 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-07-23 15:32:25,666 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-07-23 15:32:25,666 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-07-23 15:32:25,672 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.07 03:32:25" (1/1) ... [2022-07-23 15:32:25,672 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.07 03:32:25" (1/1) ... [2022-07-23 15:32:25,680 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.07 03:32:25" (1/1) ... [2022-07-23 15:32:25,680 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.07 03:32:25" (1/1) ... [2022-07-23 15:32:25,726 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.07 03:32:25" (1/1) ... [2022-07-23 15:32:25,767 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.07 03:32:25" (1/1) ... [2022-07-23 15:32:25,772 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.07 03:32:25" (1/1) ... [2022-07-23 15:32:25,782 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-07-23 15:32:25,783 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-07-23 15:32:25,783 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-07-23 15:32:25,783 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-07-23 15:32:25,784 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.07 03:32:25" (1/1) ... [2022-07-23 15:32:25,810 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-23 15:32:25,830 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-23 15:32:25,841 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-23 15:32:25,900 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-07-23 15:32:25,919 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-07-23 15:32:25,919 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-07-23 15:32:25,919 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-07-23 15:32:25,919 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-07-23 15:32:26,065 INFO L234 CfgBuilder]: Building ICFG [2022-07-23 15:32:26,070 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-07-23 15:32:27,198 INFO L275 CfgBuilder]: Performing block encoding [2022-07-23 15:32:27,209 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-07-23 15:32:27,210 INFO L299 CfgBuilder]: Removed 15 assume(true) statements. [2022-07-23 15:32:27,212 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.07 03:32:27 BoogieIcfgContainer [2022-07-23 15:32:27,213 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-07-23 15:32:27,213 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-07-23 15:32:27,213 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-07-23 15:32:27,216 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-07-23 15:32:27,216 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-23 15:32:27,216 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 23.07 03:32:25" (1/3) ... [2022-07-23 15:32:27,218 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1620f2eb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 23.07 03:32:27, skipping insertion in model container [2022-07-23 15:32:27,218 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-23 15:32:27,218 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.07 03:32:25" (2/3) ... [2022-07-23 15:32:27,218 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1620f2eb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 23.07 03:32:27, skipping insertion in model container [2022-07-23 15:32:27,218 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-23 15:32:27,218 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.07 03:32:27" (3/3) ... [2022-07-23 15:32:27,219 INFO L354 chiAutomizerObserver]: Analyzing ICFG transmitter.11.cil.c [2022-07-23 15:32:27,271 INFO L255 stractBuchiCegarLoop]: Interprodecural is true [2022-07-23 15:32:27,271 INFO L256 stractBuchiCegarLoop]: Hoare is false [2022-07-23 15:32:27,271 INFO L257 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-07-23 15:32:27,271 INFO L258 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-07-23 15:32:27,271 INFO L259 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-07-23 15:32:27,272 INFO L260 stractBuchiCegarLoop]: Difference is false [2022-07-23 15:32:27,272 INFO L261 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-07-23 15:32:27,272 INFO L265 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-07-23 15:32:27,277 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1483 states, 1482 states have (on average 1.5053981106612686) internal successors, (2231), 1482 states have internal predecessors, (2231), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:27,324 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1330 [2022-07-23 15:32:27,325 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-23 15:32:27,325 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-23 15:32:27,341 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:27,341 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:27,341 INFO L287 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-07-23 15:32:27,364 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1483 states, 1482 states have (on average 1.5053981106612686) internal successors, (2231), 1482 states have internal predecessors, (2231), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:27,373 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1330 [2022-07-23 15:32:27,374 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-23 15:32:27,374 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-23 15:32:27,377 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:27,377 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:27,388 INFO L752 eck$LassoCheckResult]: Stem: 714#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 1354#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 724#L1607true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1297#L754true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 510#L761true assume !(1 == ~m_i~0);~m_st~0 := 2; 526#L761-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 423#L766-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 365#L771-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 203#L776-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 20#L781-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1461#L786-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 43#L791-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 645#L796-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 611#L801-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 654#L806-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 1334#L811-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 261#L816-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1144#L1090true assume !(0 == ~M_E~0); 287#L1090-2true assume !(0 == ~T1_E~0); 1305#L1095-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 784#L1100-1true assume !(0 == ~T3_E~0); 810#L1105-1true assume !(0 == ~T4_E~0); 156#L1110-1true assume !(0 == ~T5_E~0); 385#L1115-1true assume !(0 == ~T6_E~0); 594#L1120-1true assume !(0 == ~T7_E~0); 1342#L1125-1true assume !(0 == ~T8_E~0); 1335#L1130-1true assume !(0 == ~T9_E~0); 808#L1135-1true assume 0 == ~T10_E~0;~T10_E~0 := 1; 264#L1140-1true assume !(0 == ~T11_E~0); 738#L1145-1true assume !(0 == ~E_1~0); 780#L1150-1true assume !(0 == ~E_2~0); 373#L1155-1true assume !(0 == ~E_3~0); 1314#L1160-1true assume !(0 == ~E_4~0); 429#L1165-1true assume !(0 == ~E_5~0); 1069#L1170-1true assume !(0 == ~E_6~0); 1254#L1175-1true assume 0 == ~E_7~0;~E_7~0 := 1; 479#L1180-1true assume !(0 == ~E_8~0); 894#L1185-1true assume !(0 == ~E_9~0); 262#L1190-1true assume !(0 == ~E_10~0); 489#L1195-1true assume !(0 == ~E_11~0); 1012#L1200-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 380#L525true assume !(1 == ~m_pc~0); 61#L525-2true is_master_triggered_~__retres1~0#1 := 0; 1008#L536true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 491#L537true activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 873#L1350true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 253#L1350-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 530#L544true assume 1 == ~t1_pc~0; 411#L545true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 735#L555true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1465#L556true activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 167#L1358true assume !(0 != activate_threads_~tmp___0~0#1); 573#L1358-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1003#L563true assume !(1 == ~t2_pc~0); 725#L563-2true is_transmit2_triggered_~__retres1~2#1 := 0; 72#L574true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 569#L575true activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 303#L1366true assume !(0 != activate_threads_~tmp___1~0#1); 633#L1366-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 736#L582true assume 1 == ~t3_pc~0; 140#L583true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1213#L593true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1426#L594true activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1081#L1374true assume !(0 != activate_threads_~tmp___2~0#1); 107#L1374-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1377#L601true assume !(1 == ~t4_pc~0); 828#L601-2true is_transmit4_triggered_~__retres1~4#1 := 0; 386#L612true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 790#L613true activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 747#L1382true assume !(0 != activate_threads_~tmp___3~0#1); 1386#L1382-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1185#L620true assume 1 == ~t5_pc~0; 86#L621true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 651#L631true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 591#L632true activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1459#L1390true assume !(0 != activate_threads_~tmp___4~0#1); 1243#L1390-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1347#L639true assume !(1 == ~t6_pc~0); 592#L639-2true is_transmit6_triggered_~__retres1~6#1 := 0; 324#L650true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1085#L651true activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1238#L1398true assume !(0 != activate_threads_~tmp___5~0#1); 390#L1398-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 939#L658true assume 1 == ~t7_pc~0; 593#L659true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1261#L669true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 620#L670true activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 686#L1406true assume !(0 != activate_threads_~tmp___6~0#1); 258#L1406-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 393#L677true assume 1 == ~t8_pc~0; 863#L678true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 147#L688true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1033#L689true activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 301#L1414true assume !(0 != activate_threads_~tmp___7~0#1); 864#L1414-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 971#L696true assume !(1 == ~t9_pc~0); 581#L696-2true is_transmit9_triggered_~__retres1~9#1 := 0; 661#L707true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 754#L708true activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 597#L1422true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 788#L1422-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1122#L715true assume 1 == ~t10_pc~0; 796#L716true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 676#L726true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 575#L727true activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 765#L1430true assume !(0 != activate_threads_~tmp___9~0#1); 474#L1430-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 144#L734true assume !(1 == ~t11_pc~0); 431#L734-2true is_transmit11_triggered_~__retres1~11#1 := 0; 482#L745true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 495#L746true activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14#L1438true assume !(0 != activate_threads_~tmp___10~0#1); 652#L1438-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1181#L1213true assume !(1 == ~M_E~0); 472#L1213-2true assume !(1 == ~T1_E~0); 957#L1218-1true assume !(1 == ~T2_E~0); 32#L1223-1true assume !(1 == ~T3_E~0); 457#L1228-1true assume !(1 == ~T4_E~0); 1244#L1233-1true assume !(1 == ~T5_E~0); 1439#L1238-1true assume !(1 == ~T6_E~0); 746#L1243-1true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1392#L1248-1true assume !(1 == ~T8_E~0); 794#L1253-1true assume !(1 == ~T9_E~0); 1086#L1258-1true assume !(1 == ~T10_E~0); 772#L1263-1true assume !(1 == ~T11_E~0); 1128#L1268-1true assume !(1 == ~E_1~0); 610#L1273-1true assume !(1 == ~E_2~0); 1224#L1278-1true assume !(1 == ~E_3~0); 323#L1283-1true assume 1 == ~E_4~0;~E_4~0 := 2; 1275#L1288-1true assume !(1 == ~E_5~0); 915#L1293-1true assume !(1 == ~E_6~0); 869#L1298-1true assume !(1 == ~E_7~0); 636#L1303-1true assume !(1 == ~E_8~0); 330#L1308-1true assume !(1 == ~E_9~0); 267#L1313-1true assume !(1 == ~E_10~0); 1360#L1318-1true assume !(1 == ~E_11~0); 273#L1323-1true assume { :end_inline_reset_delta_events } true; 1134#L1644-2true [2022-07-23 15:32:27,390 INFO L754 eck$LassoCheckResult]: Loop: 1134#L1644-2true assume !false; 684#L1645true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 764#L1065true assume !true; 866#L1080true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 761#L754-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 945#L1090-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1024#L1090-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1363#L1095-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 974#L1100-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1236#L1105-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 200#L1110-3true assume !(0 == ~T5_E~0); 1074#L1115-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 366#L1120-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 743#L1125-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1114#L1130-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1272#L1135-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 317#L1140-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 48#L1145-3true assume 0 == ~E_1~0;~E_1~0 := 1; 497#L1150-3true assume !(0 == ~E_2~0); 108#L1155-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1420#L1160-3true assume 0 == ~E_4~0;~E_4~0 := 1; 307#L1165-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1479#L1170-3true assume 0 == ~E_6~0;~E_6~0 := 1; 566#L1175-3true assume 0 == ~E_7~0;~E_7~0 := 1; 255#L1180-3true assume 0 == ~E_8~0;~E_8~0 := 1; 123#L1185-3true assume 0 == ~E_9~0;~E_9~0 := 1; 1277#L1190-3true assume !(0 == ~E_10~0); 1094#L1195-3true assume 0 == ~E_11~0;~E_11~0 := 1; 1477#L1200-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 446#L525-36true assume 1 == ~m_pc~0; 1100#L526-12true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 173#L536-12true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1350#L537-12true activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 338#L1350-36true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 565#L1350-38true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 289#L544-36true assume !(1 == ~t1_pc~0); 913#L544-38true is_transmit1_triggered_~__retres1~1#1 := 0; 666#L555-12true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 220#L556-12true activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1256#L1358-36true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1065#L1358-38true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 905#L563-36true assume !(1 == ~t2_pc~0); 951#L563-38true is_transmit2_triggered_~__retres1~2#1 := 0; 46#L574-12true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 751#L575-12true activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1253#L1366-36true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 456#L1366-38true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1362#L582-36true assume !(1 == ~t3_pc~0); 929#L582-38true is_transmit3_triggered_~__retres1~3#1 := 0; 509#L593-12true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1365#L594-12true activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 659#L1374-36true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 481#L1374-38true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 443#L601-36true assume 1 == ~t4_pc~0; 377#L602-12true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1455#L612-12true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1264#L613-12true activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1034#L1382-36true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1176#L1382-38true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 890#L620-36true assume !(1 == ~t5_pc~0); 1452#L620-38true is_transmit5_triggered_~__retres1~5#1 := 0; 728#L631-12true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 952#L632-12true activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 392#L1390-36true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 179#L1390-38true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 69#L639-36true assume !(1 == ~t6_pc~0); 1408#L639-38true is_transmit6_triggered_~__retres1~6#1 := 0; 88#L650-12true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1004#L651-12true activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 211#L1398-36true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 596#L1398-38true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1175#L658-36true assume !(1 == ~t7_pc~0); 74#L658-38true is_transmit7_triggered_~__retres1~7#1 := 0; 1005#L669-12true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1045#L670-12true activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 63#L1406-36true assume !(0 != activate_threads_~tmp___6~0#1); 711#L1406-38true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 926#L677-36true assume !(1 == ~t8_pc~0); 533#L677-38true is_transmit8_triggered_~__retres1~8#1 := 0; 634#L688-12true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1186#L689-12true activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1173#L1414-36true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 554#L1414-38true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1091#L696-36true assume 1 == ~t9_pc~0; 470#L697-12true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 826#L707-12true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 97#L708-12true activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1006#L1422-36true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 567#L1422-38true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1250#L715-36true assume 1 == ~t10_pc~0; 681#L716-12true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 15#L726-12true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 126#L727-12true activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3#L1430-36true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1051#L1430-38true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 205#L734-36true assume !(1 == ~t11_pc~0); 51#L734-38true is_transmit11_triggered_~__retres1~11#1 := 0; 215#L745-12true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 459#L746-12true activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11#L1438-36true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 615#L1438-38true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1097#L1213-3true assume 1 == ~M_E~0;~M_E~0 := 2; 371#L1213-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 709#L1218-3true assume !(1 == ~T2_E~0); 232#L1223-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 752#L1228-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 344#L1233-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1262#L1238-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 507#L1243-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1032#L1248-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1399#L1253-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1041#L1258-3true assume !(1 == ~T10_E~0); 221#L1263-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 988#L1268-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1011#L1273-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1453#L1278-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1014#L1283-3true assume 1 == ~E_4~0;~E_4~0 := 2; 427#L1288-3true assume 1 == ~E_5~0;~E_5~0 := 2; 1284#L1293-3true assume 1 == ~E_6~0;~E_6~0 := 2; 337#L1298-3true assume !(1 == ~E_7~0); 1135#L1303-3true assume 1 == ~E_8~0;~E_8~0 := 2; 682#L1308-3true assume 1 == ~E_9~0;~E_9~0 := 2; 335#L1313-3true assume 1 == ~E_10~0;~E_10~0 := 2; 1036#L1318-3true assume 1 == ~E_11~0;~E_11~0 := 2; 222#L1323-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1427#L829-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 439#L891-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 835#L892-1true start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1428#L1663true assume !(0 == start_simulation_~tmp~3#1); 1328#L1663-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 595#L829-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 525#L891-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 702#L892-2true stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 79#L1618true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 260#L1625true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1298#L1626true start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1163#L1676true assume !(0 != start_simulation_~tmp___0~1#1); 1134#L1644-2true [2022-07-23 15:32:27,394 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:27,394 INFO L85 PathProgramCache]: Analyzing trace with hash -92888918, now seen corresponding path program 1 times [2022-07-23 15:32:27,411 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:27,411 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1963264630] [2022-07-23 15:32:27,411 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:27,412 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:27,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:27,628 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:27,629 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:27,629 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1963264630] [2022-07-23 15:32:27,630 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1963264630] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:27,630 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:27,630 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-23 15:32:27,631 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [930555693] [2022-07-23 15:32:27,632 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:27,635 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-23 15:32:27,636 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:27,637 INFO L85 PathProgramCache]: Analyzing trace with hash -16570774, now seen corresponding path program 1 times [2022-07-23 15:32:27,637 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:27,638 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [987314541] [2022-07-23 15:32:27,638 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:27,638 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:27,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:27,683 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:27,688 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:27,688 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [987314541] [2022-07-23 15:32:27,688 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [987314541] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:27,688 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:27,689 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-23 15:32:27,689 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1909895825] [2022-07-23 15:32:27,689 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:27,691 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-23 15:32:27,692 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-23 15:32:27,716 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-07-23 15:32:27,717 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-07-23 15:32:27,720 INFO L87 Difference]: Start difference. First operand has 1483 states, 1482 states have (on average 1.5053981106612686) internal successors, (2231), 1482 states have internal predecessors, (2231), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 68.5) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:27,766 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-23 15:32:27,766 INFO L93 Difference]: Finished difference Result 1482 states and 2199 transitions. [2022-07-23 15:32:27,767 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-07-23 15:32:27,771 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1482 states and 2199 transitions. [2022-07-23 15:32:27,780 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-07-23 15:32:27,792 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1482 states to 1476 states and 2193 transitions. [2022-07-23 15:32:27,793 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2022-07-23 15:32:27,795 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2022-07-23 15:32:27,796 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2193 transitions. [2022-07-23 15:32:27,804 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-23 15:32:27,804 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2193 transitions. [2022-07-23 15:32:27,818 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2193 transitions. [2022-07-23 15:32:27,883 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2022-07-23 15:32:27,887 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4857723577235773) internal successors, (2193), 1475 states have internal predecessors, (2193), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:27,890 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2193 transitions. [2022-07-23 15:32:27,892 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2193 transitions. [2022-07-23 15:32:27,892 INFO L374 stractBuchiCegarLoop]: Abstraction has 1476 states and 2193 transitions. [2022-07-23 15:32:27,892 INFO L287 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-07-23 15:32:27,892 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2193 transitions. [2022-07-23 15:32:27,901 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-07-23 15:32:27,901 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-23 15:32:27,901 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-23 15:32:27,907 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:27,907 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:27,908 INFO L752 eck$LassoCheckResult]: Stem: 4096#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 4097#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 4106#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4107#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3872#L761 assume !(1 == ~m_i~0);~m_st~0 := 2; 3873#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3742#L766-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3654#L771-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3377#L776-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3012#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3013#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3061#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3062#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3990#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3991#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4029#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 3477#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3478#L1090 assume !(0 == ~M_E~0); 3523#L1090-2 assume !(0 == ~T1_E~0); 3524#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4167#L1100-1 assume !(0 == ~T3_E~0); 4168#L1105-1 assume !(0 == ~T4_E~0); 3296#L1110-1 assume !(0 == ~T5_E~0); 3297#L1115-1 assume !(0 == ~T6_E~0); 3692#L1120-1 assume !(0 == ~T7_E~0); 3969#L1125-1 assume !(0 == ~T8_E~0); 4438#L1130-1 assume !(0 == ~T9_E~0); 4187#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3482#L1140-1 assume !(0 == ~T11_E~0); 3483#L1145-1 assume !(0 == ~E_1~0); 4121#L1150-1 assume !(0 == ~E_2~0); 3667#L1155-1 assume !(0 == ~E_3~0); 3668#L1160-1 assume !(0 == ~E_4~0); 3750#L1165-1 assume !(0 == ~E_5~0); 3751#L1170-1 assume !(0 == ~E_6~0); 4359#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 3828#L1180-1 assume !(0 == ~E_8~0); 3829#L1185-1 assume !(0 == ~E_9~0); 3479#L1190-1 assume !(0 == ~E_10~0); 3480#L1195-1 assume !(0 == ~E_11~0); 3842#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3689#L525 assume !(1 == ~m_pc~0); 3100#L525-2 is_master_triggered_~__retres1~0#1 := 0; 3101#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3846#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3847#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3466#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3467#L544 assume 1 == ~t1_pc~0; 3727#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3691#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4119#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3317#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 3318#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3940#L563 assume !(1 == ~t2_pc~0); 4108#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3121#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3122#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3553#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 3554#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4013#L582 assume 1 == ~t3_pc~0; 3261#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3262#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4410#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4368#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 3195#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3196#L601 assume !(1 == ~t4_pc~0); 4136#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3693#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3694#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4130#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 4131#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4402#L620 assume 1 == ~t5_pc~0; 3154#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3155#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3965#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3966#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 4417#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4418#L639 assume !(1 == ~t6_pc~0); 3967#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3590#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3591#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4371#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 3701#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3702#L658 assume 1 == ~t7_pc~0; 3968#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3895#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4000#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4001#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 3473#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3474#L677 assume 1 == ~t8_pc~0; 3706#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3276#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3277#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3547#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 3548#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4226#L696 assume !(1 == ~t9_pc~0); 3953#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3954#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4044#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3973#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3974#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4171#L715 assume 1 == ~t10_pc~0; 4175#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4058#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3943#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3944#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 3820#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3270#L734 assume !(1 == ~t11_pc~0); 3271#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 3754#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3833#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3002#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 3003#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4028#L1213 assume !(1 == ~M_E~0); 3818#L1213-2 assume !(1 == ~T1_E~0); 3819#L1218-1 assume !(1 == ~T2_E~0); 3037#L1223-1 assume !(1 == ~T3_E~0); 3038#L1228-1 assume !(1 == ~T4_E~0); 3797#L1233-1 assume !(1 == ~T5_E~0); 4419#L1238-1 assume !(1 == ~T6_E~0); 4128#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4129#L1248-1 assume !(1 == ~T8_E~0); 4173#L1253-1 assume !(1 == ~T9_E~0); 4174#L1258-1 assume !(1 == ~T10_E~0); 4152#L1263-1 assume !(1 == ~T11_E~0); 4153#L1268-1 assume !(1 == ~E_1~0); 3988#L1273-1 assume !(1 == ~E_2~0); 3989#L1278-1 assume !(1 == ~E_3~0); 3588#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 3589#L1288-1 assume !(1 == ~E_5~0); 4266#L1293-1 assume !(1 == ~E_6~0); 4230#L1298-1 assume !(1 == ~E_7~0); 4016#L1303-1 assume !(1 == ~E_8~0); 3599#L1308-1 assume !(1 == ~E_9~0); 3488#L1313-1 assume !(1 == ~E_10~0); 3489#L1318-1 assume !(1 == ~E_11~0); 3501#L1323-1 assume { :end_inline_reset_delta_events } true; 3502#L1644-2 [2022-07-23 15:32:27,910 INFO L754 eck$LassoCheckResult]: Loop: 3502#L1644-2 assume !false; 4069#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4070#L1065 assume !false; 4145#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4415#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3119#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 4331#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3604#L906 assume !(0 != eval_~tmp~0#1); 3606#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4143#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4144#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4283#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4335#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4298#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4299#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3372#L1110-3 assume !(0 == ~T5_E~0); 3373#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3655#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3656#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4126#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4380#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3580#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 3075#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3076#L1150-3 assume !(0 == ~E_2~0); 3198#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3199#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3559#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3560#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3932#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3469#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3230#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3231#L1190-3 assume !(0 == ~E_10~0); 4374#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 4375#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3782#L525-36 assume !(1 == ~m_pc~0); 3783#L525-38 is_master_triggered_~__retres1~0#1 := 0; 3333#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3334#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3614#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3615#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3520#L544-36 assume 1 == ~t1_pc~0; 3521#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4047#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3412#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3413#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4356#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4259#L563-36 assume 1 == ~t2_pc~0; 3315#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3071#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3072#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4134#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3795#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3796#L582-36 assume !(1 == ~t3_pc~0); 3648#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 3647#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3871#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4038#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3832#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3776#L601-36 assume 1 == ~t4_pc~0; 3675#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3676#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4423#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4341#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4342#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4247#L620-36 assume 1 == ~t5_pc~0; 3715#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3716#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4109#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3703#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3337#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3115#L639-36 assume 1 == ~t6_pc~0; 3116#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3152#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3153#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3393#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3394#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3972#L658-36 assume 1 == ~t7_pc~0; 3232#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3127#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4326#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3102#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 3103#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4093#L677-36 assume !(1 == ~t8_pc~0); 3897#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 3898#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4014#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4398#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3920#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3921#L696-36 assume 1 == ~t9_pc~0; 3814#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3816#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3175#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3176#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3933#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3934#L715-36 assume !(1 == ~t10_pc~0); 3904#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 3000#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3001#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2976#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 2977#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3381#L734-36 assume 1 == ~t11_pc~0; 3382#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3081#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3403#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2994#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 2995#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3994#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3661#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3662#L1218-3 assume !(1 == ~T2_E~0); 3432#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3433#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3622#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3623#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3867#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3868#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4339#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4344#L1258-3 assume !(1 == ~T10_E~0); 3414#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 3415#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4310#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4328#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4330#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3746#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3747#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3612#L1298-3 assume !(1 == ~E_7~0); 3613#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4068#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3609#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3610#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 3416#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 3417#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3356#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3767#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 4206#L1663 assume !(0 == start_simulation_~tmp~3#1); 3249#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 3970#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3193#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3889#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 3137#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3138#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3476#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 4395#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 3502#L1644-2 [2022-07-23 15:32:27,910 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:27,911 INFO L85 PathProgramCache]: Analyzing trace with hash -92888918, now seen corresponding path program 2 times [2022-07-23 15:32:27,911 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:27,911 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [535151817] [2022-07-23 15:32:27,911 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:27,912 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:27,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:27,985 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:27,986 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:27,987 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [535151817] [2022-07-23 15:32:27,988 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [535151817] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:27,988 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:27,988 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-23 15:32:27,988 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [523536035] [2022-07-23 15:32:27,989 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:27,990 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-23 15:32:27,991 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:27,991 INFO L85 PathProgramCache]: Analyzing trace with hash -852141939, now seen corresponding path program 1 times [2022-07-23 15:32:27,992 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:27,992 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [633463669] [2022-07-23 15:32:27,993 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:27,993 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:28,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:28,092 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:28,095 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:28,095 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [633463669] [2022-07-23 15:32:28,096 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [633463669] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:28,096 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:28,096 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-23 15:32:28,097 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2087599244] [2022-07-23 15:32:28,097 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:28,097 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-23 15:32:28,097 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-23 15:32:28,098 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-23 15:32:28,098 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-23 15:32:28,098 INFO L87 Difference]: Start difference. First operand 1476 states and 2193 transitions. cyclomatic complexity: 718 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:28,125 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-23 15:32:28,126 INFO L93 Difference]: Finished difference Result 1476 states and 2192 transitions. [2022-07-23 15:32:28,126 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-23 15:32:28,127 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2192 transitions. [2022-07-23 15:32:28,134 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-07-23 15:32:28,139 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2192 transitions. [2022-07-23 15:32:28,139 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2022-07-23 15:32:28,141 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2022-07-23 15:32:28,141 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2192 transitions. [2022-07-23 15:32:28,142 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-23 15:32:28,142 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2192 transitions. [2022-07-23 15:32:28,144 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2192 transitions. [2022-07-23 15:32:28,187 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2022-07-23 15:32:28,189 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4850948509485096) internal successors, (2192), 1475 states have internal predecessors, (2192), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:28,193 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2192 transitions. [2022-07-23 15:32:28,193 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2192 transitions. [2022-07-23 15:32:28,193 INFO L374 stractBuchiCegarLoop]: Abstraction has 1476 states and 2192 transitions. [2022-07-23 15:32:28,193 INFO L287 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-07-23 15:32:28,193 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2192 transitions. [2022-07-23 15:32:28,199 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-07-23 15:32:28,199 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-23 15:32:28,199 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-23 15:32:28,204 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:28,204 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:28,204 INFO L752 eck$LassoCheckResult]: Stem: 7055#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 7056#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 7063#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7064#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6831#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 6832#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6701#L766-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 6613#L771-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 6336#L776-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5971#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5972#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6020#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6021#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6949#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 6950#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 6988#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 6436#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6437#L1090 assume !(0 == ~M_E~0); 6479#L1090-2 assume !(0 == ~T1_E~0); 6480#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7125#L1100-1 assume !(0 == ~T3_E~0); 7126#L1105-1 assume !(0 == ~T4_E~0); 6254#L1110-1 assume !(0 == ~T5_E~0); 6255#L1115-1 assume !(0 == ~T6_E~0); 6651#L1120-1 assume !(0 == ~T7_E~0); 6928#L1125-1 assume !(0 == ~T8_E~0); 7397#L1130-1 assume !(0 == ~T9_E~0); 7146#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 6441#L1140-1 assume !(0 == ~T11_E~0); 6442#L1145-1 assume !(0 == ~E_1~0); 7080#L1150-1 assume !(0 == ~E_2~0); 6626#L1155-1 assume !(0 == ~E_3~0); 6627#L1160-1 assume !(0 == ~E_4~0); 6709#L1165-1 assume !(0 == ~E_5~0); 6710#L1170-1 assume !(0 == ~E_6~0); 7318#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 6787#L1180-1 assume !(0 == ~E_8~0); 6788#L1185-1 assume !(0 == ~E_9~0); 6438#L1190-1 assume !(0 == ~E_10~0); 6439#L1195-1 assume !(0 == ~E_11~0); 6801#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6641#L525 assume !(1 == ~m_pc~0); 6059#L525-2 is_master_triggered_~__retres1~0#1 := 0; 6060#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6805#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6806#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6425#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6426#L544 assume 1 == ~t1_pc~0; 6686#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6650#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7078#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6276#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 6277#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6899#L563 assume !(1 == ~t2_pc~0); 7065#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6080#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6081#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6509#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 6510#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6972#L582 assume 1 == ~t3_pc~0; 6218#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6219#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7369#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7327#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 6154#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6155#L601 assume !(1 == ~t4_pc~0); 7095#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6652#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6653#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7089#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 7090#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7361#L620 assume 1 == ~t5_pc~0; 6109#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6110#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6924#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6925#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 7376#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7377#L639 assume !(1 == ~t6_pc~0); 6926#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6549#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6550#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7330#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 6660#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6661#L658 assume 1 == ~t7_pc~0; 6927#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6852#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6959#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6960#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 6432#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6433#L677 assume 1 == ~t8_pc~0; 6663#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6235#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6236#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6506#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 6507#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7185#L696 assume !(1 == ~t9_pc~0); 6910#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 6911#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7000#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6932#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 6933#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7130#L715 assume 1 == ~t10_pc~0; 7134#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 7017#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6902#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6903#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 6779#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6227#L734 assume !(1 == ~t11_pc~0); 6228#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 6713#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 6792#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5959#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 5960#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6987#L1213 assume !(1 == ~M_E~0); 6776#L1213-2 assume !(1 == ~T1_E~0); 6777#L1218-1 assume !(1 == ~T2_E~0); 5996#L1223-1 assume !(1 == ~T3_E~0); 5997#L1228-1 assume !(1 == ~T4_E~0); 6756#L1233-1 assume !(1 == ~T5_E~0); 7378#L1238-1 assume !(1 == ~T6_E~0); 7087#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7088#L1248-1 assume !(1 == ~T8_E~0); 7132#L1253-1 assume !(1 == ~T9_E~0); 7133#L1258-1 assume !(1 == ~T10_E~0); 7111#L1263-1 assume !(1 == ~T11_E~0); 7112#L1268-1 assume !(1 == ~E_1~0); 6947#L1273-1 assume !(1 == ~E_2~0); 6948#L1278-1 assume !(1 == ~E_3~0); 6547#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 6548#L1288-1 assume !(1 == ~E_5~0); 7225#L1293-1 assume !(1 == ~E_6~0); 7189#L1298-1 assume !(1 == ~E_7~0); 6975#L1303-1 assume !(1 == ~E_8~0); 6558#L1308-1 assume !(1 == ~E_9~0); 6447#L1313-1 assume !(1 == ~E_10~0); 6448#L1318-1 assume !(1 == ~E_11~0); 6457#L1323-1 assume { :end_inline_reset_delta_events } true; 6458#L1644-2 [2022-07-23 15:32:28,205 INFO L754 eck$LassoCheckResult]: Loop: 6458#L1644-2 assume !false; 7028#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7029#L1065 assume !false; 7104#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 7374#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6078#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 7290#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6563#L906 assume !(0 != eval_~tmp~0#1); 6565#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7101#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7102#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7242#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7294#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7257#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7258#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6331#L1110-3 assume !(0 == ~T5_E~0); 6332#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6614#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6615#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7085#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7339#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 6537#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 6032#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6033#L1150-3 assume !(0 == ~E_2~0); 6156#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6157#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6518#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6519#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6891#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6428#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6186#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 6187#L1190-3 assume !(0 == ~E_10~0); 7333#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 7334#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6741#L525-36 assume !(1 == ~m_pc~0); 6742#L525-38 is_master_triggered_~__retres1~0#1 := 0; 6287#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6288#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6573#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6574#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6482#L544-36 assume 1 == ~t1_pc~0; 6483#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7006#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6371#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6372#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7315#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7218#L563-36 assume 1 == ~t2_pc~0; 6274#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6030#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6031#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7093#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6754#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6755#L582-36 assume 1 == ~t3_pc~0; 6605#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6606#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6830#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6997#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6791#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6735#L601-36 assume 1 == ~t4_pc~0; 6634#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6635#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7382#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7300#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7301#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7206#L620-36 assume 1 == ~t5_pc~0; 6676#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6677#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7068#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6662#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6296#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6074#L639-36 assume 1 == ~t6_pc~0; 6075#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6114#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6115#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6354#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6355#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6931#L658-36 assume 1 == ~t7_pc~0; 6193#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6086#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7285#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6061#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 6062#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7052#L677-36 assume !(1 == ~t8_pc~0); 6856#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 6857#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6973#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7357#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 6879#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6880#L696-36 assume 1 == ~t9_pc~0; 6773#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 6775#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6134#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6135#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 6892#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6893#L715-36 assume 1 == ~t10_pc~0; 7026#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 5961#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5962#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5935#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5936#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6340#L734-36 assume 1 == ~t11_pc~0; 6341#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 6040#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 6362#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5953#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 5954#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6953#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6622#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6623#L1218-3 assume !(1 == ~T2_E~0); 6391#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6392#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6581#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6582#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6826#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6827#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7299#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7304#L1258-3 assume !(1 == ~T10_E~0); 6373#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 6374#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7269#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7287#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7289#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6705#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6706#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6571#L1298-3 assume !(1 == ~E_7~0); 6572#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7027#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 6568#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 6569#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 6375#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 6376#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6315#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 6726#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 7165#L1663 assume !(0 == start_simulation_~tmp~3#1); 6208#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 6929#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6152#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 6850#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 6096#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6097#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6435#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 7354#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 6458#L1644-2 [2022-07-23 15:32:28,205 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:28,206 INFO L85 PathProgramCache]: Analyzing trace with hash -456355416, now seen corresponding path program 1 times [2022-07-23 15:32:28,206 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:28,206 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1148988603] [2022-07-23 15:32:28,206 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:28,206 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:28,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:28,262 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:28,262 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:28,263 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1148988603] [2022-07-23 15:32:28,263 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1148988603] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:28,263 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:28,263 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-23 15:32:28,263 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [591436511] [2022-07-23 15:32:28,263 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:28,264 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-23 15:32:28,264 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:28,264 INFO L85 PathProgramCache]: Analyzing trace with hash 2047437327, now seen corresponding path program 1 times [2022-07-23 15:32:28,264 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:28,265 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [98466157] [2022-07-23 15:32:28,265 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:28,265 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:28,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:28,316 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:28,317 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:28,317 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [98466157] [2022-07-23 15:32:28,317 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [98466157] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:28,317 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:28,318 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-23 15:32:28,318 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1357860704] [2022-07-23 15:32:28,318 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:28,318 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-23 15:32:28,318 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-23 15:32:28,319 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-23 15:32:28,319 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-23 15:32:28,319 INFO L87 Difference]: Start difference. First operand 1476 states and 2192 transitions. cyclomatic complexity: 717 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:28,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-23 15:32:28,339 INFO L93 Difference]: Finished difference Result 1476 states and 2191 transitions. [2022-07-23 15:32:28,339 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-23 15:32:28,340 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2191 transitions. [2022-07-23 15:32:28,348 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-07-23 15:32:28,353 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2191 transitions. [2022-07-23 15:32:28,353 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2022-07-23 15:32:28,354 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2022-07-23 15:32:28,354 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2191 transitions. [2022-07-23 15:32:28,356 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-23 15:32:28,356 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2191 transitions. [2022-07-23 15:32:28,357 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2191 transitions. [2022-07-23 15:32:28,366 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2022-07-23 15:32:28,368 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4844173441734418) internal successors, (2191), 1475 states have internal predecessors, (2191), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:28,371 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2191 transitions. [2022-07-23 15:32:28,371 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2191 transitions. [2022-07-23 15:32:28,371 INFO L374 stractBuchiCegarLoop]: Abstraction has 1476 states and 2191 transitions. [2022-07-23 15:32:28,371 INFO L287 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-07-23 15:32:28,371 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2191 transitions. [2022-07-23 15:32:28,385 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-07-23 15:32:28,385 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-23 15:32:28,385 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-23 15:32:28,386 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:28,387 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:28,387 INFO L752 eck$LassoCheckResult]: Stem: 10014#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 10015#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 10024#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10025#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9790#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 9791#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9660#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9572#L771-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 9295#L776-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8930#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8931#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8979#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8980#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9908#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9909#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 9947#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9395#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9396#L1090 assume !(0 == ~M_E~0); 9438#L1090-2 assume !(0 == ~T1_E~0); 9439#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10085#L1100-1 assume !(0 == ~T3_E~0); 10086#L1105-1 assume !(0 == ~T4_E~0); 9214#L1110-1 assume !(0 == ~T5_E~0); 9215#L1115-1 assume !(0 == ~T6_E~0); 9610#L1120-1 assume !(0 == ~T7_E~0); 9887#L1125-1 assume !(0 == ~T8_E~0); 10356#L1130-1 assume !(0 == ~T9_E~0); 10105#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9400#L1140-1 assume !(0 == ~T11_E~0); 9401#L1145-1 assume !(0 == ~E_1~0); 10039#L1150-1 assume !(0 == ~E_2~0); 9585#L1155-1 assume !(0 == ~E_3~0); 9586#L1160-1 assume !(0 == ~E_4~0); 9668#L1165-1 assume !(0 == ~E_5~0); 9669#L1170-1 assume !(0 == ~E_6~0); 10277#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 9746#L1180-1 assume !(0 == ~E_8~0); 9747#L1185-1 assume !(0 == ~E_9~0); 9397#L1190-1 assume !(0 == ~E_10~0); 9398#L1195-1 assume !(0 == ~E_11~0); 9760#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9607#L525 assume !(1 == ~m_pc~0); 9018#L525-2 is_master_triggered_~__retres1~0#1 := 0; 9019#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9764#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9765#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9384#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9385#L544 assume 1 == ~t1_pc~0; 9645#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9609#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10037#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9235#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 9236#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9858#L563 assume !(1 == ~t2_pc~0); 10026#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9039#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9040#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9468#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 9469#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9931#L582 assume 1 == ~t3_pc~0; 9179#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9180#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10328#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10286#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 9113#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9114#L601 assume !(1 == ~t4_pc~0); 10054#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 9611#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9612#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10048#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 10049#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10320#L620 assume 1 == ~t5_pc~0; 9070#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9071#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9883#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9884#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 10335#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10336#L639 assume !(1 == ~t6_pc~0); 9885#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 9508#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9509#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10289#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 9619#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9620#L658 assume 1 == ~t7_pc~0; 9886#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9813#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9918#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9919#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 9391#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9392#L677 assume 1 == ~t8_pc~0; 9624#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9194#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9195#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9465#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 9466#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10144#L696 assume !(1 == ~t9_pc~0); 9871#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 9872#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9959#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9891#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9892#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10089#L715 assume 1 == ~t10_pc~0; 10093#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 9976#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9861#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9862#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 9738#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9188#L734 assume !(1 == ~t11_pc~0); 9189#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 9672#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9751#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8920#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 8921#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9946#L1213 assume !(1 == ~M_E~0); 9736#L1213-2 assume !(1 == ~T1_E~0); 9737#L1218-1 assume !(1 == ~T2_E~0); 8955#L1223-1 assume !(1 == ~T3_E~0); 8956#L1228-1 assume !(1 == ~T4_E~0); 9715#L1233-1 assume !(1 == ~T5_E~0); 10337#L1238-1 assume !(1 == ~T6_E~0); 10046#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10047#L1248-1 assume !(1 == ~T8_E~0); 10091#L1253-1 assume !(1 == ~T9_E~0); 10092#L1258-1 assume !(1 == ~T10_E~0); 10070#L1263-1 assume !(1 == ~T11_E~0); 10071#L1268-1 assume !(1 == ~E_1~0); 9906#L1273-1 assume !(1 == ~E_2~0); 9907#L1278-1 assume !(1 == ~E_3~0); 9506#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 9507#L1288-1 assume !(1 == ~E_5~0); 10184#L1293-1 assume !(1 == ~E_6~0); 10148#L1298-1 assume !(1 == ~E_7~0); 9934#L1303-1 assume !(1 == ~E_8~0); 9517#L1308-1 assume !(1 == ~E_9~0); 9406#L1313-1 assume !(1 == ~E_10~0); 9407#L1318-1 assume !(1 == ~E_11~0); 9419#L1323-1 assume { :end_inline_reset_delta_events } true; 9420#L1644-2 [2022-07-23 15:32:28,387 INFO L754 eck$LassoCheckResult]: Loop: 9420#L1644-2 assume !false; 9987#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9988#L1065 assume !false; 10063#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 10333#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9037#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 10249#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9522#L906 assume !(0 != eval_~tmp~0#1); 9524#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10061#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10062#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10201#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10253#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10216#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10217#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9290#L1110-3 assume !(0 == ~T5_E~0); 9291#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9573#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9574#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 10044#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10298#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9498#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 8993#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8994#L1150-3 assume !(0 == ~E_2~0); 9116#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9117#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9477#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9478#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9850#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9387#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9146#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 9147#L1190-3 assume !(0 == ~E_10~0); 10292#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 10293#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9700#L525-36 assume !(1 == ~m_pc~0); 9701#L525-38 is_master_triggered_~__retres1~0#1 := 0; 9251#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9252#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9533#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9534#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9441#L544-36 assume 1 == ~t1_pc~0; 9442#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9965#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9336#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9337#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10275#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10177#L563-36 assume 1 == ~t2_pc~0; 9233#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8989#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8990#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10052#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9713#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9714#L582-36 assume 1 == ~t3_pc~0; 9564#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9565#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9789#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9956#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9750#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9691#L601-36 assume 1 == ~t4_pc~0; 9593#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9594#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10341#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10259#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10260#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10163#L620-36 assume 1 == ~t5_pc~0; 9633#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9634#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10027#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9621#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9255#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9033#L639-36 assume 1 == ~t6_pc~0; 9034#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9068#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9069#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9311#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9312#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9890#L658-36 assume !(1 == ~t7_pc~0); 9044#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 9045#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10244#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9020#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 9021#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10011#L677-36 assume !(1 == ~t8_pc~0); 9815#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 9816#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9932#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10316#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9838#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9839#L696-36 assume 1 == ~t9_pc~0; 9732#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9734#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9090#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9091#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9851#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9852#L715-36 assume 1 == ~t10_pc~0; 9985#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8918#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8919#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8894#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8895#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9299#L734-36 assume 1 == ~t11_pc~0; 9300#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 8999#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9321#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8912#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 8913#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9912#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9579#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9580#L1218-3 assume !(1 == ~T2_E~0); 9350#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9351#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9540#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9541#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9785#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9786#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10257#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 10262#L1258-3 assume !(1 == ~T10_E~0); 9330#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 9331#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10228#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10246#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10248#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9664#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9665#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9530#L1298-3 assume !(1 == ~E_7~0); 9531#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9986#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9527#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 9528#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 9332#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 9333#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9274#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 9685#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 10124#L1663 assume !(0 == start_simulation_~tmp~3#1); 9162#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 9888#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9111#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 9807#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 9052#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9053#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9394#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 10313#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 9420#L1644-2 [2022-07-23 15:32:28,388 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:28,388 INFO L85 PathProgramCache]: Analyzing trace with hash 88517158, now seen corresponding path program 1 times [2022-07-23 15:32:28,388 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:28,388 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [272468399] [2022-07-23 15:32:28,388 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:28,389 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:28,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:28,419 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:28,420 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:28,420 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [272468399] [2022-07-23 15:32:28,420 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [272468399] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:28,420 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:28,421 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-23 15:32:28,422 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [945451112] [2022-07-23 15:32:28,422 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:28,423 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-23 15:32:28,423 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:28,423 INFO L85 PathProgramCache]: Analyzing trace with hash 869462766, now seen corresponding path program 1 times [2022-07-23 15:32:28,423 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:28,423 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1967761408] [2022-07-23 15:32:28,424 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:28,424 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:28,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:28,449 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:28,450 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:28,450 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1967761408] [2022-07-23 15:32:28,450 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1967761408] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:28,450 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:28,450 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-23 15:32:28,451 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1846731843] [2022-07-23 15:32:28,451 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:28,451 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-23 15:32:28,451 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-23 15:32:28,451 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-23 15:32:28,452 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-23 15:32:28,452 INFO L87 Difference]: Start difference. First operand 1476 states and 2191 transitions. cyclomatic complexity: 716 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:28,467 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-23 15:32:28,468 INFO L93 Difference]: Finished difference Result 1476 states and 2190 transitions. [2022-07-23 15:32:28,468 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-23 15:32:28,469 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2190 transitions. [2022-07-23 15:32:28,475 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-07-23 15:32:28,480 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2190 transitions. [2022-07-23 15:32:28,480 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2022-07-23 15:32:28,481 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2022-07-23 15:32:28,481 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2190 transitions. [2022-07-23 15:32:28,482 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-23 15:32:28,482 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2190 transitions. [2022-07-23 15:32:28,484 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2190 transitions. [2022-07-23 15:32:28,492 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2022-07-23 15:32:28,494 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.483739837398374) internal successors, (2190), 1475 states have internal predecessors, (2190), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:28,497 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2190 transitions. [2022-07-23 15:32:28,497 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2190 transitions. [2022-07-23 15:32:28,497 INFO L374 stractBuchiCegarLoop]: Abstraction has 1476 states and 2190 transitions. [2022-07-23 15:32:28,497 INFO L287 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-07-23 15:32:28,497 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2190 transitions. [2022-07-23 15:32:28,502 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-07-23 15:32:28,502 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-23 15:32:28,502 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-23 15:32:28,503 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:28,503 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:28,503 INFO L752 eck$LassoCheckResult]: Stem: 12973#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 12974#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 12981#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12982#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12749#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 12750#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12619#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12531#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12254#L776-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 11889#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11890#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 11938#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11939#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12867#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12868#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 12906#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12354#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12355#L1090 assume !(0 == ~M_E~0); 12397#L1090-2 assume !(0 == ~T1_E~0); 12398#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13043#L1100-1 assume !(0 == ~T3_E~0); 13044#L1105-1 assume !(0 == ~T4_E~0); 12172#L1110-1 assume !(0 == ~T5_E~0); 12173#L1115-1 assume !(0 == ~T6_E~0); 12569#L1120-1 assume !(0 == ~T7_E~0); 12846#L1125-1 assume !(0 == ~T8_E~0); 13315#L1130-1 assume !(0 == ~T9_E~0); 13064#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12359#L1140-1 assume !(0 == ~T11_E~0); 12360#L1145-1 assume !(0 == ~E_1~0); 12998#L1150-1 assume !(0 == ~E_2~0); 12544#L1155-1 assume !(0 == ~E_3~0); 12545#L1160-1 assume !(0 == ~E_4~0); 12627#L1165-1 assume !(0 == ~E_5~0); 12628#L1170-1 assume !(0 == ~E_6~0); 13236#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 12705#L1180-1 assume !(0 == ~E_8~0); 12706#L1185-1 assume !(0 == ~E_9~0); 12356#L1190-1 assume !(0 == ~E_10~0); 12357#L1195-1 assume !(0 == ~E_11~0); 12719#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12559#L525 assume !(1 == ~m_pc~0); 11977#L525-2 is_master_triggered_~__retres1~0#1 := 0; 11978#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12723#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12724#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12343#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12344#L544 assume 1 == ~t1_pc~0; 12604#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12568#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12996#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12194#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 12195#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12817#L563 assume !(1 == ~t2_pc~0); 12983#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11998#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11999#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12427#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 12428#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12890#L582 assume 1 == ~t3_pc~0; 12136#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12137#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13287#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13245#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 12072#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12073#L601 assume !(1 == ~t4_pc~0); 13013#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12570#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12571#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13007#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 13008#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13279#L620 assume 1 == ~t5_pc~0; 12027#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12028#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12842#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12843#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 13294#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13295#L639 assume !(1 == ~t6_pc~0); 12844#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12467#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12468#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13248#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 12578#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12579#L658 assume 1 == ~t7_pc~0; 12845#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12770#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12877#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12878#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 12350#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12351#L677 assume 1 == ~t8_pc~0; 12581#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12153#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12154#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12424#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 12425#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13103#L696 assume !(1 == ~t9_pc~0); 12828#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 12829#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12918#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12850#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12851#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13048#L715 assume 1 == ~t10_pc~0; 13052#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 12935#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12820#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12821#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 12697#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12145#L734 assume !(1 == ~t11_pc~0); 12146#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 12631#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12710#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11877#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 11878#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12905#L1213 assume !(1 == ~M_E~0); 12694#L1213-2 assume !(1 == ~T1_E~0); 12695#L1218-1 assume !(1 == ~T2_E~0); 11914#L1223-1 assume !(1 == ~T3_E~0); 11915#L1228-1 assume !(1 == ~T4_E~0); 12674#L1233-1 assume !(1 == ~T5_E~0); 13296#L1238-1 assume !(1 == ~T6_E~0); 13005#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13006#L1248-1 assume !(1 == ~T8_E~0); 13050#L1253-1 assume !(1 == ~T9_E~0); 13051#L1258-1 assume !(1 == ~T10_E~0); 13029#L1263-1 assume !(1 == ~T11_E~0); 13030#L1268-1 assume !(1 == ~E_1~0); 12865#L1273-1 assume !(1 == ~E_2~0); 12866#L1278-1 assume !(1 == ~E_3~0); 12465#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 12466#L1288-1 assume !(1 == ~E_5~0); 13143#L1293-1 assume !(1 == ~E_6~0); 13107#L1298-1 assume !(1 == ~E_7~0); 12893#L1303-1 assume !(1 == ~E_8~0); 12476#L1308-1 assume !(1 == ~E_9~0); 12365#L1313-1 assume !(1 == ~E_10~0); 12366#L1318-1 assume !(1 == ~E_11~0); 12375#L1323-1 assume { :end_inline_reset_delta_events } true; 12376#L1644-2 [2022-07-23 15:32:28,504 INFO L754 eck$LassoCheckResult]: Loop: 12376#L1644-2 assume !false; 12946#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12947#L1065 assume !false; 13022#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 13292#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 11996#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 13208#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 12481#L906 assume !(0 != eval_~tmp~0#1); 12483#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13019#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13020#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13160#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13212#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13175#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13176#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12249#L1110-3 assume !(0 == ~T5_E~0); 12250#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12532#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12533#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13003#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13257#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12455#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 11950#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11951#L1150-3 assume !(0 == ~E_2~0); 12074#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12075#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12436#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12437#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12809#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12346#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12104#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12105#L1190-3 assume !(0 == ~E_10~0); 13251#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 13252#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12659#L525-36 assume !(1 == ~m_pc~0); 12660#L525-38 is_master_triggered_~__retres1~0#1 := 0; 12205#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12206#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12491#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12492#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12400#L544-36 assume 1 == ~t1_pc~0; 12401#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12924#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12289#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12290#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13233#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13136#L563-36 assume 1 == ~t2_pc~0; 12192#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11948#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11949#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13011#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12672#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12673#L582-36 assume 1 == ~t3_pc~0; 12523#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12524#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12748#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12915#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12709#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12653#L601-36 assume 1 == ~t4_pc~0; 12552#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12553#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13300#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13218#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13219#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13124#L620-36 assume 1 == ~t5_pc~0; 12594#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12595#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12986#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12580#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12214#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11992#L639-36 assume 1 == ~t6_pc~0; 11993#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12032#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12033#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12272#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12273#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12849#L658-36 assume !(1 == ~t7_pc~0); 12003#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 12004#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13203#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11979#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 11980#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12970#L677-36 assume !(1 == ~t8_pc~0); 12774#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 12775#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12891#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13275#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12797#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12798#L696-36 assume 1 == ~t9_pc~0; 12691#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12693#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12052#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12053#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12810#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12811#L715-36 assume 1 == ~t10_pc~0; 12944#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 11879#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11880#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11853#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 11854#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12258#L734-36 assume 1 == ~t11_pc~0; 12259#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 11958#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12280#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11871#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 11872#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12871#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12540#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12541#L1218-3 assume !(1 == ~T2_E~0); 12309#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12310#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12499#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12500#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12744#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12745#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13217#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 13222#L1258-3 assume !(1 == ~T10_E~0); 12291#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 12292#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13187#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13205#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13207#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12623#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12624#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12489#L1298-3 assume !(1 == ~E_7~0); 12490#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12945#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12486#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12487#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 12293#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 12294#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12233#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 12644#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 13083#L1663 assume !(0 == start_simulation_~tmp~3#1); 12126#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 12847#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12070#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 12768#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 12014#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12015#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12353#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 13272#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 12376#L1644-2 [2022-07-23 15:32:28,504 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:28,504 INFO L85 PathProgramCache]: Analyzing trace with hash -586642968, now seen corresponding path program 1 times [2022-07-23 15:32:28,505 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:28,505 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1099788652] [2022-07-23 15:32:28,505 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:28,505 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:28,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:28,523 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:28,523 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:28,523 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1099788652] [2022-07-23 15:32:28,523 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1099788652] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:28,524 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:28,524 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-23 15:32:28,524 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1443233342] [2022-07-23 15:32:28,524 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:28,524 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-23 15:32:28,524 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:28,525 INFO L85 PathProgramCache]: Analyzing trace with hash 869462766, now seen corresponding path program 2 times [2022-07-23 15:32:28,525 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:28,525 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [114951863] [2022-07-23 15:32:28,525 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:28,525 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:28,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:28,568 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:28,568 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:28,569 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [114951863] [2022-07-23 15:32:28,569 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [114951863] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:28,569 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:28,569 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-23 15:32:28,569 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [780973487] [2022-07-23 15:32:28,569 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:28,570 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-23 15:32:28,570 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-23 15:32:28,570 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-23 15:32:28,570 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-23 15:32:28,570 INFO L87 Difference]: Start difference. First operand 1476 states and 2190 transitions. cyclomatic complexity: 715 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:28,586 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-23 15:32:28,587 INFO L93 Difference]: Finished difference Result 1476 states and 2189 transitions. [2022-07-23 15:32:28,587 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-23 15:32:28,587 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2189 transitions. [2022-07-23 15:32:28,593 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-07-23 15:32:28,598 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2189 transitions. [2022-07-23 15:32:28,598 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2022-07-23 15:32:28,599 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2022-07-23 15:32:28,599 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2189 transitions. [2022-07-23 15:32:28,601 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-23 15:32:28,601 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2189 transitions. [2022-07-23 15:32:28,602 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2189 transitions. [2022-07-23 15:32:28,612 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2022-07-23 15:32:28,614 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4830623306233062) internal successors, (2189), 1475 states have internal predecessors, (2189), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:28,617 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2189 transitions. [2022-07-23 15:32:28,618 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2189 transitions. [2022-07-23 15:32:28,618 INFO L374 stractBuchiCegarLoop]: Abstraction has 1476 states and 2189 transitions. [2022-07-23 15:32:28,618 INFO L287 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-07-23 15:32:28,618 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2189 transitions. [2022-07-23 15:32:28,622 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-07-23 15:32:28,623 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-23 15:32:28,623 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-23 15:32:28,624 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:28,624 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:28,624 INFO L752 eck$LassoCheckResult]: Stem: 15932#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 15933#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 15942#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15943#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15708#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 15709#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15578#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15490#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15213#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14848#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 14849#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 14897#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14898#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 15826#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 15827#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 15865#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 15313#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15314#L1090 assume !(0 == ~M_E~0); 15356#L1090-2 assume !(0 == ~T1_E~0); 15357#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16003#L1100-1 assume !(0 == ~T3_E~0); 16004#L1105-1 assume !(0 == ~T4_E~0); 15132#L1110-1 assume !(0 == ~T5_E~0); 15133#L1115-1 assume !(0 == ~T6_E~0); 15528#L1120-1 assume !(0 == ~T7_E~0); 15805#L1125-1 assume !(0 == ~T8_E~0); 16274#L1130-1 assume !(0 == ~T9_E~0); 16023#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 15318#L1140-1 assume !(0 == ~T11_E~0); 15319#L1145-1 assume !(0 == ~E_1~0); 15957#L1150-1 assume !(0 == ~E_2~0); 15503#L1155-1 assume !(0 == ~E_3~0); 15504#L1160-1 assume !(0 == ~E_4~0); 15586#L1165-1 assume !(0 == ~E_5~0); 15587#L1170-1 assume !(0 == ~E_6~0); 16195#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 15664#L1180-1 assume !(0 == ~E_8~0); 15665#L1185-1 assume !(0 == ~E_9~0); 15315#L1190-1 assume !(0 == ~E_10~0); 15316#L1195-1 assume !(0 == ~E_11~0); 15678#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15525#L525 assume !(1 == ~m_pc~0); 14936#L525-2 is_master_triggered_~__retres1~0#1 := 0; 14937#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15682#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15683#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15302#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15303#L544 assume 1 == ~t1_pc~0; 15563#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15527#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15955#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15153#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 15154#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15776#L563 assume !(1 == ~t2_pc~0); 15944#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14957#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14958#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15386#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 15387#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15849#L582 assume 1 == ~t3_pc~0; 15097#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15098#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16246#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16204#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 15031#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15032#L601 assume !(1 == ~t4_pc~0); 15972#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 15529#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15530#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15966#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 15967#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16238#L620 assume 1 == ~t5_pc~0; 14988#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14989#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15801#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15802#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 16253#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16254#L639 assume !(1 == ~t6_pc~0); 15803#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 15426#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15427#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16207#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 15537#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15538#L658 assume 1 == ~t7_pc~0; 15804#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15729#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15836#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15837#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 15309#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15310#L677 assume 1 == ~t8_pc~0; 15540#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15112#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15113#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15383#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 15384#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16062#L696 assume !(1 == ~t9_pc~0); 15789#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 15790#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15877#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15809#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 15810#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16007#L715 assume 1 == ~t10_pc~0; 16011#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 15894#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 15779#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 15780#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 15656#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 15106#L734 assume !(1 == ~t11_pc~0); 15107#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 15590#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15669#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14838#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 14839#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15864#L1213 assume !(1 == ~M_E~0); 15654#L1213-2 assume !(1 == ~T1_E~0); 15655#L1218-1 assume !(1 == ~T2_E~0); 14873#L1223-1 assume !(1 == ~T3_E~0); 14874#L1228-1 assume !(1 == ~T4_E~0); 15633#L1233-1 assume !(1 == ~T5_E~0); 16255#L1238-1 assume !(1 == ~T6_E~0); 15964#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15965#L1248-1 assume !(1 == ~T8_E~0); 16009#L1253-1 assume !(1 == ~T9_E~0); 16010#L1258-1 assume !(1 == ~T10_E~0); 15988#L1263-1 assume !(1 == ~T11_E~0); 15989#L1268-1 assume !(1 == ~E_1~0); 15824#L1273-1 assume !(1 == ~E_2~0); 15825#L1278-1 assume !(1 == ~E_3~0); 15424#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 15425#L1288-1 assume !(1 == ~E_5~0); 16102#L1293-1 assume !(1 == ~E_6~0); 16066#L1298-1 assume !(1 == ~E_7~0); 15852#L1303-1 assume !(1 == ~E_8~0); 15435#L1308-1 assume !(1 == ~E_9~0); 15324#L1313-1 assume !(1 == ~E_10~0); 15325#L1318-1 assume !(1 == ~E_11~0); 15337#L1323-1 assume { :end_inline_reset_delta_events } true; 15338#L1644-2 [2022-07-23 15:32:28,625 INFO L754 eck$LassoCheckResult]: Loop: 15338#L1644-2 assume !false; 15905#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15906#L1065 assume !false; 15981#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 16251#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 14955#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 16167#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15440#L906 assume !(0 != eval_~tmp~0#1); 15442#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15978#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15979#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16119#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16171#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16134#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16135#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15208#L1110-3 assume !(0 == ~T5_E~0); 15209#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15491#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15492#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 15962#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16216#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 15414#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 14911#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14912#L1150-3 assume !(0 == ~E_2~0); 15034#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15035#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15395#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15396#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15768#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15305#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 15064#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15065#L1190-3 assume !(0 == ~E_10~0); 16210#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16211#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15618#L525-36 assume !(1 == ~m_pc~0); 15619#L525-38 is_master_triggered_~__retres1~0#1 := 0; 15169#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15170#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15451#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15452#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15359#L544-36 assume 1 == ~t1_pc~0; 15360#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15883#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15254#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15255#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16193#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16095#L563-36 assume !(1 == ~t2_pc~0); 15152#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 14907#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14908#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15970#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15631#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15632#L582-36 assume 1 == ~t3_pc~0; 15482#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15483#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15707#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15874#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15668#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15612#L601-36 assume 1 == ~t4_pc~0; 15511#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15512#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16259#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16177#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16178#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16083#L620-36 assume 1 == ~t5_pc~0; 15554#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15555#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15947#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15539#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15173#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14948#L639-36 assume 1 == ~t6_pc~0; 14949#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14986#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14987#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15227#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15228#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15808#L658-36 assume 1 == ~t7_pc~0; 15068#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14960#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16162#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14938#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 14939#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15929#L677-36 assume !(1 == ~t8_pc~0); 15732#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 15733#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15850#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16234#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 15756#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15757#L696-36 assume 1 == ~t9_pc~0; 15650#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15652#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15008#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15009#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 15769#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 15770#L715-36 assume !(1 == ~t10_pc~0); 15740#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 14836#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14837#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14812#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 14813#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 15217#L734-36 assume 1 == ~t11_pc~0; 15218#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 14917#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15239#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14830#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 14831#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15830#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15497#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15498#L1218-3 assume !(1 == ~T2_E~0); 15268#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15269#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15458#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15459#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15703#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15704#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16175#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16180#L1258-3 assume !(1 == ~T10_E~0); 15248#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 15249#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16146#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16164#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16166#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15582#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15583#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15447#L1298-3 assume !(1 == ~E_7~0); 15448#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 15904#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 15445#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 15446#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 15250#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 15251#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15192#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 15603#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 16042#L1663 assume !(0 == start_simulation_~tmp~3#1); 15078#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 15806#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15029#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 15725#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 14970#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14971#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15312#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 16231#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 15338#L1644-2 [2022-07-23 15:32:28,625 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:28,625 INFO L85 PathProgramCache]: Analyzing trace with hash 361408998, now seen corresponding path program 1 times [2022-07-23 15:32:28,625 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:28,626 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1299156151] [2022-07-23 15:32:28,626 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:28,626 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:28,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:28,643 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:28,644 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:28,644 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1299156151] [2022-07-23 15:32:28,644 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1299156151] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:28,644 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:28,644 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-23 15:32:28,645 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [448774162] [2022-07-23 15:32:28,645 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:28,645 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-23 15:32:28,645 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:28,645 INFO L85 PathProgramCache]: Analyzing trace with hash -459098803, now seen corresponding path program 1 times [2022-07-23 15:32:28,646 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:28,646 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [786988716] [2022-07-23 15:32:28,646 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:28,646 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:28,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:28,669 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:28,670 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:28,670 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [786988716] [2022-07-23 15:32:28,670 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [786988716] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:28,670 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:28,670 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-23 15:32:28,670 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1237931238] [2022-07-23 15:32:28,671 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:28,671 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-23 15:32:28,671 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-23 15:32:28,671 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-23 15:32:28,671 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-23 15:32:28,672 INFO L87 Difference]: Start difference. First operand 1476 states and 2189 transitions. cyclomatic complexity: 714 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:28,687 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-23 15:32:28,687 INFO L93 Difference]: Finished difference Result 1476 states and 2188 transitions. [2022-07-23 15:32:28,688 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-23 15:32:28,688 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2188 transitions. [2022-07-23 15:32:28,694 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-07-23 15:32:28,699 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2188 transitions. [2022-07-23 15:32:28,699 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2022-07-23 15:32:28,700 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2022-07-23 15:32:28,700 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2188 transitions. [2022-07-23 15:32:28,701 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-23 15:32:28,701 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2188 transitions. [2022-07-23 15:32:28,703 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2188 transitions. [2022-07-23 15:32:28,731 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2022-07-23 15:32:28,733 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4823848238482384) internal successors, (2188), 1475 states have internal predecessors, (2188), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:28,736 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2188 transitions. [2022-07-23 15:32:28,736 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2188 transitions. [2022-07-23 15:32:28,736 INFO L374 stractBuchiCegarLoop]: Abstraction has 1476 states and 2188 transitions. [2022-07-23 15:32:28,736 INFO L287 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-07-23 15:32:28,737 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2188 transitions. [2022-07-23 15:32:28,740 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-07-23 15:32:28,740 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-23 15:32:28,740 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-23 15:32:28,741 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:28,741 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:28,742 INFO L752 eck$LassoCheckResult]: Stem: 18891#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 18892#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 18901#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18902#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18667#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 18668#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18537#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18449#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18172#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17807#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17808#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17856#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17857#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 18787#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 18788#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 18831#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 18272#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18273#L1090 assume !(0 == ~M_E~0); 18319#L1090-2 assume !(0 == ~T1_E~0); 18320#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18962#L1100-1 assume !(0 == ~T3_E~0); 18963#L1105-1 assume !(0 == ~T4_E~0); 18091#L1110-1 assume !(0 == ~T5_E~0); 18092#L1115-1 assume !(0 == ~T6_E~0); 18490#L1120-1 assume !(0 == ~T7_E~0); 18764#L1125-1 assume !(0 == ~T8_E~0); 19233#L1130-1 assume !(0 == ~T9_E~0); 18982#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 18279#L1140-1 assume !(0 == ~T11_E~0); 18280#L1145-1 assume !(0 == ~E_1~0); 18916#L1150-1 assume !(0 == ~E_2~0); 18462#L1155-1 assume !(0 == ~E_3~0); 18463#L1160-1 assume !(0 == ~E_4~0); 18545#L1165-1 assume !(0 == ~E_5~0); 18546#L1170-1 assume !(0 == ~E_6~0); 19154#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 18623#L1180-1 assume !(0 == ~E_8~0); 18624#L1185-1 assume !(0 == ~E_9~0); 18274#L1190-1 assume !(0 == ~E_10~0); 18275#L1195-1 assume !(0 == ~E_11~0); 18637#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18484#L525 assume !(1 == ~m_pc~0); 17895#L525-2 is_master_triggered_~__retres1~0#1 := 0; 17896#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18641#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18642#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18262#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18263#L544 assume 1 == ~t1_pc~0; 18522#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18486#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18914#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18112#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 18113#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18735#L563 assume !(1 == ~t2_pc~0); 18903#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 17916#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17917#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18348#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 18349#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18808#L582 assume 1 == ~t3_pc~0; 18056#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18057#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19205#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19164#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 17990#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17991#L601 assume !(1 == ~t4_pc~0); 18931#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 18491#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18492#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18925#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 18926#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19197#L620 assume 1 == ~t5_pc~0; 17949#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17950#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18761#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18762#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 19212#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19213#L639 assume !(1 == ~t6_pc~0); 18763#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 18385#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18386#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19166#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 18496#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18497#L658 assume 1 == ~t7_pc~0; 18760#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18688#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18795#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18796#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 18268#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18269#L677 assume 1 == ~t8_pc~0; 18499#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18071#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18072#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18342#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 18343#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19021#L696 assume !(1 == ~t9_pc~0); 18746#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 18747#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18836#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18768#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 18769#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18966#L715 assume 1 == ~t10_pc~0; 18970#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 18853#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18738#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 18739#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 18615#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18063#L734 assume !(1 == ~t11_pc~0); 18064#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 18549#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18628#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17795#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 17796#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18823#L1213 assume !(1 == ~M_E~0); 18612#L1213-2 assume !(1 == ~T1_E~0); 18613#L1218-1 assume !(1 == ~T2_E~0); 17832#L1223-1 assume !(1 == ~T3_E~0); 17833#L1228-1 assume !(1 == ~T4_E~0); 18592#L1233-1 assume !(1 == ~T5_E~0); 19214#L1238-1 assume !(1 == ~T6_E~0); 18923#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18924#L1248-1 assume !(1 == ~T8_E~0); 18968#L1253-1 assume !(1 == ~T9_E~0); 18969#L1258-1 assume !(1 == ~T10_E~0); 18947#L1263-1 assume !(1 == ~T11_E~0); 18948#L1268-1 assume !(1 == ~E_1~0); 18783#L1273-1 assume !(1 == ~E_2~0); 18784#L1278-1 assume !(1 == ~E_3~0); 18383#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 18384#L1288-1 assume !(1 == ~E_5~0); 19061#L1293-1 assume !(1 == ~E_6~0); 19025#L1298-1 assume !(1 == ~E_7~0); 18811#L1303-1 assume !(1 == ~E_8~0); 18394#L1308-1 assume !(1 == ~E_9~0); 18283#L1313-1 assume !(1 == ~E_10~0); 18284#L1318-1 assume !(1 == ~E_11~0); 18293#L1323-1 assume { :end_inline_reset_delta_events } true; 18294#L1644-2 [2022-07-23 15:32:28,742 INFO L754 eck$LassoCheckResult]: Loop: 18294#L1644-2 assume !false; 18864#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18865#L1065 assume !false; 18940#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 19210#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 17914#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 19126#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 18399#L906 assume !(0 != eval_~tmp~0#1); 18401#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18937#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18938#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19078#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19130#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19093#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19094#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18167#L1110-3 assume !(0 == ~T5_E~0); 18168#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18450#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18451#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 18921#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19175#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 18373#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 17868#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17869#L1150-3 assume !(0 == ~E_2~0); 17992#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17993#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18354#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18355#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 18727#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 18264#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 18022#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 18023#L1190-3 assume !(0 == ~E_10~0); 19169#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 19170#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18577#L525-36 assume !(1 == ~m_pc~0); 18578#L525-38 is_master_triggered_~__retres1~0#1 := 0; 18123#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18124#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18409#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18410#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18316#L544-36 assume 1 == ~t1_pc~0; 18317#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18842#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18207#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18208#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19151#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19054#L563-36 assume 1 == ~t2_pc~0; 18110#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17866#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17867#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18929#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18590#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18591#L582-36 assume 1 == ~t3_pc~0; 18441#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18442#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18666#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18833#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18627#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18571#L601-36 assume 1 == ~t4_pc~0; 18470#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18471#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19218#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19136#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19137#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19042#L620-36 assume 1 == ~t5_pc~0; 18512#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 18513#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18904#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18498#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18132#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17910#L639-36 assume 1 == ~t6_pc~0; 17911#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17947#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17948#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18190#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 18191#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18767#L658-36 assume !(1 == ~t7_pc~0); 17921#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 17922#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19121#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17897#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 17898#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18888#L677-36 assume !(1 == ~t8_pc~0); 18692#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 18693#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18809#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19193#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18715#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18716#L696-36 assume 1 == ~t9_pc~0; 18609#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18611#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17970#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17971#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 18728#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18729#L715-36 assume !(1 == ~t10_pc~0); 18699#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 17797#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17798#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17771#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 17772#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18176#L734-36 assume 1 == ~t11_pc~0; 18177#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 17876#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18198#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17789#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 17790#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18789#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18458#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18459#L1218-3 assume !(1 == ~T2_E~0); 18227#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18228#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18417#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18418#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18662#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18663#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19135#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19140#L1258-3 assume !(1 == ~T10_E~0); 18209#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 18210#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19105#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19123#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19125#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18541#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18542#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18407#L1298-3 assume !(1 == ~E_7~0); 18408#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 18863#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 18404#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 18405#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 18211#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 18212#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 18151#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 18562#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 19001#L1663 assume !(0 == start_simulation_~tmp~3#1); 18044#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 18765#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 17988#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 18686#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 17932#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17933#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18271#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 19190#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 18294#L1644-2 [2022-07-23 15:32:28,743 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:28,743 INFO L85 PathProgramCache]: Analyzing trace with hash 946180648, now seen corresponding path program 1 times [2022-07-23 15:32:28,743 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:28,743 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1246183846] [2022-07-23 15:32:28,743 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:28,743 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:28,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:28,761 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:28,761 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:28,761 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1246183846] [2022-07-23 15:32:28,761 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1246183846] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:28,761 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:28,761 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-23 15:32:28,762 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1850638833] [2022-07-23 15:32:28,762 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:28,762 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-23 15:32:28,762 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:28,762 INFO L85 PathProgramCache]: Analyzing trace with hash -1992669811, now seen corresponding path program 1 times [2022-07-23 15:32:28,762 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:28,763 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1083644323] [2022-07-23 15:32:28,763 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:28,763 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:28,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:28,786 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:28,786 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:28,786 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1083644323] [2022-07-23 15:32:28,787 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1083644323] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:28,787 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:28,787 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-23 15:32:28,787 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [759314254] [2022-07-23 15:32:28,787 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:28,787 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-23 15:32:28,788 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-23 15:32:28,788 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-23 15:32:28,788 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-23 15:32:28,788 INFO L87 Difference]: Start difference. First operand 1476 states and 2188 transitions. cyclomatic complexity: 713 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:28,804 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-23 15:32:28,804 INFO L93 Difference]: Finished difference Result 1476 states and 2187 transitions. [2022-07-23 15:32:28,804 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-23 15:32:28,805 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2187 transitions. [2022-07-23 15:32:28,810 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-07-23 15:32:28,814 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2187 transitions. [2022-07-23 15:32:28,815 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2022-07-23 15:32:28,816 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2022-07-23 15:32:28,816 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2187 transitions. [2022-07-23 15:32:28,817 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-23 15:32:28,817 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2187 transitions. [2022-07-23 15:32:28,818 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2187 transitions. [2022-07-23 15:32:28,827 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2022-07-23 15:32:28,829 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4817073170731707) internal successors, (2187), 1475 states have internal predecessors, (2187), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:28,832 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2187 transitions. [2022-07-23 15:32:28,832 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2187 transitions. [2022-07-23 15:32:28,832 INFO L374 stractBuchiCegarLoop]: Abstraction has 1476 states and 2187 transitions. [2022-07-23 15:32:28,832 INFO L287 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-07-23 15:32:28,832 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2187 transitions. [2022-07-23 15:32:28,836 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-07-23 15:32:28,836 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-23 15:32:28,836 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-23 15:32:28,837 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:28,837 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:28,837 INFO L752 eck$LassoCheckResult]: Stem: 21850#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 21851#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 21858#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21859#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21626#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 21627#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21496#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21408#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21131#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20766#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20767#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 20815#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 20816#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 21744#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21745#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21783#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21231#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21232#L1090 assume !(0 == ~M_E~0); 21274#L1090-2 assume !(0 == ~T1_E~0); 21275#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21920#L1100-1 assume !(0 == ~T3_E~0); 21921#L1105-1 assume !(0 == ~T4_E~0); 21049#L1110-1 assume !(0 == ~T5_E~0); 21050#L1115-1 assume !(0 == ~T6_E~0); 21446#L1120-1 assume !(0 == ~T7_E~0); 21723#L1125-1 assume !(0 == ~T8_E~0); 22192#L1130-1 assume !(0 == ~T9_E~0); 21941#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21236#L1140-1 assume !(0 == ~T11_E~0); 21237#L1145-1 assume !(0 == ~E_1~0); 21875#L1150-1 assume !(0 == ~E_2~0); 21421#L1155-1 assume !(0 == ~E_3~0); 21422#L1160-1 assume !(0 == ~E_4~0); 21504#L1165-1 assume !(0 == ~E_5~0); 21505#L1170-1 assume !(0 == ~E_6~0); 22113#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 21582#L1180-1 assume !(0 == ~E_8~0); 21583#L1185-1 assume !(0 == ~E_9~0); 21233#L1190-1 assume !(0 == ~E_10~0); 21234#L1195-1 assume !(0 == ~E_11~0); 21596#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21438#L525 assume !(1 == ~m_pc~0); 20854#L525-2 is_master_triggered_~__retres1~0#1 := 0; 20855#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21600#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 21601#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21220#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21221#L544 assume 1 == ~t1_pc~0; 21481#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21445#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21873#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21071#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 21072#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21694#L563 assume !(1 == ~t2_pc~0); 21860#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 20875#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20876#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 21304#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 21305#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21767#L582 assume 1 == ~t3_pc~0; 21013#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21014#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22164#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22122#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 20949#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20950#L601 assume !(1 == ~t4_pc~0); 21890#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 21447#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21448#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21884#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 21885#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22156#L620 assume 1 == ~t5_pc~0; 20904#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20905#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21719#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21720#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 22171#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22172#L639 assume !(1 == ~t6_pc~0); 21721#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 21344#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21345#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22125#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 21455#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21456#L658 assume 1 == ~t7_pc~0; 21722#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21647#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21754#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21755#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 21227#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21228#L677 assume 1 == ~t8_pc~0; 21458#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21030#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21031#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21301#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 21302#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21980#L696 assume !(1 == ~t9_pc~0); 21705#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 21706#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21795#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21727#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21728#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21925#L715 assume 1 == ~t10_pc~0; 21929#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21812#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21697#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21698#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 21574#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21022#L734 assume !(1 == ~t11_pc~0); 21023#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 21508#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21587#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20756#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 20757#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21782#L1213 assume !(1 == ~M_E~0); 21571#L1213-2 assume !(1 == ~T1_E~0); 21572#L1218-1 assume !(1 == ~T2_E~0); 20791#L1223-1 assume !(1 == ~T3_E~0); 20792#L1228-1 assume !(1 == ~T4_E~0); 21551#L1233-1 assume !(1 == ~T5_E~0); 22173#L1238-1 assume !(1 == ~T6_E~0); 21882#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 21883#L1248-1 assume !(1 == ~T8_E~0); 21927#L1253-1 assume !(1 == ~T9_E~0); 21928#L1258-1 assume !(1 == ~T10_E~0); 21906#L1263-1 assume !(1 == ~T11_E~0); 21907#L1268-1 assume !(1 == ~E_1~0); 21742#L1273-1 assume !(1 == ~E_2~0); 21743#L1278-1 assume !(1 == ~E_3~0); 21342#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 21343#L1288-1 assume !(1 == ~E_5~0); 22020#L1293-1 assume !(1 == ~E_6~0); 21984#L1298-1 assume !(1 == ~E_7~0); 21770#L1303-1 assume !(1 == ~E_8~0); 21353#L1308-1 assume !(1 == ~E_9~0); 21242#L1313-1 assume !(1 == ~E_10~0); 21243#L1318-1 assume !(1 == ~E_11~0); 21252#L1323-1 assume { :end_inline_reset_delta_events } true; 21253#L1644-2 [2022-07-23 15:32:28,838 INFO L754 eck$LassoCheckResult]: Loop: 21253#L1644-2 assume !false; 21823#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21824#L1065 assume !false; 21899#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 22169#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 20873#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 22085#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 21358#L906 assume !(0 != eval_~tmp~0#1); 21360#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21896#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21897#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22037#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22089#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22052#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22053#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21126#L1110-3 assume !(0 == ~T5_E~0); 21127#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 21409#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 21410#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21880#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22134#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21332#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 20827#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20828#L1150-3 assume !(0 == ~E_2~0); 20952#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20953#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 21313#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 21314#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21686#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 21223#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20981#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 20982#L1190-3 assume !(0 == ~E_10~0); 22128#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22129#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21536#L525-36 assume !(1 == ~m_pc~0); 21537#L525-38 is_master_triggered_~__retres1~0#1 := 0; 21082#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21083#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 21368#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21369#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21277#L544-36 assume 1 == ~t1_pc~0; 21278#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21801#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21172#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21173#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22111#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22013#L563-36 assume 1 == ~t2_pc~0; 21069#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20825#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20826#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 21888#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21549#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21550#L582-36 assume 1 == ~t3_pc~0; 21400#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21401#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21625#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21792#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21586#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21530#L601-36 assume 1 == ~t4_pc~0; 21429#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21430#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22177#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22095#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22096#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22001#L620-36 assume 1 == ~t5_pc~0; 21472#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 21473#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21865#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21457#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21091#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20869#L639-36 assume 1 == ~t6_pc~0; 20870#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20909#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20910#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21149#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 21150#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21726#L658-36 assume !(1 == ~t7_pc~0); 20880#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 20881#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22080#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20856#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 20857#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21847#L677-36 assume !(1 == ~t8_pc~0); 21651#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 21652#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21768#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22152#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21674#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21675#L696-36 assume 1 == ~t9_pc~0; 21568#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21570#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20926#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20927#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21687#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21688#L715-36 assume !(1 == ~t10_pc~0); 21658#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 20754#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20755#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20730#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 20731#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21132#L734-36 assume !(1 == ~t11_pc~0); 20834#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 20835#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21157#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20748#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 20749#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21748#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21415#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21416#L1218-3 assume !(1 == ~T2_E~0); 21186#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21187#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21376#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 21377#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21621#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 21622#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22093#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22098#L1258-3 assume !(1 == ~T10_E~0); 21166#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21167#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22064#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22082#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22083#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21500#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21501#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21365#L1298-3 assume !(1 == ~E_7~0); 21366#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21822#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 21363#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 21364#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 21168#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 21169#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 21110#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 21521#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 21960#L1663 assume !(0 == start_simulation_~tmp~3#1); 20996#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 21724#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 20947#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 21643#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 20888#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 20889#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21230#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 22149#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 21253#L1644-2 [2022-07-23 15:32:28,838 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:28,838 INFO L85 PathProgramCache]: Analyzing trace with hash 1380686246, now seen corresponding path program 1 times [2022-07-23 15:32:28,838 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:28,839 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1119733089] [2022-07-23 15:32:28,839 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:28,839 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:28,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:28,856 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:28,856 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:28,857 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1119733089] [2022-07-23 15:32:28,857 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1119733089] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:28,857 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:28,857 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-23 15:32:28,857 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1545695691] [2022-07-23 15:32:28,857 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:28,858 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-23 15:32:28,858 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:28,858 INFO L85 PathProgramCache]: Analyzing trace with hash 146783084, now seen corresponding path program 1 times [2022-07-23 15:32:28,858 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:28,858 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1283239333] [2022-07-23 15:32:28,858 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:28,858 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:28,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:28,901 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:28,902 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:28,902 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1283239333] [2022-07-23 15:32:28,902 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1283239333] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:28,902 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:28,902 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-23 15:32:28,903 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [841845315] [2022-07-23 15:32:28,903 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:28,903 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-23 15:32:28,903 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-23 15:32:28,903 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-23 15:32:28,904 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-23 15:32:28,904 INFO L87 Difference]: Start difference. First operand 1476 states and 2187 transitions. cyclomatic complexity: 712 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:28,922 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-23 15:32:28,922 INFO L93 Difference]: Finished difference Result 1476 states and 2186 transitions. [2022-07-23 15:32:28,922 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-23 15:32:28,923 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2186 transitions. [2022-07-23 15:32:28,928 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-07-23 15:32:28,933 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2186 transitions. [2022-07-23 15:32:28,934 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2022-07-23 15:32:28,934 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2022-07-23 15:32:28,934 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2186 transitions. [2022-07-23 15:32:28,936 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-23 15:32:28,936 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2186 transitions. [2022-07-23 15:32:28,937 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2186 transitions. [2022-07-23 15:32:28,946 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2022-07-23 15:32:28,948 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.481029810298103) internal successors, (2186), 1475 states have internal predecessors, (2186), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:28,951 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2186 transitions. [2022-07-23 15:32:28,951 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2186 transitions. [2022-07-23 15:32:28,951 INFO L374 stractBuchiCegarLoop]: Abstraction has 1476 states and 2186 transitions. [2022-07-23 15:32:28,951 INFO L287 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-07-23 15:32:28,951 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2186 transitions. [2022-07-23 15:32:28,955 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-07-23 15:32:28,955 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-23 15:32:28,955 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-23 15:32:28,956 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:28,957 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:28,957 INFO L752 eck$LassoCheckResult]: Stem: 24809#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 24810#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 24819#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24820#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24585#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 24586#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24455#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24367#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 24090#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 23725#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23726#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 23774#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 23775#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 24705#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24706#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 24749#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 24190#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24191#L1090 assume !(0 == ~M_E~0); 24237#L1090-2 assume !(0 == ~T1_E~0); 24238#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 24880#L1100-1 assume !(0 == ~T3_E~0); 24881#L1105-1 assume !(0 == ~T4_E~0); 24009#L1110-1 assume !(0 == ~T5_E~0); 24010#L1115-1 assume !(0 == ~T6_E~0); 24408#L1120-1 assume !(0 == ~T7_E~0); 24682#L1125-1 assume !(0 == ~T8_E~0); 25151#L1130-1 assume !(0 == ~T9_E~0); 24900#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24197#L1140-1 assume !(0 == ~T11_E~0); 24198#L1145-1 assume !(0 == ~E_1~0); 24834#L1150-1 assume !(0 == ~E_2~0); 24380#L1155-1 assume !(0 == ~E_3~0); 24381#L1160-1 assume !(0 == ~E_4~0); 24463#L1165-1 assume !(0 == ~E_5~0); 24464#L1170-1 assume !(0 == ~E_6~0); 25072#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 24541#L1180-1 assume !(0 == ~E_8~0); 24542#L1185-1 assume !(0 == ~E_9~0); 24192#L1190-1 assume !(0 == ~E_10~0); 24193#L1195-1 assume !(0 == ~E_11~0); 24555#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24402#L525 assume !(1 == ~m_pc~0); 23813#L525-2 is_master_triggered_~__retres1~0#1 := 0; 23814#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24559#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24560#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24179#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24180#L544 assume 1 == ~t1_pc~0; 24440#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24404#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24832#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24030#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 24031#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24653#L563 assume !(1 == ~t2_pc~0); 24821#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 23834#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23835#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24266#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 24267#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24726#L582 assume 1 == ~t3_pc~0; 23974#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23975#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25123#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25081#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 23908#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23909#L601 assume !(1 == ~t4_pc~0); 24849#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24409#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24410#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24843#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 24844#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25115#L620 assume 1 == ~t5_pc~0; 23867#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23868#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24678#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24679#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 25130#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25131#L639 assume !(1 == ~t6_pc~0); 24680#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 24303#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24304#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25084#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 24414#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24415#L658 assume 1 == ~t7_pc~0; 24681#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24608#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24713#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24714#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 24186#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24187#L677 assume 1 == ~t8_pc~0; 24419#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 23992#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23993#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24260#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 24261#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24939#L696 assume !(1 == ~t9_pc~0); 24667#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 24668#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24757#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24688#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24689#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24884#L715 assume 1 == ~t10_pc~0; 24888#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 24771#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24656#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24657#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 24533#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 23983#L734 assume !(1 == ~t11_pc~0); 23984#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 24467#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24546#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23715#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 23716#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24741#L1213 assume !(1 == ~M_E~0); 24531#L1213-2 assume !(1 == ~T1_E~0); 24532#L1218-1 assume !(1 == ~T2_E~0); 23750#L1223-1 assume !(1 == ~T3_E~0); 23751#L1228-1 assume !(1 == ~T4_E~0); 24510#L1233-1 assume !(1 == ~T5_E~0); 25132#L1238-1 assume !(1 == ~T6_E~0); 24841#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 24842#L1248-1 assume !(1 == ~T8_E~0); 24886#L1253-1 assume !(1 == ~T9_E~0); 24887#L1258-1 assume !(1 == ~T10_E~0); 24865#L1263-1 assume !(1 == ~T11_E~0); 24866#L1268-1 assume !(1 == ~E_1~0); 24701#L1273-1 assume !(1 == ~E_2~0); 24702#L1278-1 assume !(1 == ~E_3~0); 24301#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 24302#L1288-1 assume !(1 == ~E_5~0); 24979#L1293-1 assume !(1 == ~E_6~0); 24943#L1298-1 assume !(1 == ~E_7~0); 24729#L1303-1 assume !(1 == ~E_8~0); 24312#L1308-1 assume !(1 == ~E_9~0); 24201#L1313-1 assume !(1 == ~E_10~0); 24202#L1318-1 assume !(1 == ~E_11~0); 24214#L1323-1 assume { :end_inline_reset_delta_events } true; 24215#L1644-2 [2022-07-23 15:32:28,957 INFO L754 eck$LassoCheckResult]: Loop: 24215#L1644-2 assume !false; 24782#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24783#L1065 assume !false; 24858#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 25128#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 23832#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 25044#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 24317#L906 assume !(0 != eval_~tmp~0#1); 24319#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 24856#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24857#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 24996#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25048#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25011#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25012#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24085#L1110-3 assume !(0 == ~T5_E~0); 24086#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24368#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24369#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24839#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25093#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24291#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 23786#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23787#L1150-3 assume !(0 == ~E_2~0); 23910#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23911#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 24272#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 24273#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 24645#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 24182#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23940#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 23941#L1190-3 assume !(0 == ~E_10~0); 25087#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 25088#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24492#L525-36 assume !(1 == ~m_pc~0); 24493#L525-38 is_master_triggered_~__retres1~0#1 := 0; 24041#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24042#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24327#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24328#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24234#L544-36 assume 1 == ~t1_pc~0; 24235#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24760#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24125#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24126#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25069#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24972#L563-36 assume 1 == ~t2_pc~0; 24028#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 23784#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23785#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24847#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24508#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24509#L582-36 assume 1 == ~t3_pc~0; 24359#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 24360#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24584#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24751#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24545#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24489#L601-36 assume 1 == ~t4_pc~0; 24388#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 24389#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25136#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25054#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25055#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24960#L620-36 assume 1 == ~t5_pc~0; 24428#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24429#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24822#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24416#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 24050#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23828#L639-36 assume 1 == ~t6_pc~0; 23829#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23865#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23866#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24106#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 24107#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24685#L658-36 assume 1 == ~t7_pc~0; 23947#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23840#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25039#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23815#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 23816#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24806#L677-36 assume !(1 == ~t8_pc~0); 24610#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 24611#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24727#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25111#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24633#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24634#L696-36 assume !(1 == ~t9_pc~0); 24528#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 24529#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23888#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23889#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24646#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24647#L715-36 assume !(1 == ~t10_pc~0); 24617#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 23713#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 23714#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 23689#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 23690#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24094#L734-36 assume !(1 == ~t11_pc~0); 23793#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 23794#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24116#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23707#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 23708#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24707#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 24374#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24375#L1218-3 assume !(1 == ~T2_E~0); 24145#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24146#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 24335#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 24336#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 24580#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 24581#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25052#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25057#L1258-3 assume !(1 == ~T10_E~0); 24127#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 24128#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25023#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25041#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25043#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 24459#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 24460#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 24325#L1298-3 assume !(1 == ~E_7~0); 24326#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 24781#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 24322#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 24323#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 24129#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 24130#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 24069#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 24480#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 24919#L1663 assume !(0 == start_simulation_~tmp~3#1); 23962#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 24683#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 23906#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 24602#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 23850#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23851#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24189#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 25108#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 24215#L1644-2 [2022-07-23 15:32:28,958 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:28,958 INFO L85 PathProgramCache]: Analyzing trace with hash 1810344552, now seen corresponding path program 1 times [2022-07-23 15:32:28,958 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:28,958 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1154359906] [2022-07-23 15:32:28,958 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:28,959 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:28,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:28,978 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:28,978 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:28,978 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1154359906] [2022-07-23 15:32:28,978 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1154359906] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:28,979 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:28,979 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-23 15:32:28,979 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [568951420] [2022-07-23 15:32:28,979 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:28,979 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-23 15:32:28,980 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:28,980 INFO L85 PathProgramCache]: Analyzing trace with hash 1427558892, now seen corresponding path program 1 times [2022-07-23 15:32:28,980 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:28,980 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [175312810] [2022-07-23 15:32:28,980 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:28,980 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:28,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:29,007 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:29,008 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:29,008 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [175312810] [2022-07-23 15:32:29,008 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [175312810] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:29,008 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:29,008 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-23 15:32:29,008 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [600133886] [2022-07-23 15:32:29,009 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:29,009 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-23 15:32:29,009 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-23 15:32:29,009 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-23 15:32:29,009 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-23 15:32:29,010 INFO L87 Difference]: Start difference. First operand 1476 states and 2186 transitions. cyclomatic complexity: 711 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:29,027 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-23 15:32:29,028 INFO L93 Difference]: Finished difference Result 1476 states and 2185 transitions. [2022-07-23 15:32:29,028 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-23 15:32:29,029 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2185 transitions. [2022-07-23 15:32:29,034 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-07-23 15:32:29,039 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2185 transitions. [2022-07-23 15:32:29,039 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2022-07-23 15:32:29,040 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2022-07-23 15:32:29,040 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2185 transitions. [2022-07-23 15:32:29,042 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-23 15:32:29,042 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2185 transitions. [2022-07-23 15:32:29,043 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2185 transitions. [2022-07-23 15:32:29,054 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2022-07-23 15:32:29,056 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4803523035230353) internal successors, (2185), 1475 states have internal predecessors, (2185), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:29,059 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2185 transitions. [2022-07-23 15:32:29,059 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2185 transitions. [2022-07-23 15:32:29,060 INFO L374 stractBuchiCegarLoop]: Abstraction has 1476 states and 2185 transitions. [2022-07-23 15:32:29,060 INFO L287 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-07-23 15:32:29,060 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2185 transitions. [2022-07-23 15:32:29,063 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-07-23 15:32:29,064 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-23 15:32:29,064 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-23 15:32:29,065 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:29,065 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:29,065 INFO L752 eck$LassoCheckResult]: Stem: 27768#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 27769#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 27776#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27777#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27544#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 27545#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27414#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27326#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27049#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26684#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26685#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26733#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26734#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 27662#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 27663#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 27701#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 27149#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27150#L1090 assume !(0 == ~M_E~0); 27192#L1090-2 assume !(0 == ~T1_E~0); 27193#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27838#L1100-1 assume !(0 == ~T3_E~0); 27839#L1105-1 assume !(0 == ~T4_E~0); 26967#L1110-1 assume !(0 == ~T5_E~0); 26968#L1115-1 assume !(0 == ~T6_E~0); 27364#L1120-1 assume !(0 == ~T7_E~0); 27641#L1125-1 assume !(0 == ~T8_E~0); 28110#L1130-1 assume !(0 == ~T9_E~0); 27859#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 27154#L1140-1 assume !(0 == ~T11_E~0); 27155#L1145-1 assume !(0 == ~E_1~0); 27793#L1150-1 assume !(0 == ~E_2~0); 27339#L1155-1 assume !(0 == ~E_3~0); 27340#L1160-1 assume !(0 == ~E_4~0); 27422#L1165-1 assume !(0 == ~E_5~0); 27423#L1170-1 assume !(0 == ~E_6~0); 28031#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 27500#L1180-1 assume !(0 == ~E_8~0); 27501#L1185-1 assume !(0 == ~E_9~0); 27151#L1190-1 assume !(0 == ~E_10~0); 27152#L1195-1 assume !(0 == ~E_11~0); 27514#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27354#L525 assume !(1 == ~m_pc~0); 26772#L525-2 is_master_triggered_~__retres1~0#1 := 0; 26773#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27518#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27519#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27138#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27139#L544 assume 1 == ~t1_pc~0; 27399#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27363#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27791#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26989#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 26990#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27612#L563 assume !(1 == ~t2_pc~0); 27778#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 26793#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26794#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27222#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 27223#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27685#L582 assume 1 == ~t3_pc~0; 26931#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26932#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28082#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28040#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 26867#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26868#L601 assume !(1 == ~t4_pc~0); 27808#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 27365#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27366#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27802#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 27803#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28074#L620 assume 1 == ~t5_pc~0; 26822#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26823#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27637#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27638#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 28089#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28090#L639 assume !(1 == ~t6_pc~0); 27639#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 27262#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27263#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28043#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 27373#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27374#L658 assume 1 == ~t7_pc~0; 27640#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 27565#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27672#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27673#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 27145#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27146#L677 assume 1 == ~t8_pc~0; 27376#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 26948#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26949#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27219#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 27220#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27898#L696 assume !(1 == ~t9_pc~0); 27623#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 27624#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27713#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27645#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 27646#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 27843#L715 assume 1 == ~t10_pc~0; 27847#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 27730#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 27615#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 27616#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 27492#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26940#L734 assume !(1 == ~t11_pc~0); 26941#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 27426#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27505#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26672#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 26673#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27700#L1213 assume !(1 == ~M_E~0); 27489#L1213-2 assume !(1 == ~T1_E~0); 27490#L1218-1 assume !(1 == ~T2_E~0); 26709#L1223-1 assume !(1 == ~T3_E~0); 26710#L1228-1 assume !(1 == ~T4_E~0); 27469#L1233-1 assume !(1 == ~T5_E~0); 28091#L1238-1 assume !(1 == ~T6_E~0); 27800#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27801#L1248-1 assume !(1 == ~T8_E~0); 27845#L1253-1 assume !(1 == ~T9_E~0); 27846#L1258-1 assume !(1 == ~T10_E~0); 27824#L1263-1 assume !(1 == ~T11_E~0); 27825#L1268-1 assume !(1 == ~E_1~0); 27660#L1273-1 assume !(1 == ~E_2~0); 27661#L1278-1 assume !(1 == ~E_3~0); 27260#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 27261#L1288-1 assume !(1 == ~E_5~0); 27938#L1293-1 assume !(1 == ~E_6~0); 27902#L1298-1 assume !(1 == ~E_7~0); 27688#L1303-1 assume !(1 == ~E_8~0); 27271#L1308-1 assume !(1 == ~E_9~0); 27160#L1313-1 assume !(1 == ~E_10~0); 27161#L1318-1 assume !(1 == ~E_11~0); 27170#L1323-1 assume { :end_inline_reset_delta_events } true; 27171#L1644-2 [2022-07-23 15:32:29,066 INFO L754 eck$LassoCheckResult]: Loop: 27171#L1644-2 assume !false; 27741#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 27742#L1065 assume !false; 27817#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 28087#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 26791#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 28003#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 27276#L906 assume !(0 != eval_~tmp~0#1); 27278#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27814#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 27815#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 27955#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28007#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27970#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 27971#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 27044#L1110-3 assume !(0 == ~T5_E~0); 27045#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27327#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27328#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 27798#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28052#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 27250#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 26745#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26746#L1150-3 assume !(0 == ~E_2~0); 26869#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26870#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 27231#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 27232#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 27604#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 27141#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 26899#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 26900#L1190-3 assume !(0 == ~E_10~0); 28046#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28047#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27454#L525-36 assume 1 == ~m_pc~0; 27456#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 27000#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27001#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27286#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27287#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27195#L544-36 assume 1 == ~t1_pc~0; 27196#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27719#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27084#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 27085#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28028#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27931#L563-36 assume 1 == ~t2_pc~0; 26987#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 26743#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26744#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27806#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 27467#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27468#L582-36 assume 1 == ~t3_pc~0; 27318#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27319#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27543#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27710#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 27504#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27448#L601-36 assume 1 == ~t4_pc~0; 27347#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 27348#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28095#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28013#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28014#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27919#L620-36 assume 1 == ~t5_pc~0; 27389#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27390#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27781#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27375#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 27009#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26787#L639-36 assume 1 == ~t6_pc~0; 26788#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26827#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26828#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27067#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 27068#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27644#L658-36 assume 1 == ~t7_pc~0; 26906#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26799#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27998#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26774#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 26775#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27765#L677-36 assume !(1 == ~t8_pc~0); 27569#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 27570#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27686#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28070#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 27592#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27593#L696-36 assume 1 == ~t9_pc~0; 27486#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27488#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26847#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26848#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 27605#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 27606#L715-36 assume !(1 == ~t10_pc~0); 27576#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 26674#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26675#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26648#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 26649#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 27053#L734-36 assume !(1 == ~t11_pc~0); 26752#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 26753#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27075#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26666#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 26667#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27666#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 27335#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27336#L1218-3 assume !(1 == ~T2_E~0); 27104#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27105#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27294#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 27295#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27539#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27540#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 28012#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28017#L1258-3 assume !(1 == ~T10_E~0); 27086#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 27087#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 27982#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 28000#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 28002#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27418#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27419#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 27284#L1298-3 assume !(1 == ~E_7~0); 27285#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 27740#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 27281#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 27282#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 27088#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 27089#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 27028#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 27439#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 27878#L1663 assume !(0 == start_simulation_~tmp~3#1); 26914#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 27642#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 26865#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 27563#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 26809#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26810#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27148#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 28067#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 27171#L1644-2 [2022-07-23 15:32:29,067 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:29,067 INFO L85 PathProgramCache]: Analyzing trace with hash -1778026138, now seen corresponding path program 1 times [2022-07-23 15:32:29,067 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:29,067 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1686208466] [2022-07-23 15:32:29,067 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:29,067 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:29,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:29,087 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:29,088 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:29,088 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1686208466] [2022-07-23 15:32:29,088 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1686208466] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:29,088 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:29,088 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-23 15:32:29,088 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [277209447] [2022-07-23 15:32:29,089 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:29,089 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-23 15:32:29,089 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:29,089 INFO L85 PathProgramCache]: Analyzing trace with hash 1771516014, now seen corresponding path program 1 times [2022-07-23 15:32:29,089 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:29,090 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1946867853] [2022-07-23 15:32:29,090 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:29,090 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:29,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:29,115 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:29,115 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:29,115 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1946867853] [2022-07-23 15:32:29,115 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1946867853] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:29,116 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:29,116 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-23 15:32:29,116 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1661459398] [2022-07-23 15:32:29,116 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:29,116 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-23 15:32:29,116 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-23 15:32:29,117 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-23 15:32:29,117 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-23 15:32:29,117 INFO L87 Difference]: Start difference. First operand 1476 states and 2185 transitions. cyclomatic complexity: 710 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:29,148 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-23 15:32:29,149 INFO L93 Difference]: Finished difference Result 1476 states and 2184 transitions. [2022-07-23 15:32:29,149 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-23 15:32:29,150 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2184 transitions. [2022-07-23 15:32:29,155 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-07-23 15:32:29,160 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2184 transitions. [2022-07-23 15:32:29,160 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2022-07-23 15:32:29,161 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2022-07-23 15:32:29,162 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2184 transitions. [2022-07-23 15:32:29,163 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-23 15:32:29,163 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2184 transitions. [2022-07-23 15:32:29,164 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2184 transitions. [2022-07-23 15:32:29,175 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2022-07-23 15:32:29,177 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4796747967479675) internal successors, (2184), 1475 states have internal predecessors, (2184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:29,180 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2184 transitions. [2022-07-23 15:32:29,181 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2184 transitions. [2022-07-23 15:32:29,181 INFO L374 stractBuchiCegarLoop]: Abstraction has 1476 states and 2184 transitions. [2022-07-23 15:32:29,181 INFO L287 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-07-23 15:32:29,181 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2184 transitions. [2022-07-23 15:32:29,185 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-07-23 15:32:29,185 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-23 15:32:29,185 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-23 15:32:29,186 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:29,186 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:29,186 INFO L752 eck$LassoCheckResult]: Stem: 30727#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 30728#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 30737#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30738#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30503#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 30504#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30373#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30285#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30008#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29643#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29644#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29692#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29693#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 30621#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 30622#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 30660#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 30108#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30109#L1090 assume !(0 == ~M_E~0); 30154#L1090-2 assume !(0 == ~T1_E~0); 30155#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30798#L1100-1 assume !(0 == ~T3_E~0); 30799#L1105-1 assume !(0 == ~T4_E~0); 29927#L1110-1 assume !(0 == ~T5_E~0); 29928#L1115-1 assume !(0 == ~T6_E~0); 30323#L1120-1 assume !(0 == ~T7_E~0); 30600#L1125-1 assume !(0 == ~T8_E~0); 31069#L1130-1 assume !(0 == ~T9_E~0); 30818#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 30113#L1140-1 assume !(0 == ~T11_E~0); 30114#L1145-1 assume !(0 == ~E_1~0); 30752#L1150-1 assume !(0 == ~E_2~0); 30298#L1155-1 assume !(0 == ~E_3~0); 30299#L1160-1 assume !(0 == ~E_4~0); 30381#L1165-1 assume !(0 == ~E_5~0); 30382#L1170-1 assume !(0 == ~E_6~0); 30990#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 30459#L1180-1 assume !(0 == ~E_8~0); 30460#L1185-1 assume !(0 == ~E_9~0); 30110#L1190-1 assume !(0 == ~E_10~0); 30111#L1195-1 assume !(0 == ~E_11~0); 30473#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30320#L525 assume !(1 == ~m_pc~0); 29731#L525-2 is_master_triggered_~__retres1~0#1 := 0; 29732#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30477#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 30478#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30097#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30098#L544 assume 1 == ~t1_pc~0; 30358#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30322#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30750#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 29948#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 29949#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30571#L563 assume !(1 == ~t2_pc~0); 30739#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 29752#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29753#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 30184#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 30185#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30644#L582 assume 1 == ~t3_pc~0; 29892#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29893#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31041#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30999#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 29826#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29827#L601 assume !(1 == ~t4_pc~0); 30767#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 30324#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30325#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30761#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 30762#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31033#L620 assume 1 == ~t5_pc~0; 29785#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 29786#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30596#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30597#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 31048#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31049#L639 assume !(1 == ~t6_pc~0); 30598#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 30221#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 30222#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 31002#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 30332#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30333#L658 assume 1 == ~t7_pc~0; 30599#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30526#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30631#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30632#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 30104#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30105#L677 assume 1 == ~t8_pc~0; 30337#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 29907#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29908#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30178#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 30179#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30857#L696 assume !(1 == ~t9_pc~0); 30584#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 30585#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30675#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30604#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 30605#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 30802#L715 assume 1 == ~t10_pc~0; 30806#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 30689#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30574#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30575#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 30451#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29901#L734 assume !(1 == ~t11_pc~0); 29902#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 30385#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30464#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29633#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 29634#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30659#L1213 assume !(1 == ~M_E~0); 30449#L1213-2 assume !(1 == ~T1_E~0); 30450#L1218-1 assume !(1 == ~T2_E~0); 29668#L1223-1 assume !(1 == ~T3_E~0); 29669#L1228-1 assume !(1 == ~T4_E~0); 30428#L1233-1 assume !(1 == ~T5_E~0); 31050#L1238-1 assume !(1 == ~T6_E~0); 30759#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30760#L1248-1 assume !(1 == ~T8_E~0); 30804#L1253-1 assume !(1 == ~T9_E~0); 30805#L1258-1 assume !(1 == ~T10_E~0); 30783#L1263-1 assume !(1 == ~T11_E~0); 30784#L1268-1 assume !(1 == ~E_1~0); 30619#L1273-1 assume !(1 == ~E_2~0); 30620#L1278-1 assume !(1 == ~E_3~0); 30219#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 30220#L1288-1 assume !(1 == ~E_5~0); 30897#L1293-1 assume !(1 == ~E_6~0); 30861#L1298-1 assume !(1 == ~E_7~0); 30647#L1303-1 assume !(1 == ~E_8~0); 30230#L1308-1 assume !(1 == ~E_9~0); 30119#L1313-1 assume !(1 == ~E_10~0); 30120#L1318-1 assume !(1 == ~E_11~0); 30132#L1323-1 assume { :end_inline_reset_delta_events } true; 30133#L1644-2 [2022-07-23 15:32:29,187 INFO L754 eck$LassoCheckResult]: Loop: 30133#L1644-2 assume !false; 30700#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 30701#L1065 assume !false; 30776#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 31046#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 29750#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 30962#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 30235#L906 assume !(0 != eval_~tmp~0#1); 30237#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 30774#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30775#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 30914#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30966#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30929#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30930#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 30003#L1110-3 assume !(0 == ~T5_E~0); 30004#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 30286#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 30287#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 30757#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 31011#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 30211#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 29706#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29707#L1150-3 assume !(0 == ~E_2~0); 29829#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29830#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30190#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30191#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30563#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30100#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 29861#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 29862#L1190-3 assume !(0 == ~E_10~0); 31005#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 31006#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30413#L525-36 assume !(1 == ~m_pc~0); 30414#L525-38 is_master_triggered_~__retres1~0#1 := 0; 29964#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29965#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 30245#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30246#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30151#L544-36 assume 1 == ~t1_pc~0; 30152#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30678#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30043#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 30044#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 30987#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30890#L563-36 assume 1 == ~t2_pc~0; 29946#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29702#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29703#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 30765#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30426#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30427#L582-36 assume 1 == ~t3_pc~0; 30277#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30278#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30502#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30669#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30463#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30407#L601-36 assume 1 == ~t4_pc~0; 30306#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30307#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31054#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30972#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30973#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30878#L620-36 assume 1 == ~t5_pc~0; 30346#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30347#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30740#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30334#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29968#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29746#L639-36 assume 1 == ~t6_pc~0; 29747#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29783#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29784#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30024#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 30025#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30603#L658-36 assume 1 == ~t7_pc~0; 29863#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29758#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30957#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29733#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 29734#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30724#L677-36 assume !(1 == ~t8_pc~0); 30528#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 30529#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30645#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 31029#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 30551#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30552#L696-36 assume 1 == ~t9_pc~0; 30445#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 30447#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29806#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29807#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 30564#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 30565#L715-36 assume !(1 == ~t10_pc~0); 30535#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 29631#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29632#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29607#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 29608#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30012#L734-36 assume 1 == ~t11_pc~0; 30013#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29712#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30034#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29625#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 29626#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30625#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 30292#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30293#L1218-3 assume !(1 == ~T2_E~0); 30063#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30064#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30253#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30254#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30498#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30499#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30970#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30975#L1258-3 assume !(1 == ~T10_E~0); 30045#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 30046#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30941#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30959#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30961#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30377#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30378#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30243#L1298-3 assume !(1 == ~E_7~0); 30244#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 30699#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 30240#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 30241#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 30047#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 30048#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 29987#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 30398#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 30837#L1663 assume !(0 == start_simulation_~tmp~3#1); 29880#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 30601#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 29824#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 30520#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 29768#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 29769#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30107#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 31026#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 30133#L1644-2 [2022-07-23 15:32:29,187 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:29,187 INFO L85 PathProgramCache]: Analyzing trace with hash 1655107556, now seen corresponding path program 1 times [2022-07-23 15:32:29,188 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:29,188 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [863940555] [2022-07-23 15:32:29,188 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:29,188 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:29,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:29,206 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:29,207 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:29,207 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [863940555] [2022-07-23 15:32:29,207 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [863940555] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:29,207 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:29,207 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-23 15:32:29,207 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [451059506] [2022-07-23 15:32:29,207 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:29,208 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-23 15:32:29,208 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:29,208 INFO L85 PathProgramCache]: Analyzing trace with hash -814695250, now seen corresponding path program 1 times [2022-07-23 15:32:29,208 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:29,208 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [130869181] [2022-07-23 15:32:29,208 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:29,209 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:29,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:29,233 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:29,234 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:29,234 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [130869181] [2022-07-23 15:32:29,234 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [130869181] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:29,234 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:29,234 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-23 15:32:29,234 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [156449489] [2022-07-23 15:32:29,234 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:29,235 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-23 15:32:29,235 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-23 15:32:29,235 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-23 15:32:29,235 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-23 15:32:29,236 INFO L87 Difference]: Start difference. First operand 1476 states and 2184 transitions. cyclomatic complexity: 709 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:29,252 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-23 15:32:29,252 INFO L93 Difference]: Finished difference Result 1476 states and 2183 transitions. [2022-07-23 15:32:29,253 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-23 15:32:29,253 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2183 transitions. [2022-07-23 15:32:29,258 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-07-23 15:32:29,263 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2183 transitions. [2022-07-23 15:32:29,263 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2022-07-23 15:32:29,264 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2022-07-23 15:32:29,264 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2183 transitions. [2022-07-23 15:32:29,265 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-23 15:32:29,265 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2183 transitions. [2022-07-23 15:32:29,267 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2183 transitions. [2022-07-23 15:32:29,277 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2022-07-23 15:32:29,279 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4789972899728998) internal successors, (2183), 1475 states have internal predecessors, (2183), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:29,281 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2183 transitions. [2022-07-23 15:32:29,282 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2183 transitions. [2022-07-23 15:32:29,282 INFO L374 stractBuchiCegarLoop]: Abstraction has 1476 states and 2183 transitions. [2022-07-23 15:32:29,282 INFO L287 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-07-23 15:32:29,282 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2183 transitions. [2022-07-23 15:32:29,285 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-07-23 15:32:29,286 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-23 15:32:29,286 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-23 15:32:29,287 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:29,287 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:29,287 INFO L752 eck$LassoCheckResult]: Stem: 33686#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 33687#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 33694#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33695#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 33462#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 33463#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33332#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33244#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32967#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32602#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 32603#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 32651#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 32652#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 33580#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33581#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 33619#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 33067#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33068#L1090 assume !(0 == ~M_E~0); 33110#L1090-2 assume !(0 == ~T1_E~0); 33111#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 33756#L1100-1 assume !(0 == ~T3_E~0); 33757#L1105-1 assume !(0 == ~T4_E~0); 32885#L1110-1 assume !(0 == ~T5_E~0); 32886#L1115-1 assume !(0 == ~T6_E~0); 33282#L1120-1 assume !(0 == ~T7_E~0); 33559#L1125-1 assume !(0 == ~T8_E~0); 34028#L1130-1 assume !(0 == ~T9_E~0); 33777#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 33072#L1140-1 assume !(0 == ~T11_E~0); 33073#L1145-1 assume !(0 == ~E_1~0); 33711#L1150-1 assume !(0 == ~E_2~0); 33257#L1155-1 assume !(0 == ~E_3~0); 33258#L1160-1 assume !(0 == ~E_4~0); 33340#L1165-1 assume !(0 == ~E_5~0); 33341#L1170-1 assume !(0 == ~E_6~0); 33949#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 33418#L1180-1 assume !(0 == ~E_8~0); 33419#L1185-1 assume !(0 == ~E_9~0); 33069#L1190-1 assume !(0 == ~E_10~0); 33070#L1195-1 assume !(0 == ~E_11~0); 33432#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33272#L525 assume !(1 == ~m_pc~0); 32690#L525-2 is_master_triggered_~__retres1~0#1 := 0; 32691#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33436#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33437#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 33056#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33057#L544 assume 1 == ~t1_pc~0; 33317#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33281#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33709#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 32907#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 32908#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33530#L563 assume !(1 == ~t2_pc~0); 33696#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 32711#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32712#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33140#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 33141#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33603#L582 assume 1 == ~t3_pc~0; 32849#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 32850#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34000#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33958#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 32785#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32786#L601 assume !(1 == ~t4_pc~0); 33726#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 33283#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33284#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33720#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 33721#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33992#L620 assume 1 == ~t5_pc~0; 32740#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 32741#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33555#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33556#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 34007#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34008#L639 assume !(1 == ~t6_pc~0); 33557#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 33180#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33181#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33961#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 33291#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33292#L658 assume 1 == ~t7_pc~0; 33558#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 33483#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33590#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33591#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 33063#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33064#L677 assume 1 == ~t8_pc~0; 33294#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 32866#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32867#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33137#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 33138#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33816#L696 assume !(1 == ~t9_pc~0); 33541#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 33542#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33631#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33563#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 33564#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33761#L715 assume 1 == ~t10_pc~0; 33765#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 33648#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33533#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33534#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 33410#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32858#L734 assume !(1 == ~t11_pc~0); 32859#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 33344#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33423#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32590#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 32591#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33618#L1213 assume !(1 == ~M_E~0); 33407#L1213-2 assume !(1 == ~T1_E~0); 33408#L1218-1 assume !(1 == ~T2_E~0); 32627#L1223-1 assume !(1 == ~T3_E~0); 32628#L1228-1 assume !(1 == ~T4_E~0); 33387#L1233-1 assume !(1 == ~T5_E~0); 34009#L1238-1 assume !(1 == ~T6_E~0); 33718#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 33719#L1248-1 assume !(1 == ~T8_E~0); 33763#L1253-1 assume !(1 == ~T9_E~0); 33764#L1258-1 assume !(1 == ~T10_E~0); 33742#L1263-1 assume !(1 == ~T11_E~0); 33743#L1268-1 assume !(1 == ~E_1~0); 33578#L1273-1 assume !(1 == ~E_2~0); 33579#L1278-1 assume !(1 == ~E_3~0); 33178#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 33179#L1288-1 assume !(1 == ~E_5~0); 33856#L1293-1 assume !(1 == ~E_6~0); 33820#L1298-1 assume !(1 == ~E_7~0); 33606#L1303-1 assume !(1 == ~E_8~0); 33189#L1308-1 assume !(1 == ~E_9~0); 33078#L1313-1 assume !(1 == ~E_10~0); 33079#L1318-1 assume !(1 == ~E_11~0); 33088#L1323-1 assume { :end_inline_reset_delta_events } true; 33089#L1644-2 [2022-07-23 15:32:29,288 INFO L754 eck$LassoCheckResult]: Loop: 33089#L1644-2 assume !false; 33659#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33660#L1065 assume !false; 33735#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 34005#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 32709#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 33921#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 33194#L906 assume !(0 != eval_~tmp~0#1); 33196#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33732#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33733#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 33873#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33925#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 33888#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 33889#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32962#L1110-3 assume !(0 == ~T5_E~0); 32963#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 33245#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 33246#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 33716#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 33970#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 33168#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 32663#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32664#L1150-3 assume !(0 == ~E_2~0); 32787#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32788#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 33149#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 33150#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 33522#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 33059#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 32817#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 32818#L1190-3 assume !(0 == ~E_10~0); 33964#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 33965#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33372#L525-36 assume !(1 == ~m_pc~0); 33373#L525-38 is_master_triggered_~__retres1~0#1 := 0; 32918#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32919#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33204#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 33205#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33113#L544-36 assume 1 == ~t1_pc~0; 33114#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33637#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33002#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 33003#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33946#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33849#L563-36 assume 1 == ~t2_pc~0; 32905#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32661#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32662#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33724#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33385#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33386#L582-36 assume 1 == ~t3_pc~0; 33236#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33237#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33461#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33628#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33422#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33366#L601-36 assume 1 == ~t4_pc~0; 33265#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33266#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34013#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33931#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33932#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33837#L620-36 assume 1 == ~t5_pc~0; 33307#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33308#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33699#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33293#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 32927#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32705#L639-36 assume 1 == ~t6_pc~0; 32706#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 32745#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32746#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32985#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 32986#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33562#L658-36 assume 1 == ~t7_pc~0; 32824#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 32717#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33916#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32692#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 32693#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33683#L677-36 assume 1 == ~t8_pc~0; 33861#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33488#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33604#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33988#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 33510#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33511#L696-36 assume 1 == ~t9_pc~0; 33404#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33406#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32765#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32766#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 33523#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33524#L715-36 assume !(1 == ~t10_pc~0); 33494#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 32592#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32593#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32566#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 32567#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32971#L734-36 assume 1 == ~t11_pc~0; 32972#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32671#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32993#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32584#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 32585#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33584#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 33253#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33254#L1218-3 assume !(1 == ~T2_E~0); 33022#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33023#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33212#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 33213#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33457#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 33458#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 33930#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 33935#L1258-3 assume !(1 == ~T10_E~0); 33004#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 33005#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 33900#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 33918#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 33920#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33336#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 33337#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 33202#L1298-3 assume !(1 == ~E_7~0); 33203#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 33658#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 33199#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 33200#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 33006#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 33007#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 32946#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 33357#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 33796#L1663 assume !(0 == start_simulation_~tmp~3#1); 32839#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 33560#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 32783#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 33481#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 32727#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 32728#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 33066#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 33985#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 33089#L1644-2 [2022-07-23 15:32:29,288 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:29,288 INFO L85 PathProgramCache]: Analyzing trace with hash -589450842, now seen corresponding path program 1 times [2022-07-23 15:32:29,288 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:29,289 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [427983014] [2022-07-23 15:32:29,289 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:29,289 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:29,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:29,313 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:29,313 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:29,313 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [427983014] [2022-07-23 15:32:29,313 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [427983014] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:29,313 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:29,314 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-23 15:32:29,314 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1464061179] [2022-07-23 15:32:29,314 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:29,314 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-23 15:32:29,314 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:29,315 INFO L85 PathProgramCache]: Analyzing trace with hash 1091788943, now seen corresponding path program 1 times [2022-07-23 15:32:29,315 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:29,315 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1275938671] [2022-07-23 15:32:29,315 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:29,315 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:29,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:29,339 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:29,340 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:29,340 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1275938671] [2022-07-23 15:32:29,340 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1275938671] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:29,340 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:29,340 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-23 15:32:29,340 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [605930324] [2022-07-23 15:32:29,340 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:29,341 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-23 15:32:29,341 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-23 15:32:29,341 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-23 15:32:29,341 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-23 15:32:29,341 INFO L87 Difference]: Start difference. First operand 1476 states and 2183 transitions. cyclomatic complexity: 708 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:29,362 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-23 15:32:29,362 INFO L93 Difference]: Finished difference Result 1476 states and 2178 transitions. [2022-07-23 15:32:29,363 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-23 15:32:29,363 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2178 transitions. [2022-07-23 15:32:29,368 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-07-23 15:32:29,372 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2178 transitions. [2022-07-23 15:32:29,372 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2022-07-23 15:32:29,373 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2022-07-23 15:32:29,373 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2178 transitions. [2022-07-23 15:32:29,375 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-23 15:32:29,375 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2178 transitions. [2022-07-23 15:32:29,376 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2178 transitions. [2022-07-23 15:32:29,385 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2022-07-23 15:32:29,387 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.475609756097561) internal successors, (2178), 1475 states have internal predecessors, (2178), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:29,390 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2178 transitions. [2022-07-23 15:32:29,390 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2178 transitions. [2022-07-23 15:32:29,390 INFO L374 stractBuchiCegarLoop]: Abstraction has 1476 states and 2178 transitions. [2022-07-23 15:32:29,390 INFO L287 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-07-23 15:32:29,390 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2178 transitions. [2022-07-23 15:32:29,393 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-07-23 15:32:29,394 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-23 15:32:29,394 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-23 15:32:29,395 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:29,395 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:29,395 INFO L752 eck$LassoCheckResult]: Stem: 36645#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 36646#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 36655#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 36656#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36421#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 36422#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36291#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36203#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35926#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35561#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 35562#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 35610#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35611#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 36539#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 36540#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 36578#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 36026#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36027#L1090 assume !(0 == ~M_E~0); 36069#L1090-2 assume !(0 == ~T1_E~0); 36070#L1095-1 assume !(0 == ~T2_E~0); 36716#L1100-1 assume !(0 == ~T3_E~0); 36717#L1105-1 assume !(0 == ~T4_E~0); 35845#L1110-1 assume !(0 == ~T5_E~0); 35846#L1115-1 assume !(0 == ~T6_E~0); 36241#L1120-1 assume !(0 == ~T7_E~0); 36518#L1125-1 assume !(0 == ~T8_E~0); 36987#L1130-1 assume !(0 == ~T9_E~0); 36736#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 36031#L1140-1 assume !(0 == ~T11_E~0); 36032#L1145-1 assume !(0 == ~E_1~0); 36670#L1150-1 assume !(0 == ~E_2~0); 36216#L1155-1 assume !(0 == ~E_3~0); 36217#L1160-1 assume !(0 == ~E_4~0); 36299#L1165-1 assume !(0 == ~E_5~0); 36300#L1170-1 assume !(0 == ~E_6~0); 36908#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 36377#L1180-1 assume !(0 == ~E_8~0); 36378#L1185-1 assume !(0 == ~E_9~0); 36028#L1190-1 assume !(0 == ~E_10~0); 36029#L1195-1 assume !(0 == ~E_11~0); 36391#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36238#L525 assume !(1 == ~m_pc~0); 35649#L525-2 is_master_triggered_~__retres1~0#1 := 0; 35650#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36395#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 36396#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36015#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36016#L544 assume 1 == ~t1_pc~0; 36276#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36240#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36668#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 35866#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 35867#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36489#L563 assume !(1 == ~t2_pc~0); 36657#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 35670#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35671#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36099#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 36100#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36562#L582 assume 1 == ~t3_pc~0; 35810#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 35811#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36959#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36917#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 35744#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35745#L601 assume !(1 == ~t4_pc~0); 36685#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 36242#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36243#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36679#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 36680#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36951#L620 assume 1 == ~t5_pc~0; 35701#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35702#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36514#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36515#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 36966#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36967#L639 assume !(1 == ~t6_pc~0); 36516#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 36139#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36140#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36920#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 36250#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36251#L658 assume 1 == ~t7_pc~0; 36517#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36444#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36549#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36550#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 36022#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36023#L677 assume 1 == ~t8_pc~0; 36255#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 35825#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35826#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36096#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 36097#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36775#L696 assume !(1 == ~t9_pc~0); 36502#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 36503#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36590#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36522#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 36523#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36720#L715 assume 1 == ~t10_pc~0; 36724#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 36607#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36492#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36493#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 36369#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35819#L734 assume !(1 == ~t11_pc~0); 35820#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 36303#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36382#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35551#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 35552#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36577#L1213 assume !(1 == ~M_E~0); 36367#L1213-2 assume !(1 == ~T1_E~0); 36368#L1218-1 assume !(1 == ~T2_E~0); 35586#L1223-1 assume !(1 == ~T3_E~0); 35587#L1228-1 assume !(1 == ~T4_E~0); 36346#L1233-1 assume !(1 == ~T5_E~0); 36968#L1238-1 assume !(1 == ~T6_E~0); 36677#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 36678#L1248-1 assume !(1 == ~T8_E~0); 36722#L1253-1 assume !(1 == ~T9_E~0); 36723#L1258-1 assume !(1 == ~T10_E~0); 36701#L1263-1 assume !(1 == ~T11_E~0); 36702#L1268-1 assume !(1 == ~E_1~0); 36537#L1273-1 assume !(1 == ~E_2~0); 36538#L1278-1 assume !(1 == ~E_3~0); 36137#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 36138#L1288-1 assume !(1 == ~E_5~0); 36815#L1293-1 assume !(1 == ~E_6~0); 36779#L1298-1 assume !(1 == ~E_7~0); 36565#L1303-1 assume !(1 == ~E_8~0); 36148#L1308-1 assume !(1 == ~E_9~0); 36037#L1313-1 assume !(1 == ~E_10~0); 36038#L1318-1 assume !(1 == ~E_11~0); 36050#L1323-1 assume { :end_inline_reset_delta_events } true; 36051#L1644-2 [2022-07-23 15:32:29,396 INFO L754 eck$LassoCheckResult]: Loop: 36051#L1644-2 assume !false; 36618#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36619#L1065 assume !false; 36694#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 36964#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 35668#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 36880#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 36153#L906 assume !(0 != eval_~tmp~0#1); 36155#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36692#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36693#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 36832#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36884#L1095-3 assume !(0 == ~T2_E~0); 36847#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36848#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 35921#L1110-3 assume !(0 == ~T5_E~0); 35922#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36204#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36205#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36675#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 36929#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 36129#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 35624#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 35625#L1150-3 assume !(0 == ~E_2~0); 35747#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 35748#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 36108#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 36109#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 36481#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 36018#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 35777#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 35778#L1190-3 assume !(0 == ~E_10~0); 36923#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 36924#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36331#L525-36 assume !(1 == ~m_pc~0); 36332#L525-38 is_master_triggered_~__retres1~0#1 := 0; 35882#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35883#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 36164#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36165#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36072#L544-36 assume 1 == ~t1_pc~0; 36073#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36596#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35967#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 35968#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36906#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36808#L563-36 assume 1 == ~t2_pc~0; 35864#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35620#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35621#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36683#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36344#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36345#L582-36 assume 1 == ~t3_pc~0; 36195#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36196#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36420#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36587#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36381#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36322#L601-36 assume 1 == ~t4_pc~0; 36224#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 36225#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36972#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36890#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36891#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36794#L620-36 assume 1 == ~t5_pc~0; 36264#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 36265#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36658#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36252#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 35886#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35664#L639-36 assume 1 == ~t6_pc~0; 35665#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 35699#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35700#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35942#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35943#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36521#L658-36 assume 1 == ~t7_pc~0; 35781#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 35676#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36875#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 35651#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 35652#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36642#L677-36 assume 1 == ~t8_pc~0; 36820#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36447#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36563#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36947#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36469#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36470#L696-36 assume 1 == ~t9_pc~0; 36363#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36365#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35721#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 35722#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 36482#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36483#L715-36 assume !(1 == ~t10_pc~0); 36453#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 35549#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35550#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35525#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 35526#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35930#L734-36 assume 1 == ~t11_pc~0; 35931#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 35630#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35952#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35543#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35544#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36543#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 36210#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36211#L1218-3 assume !(1 == ~T2_E~0); 35981#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 35982#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36171#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36172#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36416#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 36417#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 36888#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 36893#L1258-3 assume !(1 == ~T10_E~0); 35961#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 35962#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 36859#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 36877#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 36879#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36295#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 36296#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 36161#L1298-3 assume !(1 == ~E_7~0); 36162#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 36617#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 36158#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 36159#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 35963#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 35964#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 35905#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 36316#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 36755#L1663 assume !(0 == start_simulation_~tmp~3#1); 35793#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 36519#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 35742#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 36438#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 35683#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 35684#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 36025#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 36944#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 36051#L1644-2 [2022-07-23 15:32:29,396 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:29,396 INFO L85 PathProgramCache]: Analyzing trace with hash 1863040740, now seen corresponding path program 1 times [2022-07-23 15:32:29,397 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:29,397 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1993122188] [2022-07-23 15:32:29,397 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:29,397 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:29,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:29,422 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:29,422 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:29,422 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1993122188] [2022-07-23 15:32:29,423 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1993122188] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:29,423 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:29,423 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-23 15:32:29,423 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1178067721] [2022-07-23 15:32:29,423 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:29,423 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-23 15:32:29,424 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:29,424 INFO L85 PathProgramCache]: Analyzing trace with hash 1766949069, now seen corresponding path program 1 times [2022-07-23 15:32:29,424 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:29,424 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1531574062] [2022-07-23 15:32:29,424 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:29,424 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:29,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:29,454 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:29,454 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:29,455 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1531574062] [2022-07-23 15:32:29,455 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1531574062] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:29,455 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:29,455 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-23 15:32:29,455 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1499033866] [2022-07-23 15:32:29,455 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:29,455 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-23 15:32:29,456 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-23 15:32:29,456 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-23 15:32:29,456 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-23 15:32:29,456 INFO L87 Difference]: Start difference. First operand 1476 states and 2178 transitions. cyclomatic complexity: 703 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:29,550 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-23 15:32:29,551 INFO L93 Difference]: Finished difference Result 2816 states and 4147 transitions. [2022-07-23 15:32:29,551 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-23 15:32:29,551 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2816 states and 4147 transitions. [2022-07-23 15:32:29,561 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2654 [2022-07-23 15:32:29,572 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2816 states to 2816 states and 4147 transitions. [2022-07-23 15:32:29,572 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2816 [2022-07-23 15:32:29,574 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2816 [2022-07-23 15:32:29,574 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2816 states and 4147 transitions. [2022-07-23 15:32:29,577 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-23 15:32:29,577 INFO L369 hiAutomatonCegarLoop]: Abstraction has 2816 states and 4147 transitions. [2022-07-23 15:32:29,578 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2816 states and 4147 transitions. [2022-07-23 15:32:29,592 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2816 to 1476. [2022-07-23 15:32:29,594 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4742547425474255) internal successors, (2176), 1475 states have internal predecessors, (2176), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:29,596 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2176 transitions. [2022-07-23 15:32:29,596 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2176 transitions. [2022-07-23 15:32:29,596 INFO L374 stractBuchiCegarLoop]: Abstraction has 1476 states and 2176 transitions. [2022-07-23 15:32:29,597 INFO L287 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-07-23 15:32:29,597 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2176 transitions. [2022-07-23 15:32:29,600 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-07-23 15:32:29,600 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-23 15:32:29,600 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-23 15:32:29,601 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:29,601 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:29,602 INFO L752 eck$LassoCheckResult]: Stem: 40947#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 40948#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 40955#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 40956#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 40723#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 40724#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40593#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40505#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 40228#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39863#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 39864#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 39912#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 39913#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 40841#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 40842#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 40880#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 40328#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40329#L1090 assume !(0 == ~M_E~0); 40371#L1090-2 assume !(0 == ~T1_E~0); 40372#L1095-1 assume !(0 == ~T2_E~0); 41017#L1100-1 assume !(0 == ~T3_E~0); 41018#L1105-1 assume !(0 == ~T4_E~0); 40146#L1110-1 assume !(0 == ~T5_E~0); 40147#L1115-1 assume !(0 == ~T6_E~0); 40543#L1120-1 assume !(0 == ~T7_E~0); 40820#L1125-1 assume !(0 == ~T8_E~0); 41289#L1130-1 assume !(0 == ~T9_E~0); 41038#L1135-1 assume !(0 == ~T10_E~0); 40333#L1140-1 assume !(0 == ~T11_E~0); 40334#L1145-1 assume !(0 == ~E_1~0); 40972#L1150-1 assume !(0 == ~E_2~0); 40518#L1155-1 assume !(0 == ~E_3~0); 40519#L1160-1 assume !(0 == ~E_4~0); 40601#L1165-1 assume !(0 == ~E_5~0); 40602#L1170-1 assume !(0 == ~E_6~0); 41210#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 40679#L1180-1 assume !(0 == ~E_8~0); 40680#L1185-1 assume !(0 == ~E_9~0); 40330#L1190-1 assume !(0 == ~E_10~0); 40331#L1195-1 assume !(0 == ~E_11~0); 40693#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40533#L525 assume !(1 == ~m_pc~0); 39951#L525-2 is_master_triggered_~__retres1~0#1 := 0; 39952#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40697#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 40698#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 40317#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40318#L544 assume 1 == ~t1_pc~0; 40578#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 40542#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40970#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 40168#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 40169#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40791#L563 assume !(1 == ~t2_pc~0); 40957#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 39972#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39973#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 40401#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 40402#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40864#L582 assume 1 == ~t3_pc~0; 40110#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 40111#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41261#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41219#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 40046#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40047#L601 assume !(1 == ~t4_pc~0); 40987#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 40544#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40545#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 40981#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 40982#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41253#L620 assume 1 == ~t5_pc~0; 40001#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 40002#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40816#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40817#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 41268#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41269#L639 assume !(1 == ~t6_pc~0); 40818#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 40441#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40442#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41222#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 40552#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40553#L658 assume 1 == ~t7_pc~0; 40819#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 40744#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40851#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40852#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 40324#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40325#L677 assume 1 == ~t8_pc~0; 40555#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 40127#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40128#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40398#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 40399#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41077#L696 assume !(1 == ~t9_pc~0); 40802#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 40803#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40892#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40824#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 40825#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41022#L715 assume 1 == ~t10_pc~0; 41026#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 40909#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40794#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 40795#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 40671#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40119#L734 assume !(1 == ~t11_pc~0); 40120#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 40605#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 40684#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 39851#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 39852#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40879#L1213 assume !(1 == ~M_E~0); 40668#L1213-2 assume !(1 == ~T1_E~0); 40669#L1218-1 assume !(1 == ~T2_E~0); 39888#L1223-1 assume !(1 == ~T3_E~0); 39889#L1228-1 assume !(1 == ~T4_E~0); 40648#L1233-1 assume !(1 == ~T5_E~0); 41270#L1238-1 assume !(1 == ~T6_E~0); 40979#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 40980#L1248-1 assume !(1 == ~T8_E~0); 41024#L1253-1 assume !(1 == ~T9_E~0); 41025#L1258-1 assume !(1 == ~T10_E~0); 41003#L1263-1 assume !(1 == ~T11_E~0); 41004#L1268-1 assume !(1 == ~E_1~0); 40839#L1273-1 assume !(1 == ~E_2~0); 40840#L1278-1 assume !(1 == ~E_3~0); 40439#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 40440#L1288-1 assume !(1 == ~E_5~0); 41117#L1293-1 assume !(1 == ~E_6~0); 41081#L1298-1 assume !(1 == ~E_7~0); 40867#L1303-1 assume !(1 == ~E_8~0); 40450#L1308-1 assume !(1 == ~E_9~0); 40339#L1313-1 assume !(1 == ~E_10~0); 40340#L1318-1 assume !(1 == ~E_11~0); 40349#L1323-1 assume { :end_inline_reset_delta_events } true; 40350#L1644-2 [2022-07-23 15:32:29,602 INFO L754 eck$LassoCheckResult]: Loop: 40350#L1644-2 assume !false; 40920#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40921#L1065 assume !false; 40996#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 41266#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 39970#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 41182#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 40455#L906 assume !(0 != eval_~tmp~0#1); 40457#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 40993#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 40994#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 41134#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41186#L1095-3 assume !(0 == ~T2_E~0); 41149#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 41150#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 40223#L1110-3 assume !(0 == ~T5_E~0); 40224#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 40506#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 40507#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40977#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 41231#L1135-3 assume !(0 == ~T10_E~0); 40429#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 39924#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 39925#L1150-3 assume !(0 == ~E_2~0); 40048#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 40049#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 40410#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 40411#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 40783#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 40320#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 40078#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 40079#L1190-3 assume !(0 == ~E_10~0); 41225#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 41226#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40633#L525-36 assume !(1 == ~m_pc~0); 40634#L525-38 is_master_triggered_~__retres1~0#1 := 0; 40179#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40180#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 40465#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 40466#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40374#L544-36 assume 1 == ~t1_pc~0; 40375#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 40898#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40263#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 40264#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 41207#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41110#L563-36 assume 1 == ~t2_pc~0; 40166#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 39922#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39923#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 40985#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 40646#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40647#L582-36 assume 1 == ~t3_pc~0; 40497#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 40498#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40722#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40889#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 40683#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40627#L601-36 assume !(1 == ~t4_pc~0); 40528#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 40527#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41274#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41192#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 41193#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41098#L620-36 assume 1 == ~t5_pc~0; 40568#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 40569#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40960#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40554#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 40188#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39966#L639-36 assume !(1 == ~t6_pc~0); 39968#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 40006#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40007#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40246#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 40247#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40823#L658-36 assume 1 == ~t7_pc~0; 40085#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 39978#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41177#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39953#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 39954#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40944#L677-36 assume 1 == ~t8_pc~0; 41122#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 40749#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40865#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41249#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 40771#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40772#L696-36 assume 1 == ~t9_pc~0; 40665#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40667#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40026#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40027#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 40784#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 40785#L715-36 assume !(1 == ~t10_pc~0); 40755#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 39853#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 39854#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 39827#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 39828#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40232#L734-36 assume 1 == ~t11_pc~0; 40233#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 39932#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 40254#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 39845#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 39846#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40845#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 40514#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 40515#L1218-3 assume !(1 == ~T2_E~0); 40283#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40284#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 40473#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 40474#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 40718#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 40719#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 41191#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 41196#L1258-3 assume !(1 == ~T10_E~0); 40265#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 40266#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 41161#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 41179#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 41181#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 40597#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 40598#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 40463#L1298-3 assume !(1 == ~E_7~0); 40464#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 40919#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 40460#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 40461#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 40267#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 40268#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 40207#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 40618#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 41057#L1663 assume !(0 == start_simulation_~tmp~3#1); 40100#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 40821#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 40044#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 40742#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 39988#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 39989#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 40327#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 41246#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 40350#L1644-2 [2022-07-23 15:32:29,603 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:29,603 INFO L85 PathProgramCache]: Analyzing trace with hash -268309982, now seen corresponding path program 1 times [2022-07-23 15:32:29,603 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:29,603 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1428546284] [2022-07-23 15:32:29,603 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:29,603 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:29,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:29,625 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:29,626 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:29,626 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1428546284] [2022-07-23 15:32:29,626 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1428546284] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:29,626 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:29,626 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-23 15:32:29,626 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [306338799] [2022-07-23 15:32:29,626 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:29,627 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-23 15:32:29,627 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:29,627 INFO L85 PathProgramCache]: Analyzing trace with hash -1223781431, now seen corresponding path program 1 times [2022-07-23 15:32:29,627 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:29,627 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1514767604] [2022-07-23 15:32:29,627 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:29,627 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:29,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:29,651 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:29,651 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:29,651 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1514767604] [2022-07-23 15:32:29,651 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1514767604] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:29,652 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:29,652 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-23 15:32:29,652 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1579331030] [2022-07-23 15:32:29,652 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:29,652 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-23 15:32:29,652 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-23 15:32:29,653 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-23 15:32:29,653 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-23 15:32:29,653 INFO L87 Difference]: Start difference. First operand 1476 states and 2176 transitions. cyclomatic complexity: 701 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:29,691 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-23 15:32:29,692 INFO L93 Difference]: Finished difference Result 1476 states and 2158 transitions. [2022-07-23 15:32:29,692 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-23 15:32:29,692 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2158 transitions. [2022-07-23 15:32:29,697 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-07-23 15:32:29,700 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2158 transitions. [2022-07-23 15:32:29,701 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2022-07-23 15:32:29,702 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2022-07-23 15:32:29,702 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2158 transitions. [2022-07-23 15:32:29,703 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-23 15:32:29,703 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2158 transitions. [2022-07-23 15:32:29,704 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2158 transitions. [2022-07-23 15:32:29,713 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2022-07-23 15:32:29,714 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.462059620596206) internal successors, (2158), 1475 states have internal predecessors, (2158), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:29,717 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2158 transitions. [2022-07-23 15:32:29,717 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2158 transitions. [2022-07-23 15:32:29,717 INFO L374 stractBuchiCegarLoop]: Abstraction has 1476 states and 2158 transitions. [2022-07-23 15:32:29,717 INFO L287 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-07-23 15:32:29,717 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2158 transitions. [2022-07-23 15:32:29,721 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-07-23 15:32:29,721 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-23 15:32:29,721 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-23 15:32:29,722 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:29,722 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:29,722 INFO L752 eck$LassoCheckResult]: Stem: 43906#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 43907#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 43914#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 43915#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 43681#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 43682#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43552#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43464#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43187#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 42822#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 42823#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 42871#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 42872#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 43800#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 43801#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 43839#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 43287#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 43288#L1090 assume !(0 == ~M_E~0); 43330#L1090-2 assume !(0 == ~T1_E~0); 43331#L1095-1 assume !(0 == ~T2_E~0); 43976#L1100-1 assume !(0 == ~T3_E~0); 43977#L1105-1 assume !(0 == ~T4_E~0); 43105#L1110-1 assume !(0 == ~T5_E~0); 43106#L1115-1 assume !(0 == ~T6_E~0); 43502#L1120-1 assume !(0 == ~T7_E~0); 43778#L1125-1 assume !(0 == ~T8_E~0); 44248#L1130-1 assume !(0 == ~T9_E~0); 43997#L1135-1 assume !(0 == ~T10_E~0); 43292#L1140-1 assume !(0 == ~T11_E~0); 43293#L1145-1 assume !(0 == ~E_1~0); 43931#L1150-1 assume !(0 == ~E_2~0); 43477#L1155-1 assume !(0 == ~E_3~0); 43478#L1160-1 assume !(0 == ~E_4~0); 43560#L1165-1 assume !(0 == ~E_5~0); 43561#L1170-1 assume !(0 == ~E_6~0); 44169#L1175-1 assume !(0 == ~E_7~0); 43637#L1180-1 assume !(0 == ~E_8~0); 43638#L1185-1 assume !(0 == ~E_9~0); 43289#L1190-1 assume !(0 == ~E_10~0); 43290#L1195-1 assume !(0 == ~E_11~0); 43651#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43492#L525 assume !(1 == ~m_pc~0); 42910#L525-2 is_master_triggered_~__retres1~0#1 := 0; 42911#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43655#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 43656#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 43276#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43277#L544 assume 1 == ~t1_pc~0; 43537#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 43501#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43929#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 43127#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 43128#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43749#L563 assume !(1 == ~t2_pc~0); 43916#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 42931#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42932#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 43360#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 43361#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43823#L582 assume 1 == ~t3_pc~0; 43069#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 43070#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44220#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44178#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 43005#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43006#L601 assume !(1 == ~t4_pc~0); 43946#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 43503#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43504#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43940#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 43941#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44212#L620 assume 1 == ~t5_pc~0; 42960#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 42961#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43774#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43775#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 44227#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 44228#L639 assume !(1 == ~t6_pc~0); 43776#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 43400#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 43401#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 44181#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 43511#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43512#L658 assume !(1 == ~t7_pc~0); 43701#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 43702#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 43810#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43811#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 43283#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43284#L677 assume 1 == ~t8_pc~0; 43514#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 43086#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43087#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 43357#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 43358#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44036#L696 assume !(1 == ~t9_pc~0); 43760#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 43761#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 43851#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43782#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 43783#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43981#L715 assume 1 == ~t10_pc~0; 43985#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 43868#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43752#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43753#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 43629#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43078#L734 assume !(1 == ~t11_pc~0); 43079#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 43564#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43642#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42810#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 42811#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43838#L1213 assume !(1 == ~M_E~0); 43626#L1213-2 assume !(1 == ~T1_E~0); 43627#L1218-1 assume !(1 == ~T2_E~0); 42847#L1223-1 assume !(1 == ~T3_E~0); 42848#L1228-1 assume !(1 == ~T4_E~0); 43606#L1233-1 assume !(1 == ~T5_E~0); 44229#L1238-1 assume !(1 == ~T6_E~0); 43938#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 43939#L1248-1 assume !(1 == ~T8_E~0); 43983#L1253-1 assume !(1 == ~T9_E~0); 43984#L1258-1 assume !(1 == ~T10_E~0); 43962#L1263-1 assume !(1 == ~T11_E~0); 43963#L1268-1 assume !(1 == ~E_1~0); 43798#L1273-1 assume !(1 == ~E_2~0); 43799#L1278-1 assume !(1 == ~E_3~0); 43398#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 43399#L1288-1 assume !(1 == ~E_5~0); 44076#L1293-1 assume !(1 == ~E_6~0); 44040#L1298-1 assume !(1 == ~E_7~0); 43826#L1303-1 assume !(1 == ~E_8~0); 43409#L1308-1 assume !(1 == ~E_9~0); 43298#L1313-1 assume !(1 == ~E_10~0); 43299#L1318-1 assume !(1 == ~E_11~0); 43308#L1323-1 assume { :end_inline_reset_delta_events } true; 43309#L1644-2 [2022-07-23 15:32:29,723 INFO L754 eck$LassoCheckResult]: Loop: 43309#L1644-2 assume !false; 43879#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 43880#L1065 assume !false; 43955#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 44225#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 42929#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 44141#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 43414#L906 assume !(0 != eval_~tmp~0#1); 43416#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 43952#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 43953#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 44093#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44145#L1095-3 assume !(0 == ~T2_E~0); 44108#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 44109#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 43182#L1110-3 assume !(0 == ~T5_E~0); 43183#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 43465#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 43466#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 43936#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 44190#L1135-3 assume !(0 == ~T10_E~0); 43388#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 42883#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 42884#L1150-3 assume !(0 == ~E_2~0); 43007#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 43008#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 43369#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 43370#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 43741#L1175-3 assume !(0 == ~E_7~0); 43279#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 43037#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 43038#L1190-3 assume !(0 == ~E_10~0); 44184#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 44185#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43591#L525-36 assume !(1 == ~m_pc~0); 43592#L525-38 is_master_triggered_~__retres1~0#1 := 0; 43138#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43139#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 43424#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 43425#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43333#L544-36 assume 1 == ~t1_pc~0; 43334#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 43857#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43222#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 43223#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 44166#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44069#L563-36 assume 1 == ~t2_pc~0; 43125#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 42881#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42882#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 43944#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 43604#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43605#L582-36 assume 1 == ~t3_pc~0; 43456#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 43457#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43680#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43848#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 43641#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43585#L601-36 assume 1 == ~t4_pc~0; 43485#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 43486#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44233#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44151#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 44152#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44057#L620-36 assume 1 == ~t5_pc~0; 43527#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 43528#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43919#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43513#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 43147#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42925#L639-36 assume 1 == ~t6_pc~0; 42926#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 42965#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42966#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43205#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 43206#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43781#L658-36 assume !(1 == ~t7_pc~0); 42936#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 42937#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44136#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 42912#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 42913#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43903#L677-36 assume 1 == ~t8_pc~0; 44081#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 43707#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43824#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44208#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 43729#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 43730#L696-36 assume 1 == ~t9_pc~0; 43623#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 43625#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 42985#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 42986#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 43742#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43743#L715-36 assume !(1 == ~t10_pc~0); 43713#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 42812#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 42813#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 42786#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 42787#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43191#L734-36 assume 1 == ~t11_pc~0; 43192#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 42891#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43213#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42804#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 42805#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43804#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 43473#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 43474#L1218-3 assume !(1 == ~T2_E~0); 43242#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 43243#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43432#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 43433#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 43676#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 43677#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 44150#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 44155#L1258-3 assume !(1 == ~T10_E~0); 43224#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 43225#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 44120#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 44138#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 44140#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 43556#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 43557#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 43422#L1298-3 assume !(1 == ~E_7~0); 43423#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 43878#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 43419#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 43420#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 43226#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 43227#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 43166#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 43577#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 44016#L1663 assume !(0 == start_simulation_~tmp~3#1); 43059#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 43779#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 43003#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 43700#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 42947#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 42948#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 43286#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 44205#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 43309#L1644-2 [2022-07-23 15:32:29,723 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:29,723 INFO L85 PathProgramCache]: Analyzing trace with hash -2032217409, now seen corresponding path program 1 times [2022-07-23 15:32:29,723 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:29,724 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1000017691] [2022-07-23 15:32:29,724 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:29,724 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:29,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:29,750 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:29,751 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:29,751 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1000017691] [2022-07-23 15:32:29,751 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1000017691] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:29,751 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:29,751 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-23 15:32:29,751 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [205880357] [2022-07-23 15:32:29,751 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:29,752 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-23 15:32:29,752 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:29,752 INFO L85 PathProgramCache]: Analyzing trace with hash 540451880, now seen corresponding path program 1 times [2022-07-23 15:32:29,752 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:29,752 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [977634609] [2022-07-23 15:32:29,752 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:29,753 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:29,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:29,776 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:29,777 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:29,777 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [977634609] [2022-07-23 15:32:29,777 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [977634609] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:29,777 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:29,777 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-23 15:32:29,777 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [986893700] [2022-07-23 15:32:29,777 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:29,778 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-23 15:32:29,778 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-23 15:32:29,778 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-07-23 15:32:29,778 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-07-23 15:32:29,778 INFO L87 Difference]: Start difference. First operand 1476 states and 2158 transitions. cyclomatic complexity: 683 Second operand has 5 states, 5 states have (on average 27.4) internal successors, (137), 5 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:29,997 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-23 15:32:29,997 INFO L93 Difference]: Finished difference Result 4220 states and 6138 transitions. [2022-07-23 15:32:29,997 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-07-23 15:32:29,998 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4220 states and 6138 transitions. [2022-07-23 15:32:30,014 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3864 [2022-07-23 15:32:30,026 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4220 states to 4220 states and 6138 transitions. [2022-07-23 15:32:30,027 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4220 [2022-07-23 15:32:30,029 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4220 [2022-07-23 15:32:30,029 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4220 states and 6138 transitions. [2022-07-23 15:32:30,032 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-23 15:32:30,032 INFO L369 hiAutomatonCegarLoop]: Abstraction has 4220 states and 6138 transitions. [2022-07-23 15:32:30,034 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4220 states and 6138 transitions. [2022-07-23 15:32:30,048 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4220 to 1518. [2022-07-23 15:32:30,050 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1518 states, 1518 states have (on average 1.4492753623188406) internal successors, (2200), 1517 states have internal predecessors, (2200), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:30,052 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1518 states to 1518 states and 2200 transitions. [2022-07-23 15:32:30,053 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1518 states and 2200 transitions. [2022-07-23 15:32:30,053 INFO L374 stractBuchiCegarLoop]: Abstraction has 1518 states and 2200 transitions. [2022-07-23 15:32:30,053 INFO L287 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-07-23 15:32:30,053 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1518 states and 2200 transitions. [2022-07-23 15:32:30,056 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1366 [2022-07-23 15:32:30,056 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-23 15:32:30,056 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-23 15:32:30,057 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:30,058 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:30,058 INFO L752 eck$LassoCheckResult]: Stem: 49632#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 49633#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 49640#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 49641#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 49399#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 49400#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49268#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49178#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 48898#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 48533#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 48534#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 48582#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 48583#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49520#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 49521#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 49559#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 48999#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49000#L1090 assume !(0 == ~M_E~0); 49042#L1090-2 assume !(0 == ~T1_E~0); 49043#L1095-1 assume !(0 == ~T2_E~0); 49703#L1100-1 assume !(0 == ~T3_E~0); 49704#L1105-1 assume !(0 == ~T4_E~0); 48816#L1110-1 assume !(0 == ~T5_E~0); 48817#L1115-1 assume !(0 == ~T6_E~0); 49216#L1120-1 assume !(0 == ~T7_E~0); 49498#L1125-1 assume !(0 == ~T8_E~0); 49992#L1130-1 assume !(0 == ~T9_E~0); 49724#L1135-1 assume !(0 == ~T10_E~0); 49004#L1140-1 assume !(0 == ~T11_E~0); 49005#L1145-1 assume !(0 == ~E_1~0); 49657#L1150-1 assume !(0 == ~E_2~0); 49191#L1155-1 assume !(0 == ~E_3~0); 49192#L1160-1 assume !(0 == ~E_4~0); 49276#L1165-1 assume !(0 == ~E_5~0); 49277#L1170-1 assume !(0 == ~E_6~0); 49904#L1175-1 assume !(0 == ~E_7~0); 49354#L1180-1 assume !(0 == ~E_8~0); 49355#L1185-1 assume !(0 == ~E_9~0); 49001#L1190-1 assume !(0 == ~E_10~0); 49002#L1195-1 assume !(0 == ~E_11~0); 49368#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49206#L525 assume !(1 == ~m_pc~0); 48621#L525-2 is_master_triggered_~__retres1~0#1 := 0; 48622#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49869#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 49770#L1350 assume !(0 != activate_threads_~tmp~1#1); 48988#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48989#L544 assume 1 == ~t1_pc~0; 49251#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49215#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49655#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 48838#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 48839#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49468#L563 assume !(1 == ~t2_pc~0); 49642#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 48642#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48643#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49072#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 49073#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49543#L582 assume 1 == ~t3_pc~0; 48780#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 48781#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49959#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49913#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 48716#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48717#L601 assume !(1 == ~t4_pc~0); 49672#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 49217#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49218#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49666#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 49667#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49950#L620 assume 1 == ~t5_pc~0; 48671#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 48672#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49494#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49495#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 49968#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49969#L639 assume !(1 == ~t6_pc~0); 49496#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 49113#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49114#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49916#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 49225#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49226#L658 assume !(1 == ~t7_pc~0); 49419#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 49420#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49530#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49531#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 48995#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 48996#L677 assume 1 == ~t8_pc~0; 49228#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 48797#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48798#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49069#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 49070#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49764#L696 assume !(1 == ~t9_pc~0); 49479#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 49480#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49571#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49502#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 49503#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49708#L715 assume 1 == ~t10_pc~0; 49712#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 49588#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 49471#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49472#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 49346#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48789#L734 assume !(1 == ~t11_pc~0); 48790#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 49280#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49359#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 48521#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 48522#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49558#L1213 assume !(1 == ~M_E~0); 49343#L1213-2 assume !(1 == ~T1_E~0); 49344#L1218-1 assume !(1 == ~T2_E~0); 48558#L1223-1 assume !(1 == ~T3_E~0); 48559#L1228-1 assume !(1 == ~T4_E~0); 49323#L1233-1 assume !(1 == ~T5_E~0); 49970#L1238-1 assume !(1 == ~T6_E~0); 49664#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 49665#L1248-1 assume !(1 == ~T8_E~0); 49710#L1253-1 assume !(1 == ~T9_E~0); 49711#L1258-1 assume !(1 == ~T10_E~0); 49688#L1263-1 assume !(1 == ~T11_E~0); 49689#L1268-1 assume !(1 == ~E_1~0); 49518#L1273-1 assume !(1 == ~E_2~0); 49519#L1278-1 assume !(1 == ~E_3~0); 49111#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 49112#L1288-1 assume !(1 == ~E_5~0); 49806#L1293-1 assume !(1 == ~E_6~0); 49768#L1298-1 assume !(1 == ~E_7~0); 49546#L1303-1 assume !(1 == ~E_8~0); 49123#L1308-1 assume !(1 == ~E_9~0); 49010#L1313-1 assume !(1 == ~E_10~0); 49011#L1318-1 assume !(1 == ~E_11~0); 49020#L1323-1 assume { :end_inline_reset_delta_events } true; 49021#L1644-2 [2022-07-23 15:32:30,058 INFO L754 eck$LassoCheckResult]: Loop: 49021#L1644-2 assume !false; 49602#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49603#L1065 assume !false; 49681#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 49966#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 48640#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 49874#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 49128#L906 assume !(0 != eval_~tmp~0#1); 49130#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 49678#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 49679#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 49824#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 49878#L1095-3 assume !(0 == ~T2_E~0); 49839#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 49840#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 48893#L1110-3 assume !(0 == ~T5_E~0); 48894#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 49179#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 49180#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 49662#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 49926#L1135-3 assume !(0 == ~T10_E~0); 49100#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 48594#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 48595#L1150-3 assume !(0 == ~E_2~0); 48718#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 48719#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 49081#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 49082#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 49460#L1175-3 assume !(0 == ~E_7~0); 48991#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 48748#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 48749#L1190-3 assume !(0 == ~E_10~0); 49919#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 49920#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49307#L525-36 assume !(1 == ~m_pc~0); 49308#L525-38 is_master_triggered_~__retres1~0#1 := 0; 48849#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48850#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 49138#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 49139#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49045#L544-36 assume 1 == ~t1_pc~0; 49046#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49577#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48933#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 48934#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 49901#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49799#L563-36 assume 1 == ~t2_pc~0; 48836#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 48592#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48593#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49670#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 49321#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49322#L582-36 assume 1 == ~t3_pc~0; 49170#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49171#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49398#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49568#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 49358#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49301#L601-36 assume !(1 == ~t4_pc~0); 49201#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 49200#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49974#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49884#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 49885#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49787#L620-36 assume 1 == ~t5_pc~0; 49241#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49242#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49645#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49227#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 48858#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 48636#L639-36 assume 1 == ~t6_pc~0; 48637#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 48676#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 48677#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 48916#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 48917#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49501#L658-36 assume !(1 == ~t7_pc~0); 48647#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 48648#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49868#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 48623#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 48624#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49629#L677-36 assume !(1 == ~t8_pc~0); 49424#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 49425#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49544#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49946#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 49447#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49448#L696-36 assume 1 == ~t9_pc~0; 49340#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 49342#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 48696#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 48697#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 49461#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49462#L715-36 assume !(1 == ~t10_pc~0); 49431#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 48523#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 48524#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 48497#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 48498#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48902#L734-36 assume 1 == ~t11_pc~0; 48903#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 48602#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 48924#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 48515#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 48516#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49524#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 49187#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 49188#L1218-3 assume !(1 == ~T2_E~0); 48953#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 48954#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 49146#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 49147#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 49394#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 49395#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 49883#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 49888#L1258-3 assume !(1 == ~T10_E~0); 48935#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 48936#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 49851#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 49871#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 49873#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49272#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 49273#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 49136#L1298-3 assume !(1 == ~E_7~0); 49137#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 49599#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 49133#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 49134#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 48937#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 48938#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 48877#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 49293#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 49744#L1663 assume !(0 == start_simulation_~tmp~3#1); 48770#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 49499#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 48714#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 49418#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 48658#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 48659#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 48998#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 49942#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 49021#L1644-2 [2022-07-23 15:32:30,059 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:30,059 INFO L85 PathProgramCache]: Analyzing trace with hash -2060717699, now seen corresponding path program 1 times [2022-07-23 15:32:30,059 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:30,059 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [108040227] [2022-07-23 15:32:30,059 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:30,059 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:30,067 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:30,081 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:30,082 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:30,082 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [108040227] [2022-07-23 15:32:30,082 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [108040227] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:30,082 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:30,082 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-23 15:32:30,082 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [919057391] [2022-07-23 15:32:30,082 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:30,083 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-23 15:32:30,083 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:30,083 INFO L85 PathProgramCache]: Analyzing trace with hash -431644380, now seen corresponding path program 1 times [2022-07-23 15:32:30,083 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:30,083 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [118896890] [2022-07-23 15:32:30,083 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:30,083 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:30,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:30,106 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:30,107 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:30,107 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [118896890] [2022-07-23 15:32:30,107 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [118896890] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:30,107 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:30,107 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-23 15:32:30,107 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1763957643] [2022-07-23 15:32:30,107 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:30,108 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-23 15:32:30,108 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-23 15:32:30,108 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-23 15:32:30,108 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-23 15:32:30,109 INFO L87 Difference]: Start difference. First operand 1518 states and 2200 transitions. cyclomatic complexity: 683 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:30,280 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-23 15:32:30,280 INFO L93 Difference]: Finished difference Result 4068 states and 5826 transitions. [2022-07-23 15:32:30,280 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-23 15:32:30,280 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4068 states and 5826 transitions. [2022-07-23 15:32:30,296 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3828 [2022-07-23 15:32:30,305 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4068 states to 4068 states and 5826 transitions. [2022-07-23 15:32:30,306 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4068 [2022-07-23 15:32:30,325 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4068 [2022-07-23 15:32:30,325 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4068 states and 5826 transitions. [2022-07-23 15:32:30,330 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-23 15:32:30,330 INFO L369 hiAutomatonCegarLoop]: Abstraction has 4068 states and 5826 transitions. [2022-07-23 15:32:30,333 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4068 states and 5826 transitions. [2022-07-23 15:32:30,370 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4068 to 3902. [2022-07-23 15:32:30,374 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3902 states, 3902 states have (on average 1.4349051768323937) internal successors, (5599), 3901 states have internal predecessors, (5599), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:30,382 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3902 states to 3902 states and 5599 transitions. [2022-07-23 15:32:30,382 INFO L392 hiAutomatonCegarLoop]: Abstraction has 3902 states and 5599 transitions. [2022-07-23 15:32:30,382 INFO L374 stractBuchiCegarLoop]: Abstraction has 3902 states and 5599 transitions. [2022-07-23 15:32:30,382 INFO L287 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-07-23 15:32:30,382 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3902 states and 5599 transitions. [2022-07-23 15:32:30,393 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3750 [2022-07-23 15:32:30,394 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-23 15:32:30,394 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-23 15:32:30,395 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:30,395 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:30,395 INFO L752 eck$LassoCheckResult]: Stem: 55230#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 55231#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 55238#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 55239#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 54996#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 54997#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 54866#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 54775#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 54496#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 54131#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 54132#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 54180#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 54181#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 55121#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 55122#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 55160#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 54597#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 54598#L1090 assume !(0 == ~M_E~0); 54641#L1090-2 assume !(0 == ~T1_E~0); 54642#L1095-1 assume !(0 == ~T2_E~0); 55303#L1100-1 assume !(0 == ~T3_E~0); 55304#L1105-1 assume !(0 == ~T4_E~0); 54414#L1110-1 assume !(0 == ~T5_E~0); 54415#L1115-1 assume !(0 == ~T6_E~0); 54816#L1120-1 assume !(0 == ~T7_E~0); 55099#L1125-1 assume !(0 == ~T8_E~0); 55638#L1130-1 assume !(0 == ~T9_E~0); 55327#L1135-1 assume !(0 == ~T10_E~0); 54602#L1140-1 assume !(0 == ~T11_E~0); 54603#L1145-1 assume !(0 == ~E_1~0); 55255#L1150-1 assume !(0 == ~E_2~0); 54789#L1155-1 assume !(0 == ~E_3~0); 54790#L1160-1 assume !(0 == ~E_4~0); 54874#L1165-1 assume !(0 == ~E_5~0); 54875#L1170-1 assume !(0 == ~E_6~0); 55525#L1175-1 assume !(0 == ~E_7~0); 54951#L1180-1 assume !(0 == ~E_8~0); 54952#L1185-1 assume !(0 == ~E_9~0); 54599#L1190-1 assume !(0 == ~E_10~0); 54600#L1195-1 assume !(0 == ~E_11~0); 54965#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54806#L525 assume !(1 == ~m_pc~0); 54219#L525-2 is_master_triggered_~__retres1~0#1 := 0; 54220#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54969#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 54970#L1350 assume !(0 != activate_threads_~tmp~1#1); 54586#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54587#L544 assume !(1 == ~t1_pc~0); 54814#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 54815#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55253#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 54435#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 54436#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55069#L563 assume !(1 == ~t2_pc~0); 55240#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 54240#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54241#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 54671#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 54672#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55144#L582 assume 1 == ~t3_pc~0; 54378#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 54379#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55595#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 55537#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 54314#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54315#L601 assume !(1 == ~t4_pc~0); 55272#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 54817#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54818#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 55266#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 55267#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 55587#L620 assume 1 == ~t5_pc~0; 54269#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 54270#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 55095#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 55096#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 55611#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 55612#L639 assume !(1 == ~t6_pc~0); 55097#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 54710#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54711#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 55540#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 54824#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54825#L658 assume !(1 == ~t7_pc~0); 55017#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 55018#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 55131#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 55132#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 54593#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 54594#L677 assume 1 == ~t8_pc~0; 54828#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 54395#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 54396#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 54668#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 54669#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 55369#L696 assume !(1 == ~t9_pc~0); 55080#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 55081#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 55171#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 55103#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 55104#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 55308#L715 assume 1 == ~t10_pc~0; 55315#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 55188#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 55072#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 55073#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 54942#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 54387#L734 assume !(1 == ~t11_pc~0); 54388#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 54878#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 54956#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54119#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 54120#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 55159#L1213 assume !(1 == ~M_E~0); 54939#L1213-2 assume !(1 == ~T1_E~0); 54940#L1218-1 assume !(1 == ~T2_E~0); 54156#L1223-1 assume !(1 == ~T3_E~0); 54157#L1228-1 assume !(1 == ~T4_E~0); 54919#L1233-1 assume !(1 == ~T5_E~0); 55613#L1238-1 assume !(1 == ~T6_E~0); 55264#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 55265#L1248-1 assume !(1 == ~T8_E~0); 55313#L1253-1 assume !(1 == ~T9_E~0); 55314#L1258-1 assume !(1 == ~T10_E~0); 55288#L1263-1 assume !(1 == ~T11_E~0); 55289#L1268-1 assume !(1 == ~E_1~0); 55119#L1273-1 assume !(1 == ~E_2~0); 55120#L1278-1 assume !(1 == ~E_3~0); 54708#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 54709#L1288-1 assume !(1 == ~E_5~0); 55417#L1293-1 assume !(1 == ~E_6~0); 55375#L1298-1 assume !(1 == ~E_7~0); 55147#L1303-1 assume !(1 == ~E_8~0); 54719#L1308-1 assume !(1 == ~E_9~0); 54608#L1313-1 assume !(1 == ~E_10~0); 54609#L1318-1 assume !(1 == ~E_11~0); 54618#L1323-1 assume { :end_inline_reset_delta_events } true; 54619#L1644-2 [2022-07-23 15:32:30,395 INFO L754 eck$LassoCheckResult]: Loop: 54619#L1644-2 assume !false; 55201#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 55202#L1065 assume !false; 55281#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 55609#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 54238#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 55491#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 54724#L906 assume !(0 != eval_~tmp~0#1); 54726#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 55278#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 55279#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 55496#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 55497#L1095-3 assume !(0 == ~T2_E~0); 55454#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 55455#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 55608#L1110-3 assume !(0 == ~T5_E~0); 55529#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 55530#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 57991#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 57990#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 55623#L1135-3 assume !(0 == ~T10_E~0); 54698#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 54192#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 54193#L1150-3 assume !(0 == ~E_2~0); 54316#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 54317#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 55654#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 55662#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 55663#L1175-3 assume !(0 == ~E_7~0); 54589#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 54346#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 54347#L1190-3 assume !(0 == ~E_10~0); 55543#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 55544#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54905#L525-36 assume !(1 == ~m_pc~0); 54906#L525-38 is_master_triggered_~__retres1~0#1 := 0; 54446#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54447#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 54734#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 54735#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54646#L544-36 assume !(1 == ~t1_pc~0); 54647#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 55177#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54531#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 54532#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 55522#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55408#L563-36 assume 1 == ~t2_pc~0; 54433#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 54190#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54191#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 55270#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 54917#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54918#L582-36 assume !(1 == ~t3_pc~0); 54769#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 54768#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54995#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 55168#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 54955#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54899#L601-36 assume !(1 == ~t4_pc~0); 54801#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 54800#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55618#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 55503#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 55504#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 55396#L620-36 assume 1 == ~t5_pc~0; 54841#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 54842#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 55243#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 54827#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 54455#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54234#L639-36 assume 1 == ~t6_pc~0; 54235#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 54274#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54275#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 54512#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 54513#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 55102#L658-36 assume !(1 == ~t7_pc~0); 54245#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 54246#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 55486#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54221#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 54222#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 55227#L677-36 assume 1 == ~t8_pc~0; 55425#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 55023#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 55145#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 55579#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 55046#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 55047#L696-36 assume 1 == ~t9_pc~0; 54936#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 54938#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 54294#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 54295#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 55062#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 55063#L715-36 assume !(1 == ~t10_pc~0); 55030#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 54121#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 54122#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 54095#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 54096#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 54500#L734-36 assume 1 == ~t11_pc~0; 54501#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 54200#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 54522#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54113#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 54114#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 55125#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 54785#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 54786#L1218-3 assume !(1 == ~T2_E~0); 54551#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 54552#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 54742#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 54743#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 54991#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 54992#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 55502#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 55508#L1258-3 assume !(1 == ~T10_E~0); 54533#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 54534#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 55467#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 55488#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 55490#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 54870#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 54871#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 54732#L1298-3 assume !(1 == ~E_7~0); 54733#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 55199#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 54729#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 54730#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 54535#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 54536#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 54474#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 54891#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 55349#L1663 assume !(0 == start_simulation_~tmp~3#1); 54368#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 55100#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 54312#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 55016#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 54256#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 54257#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 54596#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 55572#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 54619#L1644-2 [2022-07-23 15:32:30,396 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:30,396 INFO L85 PathProgramCache]: Analyzing trace with hash -2098164388, now seen corresponding path program 1 times [2022-07-23 15:32:30,396 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:30,396 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [179728988] [2022-07-23 15:32:30,396 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:30,396 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:30,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:30,442 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:30,442 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:30,442 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [179728988] [2022-07-23 15:32:30,442 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [179728988] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:30,442 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:30,442 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-23 15:32:30,443 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1361880837] [2022-07-23 15:32:30,443 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:30,443 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-23 15:32:30,443 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:30,443 INFO L85 PathProgramCache]: Analyzing trace with hash -427579837, now seen corresponding path program 1 times [2022-07-23 15:32:30,443 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:30,443 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1437283271] [2022-07-23 15:32:30,443 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:30,444 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:30,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:30,470 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:30,470 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:30,470 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1437283271] [2022-07-23 15:32:30,470 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1437283271] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:30,470 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:30,470 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-23 15:32:30,471 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [556764392] [2022-07-23 15:32:30,471 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:30,471 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-23 15:32:30,471 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-23 15:32:30,471 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-23 15:32:30,471 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-23 15:32:30,471 INFO L87 Difference]: Start difference. First operand 3902 states and 5599 transitions. cyclomatic complexity: 1699 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:30,654 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-23 15:32:30,654 INFO L93 Difference]: Finished difference Result 10909 states and 15519 transitions. [2022-07-23 15:32:30,654 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-23 15:32:30,655 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10909 states and 15519 transitions. [2022-07-23 15:32:30,705 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 10559 [2022-07-23 15:32:30,735 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10909 states to 10909 states and 15519 transitions. [2022-07-23 15:32:30,735 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10909 [2022-07-23 15:32:30,743 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10909 [2022-07-23 15:32:30,744 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10909 states and 15519 transitions. [2022-07-23 15:32:30,755 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-23 15:32:30,755 INFO L369 hiAutomatonCegarLoop]: Abstraction has 10909 states and 15519 transitions. [2022-07-23 15:32:30,764 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10909 states and 15519 transitions. [2022-07-23 15:32:30,874 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10909 to 10528. [2022-07-23 15:32:30,887 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10528 states, 10528 states have (on average 1.425056990881459) internal successors, (15003), 10527 states have internal predecessors, (15003), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:30,905 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10528 states to 10528 states and 15003 transitions. [2022-07-23 15:32:30,905 INFO L392 hiAutomatonCegarLoop]: Abstraction has 10528 states and 15003 transitions. [2022-07-23 15:32:30,905 INFO L374 stractBuchiCegarLoop]: Abstraction has 10528 states and 15003 transitions. [2022-07-23 15:32:30,905 INFO L287 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-07-23 15:32:30,905 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10528 states and 15003 transitions. [2022-07-23 15:32:30,936 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 10367 [2022-07-23 15:32:30,936 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-23 15:32:30,936 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-23 15:32:30,937 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:30,937 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:30,938 INFO L752 eck$LassoCheckResult]: Stem: 70060#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 70061#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 70069#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 70070#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 69825#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 69826#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 69691#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 69598#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 69316#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 68954#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 68955#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 69003#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 69004#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 69947#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 69948#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 69992#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 69421#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 69422#L1090 assume !(0 == ~M_E~0); 69469#L1090-2 assume !(0 == ~T1_E~0); 69470#L1095-1 assume !(0 == ~T2_E~0); 70136#L1100-1 assume !(0 == ~T3_E~0); 70137#L1105-1 assume !(0 == ~T4_E~0); 69234#L1110-1 assume !(0 == ~T5_E~0); 69235#L1115-1 assume !(0 == ~T6_E~0); 69640#L1120-1 assume !(0 == ~T7_E~0); 69922#L1125-1 assume !(0 == ~T8_E~0); 70490#L1130-1 assume !(0 == ~T9_E~0); 70161#L1135-1 assume !(0 == ~T10_E~0); 69428#L1140-1 assume !(0 == ~T11_E~0); 69429#L1145-1 assume !(0 == ~E_1~0); 70087#L1150-1 assume !(0 == ~E_2~0); 69612#L1155-1 assume !(0 == ~E_3~0); 69613#L1160-1 assume !(0 == ~E_4~0); 69699#L1165-1 assume !(0 == ~E_5~0); 69700#L1170-1 assume !(0 == ~E_6~0); 70366#L1175-1 assume !(0 == ~E_7~0); 69779#L1180-1 assume !(0 == ~E_8~0); 69780#L1185-1 assume !(0 == ~E_9~0); 69423#L1190-1 assume !(0 == ~E_10~0); 69424#L1195-1 assume !(0 == ~E_11~0); 69793#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 69631#L525 assume !(1 == ~m_pc~0); 69041#L525-2 is_master_triggered_~__retres1~0#1 := 0; 69042#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69797#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 69798#L1350 assume !(0 != activate_threads_~tmp~1#1); 69411#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69412#L544 assume !(1 == ~t1_pc~0); 69636#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 69637#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 70084#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 69255#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 69256#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 69893#L563 assume !(1 == ~t2_pc~0); 70071#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 69062#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 69063#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 69493#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 69494#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 69970#L582 assume !(1 == ~t3_pc~0); 70085#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 70442#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 70443#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 70375#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 69137#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 69138#L601 assume !(1 == ~t4_pc~0); 70103#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 69641#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 69642#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 70097#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 70098#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 70435#L620 assume 1 == ~t5_pc~0; 69091#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 69092#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 69918#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 69919#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 70456#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 70457#L639 assume !(1 == ~t6_pc~0); 69920#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 69531#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 69532#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 70378#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 69646#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 69647#L658 assume !(1 == ~t7_pc~0); 69845#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 69846#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 69957#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 69958#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 69417#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 69418#L677 assume 1 == ~t8_pc~0; 69650#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 69221#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 69222#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 69490#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 69491#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 70205#L696 assume !(1 == ~t9_pc~0); 69906#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 69907#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 69997#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 69927#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 69928#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 70140#L715 assume 1 == ~t10_pc~0; 70147#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 70014#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 69896#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 69897#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 69770#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 69209#L734 assume !(1 == ~t11_pc~0); 69210#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 69706#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 69784#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 68944#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 68945#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69985#L1213 assume !(1 == ~M_E~0); 69768#L1213-2 assume !(1 == ~T1_E~0); 69769#L1218-1 assume !(1 == ~T2_E~0); 68979#L1223-1 assume !(1 == ~T3_E~0); 68980#L1228-1 assume !(1 == ~T4_E~0); 69747#L1233-1 assume !(1 == ~T5_E~0); 70458#L1238-1 assume !(1 == ~T6_E~0); 70095#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 70096#L1248-1 assume !(1 == ~T8_E~0); 70145#L1253-1 assume !(1 == ~T9_E~0); 70146#L1258-1 assume !(1 == ~T10_E~0); 70121#L1263-1 assume !(1 == ~T11_E~0); 70122#L1268-1 assume !(1 == ~E_1~0); 69944#L1273-1 assume !(1 == ~E_2~0); 69945#L1278-1 assume !(1 == ~E_3~0); 69529#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 69530#L1288-1 assume !(1 == ~E_5~0); 70253#L1293-1 assume !(1 == ~E_6~0); 70212#L1298-1 assume !(1 == ~E_7~0); 69973#L1303-1 assume !(1 == ~E_8~0); 69541#L1308-1 assume !(1 == ~E_9~0); 69434#L1313-1 assume !(1 == ~E_10~0); 69435#L1318-1 assume !(1 == ~E_11~0); 69442#L1323-1 assume { :end_inline_reset_delta_events } true; 69443#L1644-2 [2022-07-23 15:32:30,938 INFO L754 eck$LassoCheckResult]: Loop: 69443#L1644-2 assume !false; 77136#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 77132#L1065 assume !false; 77125#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 77126#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 78454#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 78453#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 78451#L906 assume !(0 != eval_~tmp~0#1); 78452#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 79371#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 79370#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 79369#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 79368#L1095-3 assume !(0 == ~T2_E~0); 79367#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 79366#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 79365#L1110-3 assume !(0 == ~T5_E~0); 79364#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 79363#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 79362#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 79361#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 79360#L1135-3 assume !(0 == ~T10_E~0); 79359#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 79358#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 79357#L1150-3 assume !(0 == ~E_2~0); 79356#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 79355#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 79354#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 79353#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 79352#L1175-3 assume !(0 == ~E_7~0); 79351#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 79350#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 79349#L1190-3 assume !(0 == ~E_10~0); 79348#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 79347#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 79346#L525-36 assume !(1 == ~m_pc~0); 79345#L525-38 is_master_triggered_~__retres1~0#1 := 0; 69269#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69270#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 69556#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 69557#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69467#L544-36 assume !(1 == ~t1_pc~0); 69468#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 70003#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 69355#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 69356#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 70363#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 70244#L563-36 assume 1 == ~t2_pc~0; 69253#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 69010#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 69011#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 70101#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 69745#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 69746#L582-36 assume !(1 == ~t3_pc~0); 70266#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 69823#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 69824#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 69994#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 69783#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 69725#L601-36 assume 1 == ~t4_pc~0; 69621#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 69622#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 70466#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 70346#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 70347#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 70230#L620-36 assume 1 == ~t5_pc~0; 69666#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 69667#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 70076#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 69649#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 69275#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 69056#L639-36 assume 1 == ~t6_pc~0; 69057#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 69096#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 69097#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 69330#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 69331#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 69925#L658-36 assume !(1 == ~t7_pc~0); 69064#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 69065#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 70321#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 69043#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 69044#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 70057#L677-36 assume 1 == ~t8_pc~0; 70258#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 69850#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 69971#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 70427#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 69874#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 69875#L696-36 assume !(1 == ~t9_pc~0); 69765#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 69766#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 69113#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 69114#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 69887#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 69888#L715-36 assume !(1 == ~t10_pc~0); 69858#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 68942#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 68943#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 68918#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 68919#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 69317#L734-36 assume 1 == ~t11_pc~0; 69318#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 69020#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 69342#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 68936#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 68937#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 70383#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 69608#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 69609#L1218-3 assume !(1 == ~T2_E~0); 69372#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 69373#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 69564#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 69565#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 69819#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 69820#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 79128#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 70350#L1258-3 assume !(1 == ~T10_E~0); 69351#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 69352#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 70323#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 70324#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 70325#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 70326#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 70474#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 70475#L1298-3 assume !(1 == ~E_7~0); 70407#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 70408#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 69551#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 69552#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 69353#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 69354#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 69716#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 69717#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 70516#L1663 assume !(0 == start_simulation_~tmp~3#1); 69184#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 77193#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 77187#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 77185#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 77183#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 77180#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 77181#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 77154#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 69443#L1644-2 [2022-07-23 15:32:30,938 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:30,938 INFO L85 PathProgramCache]: Analyzing trace with hash 919650235, now seen corresponding path program 1 times [2022-07-23 15:32:30,938 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:30,938 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1079624294] [2022-07-23 15:32:30,938 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:30,939 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:30,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:30,967 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:30,967 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:30,967 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1079624294] [2022-07-23 15:32:30,967 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1079624294] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:30,967 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:30,967 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-23 15:32:30,967 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1872305852] [2022-07-23 15:32:30,967 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:30,968 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-23 15:32:30,968 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:30,968 INFO L85 PathProgramCache]: Analyzing trace with hash 130127491, now seen corresponding path program 1 times [2022-07-23 15:32:30,968 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:30,968 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [344518354] [2022-07-23 15:32:30,968 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:30,968 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:31,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:31,040 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:31,040 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:31,040 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [344518354] [2022-07-23 15:32:31,040 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [344518354] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:31,040 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:31,040 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-23 15:32:31,040 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1922639663] [2022-07-23 15:32:31,041 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:31,041 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-23 15:32:31,041 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-23 15:32:31,041 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-23 15:32:31,041 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-23 15:32:31,041 INFO L87 Difference]: Start difference. First operand 10528 states and 15003 transitions. cyclomatic complexity: 4479 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:31,142 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-23 15:32:31,143 INFO L93 Difference]: Finished difference Result 20040 states and 28450 transitions. [2022-07-23 15:32:31,143 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-23 15:32:31,143 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20040 states and 28450 transitions. [2022-07-23 15:32:31,224 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 19847 [2022-07-23 15:32:31,280 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20040 states to 20040 states and 28450 transitions. [2022-07-23 15:32:31,281 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20040 [2022-07-23 15:32:31,298 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20040 [2022-07-23 15:32:31,298 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20040 states and 28450 transitions. [2022-07-23 15:32:31,316 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-23 15:32:31,316 INFO L369 hiAutomatonCegarLoop]: Abstraction has 20040 states and 28450 transitions. [2022-07-23 15:32:31,329 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20040 states and 28450 transitions. [2022-07-23 15:32:31,492 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20040 to 20022. [2022-07-23 15:32:31,517 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20022 states, 20022 states have (on average 1.4200379582459295) internal successors, (28432), 20021 states have internal predecessors, (28432), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:31,554 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20022 states to 20022 states and 28432 transitions. [2022-07-23 15:32:31,554 INFO L392 hiAutomatonCegarLoop]: Abstraction has 20022 states and 28432 transitions. [2022-07-23 15:32:31,554 INFO L374 stractBuchiCegarLoop]: Abstraction has 20022 states and 28432 transitions. [2022-07-23 15:32:31,554 INFO L287 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-07-23 15:32:31,554 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20022 states and 28432 transitions. [2022-07-23 15:32:31,660 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 19829 [2022-07-23 15:32:31,661 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-23 15:32:31,661 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-23 15:32:31,662 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:31,662 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:31,662 INFO L752 eck$LassoCheckResult]: Stem: 100670#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 100671#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 100681#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 100682#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 100413#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 100414#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 100273#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 100181#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 99894#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 99531#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 99532#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 99581#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 99582#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 100548#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 100549#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 100590#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 100000#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 100001#L1090 assume !(0 == ~M_E~0); 100045#L1090-2 assume !(0 == ~T1_E~0); 100046#L1095-1 assume !(0 == ~T2_E~0); 100752#L1100-1 assume !(0 == ~T3_E~0); 100753#L1105-1 assume !(0 == ~T4_E~0); 99809#L1110-1 assume !(0 == ~T5_E~0); 99810#L1115-1 assume !(0 == ~T6_E~0); 100220#L1120-1 assume !(0 == ~T7_E~0); 100521#L1125-1 assume !(0 == ~T8_E~0); 101171#L1130-1 assume !(0 == ~T9_E~0); 100776#L1135-1 assume !(0 == ~T10_E~0); 100005#L1140-1 assume !(0 == ~T11_E~0); 100006#L1145-1 assume !(0 == ~E_1~0); 100700#L1150-1 assume !(0 == ~E_2~0); 100194#L1155-1 assume !(0 == ~E_3~0); 100195#L1160-1 assume !(0 == ~E_4~0); 100283#L1165-1 assume !(0 == ~E_5~0); 100284#L1170-1 assume !(0 == ~E_6~0); 101017#L1175-1 assume !(0 == ~E_7~0); 100366#L1180-1 assume !(0 == ~E_8~0); 100367#L1185-1 assume !(0 == ~E_9~0); 100002#L1190-1 assume !(0 == ~E_10~0); 100003#L1195-1 assume !(0 == ~E_11~0); 100381#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 100210#L525 assume !(1 == ~m_pc~0); 99619#L525-2 is_master_triggered_~__retres1~0#1 := 0; 99620#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 100385#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 100386#L1350 assume !(0 != activate_threads_~tmp~1#1); 99988#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 99989#L544 assume !(1 == ~t1_pc~0); 100218#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 100219#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 100697#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 99832#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 99833#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 100486#L563 assume !(1 == ~t2_pc~0); 100683#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 99640#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 99641#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 100075#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 100076#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 100572#L582 assume !(1 == ~t3_pc~0); 100698#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 101099#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 101100#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 101029#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 99712#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 99713#L601 assume !(1 == ~t4_pc~0); 100716#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 100221#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 100222#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 100710#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 100711#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 101089#L620 assume !(1 == ~t5_pc~0); 100538#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 100539#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 100517#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 100518#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 101123#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 101124#L639 assume !(1 == ~t6_pc~0); 100519#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 100113#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 100114#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 101032#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 100228#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 100229#L658 assume !(1 == ~t7_pc~0); 100435#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 100436#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 100559#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 100560#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 99995#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 99996#L677 assume 1 == ~t8_pc~0; 100232#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 99790#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 99791#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 100071#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 100072#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 100825#L696 assume !(1 == ~t9_pc~0); 100498#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 100499#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 100601#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 100525#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 100526#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 100757#L715 assume 1 == ~t10_pc~0; 100764#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 100620#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 100489#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 100490#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 100357#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 99782#L734 assume !(1 == ~t11_pc~0); 99783#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 100287#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 100372#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 99519#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 99520#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 100589#L1213 assume !(1 == ~M_E~0); 100354#L1213-2 assume !(1 == ~T1_E~0); 100355#L1218-1 assume !(1 == ~T2_E~0); 99556#L1223-1 assume !(1 == ~T3_E~0); 99557#L1228-1 assume !(1 == ~T4_E~0); 100334#L1233-1 assume !(1 == ~T5_E~0); 101125#L1238-1 assume !(1 == ~T6_E~0); 100708#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 100709#L1248-1 assume !(1 == ~T8_E~0); 100762#L1253-1 assume !(1 == ~T9_E~0); 100763#L1258-1 assume !(1 == ~T10_E~0); 100738#L1263-1 assume !(1 == ~T11_E~0); 100739#L1268-1 assume !(1 == ~E_1~0); 100546#L1273-1 assume !(1 == ~E_2~0); 100547#L1278-1 assume !(1 == ~E_3~0); 100111#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 100112#L1288-1 assume !(1 == ~E_5~0); 100880#L1293-1 assume !(1 == ~E_6~0); 100831#L1298-1 assume !(1 == ~E_7~0); 100575#L1303-1 assume !(1 == ~E_8~0); 100122#L1308-1 assume !(1 == ~E_9~0); 100011#L1313-1 assume !(1 == ~E_10~0); 100012#L1318-1 assume !(1 == ~E_11~0); 100021#L1323-1 assume { :end_inline_reset_delta_events } true; 100022#L1644-2 [2022-07-23 15:32:31,662 INFO L754 eck$LassoCheckResult]: Loop: 100022#L1644-2 assume !false; 113354#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 113348#L1065 assume !false; 112146#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 108023#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 108013#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 107998#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 107992#L906 assume !(0 != eval_~tmp~0#1); 100827#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 100828#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 100913#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 100914#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 100982#L1095-3 assume !(0 == ~T2_E~0); 101182#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 101118#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 101119#L1110-3 assume !(0 == ~T5_E~0); 101020#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 101021#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 117368#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 117365#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 117363#L1135-3 assume !(0 == ~T10_E~0); 115121#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 115111#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 115103#L1150-3 assume !(0 == ~E_2~0); 115095#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 115089#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 115081#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 115073#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 115068#L1175-3 assume !(0 == ~E_7~0); 114703#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 114702#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 114701#L1190-3 assume !(0 == ~E_10~0); 114700#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 114695#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 114691#L525-36 assume !(1 == ~m_pc~0); 114687#L525-38 is_master_triggered_~__retres1~0#1 := 0; 114682#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 114676#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 114669#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 114663#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 114657#L544-36 assume !(1 == ~t1_pc~0); 114652#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 114646#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 114640#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 114634#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 114629#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 114622#L563-36 assume 1 == ~t2_pc~0; 114617#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 114611#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 114605#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 114599#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 114594#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 114589#L582-36 assume !(1 == ~t3_pc~0); 114584#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 114579#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 114574#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 114569#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 114564#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 114557#L601-36 assume !(1 == ~t4_pc~0); 114551#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 114545#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 114538#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 114531#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 114525#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 114519#L620-36 assume !(1 == ~t5_pc~0); 114513#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 114507#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 114499#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 113721#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 113720#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 113719#L639-36 assume !(1 == ~t6_pc~0); 113717#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 113716#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 113715#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 113714#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 113713#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 113712#L658-36 assume !(1 == ~t7_pc~0); 113710#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 113709#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 113708#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 113707#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 113706#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 113705#L677-36 assume 1 == ~t8_pc~0; 113703#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 113702#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 113701#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 113699#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 113697#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 113695#L696-36 assume 1 == ~t9_pc~0; 113693#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 113690#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 113688#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 113686#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 113684#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 113682#L715-36 assume !(1 == ~t10_pc~0); 113680#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 113677#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 113675#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 113673#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 113670#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 113668#L734-36 assume !(1 == ~t11_pc~0); 113665#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 113663#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 113661#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 113659#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 113657#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 113655#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 113653#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 113651#L1218-3 assume !(1 == ~T2_E~0); 113649#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 113647#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 113644#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 113642#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 113640#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 113638#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 113636#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 113634#L1258-3 assume !(1 == ~T10_E~0); 113632#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 113630#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 113628#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 113626#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 113624#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 113622#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 113619#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 113617#L1298-3 assume !(1 == ~E_7~0); 113615#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 113613#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 113611#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 113608#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 113606#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 113604#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 113591#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 113589#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 113586#L1663 assume !(0 == start_simulation_~tmp~3#1); 113583#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 113374#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 113369#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 113366#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 113364#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 113362#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 113360#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 113358#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 100022#L1644-2 [2022-07-23 15:32:31,663 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:31,663 INFO L85 PathProgramCache]: Analyzing trace with hash -258324326, now seen corresponding path program 1 times [2022-07-23 15:32:31,663 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:31,663 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1154718484] [2022-07-23 15:32:31,663 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:31,663 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:31,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:31,685 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:31,686 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:31,686 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1154718484] [2022-07-23 15:32:31,686 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1154718484] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:31,686 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:31,686 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-23 15:32:31,686 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1193920212] [2022-07-23 15:32:31,686 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:31,686 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-23 15:32:31,686 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:31,687 INFO L85 PathProgramCache]: Analyzing trace with hash -50695136, now seen corresponding path program 1 times [2022-07-23 15:32:31,687 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:31,687 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [400226198] [2022-07-23 15:32:31,687 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:31,687 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:31,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:31,708 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:31,708 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:31,708 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [400226198] [2022-07-23 15:32:31,708 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [400226198] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:31,709 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:31,709 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-23 15:32:31,709 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1312328154] [2022-07-23 15:32:31,709 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:31,709 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-23 15:32:31,709 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-23 15:32:31,709 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-23 15:32:31,709 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-23 15:32:31,709 INFO L87 Difference]: Start difference. First operand 20022 states and 28432 transitions. cyclomatic complexity: 8418 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:31,869 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-23 15:32:31,869 INFO L93 Difference]: Finished difference Result 38178 states and 54029 transitions. [2022-07-23 15:32:31,869 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-23 15:32:31,870 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 38178 states and 54029 transitions. [2022-07-23 15:32:32,012 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 37902 [2022-07-23 15:32:32,125 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 38178 states to 38178 states and 54029 transitions. [2022-07-23 15:32:32,125 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 38178 [2022-07-23 15:32:32,376 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 38178 [2022-07-23 15:32:32,377 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38178 states and 54029 transitions. [2022-07-23 15:32:32,393 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-23 15:32:32,394 INFO L369 hiAutomatonCegarLoop]: Abstraction has 38178 states and 54029 transitions. [2022-07-23 15:32:32,414 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38178 states and 54029 transitions. [2022-07-23 15:32:32,767 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38178 to 38142. [2022-07-23 15:32:32,806 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38142 states, 38142 states have (on average 1.415578627235069) internal successors, (53993), 38141 states have internal predecessors, (53993), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:32,868 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38142 states to 38142 states and 53993 transitions. [2022-07-23 15:32:32,868 INFO L392 hiAutomatonCegarLoop]: Abstraction has 38142 states and 53993 transitions. [2022-07-23 15:32:32,868 INFO L374 stractBuchiCegarLoop]: Abstraction has 38142 states and 53993 transitions. [2022-07-23 15:32:32,868 INFO L287 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-07-23 15:32:32,868 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38142 states and 53993 transitions. [2022-07-23 15:32:32,985 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 37866 [2022-07-23 15:32:32,985 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-23 15:32:32,986 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-23 15:32:32,987 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:32,987 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:32,987 INFO L752 eck$LassoCheckResult]: Stem: 158860#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 158861#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 158870#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 158871#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 158607#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 158608#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 158475#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 158386#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 158103#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 157740#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 157741#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 157789#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 157790#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 158745#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 158746#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 158792#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 158209#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 158210#L1090 assume !(0 == ~M_E~0); 158256#L1090-2 assume !(0 == ~T1_E~0); 158257#L1095-1 assume !(0 == ~T2_E~0); 158938#L1100-1 assume !(0 == ~T3_E~0); 158939#L1105-1 assume !(0 == ~T4_E~0); 158020#L1110-1 assume !(0 == ~T5_E~0); 158021#L1115-1 assume !(0 == ~T6_E~0); 158426#L1120-1 assume !(0 == ~T7_E~0); 158716#L1125-1 assume !(0 == ~T8_E~0); 159320#L1130-1 assume !(0 == ~T9_E~0); 158961#L1135-1 assume !(0 == ~T10_E~0); 158214#L1140-1 assume !(0 == ~T11_E~0); 158215#L1145-1 assume !(0 == ~E_1~0); 158887#L1150-1 assume !(0 == ~E_2~0); 158400#L1155-1 assume !(0 == ~E_3~0); 158401#L1160-1 assume !(0 == ~E_4~0); 158483#L1165-1 assume !(0 == ~E_5~0); 158484#L1170-1 assume !(0 == ~E_6~0); 159174#L1175-1 assume !(0 == ~E_7~0); 158561#L1180-1 assume !(0 == ~E_8~0); 158562#L1185-1 assume !(0 == ~E_9~0); 158211#L1190-1 assume !(0 == ~E_10~0); 158212#L1195-1 assume !(0 == ~E_11~0); 158575#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 158421#L525 assume !(1 == ~m_pc~0); 157826#L525-2 is_master_triggered_~__retres1~0#1 := 0; 157827#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 158579#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 158580#L1350 assume !(0 != activate_threads_~tmp~1#1); 158199#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 158200#L544 assume !(1 == ~t1_pc~0); 158422#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 158423#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 158884#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 158041#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 158042#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 158683#L563 assume !(1 == ~t2_pc~0); 158872#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 157850#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 157851#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 158283#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 158284#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 158769#L582 assume !(1 == ~t3_pc~0); 158885#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 159258#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 159259#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 159184#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 157921#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 157922#L601 assume !(1 == ~t4_pc~0); 158905#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 158427#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 158428#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 158899#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 158900#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 159245#L620 assume !(1 == ~t5_pc~0); 158736#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 158737#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 158712#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 158713#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 159275#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 159276#L639 assume !(1 == ~t6_pc~0); 158714#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 158319#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 158320#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 159188#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 158432#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 158433#L658 assume !(1 == ~t7_pc~0); 158632#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 158633#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 158754#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 158755#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 158205#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 158206#L677 assume !(1 == ~t8_pc~0); 158231#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 158006#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 158007#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 158277#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 158278#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 159003#L696 assume !(1 == ~t9_pc~0); 158699#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 158700#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 158800#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 158722#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 158723#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 158942#L715 assume 1 == ~t10_pc~0; 158948#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 158815#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 158686#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 158687#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 158552#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 157994#L734 assume !(1 == ~t11_pc~0); 157995#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 158490#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 158566#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 157730#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 157731#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 158785#L1213 assume !(1 == ~M_E~0); 158550#L1213-2 assume !(1 == ~T1_E~0); 158551#L1218-1 assume !(1 == ~T2_E~0); 157765#L1223-1 assume !(1 == ~T3_E~0); 157766#L1228-1 assume !(1 == ~T4_E~0); 158530#L1233-1 assume !(1 == ~T5_E~0); 159277#L1238-1 assume !(1 == ~T6_E~0); 158897#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 158898#L1248-1 assume !(1 == ~T8_E~0); 158946#L1253-1 assume !(1 == ~T9_E~0); 158947#L1258-1 assume !(1 == ~T10_E~0); 158922#L1263-1 assume !(1 == ~T11_E~0); 158923#L1268-1 assume !(1 == ~E_1~0); 158741#L1273-1 assume !(1 == ~E_2~0); 158742#L1278-1 assume !(1 == ~E_3~0); 158317#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 158318#L1288-1 assume !(1 == ~E_5~0); 159055#L1293-1 assume !(1 == ~E_6~0); 159012#L1298-1 assume !(1 == ~E_7~0); 158772#L1303-1 assume !(1 == ~E_8~0); 158328#L1308-1 assume !(1 == ~E_9~0); 158222#L1313-1 assume !(1 == ~E_10~0); 158223#L1318-1 assume !(1 == ~E_11~0); 158232#L1323-1 assume { :end_inline_reset_delta_events } true; 158233#L1644-2 [2022-07-23 15:32:32,988 INFO L754 eck$LassoCheckResult]: Loop: 158233#L1644-2 assume !false; 174815#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 174809#L1065 assume !false; 174807#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 174800#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 174787#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 174783#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 174778#L906 assume !(0 != eval_~tmp~0#1); 174779#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 176237#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 176236#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 176235#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 176234#L1095-3 assume !(0 == ~T2_E~0); 176233#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 176232#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 176231#L1110-3 assume !(0 == ~T5_E~0); 176230#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 176229#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 176228#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 176227#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 176226#L1135-3 assume !(0 == ~T10_E~0); 176225#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 176224#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 176223#L1150-3 assume !(0 == ~E_2~0); 176222#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 176221#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 176220#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 176219#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 176218#L1175-3 assume !(0 == ~E_7~0); 176217#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 176216#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 176215#L1190-3 assume !(0 == ~E_10~0); 176214#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 176213#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 176212#L525-36 assume !(1 == ~m_pc~0); 176211#L525-38 is_master_triggered_~__retres1~0#1 := 0; 176210#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 176209#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 176208#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 176207#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 176206#L544-36 assume !(1 == ~t1_pc~0); 176205#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 176204#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 176203#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 176202#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 176201#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 176200#L563-36 assume !(1 == ~t2_pc~0); 176198#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 176197#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 176196#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 176195#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 176194#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 176193#L582-36 assume !(1 == ~t3_pc~0); 176192#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 176191#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 176190#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 176189#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 176188#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 176187#L601-36 assume 1 == ~t4_pc~0; 176186#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 176184#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 176182#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 176180#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 176178#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 176175#L620-36 assume !(1 == ~t5_pc~0); 176172#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 176169#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 176166#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 176162#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 176159#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 176156#L639-36 assume !(1 == ~t6_pc~0); 176152#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 176149#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 176146#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 176143#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 176140#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 176137#L658-36 assume !(1 == ~t7_pc~0); 176132#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 176129#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 176125#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 176119#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 176111#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 176102#L677-36 assume !(1 == ~t8_pc~0); 176093#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 176085#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 176076#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 176024#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 176023#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 176022#L696-36 assume !(1 == ~t9_pc~0); 176018#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 176016#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 176014#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 176012#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 176010#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 176008#L715-36 assume !(1 == ~t10_pc~0); 176006#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 176004#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 175997#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 175989#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 175982#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 175976#L734-36 assume !(1 == ~t11_pc~0); 175968#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 175961#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 175951#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 175943#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 175935#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 175927#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 175919#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 175910#L1218-3 assume !(1 == ~T2_E~0); 175904#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 175895#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 175886#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 175879#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 175852#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 175823#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 175817#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 175810#L1258-3 assume !(1 == ~T10_E~0); 175802#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 175795#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 175787#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 175781#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 175774#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 175766#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 175758#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 175750#L1298-3 assume !(1 == ~E_7~0); 175742#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 175734#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 175727#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 175718#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 175713#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 174875#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 174862#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 174860#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 174857#L1663 assume !(0 == start_simulation_~tmp~3#1); 174854#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 174834#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 174828#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 174826#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 174824#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 174822#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 174820#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 174818#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 158233#L1644-2 [2022-07-23 15:32:32,988 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:32,988 INFO L85 PathProgramCache]: Analyzing trace with hash 1174510393, now seen corresponding path program 1 times [2022-07-23 15:32:32,989 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:32,989 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1663603767] [2022-07-23 15:32:32,989 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:32,989 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:33,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:33,132 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:33,132 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:33,132 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1663603767] [2022-07-23 15:32:33,132 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1663603767] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:33,132 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:33,132 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-23 15:32:33,132 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1999855179] [2022-07-23 15:32:33,132 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:33,133 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-23 15:32:33,133 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:33,133 INFO L85 PathProgramCache]: Analyzing trace with hash -1043875554, now seen corresponding path program 1 times [2022-07-23 15:32:33,133 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:33,133 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1556364943] [2022-07-23 15:32:33,133 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:33,133 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:33,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:33,160 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:33,160 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:33,160 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1556364943] [2022-07-23 15:32:33,160 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1556364943] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:33,160 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:33,160 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-23 15:32:33,160 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1638760075] [2022-07-23 15:32:33,160 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:33,160 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-23 15:32:33,161 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-23 15:32:33,161 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-07-23 15:32:33,161 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-07-23 15:32:33,161 INFO L87 Difference]: Start difference. First operand 38142 states and 53993 transitions. cyclomatic complexity: 15867 Second operand has 5 states, 5 states have (on average 27.4) internal successors, (137), 5 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:33,737 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-23 15:32:33,738 INFO L93 Difference]: Finished difference Result 88469 states and 126442 transitions. [2022-07-23 15:32:33,738 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-07-23 15:32:33,739 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 88469 states and 126442 transitions. [2022-07-23 15:32:34,107 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 87860 [2022-07-23 15:32:34,316 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 88469 states to 88469 states and 126442 transitions. [2022-07-23 15:32:34,316 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 88469 [2022-07-23 15:32:34,357 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 88469 [2022-07-23 15:32:34,357 INFO L73 IsDeterministic]: Start isDeterministic. Operand 88469 states and 126442 transitions. [2022-07-23 15:32:34,512 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-23 15:32:34,512 INFO L369 hiAutomatonCegarLoop]: Abstraction has 88469 states and 126442 transitions. [2022-07-23 15:32:34,549 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88469 states and 126442 transitions. [2022-07-23 15:32:35,085 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88469 to 39237. [2022-07-23 15:32:35,116 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39237 states, 39237 states have (on average 1.4039809363610878) internal successors, (55088), 39236 states have internal predecessors, (55088), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:35,182 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39237 states to 39237 states and 55088 transitions. [2022-07-23 15:32:35,183 INFO L392 hiAutomatonCegarLoop]: Abstraction has 39237 states and 55088 transitions. [2022-07-23 15:32:35,183 INFO L374 stractBuchiCegarLoop]: Abstraction has 39237 states and 55088 transitions. [2022-07-23 15:32:35,183 INFO L287 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-07-23 15:32:35,184 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39237 states and 55088 transitions. [2022-07-23 15:32:35,273 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 38958 [2022-07-23 15:32:35,274 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-23 15:32:35,274 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-23 15:32:35,276 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:35,276 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:35,276 INFO L752 eck$LassoCheckResult]: Stem: 285496#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 285497#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 285506#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 285507#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 285244#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 285245#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 285105#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 285018#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 284729#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 284366#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 284367#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 284415#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 284416#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 285378#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 285379#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 285426#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 284837#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 284838#L1090 assume !(0 == ~M_E~0); 284886#L1090-2 assume !(0 == ~T1_E~0); 284887#L1095-1 assume !(0 == ~T2_E~0); 285582#L1100-1 assume !(0 == ~T3_E~0); 285583#L1105-1 assume !(0 == ~T4_E~0); 284645#L1110-1 assume !(0 == ~T5_E~0); 284646#L1115-1 assume !(0 == ~T6_E~0); 285057#L1120-1 assume !(0 == ~T7_E~0); 285350#L1125-1 assume !(0 == ~T8_E~0); 285971#L1130-1 assume !(0 == ~T9_E~0); 285607#L1135-1 assume !(0 == ~T10_E~0); 284842#L1140-1 assume !(0 == ~T11_E~0); 284843#L1145-1 assume !(0 == ~E_1~0); 285527#L1150-1 assume !(0 == ~E_2~0); 285031#L1155-1 assume !(0 == ~E_3~0); 285032#L1160-1 assume !(0 == ~E_4~0); 285113#L1165-1 assume !(0 == ~E_5~0); 285114#L1170-1 assume !(0 == ~E_6~0); 285823#L1175-1 assume !(0 == ~E_7~0); 285194#L1180-1 assume !(0 == ~E_8~0); 285195#L1185-1 assume !(0 == ~E_9~0); 284839#L1190-1 assume !(0 == ~E_10~0); 284840#L1195-1 assume !(0 == ~E_11~0); 285210#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 285045#L525 assume !(1 == ~m_pc~0); 284452#L525-2 is_master_triggered_~__retres1~0#1 := 0; 284453#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 285214#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 285215#L1350 assume !(0 != activate_threads_~tmp~1#1); 284827#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 284828#L544 assume !(1 == ~t1_pc~0); 285053#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 285054#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 285524#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 284667#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 284668#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 285320#L563 assume !(1 == ~t2_pc~0); 285508#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 284476#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 284477#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 284910#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 284911#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 285402#L582 assume !(1 == ~t3_pc~0); 285525#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 285907#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 285908#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 285833#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 284547#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 284548#L601 assume !(1 == ~t4_pc~0); 285547#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 285058#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 285059#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 285540#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 285541#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 285897#L620 assume !(1 == ~t5_pc~0); 285370#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 285371#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 285346#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 285347#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 285926#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 285927#L639 assume !(1 == ~t6_pc~0); 285348#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 284948#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 284949#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 285836#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 285063#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 285064#L658 assume !(1 == ~t7_pc~0); 285268#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 285269#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 285387#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 285388#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 284833#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 284834#L677 assume !(1 == ~t8_pc~0); 284858#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 284629#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 284630#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 284907#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 284908#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 285660#L696 assume !(1 == ~t9_pc~0); 285331#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 285332#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 285433#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 285355#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 285356#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 285587#L715 assume 1 == ~t10_pc~0; 285594#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 285451#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 285323#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 285324#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 285185#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 284618#L734 assume !(1 == ~t11_pc~0); 284619#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 285117#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 285200#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 284356#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 284357#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 285419#L1213 assume !(1 == ~M_E~0); 285182#L1213-2 assume !(1 == ~T1_E~0); 285183#L1218-1 assume !(1 == ~T2_E~0); 284391#L1223-1 assume !(1 == ~T3_E~0); 284392#L1228-1 assume !(1 == ~T4_E~0); 285161#L1233-1 assume !(1 == ~T5_E~0); 285928#L1238-1 assume !(1 == ~T6_E~0); 285538#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 285539#L1248-1 assume !(1 == ~T8_E~0); 285592#L1253-1 assume !(1 == ~T9_E~0); 285593#L1258-1 assume !(1 == ~T10_E~0); 285567#L1263-1 assume !(1 == ~T11_E~0); 285568#L1268-1 assume !(1 == ~E_1~0); 285375#L1273-1 assume !(1 == ~E_2~0); 285376#L1278-1 assume !(1 == ~E_3~0); 284946#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 284947#L1288-1 assume !(1 == ~E_5~0); 285709#L1293-1 assume !(1 == ~E_6~0); 285666#L1298-1 assume !(1 == ~E_7~0); 285405#L1303-1 assume !(1 == ~E_8~0); 284957#L1308-1 assume !(1 == ~E_9~0); 284850#L1313-1 assume !(1 == ~E_10~0); 284851#L1318-1 assume !(1 == ~E_11~0); 284859#L1323-1 assume { :end_inline_reset_delta_events } true; 284860#L1644-2 [2022-07-23 15:32:35,277 INFO L754 eck$LassoCheckResult]: Loop: 284860#L1644-2 assume !false; 302789#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 302784#L1065 assume !false; 302783#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 301615#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 301603#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 301602#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 301600#L906 assume !(0 != eval_~tmp~0#1); 301601#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 323523#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 323521#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 323519#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 323517#L1095-3 assume !(0 == ~T2_E~0); 323515#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 323513#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 323511#L1110-3 assume !(0 == ~T5_E~0); 323502#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 323281#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 323280#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 323278#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 323162#L1135-3 assume !(0 == ~T10_E~0); 323157#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 323153#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 323148#L1150-3 assume !(0 == ~E_2~0); 323144#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 323140#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 323136#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 323132#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 323128#L1175-3 assume !(0 == ~E_7~0); 323123#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 323118#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 323114#L1190-3 assume !(0 == ~E_10~0); 323110#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 323106#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 323105#L525-36 assume !(1 == ~m_pc~0); 323104#L525-38 is_master_triggered_~__retres1~0#1 := 0; 323103#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 323102#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 323101#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 323100#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 323099#L544-36 assume !(1 == ~t1_pc~0); 323098#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 323097#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 323096#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 323095#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 323094#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 323093#L563-36 assume 1 == ~t2_pc~0; 323092#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 323090#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 323089#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 323088#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 323087#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 323086#L582-36 assume !(1 == ~t3_pc~0); 323085#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 323084#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 323083#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 323082#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 323081#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 323080#L601-36 assume !(1 == ~t4_pc~0); 323078#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 323077#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 323076#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 323075#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 323074#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 323073#L620-36 assume !(1 == ~t5_pc~0); 323072#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 323071#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 323070#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 323069#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 323068#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 323067#L639-36 assume !(1 == ~t6_pc~0); 323065#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 323064#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 323063#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 323062#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 323061#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 323060#L658-36 assume !(1 == ~t7_pc~0); 323058#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 323057#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 323056#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 323055#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 323054#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 323053#L677-36 assume !(1 == ~t8_pc~0); 323052#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 323049#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 323046#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 323036#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 323031#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 323030#L696-36 assume 1 == ~t9_pc~0; 323028#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 323026#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 323024#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 323022#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 323020#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 323018#L715-36 assume 1 == ~t10_pc~0; 323015#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 323013#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 322667#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 322666#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 322665#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 322664#L734-36 assume !(1 == ~t11_pc~0); 322662#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 322661#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 322660#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 322658#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 322656#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 322654#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 322652#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 322649#L1218-3 assume !(1 == ~T2_E~0); 322647#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 322645#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 322643#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 322641#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 322638#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 322636#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 322634#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 322617#L1258-3 assume !(1 == ~T10_E~0); 322615#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 322613#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 322610#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 322608#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 322606#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 322604#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 322603#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 284969#L1298-3 assume !(1 == ~E_7~0); 284970#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 285461#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 284967#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 284968#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 284764#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 284765#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 317320#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 317307#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 317304#L1663 assume !(0 == start_simulation_~tmp~3#1); 317301#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 302809#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 302803#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 302801#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 302799#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 302797#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 302794#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 302792#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 284860#L1644-2 [2022-07-23 15:32:35,277 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:35,280 INFO L85 PathProgramCache]: Analyzing trace with hash 145151095, now seen corresponding path program 1 times [2022-07-23 15:32:35,280 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:35,280 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [33126681] [2022-07-23 15:32:35,280 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:35,281 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:35,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:35,311 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:35,312 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:35,312 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [33126681] [2022-07-23 15:32:35,312 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [33126681] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:35,312 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:35,312 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-23 15:32:35,312 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [889458114] [2022-07-23 15:32:35,312 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:35,313 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-23 15:32:35,313 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:35,313 INFO L85 PathProgramCache]: Analyzing trace with hash 904953248, now seen corresponding path program 1 times [2022-07-23 15:32:35,313 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:35,313 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [712575833] [2022-07-23 15:32:35,313 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:35,314 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:35,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:35,339 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:35,339 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:35,339 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [712575833] [2022-07-23 15:32:35,339 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [712575833] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:35,340 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:35,340 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-23 15:32:35,340 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1101137221] [2022-07-23 15:32:35,340 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:35,340 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-23 15:32:35,341 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-23 15:32:35,341 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-23 15:32:35,341 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-23 15:32:35,341 INFO L87 Difference]: Start difference. First operand 39237 states and 55088 transitions. cyclomatic complexity: 15867 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:36,076 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-23 15:32:36,077 INFO L93 Difference]: Finished difference Result 110204 states and 153821 transitions. [2022-07-23 15:32:36,077 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-23 15:32:36,077 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 110204 states and 153821 transitions. [2022-07-23 15:32:36,791 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 108078 [2022-07-23 15:32:37,055 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 110204 states to 110204 states and 153821 transitions. [2022-07-23 15:32:37,055 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 110204 [2022-07-23 15:32:37,111 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 110204 [2022-07-23 15:32:37,112 INFO L73 IsDeterministic]: Start isDeterministic. Operand 110204 states and 153821 transitions. [2022-07-23 15:32:37,168 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-23 15:32:37,168 INFO L369 hiAutomatonCegarLoop]: Abstraction has 110204 states and 153821 transitions. [2022-07-23 15:32:37,220 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 110204 states and 153821 transitions. [2022-07-23 15:32:38,236 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 110204 to 108040. [2022-07-23 15:32:38,322 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 108040 states, 108040 states have (on average 1.397972972972973) internal successors, (151037), 108039 states have internal predecessors, (151037), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:38,830 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108040 states to 108040 states and 151037 transitions. [2022-07-23 15:32:38,831 INFO L392 hiAutomatonCegarLoop]: Abstraction has 108040 states and 151037 transitions. [2022-07-23 15:32:38,831 INFO L374 stractBuchiCegarLoop]: Abstraction has 108040 states and 151037 transitions. [2022-07-23 15:32:38,831 INFO L287 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-07-23 15:32:38,831 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 108040 states and 151037 transitions. [2022-07-23 15:32:39,106 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 107538 [2022-07-23 15:32:39,107 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-23 15:32:39,107 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-23 15:32:39,108 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:39,108 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:39,108 INFO L752 eck$LassoCheckResult]: Stem: 434981#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 434982#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 434990#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 434991#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 434709#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 434710#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 434570#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 434475#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 434180#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 433819#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 433820#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 433869#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 433870#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 434850#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 434851#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 434896#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 434286#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 434287#L1090 assume !(0 == ~M_E~0); 434331#L1090-2 assume !(0 == ~T1_E~0); 434332#L1095-1 assume !(0 == ~T2_E~0); 435061#L1100-1 assume !(0 == ~T3_E~0); 435062#L1105-1 assume !(0 == ~T4_E~0); 434097#L1110-1 assume !(0 == ~T5_E~0); 434098#L1115-1 assume !(0 == ~T6_E~0); 434517#L1120-1 assume !(0 == ~T7_E~0); 434823#L1125-1 assume !(0 == ~T8_E~0); 435510#L1130-1 assume !(0 == ~T9_E~0); 435087#L1135-1 assume !(0 == ~T10_E~0); 434292#L1140-1 assume !(0 == ~T11_E~0); 434293#L1145-1 assume !(0 == ~E_1~0); 435007#L1150-1 assume !(0 == ~E_2~0); 434491#L1155-1 assume !(0 == ~E_3~0); 434492#L1160-1 assume !(0 == ~E_4~0); 434578#L1165-1 assume !(0 == ~E_5~0); 434579#L1170-1 assume !(0 == ~E_6~0); 435333#L1175-1 assume !(0 == ~E_7~0); 434660#L1180-1 assume !(0 == ~E_8~0); 434661#L1185-1 assume !(0 == ~E_9~0); 434288#L1190-1 assume !(0 == ~E_10~0); 434289#L1195-1 assume !(0 == ~E_11~0); 434675#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 434507#L525 assume !(1 == ~m_pc~0); 433907#L525-2 is_master_triggered_~__retres1~0#1 := 0; 433908#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 434678#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 434679#L1350 assume !(0 != activate_threads_~tmp~1#1); 434274#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 434275#L544 assume !(1 == ~t1_pc~0); 434515#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 434516#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 435004#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 434120#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 434121#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 434788#L563 assume !(1 == ~t2_pc~0); 434992#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 433928#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 433929#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 434364#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 434365#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 434877#L582 assume !(1 == ~t3_pc~0); 435005#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 435436#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 435437#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 435348#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 434000#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 434001#L601 assume !(1 == ~t4_pc~0); 435026#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 434518#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 434519#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 435019#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 435020#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 435419#L620 assume !(1 == ~t5_pc~0); 434840#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 434841#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 434819#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 434820#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 435459#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 435460#L639 assume !(1 == ~t6_pc~0); 434821#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 434405#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 434406#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 435354#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 434525#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 434526#L658 assume !(1 == ~t7_pc~0); 434730#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 434731#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 434863#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 434864#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 434282#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 434283#L677 assume !(1 == ~t8_pc~0); 434307#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 434078#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 434079#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 434360#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 434361#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 435138#L696 assume !(1 == ~t9_pc~0); 434799#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 434800#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 434909#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 434827#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 434828#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 435068#L715 assume !(1 == ~t10_pc~0); 435374#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 434927#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 434791#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 434792#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 434651#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 434070#L734 assume !(1 == ~t11_pc~0); 434071#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 434582#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 434665#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 433807#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 433808#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 434895#L1213 assume !(1 == ~M_E~0); 434648#L1213-2 assume !(1 == ~T1_E~0); 434649#L1218-1 assume !(1 == ~T2_E~0); 433844#L1223-1 assume !(1 == ~T3_E~0); 433845#L1228-1 assume !(1 == ~T4_E~0); 434625#L1233-1 assume !(1 == ~T5_E~0); 435461#L1238-1 assume !(1 == ~T6_E~0); 435017#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 435018#L1248-1 assume !(1 == ~T8_E~0); 435072#L1253-1 assume !(1 == ~T9_E~0); 435073#L1258-1 assume !(1 == ~T10_E~0); 435047#L1263-1 assume !(1 == ~T11_E~0); 435048#L1268-1 assume !(1 == ~E_1~0); 434848#L1273-1 assume !(1 == ~E_2~0); 434849#L1278-1 assume !(1 == ~E_3~0); 434403#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 434404#L1288-1 assume !(1 == ~E_5~0); 435191#L1293-1 assume !(1 == ~E_6~0); 435143#L1298-1 assume !(1 == ~E_7~0); 434880#L1303-1 assume !(1 == ~E_8~0); 434416#L1308-1 assume !(1 == ~E_9~0); 434298#L1313-1 assume !(1 == ~E_10~0); 434299#L1318-1 assume !(1 == ~E_11~0); 434308#L1323-1 assume { :end_inline_reset_delta_events } true; 434309#L1644-2 [2022-07-23 15:32:39,109 INFO L754 eck$LassoCheckResult]: Loop: 434309#L1644-2 assume !false; 521490#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 521482#L1065 assume !false; 521478#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 521351#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 521340#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 521338#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 521335#L906 assume !(0 != eval_~tmp~0#1); 521336#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 522185#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 522184#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 522183#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 522182#L1095-3 assume !(0 == ~T2_E~0); 522181#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 522180#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 522179#L1110-3 assume !(0 == ~T5_E~0); 522178#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 522177#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 522176#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 522175#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 522174#L1135-3 assume !(0 == ~T10_E~0); 522173#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 522172#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 522171#L1150-3 assume !(0 == ~E_2~0); 522170#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 522169#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 522168#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 522167#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 522166#L1175-3 assume !(0 == ~E_7~0); 522165#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 522164#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 522163#L1190-3 assume !(0 == ~E_10~0); 522162#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 522161#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 522160#L525-36 assume !(1 == ~m_pc~0); 522159#L525-38 is_master_triggered_~__retres1~0#1 := 0; 522158#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 522157#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 522156#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 522155#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 522154#L544-36 assume !(1 == ~t1_pc~0); 522153#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 522152#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 522151#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 522150#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 522149#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 522148#L563-36 assume 1 == ~t2_pc~0; 522147#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 522145#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 522144#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 522143#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 522142#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 522141#L582-36 assume !(1 == ~t3_pc~0); 522140#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 522139#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 522138#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 522137#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 522136#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 522135#L601-36 assume 1 == ~t4_pc~0; 522134#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 522132#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 522131#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 522130#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 522129#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 522128#L620-36 assume !(1 == ~t5_pc~0); 522127#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 522126#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 522125#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 522124#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 522123#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 522122#L639-36 assume 1 == ~t6_pc~0; 522121#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 522119#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 522118#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 522117#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 522116#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 522114#L658-36 assume !(1 == ~t7_pc~0); 522111#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 522109#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 522107#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 522105#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 522103#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 522101#L677-36 assume !(1 == ~t8_pc~0); 522099#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 522097#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 522095#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 522093#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 522091#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 522089#L696-36 assume !(1 == ~t9_pc~0); 522086#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 522083#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 522080#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 522077#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 522073#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 522070#L715-36 assume !(1 == ~t10_pc~0); 522067#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 522062#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 522057#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 522052#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 522047#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 522042#L734-36 assume 1 == ~t11_pc~0; 522036#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 522030#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 522025#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 521738#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 521735#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 521733#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 521731#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 521729#L1218-3 assume !(1 == ~T2_E~0); 521727#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 521725#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 521723#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 521721#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 521719#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 521717#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 521715#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 521713#L1258-3 assume !(1 == ~T10_E~0); 521711#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 521709#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 521707#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 521705#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 521703#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 521701#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 521699#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 521697#L1298-3 assume !(1 == ~E_7~0); 521695#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 521693#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 521691#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 521689#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 521687#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 521685#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 521672#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 521670#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 521668#L1663 assume !(0 == start_simulation_~tmp~3#1); 521666#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 521584#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 521574#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 521567#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 521559#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 521549#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 521539#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 521509#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 434309#L1644-2 [2022-07-23 15:32:39,109 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:39,109 INFO L85 PathProgramCache]: Analyzing trace with hash -1619665514, now seen corresponding path program 1 times [2022-07-23 15:32:39,110 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:39,110 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [882786070] [2022-07-23 15:32:39,110 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:39,110 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:39,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:39,133 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:39,134 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:39,134 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [882786070] [2022-07-23 15:32:39,134 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [882786070] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:39,134 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:39,134 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-23 15:32:39,134 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1377101807] [2022-07-23 15:32:39,134 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:39,135 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-23 15:32:39,135 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:39,135 INFO L85 PathProgramCache]: Analyzing trace with hash 760377663, now seen corresponding path program 1 times [2022-07-23 15:32:39,135 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:39,135 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1922894017] [2022-07-23 15:32:39,135 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:39,136 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:39,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:39,157 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:39,158 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:39,158 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1922894017] [2022-07-23 15:32:39,158 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1922894017] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:39,158 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:39,158 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-23 15:32:39,158 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1170436837] [2022-07-23 15:32:39,159 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:39,159 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-23 15:32:39,159 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-23 15:32:39,159 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-23 15:32:39,159 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-23 15:32:39,160 INFO L87 Difference]: Start difference. First operand 108040 states and 151037 transitions. cyclomatic complexity: 43029 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:39,987 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-23 15:32:39,988 INFO L93 Difference]: Finished difference Result 227739 states and 318355 transitions. [2022-07-23 15:32:39,988 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-23 15:32:39,988 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 227739 states and 318355 transitions. [2022-07-23 15:32:41,174 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 226760 [2022-07-23 15:32:41,717 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 227739 states to 227739 states and 318355 transitions. [2022-07-23 15:32:41,717 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 227739 [2022-07-23 15:32:41,825 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 227739 [2022-07-23 15:32:41,825 INFO L73 IsDeterministic]: Start isDeterministic. Operand 227739 states and 318355 transitions. [2022-07-23 15:32:42,210 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-23 15:32:42,210 INFO L369 hiAutomatonCegarLoop]: Abstraction has 227739 states and 318355 transitions. [2022-07-23 15:32:42,295 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 227739 states and 318355 transitions. [2022-07-23 15:32:43,596 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 227739 to 119829. [2022-07-23 15:32:43,680 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 119829 states, 119829 states have (on average 1.3996194577272614) internal successors, (167715), 119828 states have internal predecessors, (167715), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:43,888 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 119829 states to 119829 states and 167715 transitions. [2022-07-23 15:32:43,888 INFO L392 hiAutomatonCegarLoop]: Abstraction has 119829 states and 167715 transitions. [2022-07-23 15:32:43,888 INFO L374 stractBuchiCegarLoop]: Abstraction has 119829 states and 167715 transitions. [2022-07-23 15:32:43,888 INFO L287 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-07-23 15:32:43,888 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 119829 states and 167715 transitions. [2022-07-23 15:32:44,221 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 119222 [2022-07-23 15:32:44,221 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-23 15:32:44,221 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-23 15:32:44,222 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:44,222 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:44,223 INFO L752 eck$LassoCheckResult]: Stem: 770763#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 770764#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 770772#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 770773#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 770493#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 770494#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 770357#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 770263#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 769972#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 769610#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 769611#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 769660#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 769661#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 770637#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 770638#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 770683#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 770078#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 770079#L1090 assume !(0 == ~M_E~0); 770122#L1090-2 assume !(0 == ~T1_E~0); 770123#L1095-1 assume !(0 == ~T2_E~0); 770850#L1100-1 assume !(0 == ~T3_E~0); 770851#L1105-1 assume !(0 == ~T4_E~0); 769888#L1110-1 assume !(0 == ~T5_E~0); 769889#L1115-1 assume !(0 == ~T6_E~0); 770306#L1120-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 770610#L1125-1 assume !(0 == ~T8_E~0); 771280#L1130-1 assume !(0 == ~T9_E~0); 771396#L1135-1 assume !(0 == ~T10_E~0); 770083#L1140-1 assume !(0 == ~T11_E~0); 770084#L1145-1 assume !(0 == ~E_1~0); 771395#L1150-1 assume !(0 == ~E_2~0); 770280#L1155-1 assume !(0 == ~E_3~0); 770281#L1160-1 assume !(0 == ~E_4~0); 771394#L1165-1 assume !(0 == ~E_5~0); 771107#L1170-1 assume !(0 == ~E_6~0); 771108#L1175-1 assume !(0 == ~E_7~0); 771393#L1180-1 assume !(0 == ~E_8~0); 771392#L1185-1 assume !(0 == ~E_9~0); 770080#L1190-1 assume !(0 == ~E_10~0); 770081#L1195-1 assume !(0 == ~E_11~0); 770462#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 771064#L525 assume !(1 == ~m_pc~0); 771389#L525-2 is_master_triggered_~__retres1~0#1 := 0; 771388#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 771387#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 771386#L1350 assume !(0 != activate_threads_~tmp~1#1); 771385#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 770518#L544 assume !(1 == ~t1_pc~0); 770519#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 770789#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 770790#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 769911#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 769912#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 771384#L563 assume !(1 == ~t2_pc~0); 770774#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 770775#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 770568#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 770569#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 770661#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 770662#L582 assume !(1 == ~t3_pc~0); 771278#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 771279#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 771323#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 771324#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 771383#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 771298#L601 assume !(1 == ~t4_pc~0); 771299#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 771382#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 771381#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 770808#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 770809#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 771184#L620 assume !(1 == ~t5_pc~0); 771185#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 770678#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 770679#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 771342#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 771343#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 771281#L639 assume !(1 == ~t6_pc~0); 771282#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 770194#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 770195#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 771216#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 770314#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 770315#L658 assume !(1 == ~t7_pc~0); 770607#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 771235#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 771236#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 770730#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 770074#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 770075#L677 assume !(1 == ~t8_pc~0); 770319#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 769869#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 769870#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 771079#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 771373#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 771372#L696 assume !(1 == ~t9_pc~0); 770587#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 770588#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 771380#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 770615#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 770616#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 770856#L715 assume !(1 == ~t10_pc~0); 771254#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 771255#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 770578#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 770579#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 770437#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 770438#L734 assume !(1 == ~t11_pc~0); 771360#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 771359#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 771358#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 771357#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 770680#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 770681#L1213 assume !(1 == ~M_E~0); 771356#L1213-2 assume !(1 == ~T1_E~0); 771355#L1218-1 assume !(1 == ~T2_E~0); 771354#L1223-1 assume !(1 == ~T3_E~0); 771353#L1228-1 assume !(1 == ~T4_E~0); 771221#L1233-1 assume !(1 == ~T5_E~0); 771222#L1238-1 assume !(1 == ~T6_E~0); 771352#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 770807#L1248-1 assume !(1 == ~T8_E~0); 770862#L1253-1 assume !(1 == ~T9_E~0); 770863#L1258-1 assume !(1 == ~T10_E~0); 770834#L1263-1 assume !(1 == ~T11_E~0); 770835#L1268-1 assume !(1 == ~E_1~0); 770635#L1273-1 assume !(1 == ~E_2~0); 770636#L1278-1 assume !(1 == ~E_3~0); 770192#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 770193#L1288-1 assume !(1 == ~E_5~0); 770978#L1293-1 assume !(1 == ~E_6~0); 770935#L1298-1 assume !(1 == ~E_7~0); 770665#L1303-1 assume !(1 == ~E_8~0); 770205#L1308-1 assume !(1 == ~E_9~0); 770089#L1313-1 assume !(1 == ~E_10~0); 770090#L1318-1 assume !(1 == ~E_11~0); 770100#L1323-1 assume { :end_inline_reset_delta_events } true; 770101#L1644-2 [2022-07-23 15:32:44,223 INFO L754 eck$LassoCheckResult]: Loop: 770101#L1644-2 assume !false; 864508#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 864502#L1065 assume !false; 864500#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 864493#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 864482#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 864479#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 864457#L906 assume !(0 != eval_~tmp~0#1); 864458#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 864728#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 864727#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 864726#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 864722#L1095-3 assume !(0 == ~T2_E~0); 864720#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 864718#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 864717#L1110-3 assume !(0 == ~T5_E~0); 864716#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 864711#L1120-3 assume !(0 == ~T7_E~0); 864712#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 868486#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 868485#L1135-3 assume !(0 == ~T10_E~0); 868484#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 868483#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 868482#L1150-3 assume !(0 == ~E_2~0); 868481#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 868480#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 868479#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 868478#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 868477#L1175-3 assume !(0 == ~E_7~0); 868476#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 868474#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 868473#L1190-3 assume !(0 == ~E_10~0); 868472#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 868471#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 868469#L525-36 assume !(1 == ~m_pc~0); 868467#L525-38 is_master_triggered_~__retres1~0#1 := 0; 868466#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 868462#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 868460#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 868458#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 868456#L544-36 assume !(1 == ~t1_pc~0); 868453#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 868451#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 868449#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 868448#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 868446#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 868444#L563-36 assume !(1 == ~t2_pc~0); 868441#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 868439#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 868437#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 868434#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 868432#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 868430#L582-36 assume !(1 == ~t3_pc~0); 868428#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 868426#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 868424#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 868423#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 868421#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 868419#L601-36 assume 1 == ~t4_pc~0; 868417#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 868414#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 868412#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 868409#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 868407#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 868405#L620-36 assume !(1 == ~t5_pc~0); 868403#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 868401#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 868399#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 868397#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 868395#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 868393#L639-36 assume 1 == ~t6_pc~0; 868391#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 868388#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 868386#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 868383#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 868381#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 868379#L658-36 assume !(1 == ~t7_pc~0); 868376#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 868374#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 868371#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 868369#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 868367#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 868365#L677-36 assume !(1 == ~t8_pc~0); 868363#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 868361#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 868359#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 868357#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 868355#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 868353#L696-36 assume !(1 == ~t9_pc~0); 868349#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 868347#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 868343#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 868341#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 868338#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 868336#L715-36 assume !(1 == ~t10_pc~0); 868333#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 868331#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 868329#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 868328#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 868326#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 868324#L734-36 assume !(1 == ~t11_pc~0); 868321#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 868319#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 868317#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 868314#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 868312#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 868310#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 868308#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 868306#L1218-3 assume !(1 == ~T2_E~0); 868302#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 868300#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 868298#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 865241#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 864606#L1243-3 assume !(1 == ~T7_E~0); 864603#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 864601#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 864599#L1258-3 assume !(1 == ~T10_E~0); 864596#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 864594#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 864592#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 864590#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 864588#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 864586#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 864584#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 864582#L1298-3 assume !(1 == ~E_7~0); 864580#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 864578#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 864576#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 864574#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 864571#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 864569#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 864556#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 864554#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 864551#L1663 assume !(0 == start_simulation_~tmp~3#1); 864547#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 864530#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 864524#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 864522#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 864518#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 864516#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 864514#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 864512#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 770101#L1644-2 [2022-07-23 15:32:44,223 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:44,224 INFO L85 PathProgramCache]: Analyzing trace with hash 948156820, now seen corresponding path program 1 times [2022-07-23 15:32:44,224 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:44,224 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [256630328] [2022-07-23 15:32:44,224 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:44,224 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:44,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:44,258 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:44,258 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:44,258 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [256630328] [2022-07-23 15:32:44,258 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [256630328] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:44,259 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:44,259 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-23 15:32:44,259 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [303075372] [2022-07-23 15:32:44,259 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:44,259 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-23 15:32:44,259 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:44,260 INFO L85 PathProgramCache]: Analyzing trace with hash -359933503, now seen corresponding path program 1 times [2022-07-23 15:32:44,260 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:44,260 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1354373691] [2022-07-23 15:32:44,260 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:44,260 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:44,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:44,280 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:44,280 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:44,280 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1354373691] [2022-07-23 15:32:44,280 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1354373691] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:44,280 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:44,280 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-23 15:32:44,281 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2003123636] [2022-07-23 15:32:44,281 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:44,281 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-23 15:32:44,281 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-23 15:32:44,281 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-23 15:32:44,281 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-23 15:32:44,282 INFO L87 Difference]: Start difference. First operand 119829 states and 167715 transitions. cyclomatic complexity: 47918 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:44,977 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-23 15:32:44,978 INFO L93 Difference]: Finished difference Result 108040 states and 150711 transitions. [2022-07-23 15:32:44,982 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-23 15:32:44,982 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 108040 states and 150711 transitions. [2022-07-23 15:32:45,423 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 107538 [2022-07-23 15:32:45,726 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 108040 states to 108040 states and 150711 transitions. [2022-07-23 15:32:45,727 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 108040 [2022-07-23 15:32:45,802 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 108040 [2022-07-23 15:32:45,802 INFO L73 IsDeterministic]: Start isDeterministic. Operand 108040 states and 150711 transitions. [2022-07-23 15:32:45,860 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-23 15:32:45,861 INFO L369 hiAutomatonCegarLoop]: Abstraction has 108040 states and 150711 transitions. [2022-07-23 15:32:45,925 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 108040 states and 150711 transitions. [2022-07-23 15:32:47,116 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 108040 to 108040. [2022-07-23 15:32:47,206 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 108040 states, 108040 states have (on average 1.3949555720103666) internal successors, (150711), 108039 states have internal predecessors, (150711), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:47,415 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108040 states to 108040 states and 150711 transitions. [2022-07-23 15:32:47,415 INFO L392 hiAutomatonCegarLoop]: Abstraction has 108040 states and 150711 transitions. [2022-07-23 15:32:47,415 INFO L374 stractBuchiCegarLoop]: Abstraction has 108040 states and 150711 transitions. [2022-07-23 15:32:47,416 INFO L287 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2022-07-23 15:32:47,416 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 108040 states and 150711 transitions. [2022-07-23 15:32:47,751 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 107538 [2022-07-23 15:32:47,751 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-23 15:32:47,751 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-23 15:32:47,773 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:47,773 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:47,774 INFO L752 eck$LassoCheckResult]: Stem: 998639#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 998640#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 998648#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 998649#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 998372#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 998373#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 998236#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 998142#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 997854#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 997491#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 997492#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 997540#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 997541#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 998513#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 998514#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 998559#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 997959#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 997960#L1090 assume !(0 == ~M_E~0); 998005#L1090-2 assume !(0 == ~T1_E~0); 998006#L1095-1 assume !(0 == ~T2_E~0); 998719#L1100-1 assume !(0 == ~T3_E~0); 998720#L1105-1 assume !(0 == ~T4_E~0); 997772#L1110-1 assume !(0 == ~T5_E~0); 997773#L1115-1 assume !(0 == ~T6_E~0); 998184#L1120-1 assume !(0 == ~T7_E~0); 998483#L1125-1 assume !(0 == ~T8_E~0); 999167#L1130-1 assume !(0 == ~T9_E~0); 998743#L1135-1 assume !(0 == ~T10_E~0); 997965#L1140-1 assume !(0 == ~T11_E~0); 997966#L1145-1 assume !(0 == ~E_1~0); 998665#L1150-1 assume !(0 == ~E_2~0); 998158#L1155-1 assume !(0 == ~E_3~0); 998159#L1160-1 assume !(0 == ~E_4~0); 998244#L1165-1 assume !(0 == ~E_5~0); 998245#L1170-1 assume !(0 == ~E_6~0); 998982#L1175-1 assume !(0 == ~E_7~0); 998326#L1180-1 assume !(0 == ~E_8~0); 998327#L1185-1 assume !(0 == ~E_9~0); 997961#L1190-1 assume !(0 == ~E_10~0); 997962#L1195-1 assume !(0 == ~E_11~0); 998341#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 998174#L525 assume !(1 == ~m_pc~0); 997578#L525-2 is_master_triggered_~__retres1~0#1 := 0; 997579#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 998345#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 998346#L1350 assume !(0 != activate_threads_~tmp~1#1); 997948#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 997949#L544 assume !(1 == ~t1_pc~0); 998182#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 998183#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 998662#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 997793#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 997794#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 998451#L563 assume !(1 == ~t2_pc~0); 998650#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 997599#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 997600#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 998034#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 998035#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 998539#L582 assume !(1 == ~t3_pc~0); 998663#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 999086#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 999087#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 998995#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 997672#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 997673#L601 assume !(1 == ~t4_pc~0); 998686#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 998185#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 998186#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 998676#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 998677#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 999074#L620 assume !(1 == ~t5_pc~0); 998503#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 998504#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 998481#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 998482#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 999105#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 999106#L639 assume !(1 == ~t6_pc~0); 998480#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 998074#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 998075#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 999001#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 998192#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 998193#L658 assume !(1 == ~t7_pc~0); 998395#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 998396#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 998523#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 998524#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 997955#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 997956#L677 assume !(1 == ~t8_pc~0); 997980#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 997753#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 997754#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 998031#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 998032#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 998798#L696 assume !(1 == ~t9_pc~0); 998462#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 998463#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 998570#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 998488#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 998489#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 998724#L715 assume !(1 == ~t10_pc~0); 999028#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 998588#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 998454#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 998455#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 998317#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 997745#L734 assume !(1 == ~t11_pc~0); 997746#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 998248#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 998331#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 997479#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 997480#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 998557#L1213 assume !(1 == ~M_E~0); 998314#L1213-2 assume !(1 == ~T1_E~0); 998315#L1218-1 assume !(1 == ~T2_E~0); 997516#L1223-1 assume !(1 == ~T3_E~0); 997517#L1228-1 assume !(1 == ~T4_E~0); 998292#L1233-1 assume !(1 == ~T5_E~0); 999107#L1238-1 assume !(1 == ~T6_E~0); 998674#L1243-1 assume !(1 == ~T7_E~0); 998675#L1248-1 assume !(1 == ~T8_E~0); 998729#L1253-1 assume !(1 == ~T9_E~0); 998730#L1258-1 assume !(1 == ~T10_E~0); 998705#L1263-1 assume !(1 == ~T11_E~0); 998706#L1268-1 assume !(1 == ~E_1~0); 998511#L1273-1 assume !(1 == ~E_2~0); 998512#L1278-1 assume !(1 == ~E_3~0); 998072#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 998073#L1288-1 assume !(1 == ~E_5~0); 998851#L1293-1 assume !(1 == ~E_6~0); 998803#L1298-1 assume !(1 == ~E_7~0); 998542#L1303-1 assume !(1 == ~E_8~0); 998083#L1308-1 assume !(1 == ~E_9~0); 997971#L1313-1 assume !(1 == ~E_10~0); 997972#L1318-1 assume !(1 == ~E_11~0); 997981#L1323-1 assume { :end_inline_reset_delta_events } true; 997982#L1644-2 [2022-07-23 15:32:47,774 INFO L754 eck$LassoCheckResult]: Loop: 997982#L1644-2 assume !false; 1075297#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1075290#L1065 assume !false; 1075288#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1020346#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1020335#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1020334#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1020331#L906 assume !(0 != eval_~tmp~0#1); 1020332#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1075575#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1075574#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1075573#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1075572#L1095-3 assume !(0 == ~T2_E~0); 1075571#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1075570#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1075569#L1110-3 assume !(0 == ~T5_E~0); 1075568#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1075567#L1120-3 assume !(0 == ~T7_E~0); 1075566#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1075565#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1075564#L1135-3 assume !(0 == ~T10_E~0); 1075563#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1075561#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1075560#L1150-3 assume !(0 == ~E_2~0); 1075559#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1075557#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1075556#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1075555#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1075554#L1175-3 assume !(0 == ~E_7~0); 1075553#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1075552#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1075551#L1190-3 assume !(0 == ~E_10~0); 1075550#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1075549#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1075548#L525-36 assume !(1 == ~m_pc~0); 1075547#L525-38 is_master_triggered_~__retres1~0#1 := 0; 1075546#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1075545#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1075543#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 1075541#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1075539#L544-36 assume !(1 == ~t1_pc~0); 1075537#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1075535#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1075533#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1075531#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1075529#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1075527#L563-36 assume !(1 == ~t2_pc~0); 1075524#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 1075522#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1075520#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1075518#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1075515#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1075513#L582-36 assume !(1 == ~t3_pc~0); 1075511#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1075509#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1075507#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1075505#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1075503#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1075501#L601-36 assume !(1 == ~t4_pc~0); 1075498#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 1075496#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1075494#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1075492#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1075489#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1075487#L620-36 assume !(1 == ~t5_pc~0); 1075485#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1075483#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1075481#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1075479#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1075477#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1075475#L639-36 assume !(1 == ~t6_pc~0); 1075472#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 1075470#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1075468#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1075466#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1075463#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1075461#L658-36 assume !(1 == ~t7_pc~0); 1075458#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1075456#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1075454#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1075451#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 1075449#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1075447#L677-36 assume !(1 == ~t8_pc~0); 1075445#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 1075443#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1075441#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1075439#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1075437#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1075435#L696-36 assume !(1 == ~t9_pc~0); 1075431#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 1075429#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1075427#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1075423#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 1075420#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1075418#L715-36 assume !(1 == ~t10_pc~0); 1075416#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1075413#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1075411#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1075409#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1075407#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1075405#L734-36 assume !(1 == ~t11_pc~0); 1075402#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 1075400#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1075398#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1075396#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1075393#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1075391#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1075389#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1075387#L1218-3 assume !(1 == ~T2_E~0); 1075385#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1075383#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1075381#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1075379#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1075377#L1243-3 assume !(1 == ~T7_E~0); 1075375#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1075373#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1075371#L1258-3 assume !(1 == ~T10_E~0); 1075369#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1075367#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1075365#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1075363#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1075361#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1075359#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1075357#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1075355#L1298-3 assume !(1 == ~E_7~0); 1075353#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1075351#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1075349#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1075347#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1075345#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1075343#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1075330#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1075328#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1075326#L1663 assume !(0 == start_simulation_~tmp~3#1); 1075324#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1075316#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1075311#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1075309#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 1075307#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1075305#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1075303#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1075301#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 997982#L1644-2 [2022-07-23 15:32:47,775 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:47,775 INFO L85 PathProgramCache]: Analyzing trace with hash 1086953880, now seen corresponding path program 1 times [2022-07-23 15:32:47,775 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:47,775 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1435467385] [2022-07-23 15:32:47,775 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:47,775 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:47,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:47,835 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:47,835 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:47,835 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1435467385] [2022-07-23 15:32:47,836 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1435467385] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:47,836 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:47,836 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-23 15:32:47,836 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2087878140] [2022-07-23 15:32:47,836 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:47,836 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-23 15:32:47,837 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:47,837 INFO L85 PathProgramCache]: Analyzing trace with hash -1300255105, now seen corresponding path program 1 times [2022-07-23 15:32:47,837 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:47,837 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1053221460] [2022-07-23 15:32:47,837 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:47,837 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:48,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:48,285 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:48,286 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:48,286 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1053221460] [2022-07-23 15:32:48,286 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1053221460] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:48,286 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:48,286 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-23 15:32:48,286 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [567013376] [2022-07-23 15:32:48,286 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:48,287 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-23 15:32:48,287 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-23 15:32:48,287 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-23 15:32:48,287 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-23 15:32:48,287 INFO L87 Difference]: Start difference. First operand 108040 states and 150711 transitions. cyclomatic complexity: 42703 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:48,998 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-23 15:32:48,999 INFO L93 Difference]: Finished difference Result 226717 states and 314370 transitions. [2022-07-23 15:32:48,999 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-23 15:32:49,000 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 226717 states and 314370 transitions. [2022-07-23 15:32:50,441 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 225640 [2022-07-23 15:32:50,951 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 226717 states to 226717 states and 314370 transitions. [2022-07-23 15:32:50,952 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 226717 [2022-07-23 15:32:51,062 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 226717 [2022-07-23 15:32:51,063 INFO L73 IsDeterministic]: Start isDeterministic. Operand 226717 states and 314370 transitions. [2022-07-23 15:32:51,164 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-23 15:32:51,164 INFO L369 hiAutomatonCegarLoop]: Abstraction has 226717 states and 314370 transitions. [2022-07-23 15:32:51,266 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 226717 states and 314370 transitions. [2022-07-23 15:32:53,040 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 226717 to 119829. [2022-07-23 15:32:53,129 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 119829 states, 119829 states have (on average 1.3888123909904948) internal successors, (166420), 119828 states have internal predecessors, (166420), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:53,335 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 119829 states to 119829 states and 166420 transitions. [2022-07-23 15:32:53,335 INFO L392 hiAutomatonCegarLoop]: Abstraction has 119829 states and 166420 transitions. [2022-07-23 15:32:53,335 INFO L374 stractBuchiCegarLoop]: Abstraction has 119829 states and 166420 transitions. [2022-07-23 15:32:53,335 INFO L287 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2022-07-23 15:32:53,335 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 119829 states and 166420 transitions. [2022-07-23 15:32:54,114 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 119222 [2022-07-23 15:32:54,114 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-23 15:32:54,114 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-23 15:32:54,115 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:54,116 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:54,116 INFO L752 eck$LassoCheckResult]: Stem: 1333388#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 1333389#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1333398#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1333399#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1333131#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 1333132#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1332996#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1332910#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1332622#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1332260#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1332261#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1332308#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1332309#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1333269#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1333270#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1333312#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1332729#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1332730#L1090 assume !(0 == ~M_E~0); 1332776#L1090-2 assume !(0 == ~T1_E~0); 1332777#L1095-1 assume !(0 == ~T2_E~0); 1333472#L1100-1 assume !(0 == ~T3_E~0); 1333473#L1105-1 assume !(0 == ~T4_E~0); 1332537#L1110-1 assume !(0 == ~T5_E~0); 1332538#L1115-1 assume !(0 == ~T6_E~0); 1332947#L1120-1 assume !(0 == ~T7_E~0); 1333243#L1125-1 assume !(0 == ~T8_E~0); 1333891#L1130-1 assume !(0 == ~T9_E~0); 1333495#L1135-1 assume !(0 == ~T10_E~0); 1332735#L1140-1 assume !(0 == ~T11_E~0); 1332736#L1145-1 assume !(0 == ~E_1~0); 1333420#L1150-1 assume !(0 == ~E_2~0); 1332924#L1155-1 assume !(0 == ~E_3~0); 1332925#L1160-1 assume 0 == ~E_4~0;~E_4~0 := 1; 1333878#L1165-1 assume !(0 == ~E_5~0); 1333715#L1170-1 assume !(0 == ~E_6~0); 1333716#L1175-1 assume !(0 == ~E_7~0); 1334042#L1180-1 assume !(0 == ~E_8~0); 1334041#L1185-1 assume !(0 == ~E_9~0); 1332731#L1190-1 assume !(0 == ~E_10~0); 1332732#L1195-1 assume !(0 == ~E_11~0); 1333097#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1332937#L525 assume !(1 == ~m_pc~0); 1332345#L525-2 is_master_triggered_~__retres1~0#1 := 0; 1332346#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1333101#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1333102#L1350 assume !(0 != activate_threads_~tmp~1#1); 1332717#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1332718#L544 assume !(1 == ~t1_pc~0); 1334032#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1333415#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1333416#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1332559#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 1332560#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1334031#L563 assume !(1 == ~t2_pc~0); 1334030#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1332369#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1332370#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1332805#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 1332806#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1333417#L582 assume !(1 == ~t3_pc~0); 1333418#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1333817#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1333818#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1333728#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 1332439#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1332440#L601 assume !(1 == ~t4_pc~0); 1334026#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1334025#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1334024#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1334023#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 1334022#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1334021#L620 assume !(1 == ~t5_pc~0); 1334020#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1334019#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1334018#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1334017#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 1334016#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1334015#L639 assume !(1 == ~t6_pc~0); 1334013#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1334012#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1334011#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1334010#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 1334009#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1334008#L658 assume !(1 == ~t7_pc~0); 1334006#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1334005#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1334004#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1334003#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 1334002#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1334001#L677 assume !(1 == ~t8_pc~0); 1334000#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1333999#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1333998#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1333997#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 1333996#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1333995#L696 assume !(1 == ~t9_pc~0); 1333994#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1333992#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1333990#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1333987#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 1333986#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1333985#L715 assume !(1 == ~t10_pc~0); 1333984#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1333983#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1333982#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1333981#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 1333980#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1333979#L734 assume !(1 == ~t11_pc~0); 1333977#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1333976#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1333975#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1333974#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 1333973#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1333972#L1213 assume !(1 == ~M_E~0); 1333971#L1213-2 assume !(1 == ~T1_E~0); 1333970#L1218-1 assume !(1 == ~T2_E~0); 1333969#L1223-1 assume !(1 == ~T3_E~0); 1333968#L1228-1 assume !(1 == ~T4_E~0); 1333967#L1233-1 assume !(1 == ~T5_E~0); 1333966#L1238-1 assume !(1 == ~T6_E~0); 1333965#L1243-1 assume !(1 == ~T7_E~0); 1333964#L1248-1 assume !(1 == ~T8_E~0); 1333963#L1253-1 assume !(1 == ~T9_E~0); 1333962#L1258-1 assume !(1 == ~T10_E~0); 1333961#L1263-1 assume !(1 == ~T11_E~0); 1333960#L1268-1 assume !(1 == ~E_1~0); 1333959#L1273-1 assume !(1 == ~E_2~0); 1333958#L1278-1 assume !(1 == ~E_3~0); 1333957#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1332843#L1288-1 assume !(1 == ~E_5~0); 1333597#L1293-1 assume !(1 == ~E_6~0); 1333553#L1298-1 assume !(1 == ~E_7~0); 1333298#L1303-1 assume !(1 == ~E_8~0); 1332853#L1308-1 assume !(1 == ~E_9~0); 1332741#L1313-1 assume !(1 == ~E_10~0); 1332742#L1318-1 assume !(1 == ~E_11~0); 1332752#L1323-1 assume { :end_inline_reset_delta_events } true; 1332753#L1644-2 [2022-07-23 15:32:54,116 INFO L754 eck$LassoCheckResult]: Loop: 1332753#L1644-2 assume !false; 1425097#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1425088#L1065 assume !false; 1425083#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1425069#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1425056#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1425052#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1425047#L906 assume !(0 != eval_~tmp~0#1); 1425048#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1425896#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1425888#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1425879#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1425870#L1095-3 assume !(0 == ~T2_E~0); 1425860#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1425853#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1425838#L1110-3 assume !(0 == ~T5_E~0); 1425837#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1425403#L1120-3 assume !(0 == ~T7_E~0); 1425400#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1425395#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1425390#L1135-3 assume !(0 == ~T10_E~0); 1425386#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1425381#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1425379#L1150-3 assume !(0 == ~E_2~0); 1425376#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1425374#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1351841#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1351842#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1351837#L1175-3 assume !(0 == ~E_7~0); 1351838#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1351833#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1351834#L1190-3 assume !(0 == ~E_10~0); 1351829#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1351830#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1351825#L525-36 assume !(1 == ~m_pc~0); 1351826#L525-38 is_master_triggered_~__retres1~0#1 := 0; 1351821#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1351822#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1351817#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 1351818#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1351813#L544-36 assume !(1 == ~t1_pc~0); 1351814#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1351809#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1351810#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1351805#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1351806#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1351800#L563-36 assume !(1 == ~t2_pc~0); 1351801#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 1351795#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1351796#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1351791#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1351792#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1351787#L582-36 assume !(1 == ~t3_pc~0); 1351788#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1351783#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1351784#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1351779#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1351780#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1351774#L601-36 assume 1 == ~t4_pc~0; 1351776#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1351768#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1351769#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1351764#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1351765#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1351760#L620-36 assume !(1 == ~t5_pc~0); 1351761#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1351756#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1351757#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1351752#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1351753#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1351747#L639-36 assume 1 == ~t6_pc~0; 1351748#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1351742#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1351743#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1351738#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1351739#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1351735#L658-36 assume !(1 == ~t7_pc~0); 1351734#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1351729#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1351730#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1351725#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 1351726#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1351721#L677-36 assume !(1 == ~t8_pc~0); 1351722#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 1351717#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1351718#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1351713#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1351714#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1351708#L696-36 assume !(1 == ~t9_pc~0); 1351709#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 1351702#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1351703#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1351695#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 1351694#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1351689#L715-36 assume !(1 == ~t10_pc~0); 1351690#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1351685#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1351686#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1351681#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1351682#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1351676#L734-36 assume !(1 == ~t11_pc~0); 1351677#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 1351671#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1351672#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1351667#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1351668#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1351663#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1351664#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1351659#L1218-3 assume !(1 == ~T2_E~0); 1351660#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1351655#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1351656#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1351651#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1351652#L1243-3 assume !(1 == ~T7_E~0); 1351647#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1351648#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1351643#L1258-3 assume !(1 == ~T10_E~0); 1351644#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1351639#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1351640#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1351635#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1351636#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1425370#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1425368#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1425366#L1298-3 assume !(1 == ~E_7~0); 1425364#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1425362#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1425360#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1425358#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1425356#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1425354#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1425341#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1425339#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1425336#L1663 assume !(0 == start_simulation_~tmp~3#1); 1425334#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1425156#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1425146#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1425140#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 1425134#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1425126#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1425120#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1425113#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 1332753#L1644-2 [2022-07-23 15:32:54,117 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:54,117 INFO L85 PathProgramCache]: Analyzing trace with hash 968512406, now seen corresponding path program 1 times [2022-07-23 15:32:54,117 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:54,117 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1201859264] [2022-07-23 15:32:54,117 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:54,118 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:54,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:54,138 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:54,138 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:54,138 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1201859264] [2022-07-23 15:32:54,138 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1201859264] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:54,138 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:54,139 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-23 15:32:54,139 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1901341300] [2022-07-23 15:32:54,139 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:54,139 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-23 15:32:54,139 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:54,140 INFO L85 PathProgramCache]: Analyzing trace with hash -359933503, now seen corresponding path program 2 times [2022-07-23 15:32:54,140 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:54,140 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [912620640] [2022-07-23 15:32:54,140 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:54,140 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:54,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:54,167 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:54,167 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:54,168 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [912620640] [2022-07-23 15:32:54,168 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [912620640] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:54,168 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:54,168 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-23 15:32:54,168 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [484455980] [2022-07-23 15:32:54,168 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:54,168 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-23 15:32:54,169 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-23 15:32:54,169 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-23 15:32:54,169 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-23 15:32:54,169 INFO L87 Difference]: Start difference. First operand 119829 states and 166420 transitions. cyclomatic complexity: 46623 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:54,657 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-23 15:32:54,658 INFO L93 Difference]: Finished difference Result 179524 states and 248624 transitions. [2022-07-23 15:32:54,658 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-23 15:32:54,658 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 179524 states and 248624 transitions. [2022-07-23 15:32:55,366 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 178722 [2022-07-23 15:32:56,304 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 179524 states to 179524 states and 248624 transitions. [2022-07-23 15:32:56,304 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 179524 [2022-07-23 15:32:56,389 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 179524 [2022-07-23 15:32:56,389 INFO L73 IsDeterministic]: Start isDeterministic. Operand 179524 states and 248624 transitions. [2022-07-23 15:32:56,470 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-23 15:32:56,470 INFO L369 hiAutomatonCegarLoop]: Abstraction has 179524 states and 248624 transitions. [2022-07-23 15:32:56,557 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179524 states and 248624 transitions. [2022-07-23 15:32:57,963 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179524 to 108040. [2022-07-23 15:32:58,036 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 108040 states, 108040 states have (on average 1.3829692706405035) internal successors, (149416), 108039 states have internal predecessors, (149416), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:58,243 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108040 states to 108040 states and 149416 transitions. [2022-07-23 15:32:58,244 INFO L392 hiAutomatonCegarLoop]: Abstraction has 108040 states and 149416 transitions. [2022-07-23 15:32:58,244 INFO L374 stractBuchiCegarLoop]: Abstraction has 108040 states and 149416 transitions. [2022-07-23 15:32:58,244 INFO L287 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2022-07-23 15:32:58,244 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 108040 states and 149416 transitions. [2022-07-23 15:32:58,552 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 107538 [2022-07-23 15:32:58,553 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-23 15:32:58,553 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-23 15:32:58,554 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:58,554 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:32:58,554 INFO L752 eck$LassoCheckResult]: Stem: 1632736#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 1632737#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1632747#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1632748#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1632491#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 1632492#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1632361#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1632269#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1631985#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1631625#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1631626#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1631673#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1631674#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1632620#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1632621#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1632670#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1632091#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1632092#L1090 assume !(0 == ~M_E~0); 1632140#L1090-2 assume !(0 == ~T1_E~0); 1632141#L1095-1 assume !(0 == ~T2_E~0); 1632818#L1100-1 assume !(0 == ~T3_E~0); 1632819#L1105-1 assume !(0 == ~T4_E~0); 1631904#L1110-1 assume !(0 == ~T5_E~0); 1631905#L1115-1 assume !(0 == ~T6_E~0); 1632312#L1120-1 assume !(0 == ~T7_E~0); 1632593#L1125-1 assume !(0 == ~T8_E~0); 1633206#L1130-1 assume !(0 == ~T9_E~0); 1632838#L1135-1 assume !(0 == ~T10_E~0); 1632100#L1140-1 assume !(0 == ~T11_E~0); 1632101#L1145-1 assume !(0 == ~E_1~0); 1632763#L1150-1 assume !(0 == ~E_2~0); 1632285#L1155-1 assume !(0 == ~E_3~0); 1632286#L1160-1 assume !(0 == ~E_4~0); 1632369#L1165-1 assume !(0 == ~E_5~0); 1632370#L1170-1 assume !(0 == ~E_6~0); 1633054#L1175-1 assume !(0 == ~E_7~0); 1632447#L1180-1 assume !(0 == ~E_8~0); 1632448#L1185-1 assume !(0 == ~E_9~0); 1632093#L1190-1 assume !(0 == ~E_10~0); 1632094#L1195-1 assume !(0 == ~E_11~0); 1632461#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1632304#L525 assume !(1 == ~m_pc~0); 1631711#L525-2 is_master_triggered_~__retres1~0#1 := 0; 1631712#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1632464#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1632465#L1350 assume !(0 != activate_threads_~tmp~1#1); 1632080#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1632081#L544 assume !(1 == ~t1_pc~0); 1632308#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1632309#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1632760#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1631924#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 1631925#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1632561#L563 assume !(1 == ~t2_pc~0); 1632749#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1631732#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1631733#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1632164#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 1632165#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1632643#L582 assume !(1 == ~t3_pc~0); 1632761#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1633141#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1633142#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1633068#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 1631802#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1631803#L601 assume !(1 == ~t4_pc~0); 1632782#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1632313#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1632314#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1632775#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 1632776#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1633130#L620 assume !(1 == ~t5_pc~0); 1632612#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1632613#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1632591#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1632592#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 1633163#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1633164#L639 assume !(1 == ~t6_pc~0); 1632590#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1632202#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1632203#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1633071#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 1632318#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1632319#L658 assume !(1 == ~t7_pc~0); 1632513#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1632514#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1632629#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1632630#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 1632087#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1632088#L677 assume !(1 == ~t8_pc~0); 1632115#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1631889#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1631890#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1632161#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 1632162#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1632885#L696 assume !(1 == ~t9_pc~0); 1632578#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1632579#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1632676#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1632598#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 1632599#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1632822#L715 assume !(1 == ~t10_pc~0); 1633096#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1632692#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1632564#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1632565#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 1632438#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1631877#L734 assume !(1 == ~t11_pc~0); 1631878#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1632376#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1632452#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1631615#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 1631616#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1632662#L1213 assume !(1 == ~M_E~0); 1632436#L1213-2 assume !(1 == ~T1_E~0); 1632437#L1218-1 assume !(1 == ~T2_E~0); 1631650#L1223-1 assume !(1 == ~T3_E~0); 1631651#L1228-1 assume !(1 == ~T4_E~0); 1632414#L1233-1 assume !(1 == ~T5_E~0); 1633165#L1238-1 assume !(1 == ~T6_E~0); 1632773#L1243-1 assume !(1 == ~T7_E~0); 1632774#L1248-1 assume !(1 == ~T8_E~0); 1632826#L1253-1 assume !(1 == ~T9_E~0); 1632827#L1258-1 assume !(1 == ~T10_E~0); 1632802#L1263-1 assume !(1 == ~T11_E~0); 1632803#L1268-1 assume !(1 == ~E_1~0); 1632617#L1273-1 assume !(1 == ~E_2~0); 1632618#L1278-1 assume !(1 == ~E_3~0); 1632200#L1283-1 assume !(1 == ~E_4~0); 1632201#L1288-1 assume !(1 == ~E_5~0); 1632933#L1293-1 assume !(1 == ~E_6~0); 1632892#L1298-1 assume !(1 == ~E_7~0); 1632646#L1303-1 assume !(1 == ~E_8~0); 1632212#L1308-1 assume !(1 == ~E_9~0); 1632106#L1313-1 assume !(1 == ~E_10~0); 1632107#L1318-1 assume !(1 == ~E_11~0); 1632116#L1323-1 assume { :end_inline_reset_delta_events } true; 1632117#L1644-2 [2022-07-23 15:32:58,555 INFO L754 eck$LassoCheckResult]: Loop: 1632117#L1644-2 assume !false; 1679846#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1679834#L1065 assume !false; 1679829#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1679694#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1679679#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1679673#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1679663#L906 assume !(0 != eval_~tmp~0#1); 1679664#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1680346#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1680345#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1680344#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1680343#L1095-3 assume !(0 == ~T2_E~0); 1680342#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1680341#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1680340#L1110-3 assume !(0 == ~T5_E~0); 1680339#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1680338#L1120-3 assume !(0 == ~T7_E~0); 1680337#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1680336#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1680335#L1135-3 assume !(0 == ~T10_E~0); 1680334#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1680333#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1680332#L1150-3 assume !(0 == ~E_2~0); 1680331#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1680330#L1160-3 assume !(0 == ~E_4~0); 1680329#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1680328#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1680327#L1175-3 assume !(0 == ~E_7~0); 1680326#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1680325#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1680324#L1190-3 assume !(0 == ~E_10~0); 1680323#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1680322#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1680321#L525-36 assume !(1 == ~m_pc~0); 1680320#L525-38 is_master_triggered_~__retres1~0#1 := 0; 1680319#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1680318#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1680317#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 1680316#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1680315#L544-36 assume !(1 == ~t1_pc~0); 1680314#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1680312#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1680310#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1680308#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1680306#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1680304#L563-36 assume !(1 == ~t2_pc~0); 1680301#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 1680299#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1680297#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1680295#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1680293#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1680291#L582-36 assume !(1 == ~t3_pc~0); 1680289#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1680287#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1680284#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1680282#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1680280#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1680277#L601-36 assume !(1 == ~t4_pc~0); 1680275#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 1680273#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1680271#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1680269#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1680267#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1680265#L620-36 assume !(1 == ~t5_pc~0); 1680263#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1680260#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1680258#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1680256#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1680254#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1680252#L639-36 assume !(1 == ~t6_pc~0); 1680249#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 1680247#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1680245#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1680243#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1680241#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1680239#L658-36 assume !(1 == ~t7_pc~0); 1680236#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1680234#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1680231#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1680229#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 1680227#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1680225#L677-36 assume !(1 == ~t8_pc~0); 1680223#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 1680220#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1680218#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1680216#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1680214#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1680212#L696-36 assume 1 == ~t9_pc~0; 1680209#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1680206#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1680203#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1680200#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1680198#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1680196#L715-36 assume !(1 == ~t10_pc~0); 1680194#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1680191#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1680187#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1680183#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1680179#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1680175#L734-36 assume !(1 == ~t11_pc~0); 1680171#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 1680168#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1680165#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1680162#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1680159#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1680156#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1680153#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1680150#L1218-3 assume !(1 == ~T2_E~0); 1680145#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1680142#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1680139#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1680136#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1680133#L1243-3 assume !(1 == ~T7_E~0); 1680130#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1680127#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1680124#L1258-3 assume !(1 == ~T10_E~0); 1680121#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1680118#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1680115#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1680111#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1680108#L1283-3 assume !(1 == ~E_4~0); 1680105#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1680102#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1680099#L1298-3 assume !(1 == ~E_7~0); 1680096#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1680093#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1680090#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1680087#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1680084#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1680051#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1680036#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1680031#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1680025#L1663 assume !(0 == start_simulation_~tmp~3#1); 1680021#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1679904#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1679895#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1679889#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 1679883#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1679877#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1679870#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1679864#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 1632117#L1644-2 [2022-07-23 15:32:58,555 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:58,555 INFO L85 PathProgramCache]: Analyzing trace with hash 1767012250, now seen corresponding path program 1 times [2022-07-23 15:32:58,555 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:58,556 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1760352902] [2022-07-23 15:32:58,556 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:58,556 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:58,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-23 15:32:58,564 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-23 15:32:58,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-23 15:32:58,618 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-23 15:32:58,619 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:32:58,619 INFO L85 PathProgramCache]: Analyzing trace with hash 2073690342, now seen corresponding path program 1 times [2022-07-23 15:32:58,619 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:32:58,619 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1339482534] [2022-07-23 15:32:58,620 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:32:58,620 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:32:58,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:32:58,640 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:32:58,640 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:32:58,640 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1339482534] [2022-07-23 15:32:58,641 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1339482534] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:32:58,641 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:32:58,641 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-23 15:32:58,641 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1439895505] [2022-07-23 15:32:58,641 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:32:58,641 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-23 15:32:58,641 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-23 15:32:58,642 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-07-23 15:32:58,642 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-07-23 15:32:58,642 INFO L87 Difference]: Start difference. First operand 108040 states and 149416 transitions. cyclomatic complexity: 41408 Second operand has 5 states, 5 states have (on average 28.4) internal successors, (142), 5 states have internal predecessors, (142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:32:59,252 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-23 15:32:59,252 INFO L93 Difference]: Finished difference Result 199498 states and 272698 transitions. [2022-07-23 15:32:59,252 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-07-23 15:32:59,253 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 199498 states and 272698 transitions. [2022-07-23 15:33:00,568 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 198640 [2022-07-23 15:33:01,117 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 199498 states to 199498 states and 272698 transitions. [2022-07-23 15:33:01,117 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 199498 [2022-07-23 15:33:01,248 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 199498 [2022-07-23 15:33:01,248 INFO L73 IsDeterministic]: Start isDeterministic. Operand 199498 states and 272698 transitions. [2022-07-23 15:33:01,353 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-23 15:33:01,353 INFO L369 hiAutomatonCegarLoop]: Abstraction has 199498 states and 272698 transitions. [2022-07-23 15:33:01,475 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 199498 states and 272698 transitions. [2022-07-23 15:33:03,165 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 199498 to 108364. [2022-07-23 15:33:03,249 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 108364 states, 108364 states have (on average 1.381824222066369) internal successors, (149740), 108363 states have internal predecessors, (149740), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:33:03,436 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108364 states to 108364 states and 149740 transitions. [2022-07-23 15:33:03,436 INFO L392 hiAutomatonCegarLoop]: Abstraction has 108364 states and 149740 transitions. [2022-07-23 15:33:03,436 INFO L374 stractBuchiCegarLoop]: Abstraction has 108364 states and 149740 transitions. [2022-07-23 15:33:03,436 INFO L287 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2022-07-23 15:33:03,436 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 108364 states and 149740 transitions. [2022-07-23 15:33:03,745 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 107862 [2022-07-23 15:33:03,745 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-23 15:33:03,745 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-23 15:33:03,746 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:33:03,746 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:33:03,747 INFO L752 eck$LassoCheckResult]: Stem: 1940344#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 1940345#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1940358#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1940359#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1940069#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 1940070#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1939934#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1939837#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1939547#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1939179#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1939180#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1939228#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1939229#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1940213#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1940214#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1940264#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1939657#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1939658#L1090 assume !(0 == ~M_E~0); 1939701#L1090-2 assume !(0 == ~T1_E~0); 1939702#L1095-1 assume !(0 == ~T2_E~0); 1940434#L1100-1 assume !(0 == ~T3_E~0); 1940435#L1105-1 assume !(0 == ~T4_E~0); 1939457#L1110-1 assume !(0 == ~T5_E~0); 1939458#L1115-1 assume !(0 == ~T6_E~0); 1939879#L1120-1 assume !(0 == ~T7_E~0); 1940186#L1125-1 assume !(0 == ~T8_E~0); 1940928#L1130-1 assume !(0 == ~T9_E~0); 1940458#L1135-1 assume !(0 == ~T10_E~0); 1939661#L1140-1 assume !(0 == ~T11_E~0); 1939662#L1145-1 assume !(0 == ~E_1~0); 1940377#L1150-1 assume !(0 == ~E_2~0); 1939854#L1155-1 assume !(0 == ~E_3~0); 1939855#L1160-1 assume !(0 == ~E_4~0); 1939943#L1165-1 assume !(0 == ~E_5~0); 1939944#L1170-1 assume !(0 == ~E_6~0); 1940734#L1175-1 assume !(0 == ~E_7~0); 1940023#L1180-1 assume !(0 == ~E_8~0); 1940024#L1185-1 assume !(0 == ~E_9~0); 1939655#L1190-1 assume !(0 == ~E_10~0); 1939656#L1195-1 assume !(0 == ~E_11~0); 1940038#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1939869#L525 assume !(1 == ~m_pc~0); 1939266#L525-2 is_master_triggered_~__retres1~0#1 := 0; 1939267#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1940041#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1940042#L1350 assume !(0 != activate_threads_~tmp~1#1); 1939643#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1939644#L544 assume !(1 == ~t1_pc~0); 1939877#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1939878#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1940374#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1939481#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 1939482#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1940152#L563 assume !(1 == ~t2_pc~0); 1940360#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1939287#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1939288#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1939731#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 1939732#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1940242#L582 assume !(1 == ~t3_pc~0); 1940375#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1940839#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1940840#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1940745#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 1939358#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1939359#L601 assume !(1 == ~t4_pc~0); 1940400#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1939880#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1939881#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1940392#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 1940393#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1940826#L620 assume !(1 == ~t5_pc~0); 1940203#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1940204#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1940182#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1940183#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 1940861#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1940862#L639 assume !(1 == ~t6_pc~0); 1940185#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1939772#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1939773#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1940749#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 1939887#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1939888#L658 assume !(1 == ~t7_pc~0); 1940092#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1940093#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1940224#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1940225#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 1939650#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1939651#L677 assume !(1 == ~t8_pc~0); 1939676#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1939438#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1939439#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1939728#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 1939729#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1940517#L696 assume !(1 == ~t9_pc~0); 1940164#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1940165#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1940276#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1940191#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 1940192#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1940439#L715 assume !(1 == ~t10_pc~0); 1940777#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1940293#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1940155#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1940156#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 1940014#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1939430#L734 assume !(1 == ~t11_pc~0); 1939431#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1939947#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1940028#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1939167#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 1939168#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1940263#L1213 assume !(1 == ~M_E~0); 1940011#L1213-2 assume !(1 == ~T1_E~0); 1940012#L1218-1 assume !(1 == ~T2_E~0); 1939204#L1223-1 assume !(1 == ~T3_E~0); 1939205#L1228-1 assume !(1 == ~T4_E~0); 1939989#L1233-1 assume !(1 == ~T5_E~0); 1940863#L1238-1 assume !(1 == ~T6_E~0); 1940390#L1243-1 assume !(1 == ~T7_E~0); 1940391#L1248-1 assume !(1 == ~T8_E~0); 1940444#L1253-1 assume !(1 == ~T9_E~0); 1940445#L1258-1 assume !(1 == ~T10_E~0); 1940420#L1263-1 assume !(1 == ~T11_E~0); 1940421#L1268-1 assume !(1 == ~E_1~0); 1940211#L1273-1 assume !(1 == ~E_2~0); 1940212#L1278-1 assume !(1 == ~E_3~0); 1939770#L1283-1 assume !(1 == ~E_4~0); 1939771#L1288-1 assume !(1 == ~E_5~0); 1940581#L1293-1 assume !(1 == ~E_6~0); 1940523#L1298-1 assume !(1 == ~E_7~0); 1940245#L1303-1 assume !(1 == ~E_8~0); 1939781#L1308-1 assume !(1 == ~E_9~0); 1939667#L1313-1 assume !(1 == ~E_10~0); 1939668#L1318-1 assume !(1 == ~E_11~0); 1939677#L1323-1 assume { :end_inline_reset_delta_events } true; 1939678#L1644-2 [2022-07-23 15:33:03,747 INFO L754 eck$LassoCheckResult]: Loop: 1939678#L1644-2 assume !false; 1993565#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1993359#L1065 assume !false; 1992370#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1991144#L829 assume !(0 == ~m_st~0); 1991145#L833 assume !(0 == ~t1_st~0); 1991134#L837 assume !(0 == ~t2_st~0); 1991135#L841 assume !(0 == ~t3_st~0); 1991138#L845 assume !(0 == ~t4_st~0); 1991140#L849 assume !(0 == ~t5_st~0); 1991142#L853 assume !(0 == ~t6_st~0); 1991143#L857 assume !(0 == ~t7_st~0); 1991146#L861 assume !(0 == ~t8_st~0); 1991136#L865 assume !(0 == ~t9_st~0); 1991137#L869 assume !(0 == ~t10_st~0); 1991139#L873 assume !(0 == ~t11_st~0);exists_runnable_thread_~__retres1~12#1 := 0; 1991141#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1988272#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1988273#L906 assume !(0 != eval_~tmp~0#1); 1994088#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1994087#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1994086#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1994085#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1994084#L1095-3 assume !(0 == ~T2_E~0); 1994083#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1994082#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1994081#L1110-3 assume !(0 == ~T5_E~0); 1994080#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1994079#L1120-3 assume !(0 == ~T7_E~0); 1994078#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1994077#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1994076#L1135-3 assume !(0 == ~T10_E~0); 1994075#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1994074#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1994073#L1150-3 assume !(0 == ~E_2~0); 1994072#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1994071#L1160-3 assume !(0 == ~E_4~0); 1994070#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1994069#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1994068#L1175-3 assume !(0 == ~E_7~0); 1994067#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1994066#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1994065#L1190-3 assume !(0 == ~E_10~0); 1994064#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1994063#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1994062#L525-36 assume !(1 == ~m_pc~0); 1994061#L525-38 is_master_triggered_~__retres1~0#1 := 0; 1994060#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1994059#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1994058#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 1994057#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1994056#L544-36 assume !(1 == ~t1_pc~0); 1994055#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1994054#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1994053#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1994052#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1994051#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1994050#L563-36 assume !(1 == ~t2_pc~0); 1994048#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 1994047#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1994046#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1994045#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1994044#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1994043#L582-36 assume !(1 == ~t3_pc~0); 1994042#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1994041#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1994040#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1994039#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1994038#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1994036#L601-36 assume !(1 == ~t4_pc~0); 1994035#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 1994034#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1994033#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1994032#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1994031#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1994030#L620-36 assume !(1 == ~t5_pc~0); 1994029#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1994028#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1994027#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1994026#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1994025#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1994024#L639-36 assume !(1 == ~t6_pc~0); 1994022#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 1994021#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1994020#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1994019#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1994018#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1994017#L658-36 assume !(1 == ~t7_pc~0); 1994015#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1994014#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1994013#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1994012#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 1994011#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1994010#L677-36 assume !(1 == ~t8_pc~0); 1994009#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 1994008#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1994007#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1994006#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1994005#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1994004#L696-36 assume 1 == ~t9_pc~0; 1994002#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1994000#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1993998#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1993996#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1993995#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1993994#L715-36 assume !(1 == ~t10_pc~0); 1993993#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1993992#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1993991#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1993990#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1993989#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1993988#L734-36 assume !(1 == ~t11_pc~0); 1993986#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 1993985#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1993984#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1993983#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1993982#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1993981#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1993980#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1993979#L1218-3 assume !(1 == ~T2_E~0); 1993978#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1993977#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1993976#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1993975#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1993974#L1243-3 assume !(1 == ~T7_E~0); 1993973#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1993972#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1993971#L1258-3 assume !(1 == ~T10_E~0); 1993970#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1993969#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1993968#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1993967#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1993966#L1283-3 assume !(1 == ~E_4~0); 1993965#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1993964#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1993963#L1298-3 assume !(1 == ~E_7~0); 1993962#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1993961#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1993960#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1993959#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1993958#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1993957#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1993944#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1993942#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1993940#L1663 assume !(0 == start_simulation_~tmp~3#1); 1993593#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1993585#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1993579#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1993577#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 1993575#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1993573#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1993570#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1993568#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 1939678#L1644-2 [2022-07-23 15:33:03,748 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:33:03,748 INFO L85 PathProgramCache]: Analyzing trace with hash 1767012250, now seen corresponding path program 2 times [2022-07-23 15:33:03,748 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:33:03,748 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [775098892] [2022-07-23 15:33:03,748 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:33:03,748 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:33:03,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-23 15:33:03,758 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-23 15:33:03,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-23 15:33:03,798 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-23 15:33:03,799 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:33:03,799 INFO L85 PathProgramCache]: Analyzing trace with hash -1213168140, now seen corresponding path program 1 times [2022-07-23 15:33:03,799 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:33:03,799 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [891162525] [2022-07-23 15:33:03,799 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:33:03,800 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:33:03,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-23 15:33:04,256 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-23 15:33:04,257 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-23 15:33:04,257 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [891162525] [2022-07-23 15:33:04,257 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [891162525] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-23 15:33:04,257 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-23 15:33:04,257 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-23 15:33:04,257 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [900276965] [2022-07-23 15:33:04,257 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-23 15:33:04,258 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-23 15:33:04,258 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-23 15:33:04,258 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-23 15:33:04,258 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-23 15:33:04,258 INFO L87 Difference]: Start difference. First operand 108364 states and 149740 transitions. cyclomatic complexity: 41408 Second operand has 3 states, 3 states have (on average 51.0) internal successors, (153), 3 states have internal predecessors, (153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:33:04,758 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-23 15:33:04,758 INFO L93 Difference]: Finished difference Result 191532 states and 260856 transitions. [2022-07-23 15:33:04,758 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-23 15:33:04,759 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 191532 states and 260856 transitions. [2022-07-23 15:33:05,449 INFO L131 ngComponentsAnalysis]: Automaton has 60 accepting balls. 190812 [2022-07-23 15:33:06,485 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 191532 states to 191532 states and 260856 transitions. [2022-07-23 15:33:06,485 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 191532 [2022-07-23 15:33:06,534 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 191532 [2022-07-23 15:33:06,534 INFO L73 IsDeterministic]: Start isDeterministic. Operand 191532 states and 260856 transitions. [2022-07-23 15:33:06,594 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-23 15:33:06,595 INFO L369 hiAutomatonCegarLoop]: Abstraction has 191532 states and 260856 transitions. [2022-07-23 15:33:06,669 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 191532 states and 260856 transitions. [2022-07-23 15:33:08,106 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 191532 to 188924. [2022-07-23 15:33:08,237 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 188924 states, 188924 states have (on average 1.3625373165929158) internal successors, (257416), 188923 states have internal predecessors, (257416), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-23 15:33:08,543 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 188924 states to 188924 states and 257416 transitions. [2022-07-23 15:33:08,543 INFO L392 hiAutomatonCegarLoop]: Abstraction has 188924 states and 257416 transitions. [2022-07-23 15:33:08,543 INFO L374 stractBuchiCegarLoop]: Abstraction has 188924 states and 257416 transitions. [2022-07-23 15:33:08,543 INFO L287 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2022-07-23 15:33:08,544 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 188924 states and 257416 transitions. [2022-07-23 15:33:09,020 INFO L131 ngComponentsAnalysis]: Automaton has 60 accepting balls. 188204 [2022-07-23 15:33:09,020 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-23 15:33:09,021 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-23 15:33:09,022 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:33:09,022 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-23 15:33:09,026 INFO L752 eck$LassoCheckResult]: Stem: 2240235#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 2240236#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 2240245#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2240246#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2239962#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 2239963#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2239824#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2239734#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2239446#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2239081#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2239082#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2239130#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2239131#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2240107#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2240108#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 2240160#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 2239554#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2239555#L1090 assume !(0 == ~M_E~0); 2239603#L1090-2 assume !(0 == ~T1_E~0); 2239604#L1095-1 assume !(0 == ~T2_E~0); 2240316#L1100-1 assume !(0 == ~T3_E~0); 2240317#L1105-1 assume !(0 == ~T4_E~0); 2239361#L1110-1 assume !(0 == ~T5_E~0); 2239362#L1115-1 assume !(0 == ~T6_E~0); 2239777#L1120-1 assume !(0 == ~T7_E~0); 2240078#L1125-1 assume !(0 == ~T8_E~0); 2240745#L1130-1 assume !(0 == ~T9_E~0); 2240340#L1135-1 assume !(0 == ~T10_E~0); 2239560#L1140-1 assume !(0 == ~T11_E~0); 2239561#L1145-1 assume !(0 == ~E_1~0); 2240262#L1150-1 assume !(0 == ~E_2~0); 2239750#L1155-1 assume !(0 == ~E_3~0); 2239751#L1160-1 assume !(0 == ~E_4~0); 2239832#L1165-1 assume !(0 == ~E_5~0); 2239833#L1170-1 assume !(0 == ~E_6~0); 2240572#L1175-1 assume !(0 == ~E_7~0); 2239914#L1180-1 assume !(0 == ~E_8~0); 2239915#L1185-1 assume !(0 == ~E_9~0); 2239552#L1190-1 assume !(0 == ~E_10~0); 2239553#L1195-1 assume !(0 == ~E_11~0); 2239929#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2239772#L525 assume !(1 == ~m_pc~0); 2239168#L525-2 is_master_triggered_~__retres1~0#1 := 0; 2239169#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2239933#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2239934#L1350 assume !(0 != activate_threads_~tmp~1#1); 2239541#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2239542#L544 assume !(1 == ~t1_pc~0); 2239773#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2239774#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2240259#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2239382#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 2239383#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2240045#L563 assume !(1 == ~t2_pc~0); 2240247#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2239189#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2239190#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2239630#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 2239631#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2240131#L582 assume !(1 == ~t3_pc~0); 2240260#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2240672#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2240673#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2240587#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 2239259#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2239260#L601 assume !(1 == ~t4_pc~0); 2240280#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2239778#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2239779#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2240274#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 2240275#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2240657#L620 assume !(1 == ~t5_pc~0); 2240098#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2240099#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2240076#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2240077#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 2240696#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2240697#L639 assume !(1 == ~t6_pc~0); 2240075#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2239668#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2239669#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2240589#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 2239783#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2239784#L658 assume !(1 == ~t7_pc~0); 2239989#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2239990#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2240116#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2240117#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 2239548#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2239549#L677 assume !(1 == ~t8_pc~0); 2239575#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2239346#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2239347#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2239624#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 2239625#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2240389#L696 assume !(1 == ~t9_pc~0); 2240062#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2240063#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2240168#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2240087#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 2240088#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2240320#L715 assume !(1 == ~t10_pc~0); 2240614#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 2240185#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2240048#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2240049#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 2239905#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2239334#L734 assume !(1 == ~t11_pc~0); 2239335#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 2239839#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 2239919#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2239071#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 2239072#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2240152#L1213 assume !(1 == ~M_E~0); 2239903#L1213-2 assume !(1 == ~T1_E~0); 2239904#L1218-1 assume !(1 == ~T2_E~0); 2239106#L1223-1 assume !(1 == ~T3_E~0); 2239107#L1228-1 assume !(1 == ~T4_E~0); 2239878#L1233-1 assume !(1 == ~T5_E~0); 2240698#L1238-1 assume !(1 == ~T6_E~0); 2240272#L1243-1 assume !(1 == ~T7_E~0); 2240273#L1248-1 assume !(1 == ~T8_E~0); 2240324#L1253-1 assume !(1 == ~T9_E~0); 2240325#L1258-1 assume !(1 == ~T10_E~0); 2240301#L1263-1 assume !(1 == ~T11_E~0); 2240302#L1268-1 assume !(1 == ~E_1~0); 2240103#L1273-1 assume !(1 == ~E_2~0); 2240104#L1278-1 assume !(1 == ~E_3~0); 2239666#L1283-1 assume !(1 == ~E_4~0); 2239667#L1288-1 assume !(1 == ~E_5~0); 2240436#L1293-1 assume !(1 == ~E_6~0); 2240397#L1298-1 assume !(1 == ~E_7~0); 2240135#L1303-1 assume !(1 == ~E_8~0); 2239677#L1308-1 assume !(1 == ~E_9~0); 2239566#L1313-1 assume !(1 == ~E_10~0); 2239567#L1318-1 assume !(1 == ~E_11~0); 2239576#L1323-1 assume { :end_inline_reset_delta_events } true; 2239577#L1644-2 assume !false; 2299317#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2299311#L1065 [2022-07-23 15:33:09,027 INFO L754 eck$LassoCheckResult]: Loop: 2299311#L1065 assume !false; 2299309#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 2299307#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 2299304#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 2299303#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2299302#L906 assume 0 != eval_~tmp~0#1; 2299299#L906-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 2299297#L914 assume !(0 != eval_~tmp_ndt_1~0#1); 2299211#L911 assume !(0 == ~t1_st~0); 2299198#L925 assume !(0 == ~t2_st~0); 2299196#L939 assume !(0 == ~t3_st~0); 2299194#L953 assume !(0 == ~t4_st~0); 2299411#L967 assume !(0 == ~t5_st~0); 2299408#L981 assume !(0 == ~t6_st~0); 2299404#L995 assume !(0 == ~t7_st~0); 2299400#L1009 assume !(0 == ~t8_st~0); 2299396#L1023 assume !(0 == ~t9_st~0); 2299391#L1037 assume !(0 == ~t10_st~0); 2299316#L1051 assume !(0 == ~t11_st~0); 2299311#L1065 [2022-07-23 15:33:09,027 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:33:09,027 INFO L85 PathProgramCache]: Analyzing trace with hash 1586711004, now seen corresponding path program 1 times [2022-07-23 15:33:09,031 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:33:09,031 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [226741650] [2022-07-23 15:33:09,031 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:33:09,031 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:33:09,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-23 15:33:09,053 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-23 15:33:09,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-23 15:33:09,089 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-23 15:33:09,089 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:33:09,090 INFO L85 PathProgramCache]: Analyzing trace with hash 1423790277, now seen corresponding path program 1 times [2022-07-23 15:33:09,090 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:33:09,090 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1008046148] [2022-07-23 15:33:09,090 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:33:09,090 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:33:09,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-23 15:33:09,092 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-23 15:33:09,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-23 15:33:09,095 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-23 15:33:09,096 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-23 15:33:09,096 INFO L85 PathProgramCache]: Analyzing trace with hash -1661089014, now seen corresponding path program 1 times [2022-07-23 15:33:09,096 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-23 15:33:09,096 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1121170947] [2022-07-23 15:33:09,096 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-23 15:33:09,096 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-23 15:33:09,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat