./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/bist_cell.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version f4b24e32 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/bist_cell.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash de455e90ef2ae1a82fb7a87bbcdb07831c7ef68e47976e1b2868a3e9de47a0a2 --- Real Ultimate output --- This is Ultimate 0.2.2-?-f4b24e3 [2022-07-14 16:01:54,979 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-07-14 16:01:54,981 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-07-14 16:01:55,010 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-07-14 16:01:55,012 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-07-14 16:01:55,013 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-07-14 16:01:55,015 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-07-14 16:01:55,017 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-07-14 16:01:55,018 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-07-14 16:01:55,023 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-07-14 16:01:55,023 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-07-14 16:01:55,024 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-07-14 16:01:55,025 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-07-14 16:01:55,026 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-07-14 16:01:55,027 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-07-14 16:01:55,029 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-07-14 16:01:55,030 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-07-14 16:01:55,031 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-07-14 16:01:55,032 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-07-14 16:01:55,035 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-07-14 16:01:55,038 INFO L181 SettingsManager]: Resetting HornVerifier preferences to default values [2022-07-14 16:01:55,039 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-07-14 16:01:55,040 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-07-14 16:01:55,041 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-07-14 16:01:55,041 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-07-14 16:01:55,043 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-07-14 16:01:55,045 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-07-14 16:01:55,046 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-07-14 16:01:55,047 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-07-14 16:01:55,047 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-07-14 16:01:55,048 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-07-14 16:01:55,048 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-07-14 16:01:55,049 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-07-14 16:01:55,050 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-07-14 16:01:55,050 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-07-14 16:01:55,051 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-07-14 16:01:55,051 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-07-14 16:01:55,052 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-07-14 16:01:55,052 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-07-14 16:01:55,052 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-07-14 16:01:55,052 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-07-14 16:01:55,053 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-07-14 16:01:55,054 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-07-14 16:01:55,072 INFO L113 SettingsManager]: Loading preferences was successful [2022-07-14 16:01:55,075 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-07-14 16:01:55,075 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-07-14 16:01:55,075 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-07-14 16:01:55,076 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-07-14 16:01:55,076 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-07-14 16:01:55,076 INFO L138 SettingsManager]: * Use SBE=true [2022-07-14 16:01:55,077 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-07-14 16:01:55,077 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-07-14 16:01:55,077 INFO L138 SettingsManager]: * Use old map elimination=false [2022-07-14 16:01:55,078 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-07-14 16:01:55,078 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-07-14 16:01:55,078 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-07-14 16:01:55,078 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-07-14 16:01:55,078 INFO L138 SettingsManager]: * sizeof long=4 [2022-07-14 16:01:55,078 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-07-14 16:01:55,078 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-07-14 16:01:55,079 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-07-14 16:01:55,079 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-07-14 16:01:55,079 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-07-14 16:01:55,079 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-07-14 16:01:55,079 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-07-14 16:01:55,080 INFO L138 SettingsManager]: * sizeof long double=12 [2022-07-14 16:01:55,080 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-07-14 16:01:55,080 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-07-14 16:01:55,080 INFO L138 SettingsManager]: * Use constant arrays=true [2022-07-14 16:01:55,080 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-07-14 16:01:55,080 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-07-14 16:01:55,080 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-07-14 16:01:55,081 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-07-14 16:01:55,081 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-07-14 16:01:55,081 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-07-14 16:01:55,081 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> de455e90ef2ae1a82fb7a87bbcdb07831c7ef68e47976e1b2868a3e9de47a0a2 [2022-07-14 16:01:55,294 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-07-14 16:01:55,307 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-07-14 16:01:55,309 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-07-14 16:01:55,310 INFO L271 PluginConnector]: Initializing CDTParser... [2022-07-14 16:01:55,310 INFO L275 PluginConnector]: CDTParser initialized [2022-07-14 16:01:55,311 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/bist_cell.cil.c [2022-07-14 16:01:55,369 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ea35f7740/b6dc3ea84c614deb91d8f62d93b9e897/FLAGbe4f47082 [2022-07-14 16:01:55,764 INFO L306 CDTParser]: Found 1 translation units. [2022-07-14 16:01:55,764 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/bist_cell.cil.c [2022-07-14 16:01:55,771 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ea35f7740/b6dc3ea84c614deb91d8f62d93b9e897/FLAGbe4f47082 [2022-07-14 16:01:55,795 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ea35f7740/b6dc3ea84c614deb91d8f62d93b9e897 [2022-07-14 16:01:55,797 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-07-14 16:01:55,799 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-07-14 16:01:55,800 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-07-14 16:01:55,800 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-07-14 16:01:55,802 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-07-14 16:01:55,803 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.07 04:01:55" (1/1) ... [2022-07-14 16:01:55,804 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@bc53582 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:01:55, skipping insertion in model container [2022-07-14 16:01:55,804 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.07 04:01:55" (1/1) ... [2022-07-14 16:01:55,808 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-07-14 16:01:55,829 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-07-14 16:01:55,958 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/bist_cell.cil.c[639,652] [2022-07-14 16:01:56,041 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-14 16:01:56,059 INFO L203 MainTranslator]: Completed pre-run [2022-07-14 16:01:56,074 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/bist_cell.cil.c[639,652] [2022-07-14 16:01:56,101 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-14 16:01:56,118 INFO L208 MainTranslator]: Completed translation [2022-07-14 16:01:56,119 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:01:56 WrapperNode [2022-07-14 16:01:56,119 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-07-14 16:01:56,120 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-07-14 16:01:56,120 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-07-14 16:01:56,120 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-07-14 16:01:56,126 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:01:56" (1/1) ... [2022-07-14 16:01:56,132 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:01:56" (1/1) ... [2022-07-14 16:01:56,169 INFO L137 Inliner]: procedures = 30, calls = 30, calls flagged for inlining = 25, calls inlined = 31, statements flattened = 344 [2022-07-14 16:01:56,173 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-07-14 16:01:56,174 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-07-14 16:01:56,174 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-07-14 16:01:56,174 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-07-14 16:01:56,180 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:01:56" (1/1) ... [2022-07-14 16:01:56,180 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:01:56" (1/1) ... [2022-07-14 16:01:56,182 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:01:56" (1/1) ... [2022-07-14 16:01:56,183 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:01:56" (1/1) ... [2022-07-14 16:01:56,186 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:01:56" (1/1) ... [2022-07-14 16:01:56,190 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:01:56" (1/1) ... [2022-07-14 16:01:56,191 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:01:56" (1/1) ... [2022-07-14 16:01:56,193 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-07-14 16:01:56,194 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-07-14 16:01:56,194 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-07-14 16:01:56,194 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-07-14 16:01:56,195 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:01:56" (1/1) ... [2022-07-14 16:01:56,200 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 16:01:56,209 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 16:01:56,218 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-14 16:01:56,228 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-07-14 16:01:56,250 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-07-14 16:01:56,250 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-07-14 16:01:56,250 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-07-14 16:01:56,250 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-07-14 16:01:56,330 INFO L234 CfgBuilder]: Building ICFG [2022-07-14 16:01:56,332 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-07-14 16:01:56,581 INFO L275 CfgBuilder]: Performing block encoding [2022-07-14 16:01:56,587 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-07-14 16:01:56,587 INFO L299 CfgBuilder]: Removed 2 assume(true) statements. [2022-07-14 16:01:56,589 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.07 04:01:56 BoogieIcfgContainer [2022-07-14 16:01:56,589 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-07-14 16:01:56,590 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-07-14 16:01:56,590 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-07-14 16:01:56,592 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-07-14 16:01:56,593 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-14 16:01:56,593 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 14.07 04:01:55" (1/3) ... [2022-07-14 16:01:56,594 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5ba1d00d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 14.07 04:01:56, skipping insertion in model container [2022-07-14 16:01:56,594 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-14 16:01:56,594 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:01:56" (2/3) ... [2022-07-14 16:01:56,595 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5ba1d00d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 14.07 04:01:56, skipping insertion in model container [2022-07-14 16:01:56,595 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-14 16:01:56,595 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.07 04:01:56" (3/3) ... [2022-07-14 16:01:56,596 INFO L354 chiAutomizerObserver]: Analyzing ICFG bist_cell.cil.c [2022-07-14 16:01:56,632 INFO L255 stractBuchiCegarLoop]: Interprodecural is true [2022-07-14 16:01:56,632 INFO L256 stractBuchiCegarLoop]: Hoare is false [2022-07-14 16:01:56,632 INFO L257 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-07-14 16:01:56,632 INFO L258 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-07-14 16:01:56,632 INFO L259 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-07-14 16:01:56,632 INFO L260 stractBuchiCegarLoop]: Difference is false [2022-07-14 16:01:56,632 INFO L261 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-07-14 16:01:56,633 INFO L265 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-07-14 16:01:56,636 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 125 states, 124 states have (on average 1.5887096774193548) internal successors, (197), 124 states have internal predecessors, (197), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:01:56,655 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2022-07-14 16:01:56,655 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:01:56,655 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:01:56,660 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:01:56,660 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:01:56,660 INFO L287 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-07-14 16:01:56,661 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 125 states, 124 states have (on average 1.5887096774193548) internal successors, (197), 124 states have internal predecessors, (197), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:01:56,665 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2022-07-14 16:01:56,665 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:01:56,665 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:01:56,666 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:01:56,666 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:01:56,671 INFO L752 eck$LassoCheckResult]: Stem: 112#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 42#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 17#L490true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 76#L212true assume !(1 == ~b0_req_up~0); 124#L212-2true assume !(1 == ~b1_req_up~0); 84#L219-1true assume !(1 == ~d0_req_up~0); 43#L226-1true assume !(1 == ~d1_req_up~0); 66#L233-1true assume !(1 == ~z_req_up~0); 107#L240-1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15#L255true assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 117#L255-2true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 67#L321true assume !(0 == ~b0_ev~0); 83#L321-2true assume !(0 == ~b1_ev~0); 24#L326-1true assume !(0 == ~d0_ev~0); 27#L331-1true assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 8#L336-1true assume !(0 == ~z_ev~0); 122#L341-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 118#L107true assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 106#L129true is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 57#L130true activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 91#L390true assume !(0 != activate_threads_~tmp~1#1); 111#L390-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 56#L354true assume !(1 == ~b0_ev~0); 39#L354-2true assume !(1 == ~b1_ev~0); 89#L359-1true assume !(1 == ~d0_ev~0); 41#L364-1true assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 47#L369-1true assume !(1 == ~z_ev~0); 95#L374-1true assume { :end_inline_reset_delta_events } true; 34#L432-2true [2022-07-14 16:01:56,672 INFO L754 eck$LassoCheckResult]: Loop: 34#L432-2true assume !false; 70#L433true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 7#L295true assume !true; 48#L311true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 85#L212-3true assume !(1 == ~b0_req_up~0); 108#L212-5true assume !(1 == ~b1_req_up~0); 88#L219-3true assume !(1 == ~d0_req_up~0); 4#L226-3true assume !(1 == ~d1_req_up~0); 37#L233-3true assume !(1 == ~z_req_up~0); 16#L240-3true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 81#L321-3true assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 65#L321-5true assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 92#L326-3true assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 51#L331-3true assume !(0 == ~d1_ev~0); 11#L336-3true assume 0 == ~z_ev~0;~z_ev~0 := 1; 18#L341-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 114#L107-1true assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 44#L129-1true is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 121#L130-1true activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 9#L390-3true assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 23#L390-5true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32#L354-3true assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 100#L354-5true assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 98#L359-3true assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 82#L364-3true assume !(1 == ~d1_ev~0); 80#L369-3true assume 1 == ~z_ev~0;~z_ev~0 := 2; 49#L374-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 72#L268-1true assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 119#L275-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 40#L276-1true stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 13#L407true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 116#L414true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 104#L415true start_simulation_#t~ret8#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 73#L449true assume !(0 != start_simulation_~tmp~3#1); 34#L432-2true [2022-07-14 16:01:56,676 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:01:56,676 INFO L85 PathProgramCache]: Analyzing trace with hash -1345002148, now seen corresponding path program 1 times [2022-07-14 16:01:56,682 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:01:56,683 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1403853395] [2022-07-14 16:01:56,683 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:01:56,683 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:01:56,746 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:01:56,790 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:01:56,791 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:01:56,791 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1403853395] [2022-07-14 16:01:56,791 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1403853395] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:01:56,791 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:01:56,792 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:01:56,793 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2110754497] [2022-07-14 16:01:56,794 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:01:56,797 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:01:56,800 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:01:56,800 INFO L85 PathProgramCache]: Analyzing trace with hash 972845291, now seen corresponding path program 1 times [2022-07-14 16:01:56,801 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:01:56,802 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [826408460] [2022-07-14 16:01:56,802 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:01:56,802 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:01:56,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:01:56,816 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:01:56,816 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:01:56,816 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [826408460] [2022-07-14 16:01:56,816 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [826408460] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:01:56,816 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:01:56,816 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-14 16:01:56,816 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [162938928] [2022-07-14 16:01:56,817 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:01:56,817 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:01:56,818 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:01:56,838 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:01:56,838 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:01:56,840 INFO L87 Difference]: Start difference. First operand has 125 states, 124 states have (on average 1.5887096774193548) internal successors, (197), 124 states have internal predecessors, (197), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:01:56,861 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:01:56,862 INFO L93 Difference]: Finished difference Result 124 states and 190 transitions. [2022-07-14 16:01:56,863 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:01:56,868 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 124 states and 190 transitions. [2022-07-14 16:01:56,875 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2022-07-14 16:01:56,878 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 124 states to 117 states and 183 transitions. [2022-07-14 16:01:56,878 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2022-07-14 16:01:56,879 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2022-07-14 16:01:56,879 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 183 transitions. [2022-07-14 16:01:56,880 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:01:56,880 INFO L369 hiAutomatonCegarLoop]: Abstraction has 117 states and 183 transitions. [2022-07-14 16:01:56,893 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 183 transitions. [2022-07-14 16:01:56,901 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2022-07-14 16:01:56,902 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.564102564102564) internal successors, (183), 116 states have internal predecessors, (183), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:01:56,903 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 183 transitions. [2022-07-14 16:01:56,903 INFO L392 hiAutomatonCegarLoop]: Abstraction has 117 states and 183 transitions. [2022-07-14 16:01:56,904 INFO L374 stractBuchiCegarLoop]: Abstraction has 117 states and 183 transitions. [2022-07-14 16:01:56,904 INFO L287 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-07-14 16:01:56,904 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 183 transitions. [2022-07-14 16:01:56,905 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2022-07-14 16:01:56,905 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:01:56,905 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:01:56,906 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:01:56,906 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:01:56,906 INFO L752 eck$LassoCheckResult]: Stem: 372#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 320#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 282#L490 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 283#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 345#L137 assume !(~b0_val~0 != ~b0_val_t~0); 346#L137-2 ~b0_req_up~0 := 0; 340#L145 assume { :end_inline_update_b0 } true; 341#L212-2 assume !(1 == ~b1_req_up~0); 363#L219-1 assume !(1 == ~d0_req_up~0); 264#L226-1 assume !(1 == ~d1_req_up~0); 322#L233-1 assume !(1 == ~z_req_up~0); 350#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 278#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 279#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 351#L321 assume !(0 == ~b0_ev~0); 352#L321-2 assume !(0 == ~b1_ev~0); 295#L326-1 assume !(0 == ~d0_ev~0); 296#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 267#L336-1 assume !(0 == ~z_ev~0); 268#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 374#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 288#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 335#L130 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 336#L390 assume !(0 != activate_threads_~tmp~1#1); 365#L390-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 334#L354 assume !(1 == ~b0_ev~0); 315#L354-2 assume !(1 == ~b1_ev~0); 316#L359-1 assume !(1 == ~d0_ev~0); 318#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 319#L369-1 assume !(1 == ~z_ev~0); 324#L374-1 assume { :end_inline_reset_delta_events } true; 307#L432-2 [2022-07-14 16:01:56,906 INFO L754 eck$LassoCheckResult]: Loop: 307#L432-2 assume !false; 308#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 265#L295 assume !false; 266#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 292#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 293#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 258#L276 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 259#L290 assume !(0 != eval_~tmp___0~0#1); 325#L311 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 326#L212-3 assume !(1 == ~b0_req_up~0); 354#L212-5 assume !(1 == ~b1_req_up~0); 310#L219-3 assume !(1 == ~d0_req_up~0); 260#L226-3 assume !(1 == ~d1_req_up~0); 261#L233-3 assume !(1 == ~z_req_up~0); 280#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 281#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 347#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 348#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 330#L331-3 assume !(0 == ~d1_ev~0); 274#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 275#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 284#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 300#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 323#L130-1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 269#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 270#L390-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 294#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 304#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 368#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 362#L364-3 assume !(1 == ~d1_ev~0); 361#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 327#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 328#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 355#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 317#L276-1 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 276#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 277#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 369#L415 start_simulation_#t~ret8#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 356#L449 assume !(0 != start_simulation_~tmp~3#1); 307#L432-2 [2022-07-14 16:01:56,907 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:01:56,907 INFO L85 PathProgramCache]: Analyzing trace with hash -1840469421, now seen corresponding path program 1 times [2022-07-14 16:01:56,907 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:01:56,907 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [748148293] [2022-07-14 16:01:56,907 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:01:56,908 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:01:56,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:01:56,941 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:01:56,941 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:01:56,941 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [748148293] [2022-07-14 16:01:56,941 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [748148293] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:01:56,942 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:01:56,942 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:01:56,942 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2024399300] [2022-07-14 16:01:56,942 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:01:56,942 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:01:56,942 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:01:56,943 INFO L85 PathProgramCache]: Analyzing trace with hash 1200633539, now seen corresponding path program 1 times [2022-07-14 16:01:56,943 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:01:56,943 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1739115397] [2022-07-14 16:01:56,943 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:01:56,943 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:01:56,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:01:57,005 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:01:57,005 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:01:57,006 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1739115397] [2022-07-14 16:01:57,006 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1739115397] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:01:57,006 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:01:57,006 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:01:57,006 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [717303464] [2022-07-14 16:01:57,007 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:01:57,008 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:01:57,008 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:01:57,008 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:01:57,008 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:01:57,008 INFO L87 Difference]: Start difference. First operand 117 states and 183 transitions. cyclomatic complexity: 67 Second operand has 3 states, 3 states have (on average 10.333333333333334) internal successors, (31), 3 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:01:57,032 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:01:57,032 INFO L93 Difference]: Finished difference Result 117 states and 182 transitions. [2022-07-14 16:01:57,032 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:01:57,033 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 182 transitions. [2022-07-14 16:01:57,036 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2022-07-14 16:01:57,037 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 182 transitions. [2022-07-14 16:01:57,037 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2022-07-14 16:01:57,038 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2022-07-14 16:01:57,038 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 182 transitions. [2022-07-14 16:01:57,038 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:01:57,038 INFO L369 hiAutomatonCegarLoop]: Abstraction has 117 states and 182 transitions. [2022-07-14 16:01:57,038 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 182 transitions. [2022-07-14 16:01:57,041 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2022-07-14 16:01:57,042 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.5555555555555556) internal successors, (182), 116 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:01:57,042 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 182 transitions. [2022-07-14 16:01:57,042 INFO L392 hiAutomatonCegarLoop]: Abstraction has 117 states and 182 transitions. [2022-07-14 16:01:57,042 INFO L374 stractBuchiCegarLoop]: Abstraction has 117 states and 182 transitions. [2022-07-14 16:01:57,042 INFO L287 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-07-14 16:01:57,042 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 182 transitions. [2022-07-14 16:01:57,043 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2022-07-14 16:01:57,043 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:01:57,043 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:01:57,044 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:01:57,044 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:01:57,044 INFO L752 eck$LassoCheckResult]: Stem: 615#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 563#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 525#L490 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 526#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 588#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 589#L137-2 ~b0_req_up~0 := 0; 583#L145 assume { :end_inline_update_b0 } true; 584#L212-2 assume !(1 == ~b1_req_up~0); 606#L219-1 assume !(1 == ~d0_req_up~0); 507#L226-1 assume !(1 == ~d1_req_up~0); 565#L233-1 assume !(1 == ~z_req_up~0); 593#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 521#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 522#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 594#L321 assume !(0 == ~b0_ev~0); 595#L321-2 assume !(0 == ~b1_ev~0); 538#L326-1 assume !(0 == ~d0_ev~0); 539#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 510#L336-1 assume !(0 == ~z_ev~0); 511#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 617#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 531#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 578#L130 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 579#L390 assume !(0 != activate_threads_~tmp~1#1); 608#L390-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 577#L354 assume !(1 == ~b0_ev~0); 558#L354-2 assume !(1 == ~b1_ev~0); 559#L359-1 assume !(1 == ~d0_ev~0); 561#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 562#L369-1 assume !(1 == ~z_ev~0); 567#L374-1 assume { :end_inline_reset_delta_events } true; 550#L432-2 [2022-07-14 16:01:57,044 INFO L754 eck$LassoCheckResult]: Loop: 550#L432-2 assume !false; 551#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 508#L295 assume !false; 509#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 535#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 536#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 501#L276 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 502#L290 assume !(0 != eval_~tmp___0~0#1); 568#L311 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 569#L212-3 assume !(1 == ~b0_req_up~0); 597#L212-5 assume !(1 == ~b1_req_up~0); 553#L219-3 assume !(1 == ~d0_req_up~0); 503#L226-3 assume !(1 == ~d1_req_up~0); 504#L233-3 assume !(1 == ~z_req_up~0); 523#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 524#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 590#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 591#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 573#L331-3 assume !(0 == ~d1_ev~0); 517#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 518#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 527#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 543#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 566#L130-1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 512#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 513#L390-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 537#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 547#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 611#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 605#L364-3 assume !(1 == ~d1_ev~0); 604#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 570#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 571#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 598#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 560#L276-1 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 519#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 520#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 612#L415 start_simulation_#t~ret8#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 599#L449 assume !(0 != start_simulation_~tmp~3#1); 550#L432-2 [2022-07-14 16:01:57,045 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:01:57,045 INFO L85 PathProgramCache]: Analyzing trace with hash 531269841, now seen corresponding path program 1 times [2022-07-14 16:01:57,045 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:01:57,045 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [841595955] [2022-07-14 16:01:57,045 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:01:57,045 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:01:57,067 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:01:57,083 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:01:57,083 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:01:57,084 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [841595955] [2022-07-14 16:01:57,084 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [841595955] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:01:57,084 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:01:57,084 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:01:57,084 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1084127090] [2022-07-14 16:01:57,085 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:01:57,085 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:01:57,086 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:01:57,087 INFO L85 PathProgramCache]: Analyzing trace with hash 1200633539, now seen corresponding path program 2 times [2022-07-14 16:01:57,087 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:01:57,087 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [70671798] [2022-07-14 16:01:57,088 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:01:57,089 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:01:57,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:01:57,134 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:01:57,134 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:01:57,134 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [70671798] [2022-07-14 16:01:57,134 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [70671798] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:01:57,135 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:01:57,135 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:01:57,135 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [982499537] [2022-07-14 16:01:57,135 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:01:57,136 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:01:57,136 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:01:57,136 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:01:57,136 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:01:57,136 INFO L87 Difference]: Start difference. First operand 117 states and 182 transitions. cyclomatic complexity: 66 Second operand has 3 states, 3 states have (on average 10.333333333333334) internal successors, (31), 3 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:01:57,153 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:01:57,153 INFO L93 Difference]: Finished difference Result 117 states and 181 transitions. [2022-07-14 16:01:57,154 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:01:57,155 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 181 transitions. [2022-07-14 16:01:57,161 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2022-07-14 16:01:57,162 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 181 transitions. [2022-07-14 16:01:57,162 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2022-07-14 16:01:57,162 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2022-07-14 16:01:57,162 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 181 transitions. [2022-07-14 16:01:57,163 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:01:57,163 INFO L369 hiAutomatonCegarLoop]: Abstraction has 117 states and 181 transitions. [2022-07-14 16:01:57,163 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 181 transitions. [2022-07-14 16:01:57,166 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2022-07-14 16:01:57,166 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.547008547008547) internal successors, (181), 116 states have internal predecessors, (181), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:01:57,167 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 181 transitions. [2022-07-14 16:01:57,167 INFO L392 hiAutomatonCegarLoop]: Abstraction has 117 states and 181 transitions. [2022-07-14 16:01:57,167 INFO L374 stractBuchiCegarLoop]: Abstraction has 117 states and 181 transitions. [2022-07-14 16:01:57,167 INFO L287 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-07-14 16:01:57,167 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 181 transitions. [2022-07-14 16:01:57,168 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2022-07-14 16:01:57,168 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:01:57,168 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:01:57,168 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:01:57,168 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:01:57,169 INFO L752 eck$LassoCheckResult]: Stem: 858#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 806#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 768#L490 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 769#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 831#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 832#L137-2 ~b0_req_up~0 := 0; 826#L145 assume { :end_inline_update_b0 } true; 827#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 787#L152 assume !(~b1_val~0 != ~b1_val_t~0); 788#L152-2 ~b1_req_up~0 := 0; 850#L160 assume { :end_inline_update_b1 } true; 849#L219-1 assume !(1 == ~d0_req_up~0); 750#L226-1 assume !(1 == ~d1_req_up~0); 808#L233-1 assume !(1 == ~z_req_up~0); 836#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 764#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 765#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 837#L321 assume !(0 == ~b0_ev~0); 838#L321-2 assume !(0 == ~b1_ev~0); 781#L326-1 assume !(0 == ~d0_ev~0); 782#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 753#L336-1 assume !(0 == ~z_ev~0); 754#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 860#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 774#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 821#L130 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 822#L390 assume !(0 != activate_threads_~tmp~1#1); 851#L390-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 820#L354 assume !(1 == ~b0_ev~0); 801#L354-2 assume !(1 == ~b1_ev~0); 802#L359-1 assume !(1 == ~d0_ev~0); 804#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 805#L369-1 assume !(1 == ~z_ev~0); 810#L374-1 assume { :end_inline_reset_delta_events } true; 793#L432-2 [2022-07-14 16:01:57,169 INFO L754 eck$LassoCheckResult]: Loop: 793#L432-2 assume !false; 794#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 751#L295 assume !false; 752#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 778#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 779#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 744#L276 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 745#L290 assume !(0 != eval_~tmp___0~0#1); 811#L311 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 812#L212-3 assume !(1 == ~b0_req_up~0); 840#L212-5 assume !(1 == ~b1_req_up~0); 796#L219-3 assume !(1 == ~d0_req_up~0); 746#L226-3 assume !(1 == ~d1_req_up~0); 747#L233-3 assume !(1 == ~z_req_up~0); 766#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 767#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 833#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 834#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 816#L331-3 assume !(0 == ~d1_ev~0); 760#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 761#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 770#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 786#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 809#L130-1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 755#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 756#L390-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 780#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 790#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 854#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 848#L364-3 assume !(1 == ~d1_ev~0); 847#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 813#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 814#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 841#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 803#L276-1 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 762#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 763#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 855#L415 start_simulation_#t~ret8#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 842#L449 assume !(0 != start_simulation_~tmp~3#1); 793#L432-2 [2022-07-14 16:01:57,169 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:01:57,169 INFO L85 PathProgramCache]: Analyzing trace with hash 1296388927, now seen corresponding path program 1 times [2022-07-14 16:01:57,169 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:01:57,169 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [310498285] [2022-07-14 16:01:57,170 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:01:57,170 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:01:57,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:01:57,230 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:01:57,231 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:01:57,231 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [310498285] [2022-07-14 16:01:57,231 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [310498285] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:01:57,232 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:01:57,233 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-07-14 16:01:57,234 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1273535836] [2022-07-14 16:01:57,234 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:01:57,235 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:01:57,236 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:01:57,236 INFO L85 PathProgramCache]: Analyzing trace with hash 1200633539, now seen corresponding path program 3 times [2022-07-14 16:01:57,236 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:01:57,238 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1125751376] [2022-07-14 16:01:57,238 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:01:57,238 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:01:57,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:01:57,285 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:01:57,286 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:01:57,286 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1125751376] [2022-07-14 16:01:57,286 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1125751376] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:01:57,286 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:01:57,286 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:01:57,286 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [895202310] [2022-07-14 16:01:57,286 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:01:57,287 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:01:57,287 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:01:57,287 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:01:57,287 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:01:57,287 INFO L87 Difference]: Start difference. First operand 117 states and 181 transitions. cyclomatic complexity: 65 Second operand has 4 states, 4 states have (on average 8.5) internal successors, (34), 4 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:01:57,317 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:01:57,317 INFO L93 Difference]: Finished difference Result 117 states and 180 transitions. [2022-07-14 16:01:57,318 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-07-14 16:01:57,318 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 180 transitions. [2022-07-14 16:01:57,319 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2022-07-14 16:01:57,321 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 180 transitions. [2022-07-14 16:01:57,321 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2022-07-14 16:01:57,321 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2022-07-14 16:01:57,322 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 180 transitions. [2022-07-14 16:01:57,325 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:01:57,325 INFO L369 hiAutomatonCegarLoop]: Abstraction has 117 states and 180 transitions. [2022-07-14 16:01:57,325 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 180 transitions. [2022-07-14 16:01:57,328 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2022-07-14 16:01:57,328 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.5384615384615385) internal successors, (180), 116 states have internal predecessors, (180), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:01:57,328 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 180 transitions. [2022-07-14 16:01:57,328 INFO L392 hiAutomatonCegarLoop]: Abstraction has 117 states and 180 transitions. [2022-07-14 16:01:57,328 INFO L374 stractBuchiCegarLoop]: Abstraction has 117 states and 180 transitions. [2022-07-14 16:01:57,328 INFO L287 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-07-14 16:01:57,329 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 180 transitions. [2022-07-14 16:01:57,329 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2022-07-14 16:01:57,329 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:01:57,329 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:01:57,330 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:01:57,330 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:01:57,330 INFO L752 eck$LassoCheckResult]: Stem: 1104#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 1052#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 1014#L490 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1015#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 1077#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 1078#L137-2 ~b0_req_up~0 := 0; 1072#L145 assume { :end_inline_update_b0 } true; 1073#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 1033#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 1034#L152-2 ~b1_req_up~0 := 0; 1096#L160 assume { :end_inline_update_b1 } true; 1095#L219-1 assume !(1 == ~d0_req_up~0); 996#L226-1 assume !(1 == ~d1_req_up~0); 1054#L233-1 assume !(1 == ~z_req_up~0); 1082#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1010#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 1011#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1083#L321 assume !(0 == ~b0_ev~0); 1084#L321-2 assume !(0 == ~b1_ev~0); 1027#L326-1 assume !(0 == ~d0_ev~0); 1028#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 999#L336-1 assume !(0 == ~z_ev~0); 1000#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1106#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1020#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1067#L130 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1068#L390 assume !(0 != activate_threads_~tmp~1#1); 1097#L390-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1066#L354 assume !(1 == ~b0_ev~0); 1047#L354-2 assume !(1 == ~b1_ev~0); 1048#L359-1 assume !(1 == ~d0_ev~0); 1050#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 1051#L369-1 assume !(1 == ~z_ev~0); 1056#L374-1 assume { :end_inline_reset_delta_events } true; 1039#L432-2 [2022-07-14 16:01:57,330 INFO L754 eck$LassoCheckResult]: Loop: 1039#L432-2 assume !false; 1040#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 997#L295 assume !false; 998#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1024#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1025#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 990#L276 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 991#L290 assume !(0 != eval_~tmp___0~0#1); 1057#L311 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1058#L212-3 assume !(1 == ~b0_req_up~0); 1086#L212-5 assume !(1 == ~b1_req_up~0); 1042#L219-3 assume !(1 == ~d0_req_up~0); 992#L226-3 assume !(1 == ~d1_req_up~0); 993#L233-3 assume !(1 == ~z_req_up~0); 1012#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1013#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 1079#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 1080#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 1062#L331-3 assume !(0 == ~d1_ev~0); 1006#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 1007#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1016#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1032#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1055#L130-1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1001#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 1002#L390-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1026#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 1036#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 1100#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 1094#L364-3 assume !(1 == ~d1_ev~0); 1093#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 1059#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1060#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1087#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1049#L276-1 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 1008#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1009#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1101#L415 start_simulation_#t~ret8#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 1088#L449 assume !(0 != start_simulation_~tmp~3#1); 1039#L432-2 [2022-07-14 16:01:57,331 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:01:57,331 INFO L85 PathProgramCache]: Analyzing trace with hash 1234349313, now seen corresponding path program 1 times [2022-07-14 16:01:57,331 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:01:57,331 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1275712617] [2022-07-14 16:01:57,331 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:01:57,331 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:01:57,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:01:57,374 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:01:57,374 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:01:57,374 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1275712617] [2022-07-14 16:01:57,375 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1275712617] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:01:57,375 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:01:57,375 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:01:57,375 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1402118980] [2022-07-14 16:01:57,375 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:01:57,375 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:01:57,375 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:01:57,375 INFO L85 PathProgramCache]: Analyzing trace with hash 1200633539, now seen corresponding path program 4 times [2022-07-14 16:01:57,376 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:01:57,376 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1887650327] [2022-07-14 16:01:57,376 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:01:57,376 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:01:57,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:01:57,412 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:01:57,412 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:01:57,413 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1887650327] [2022-07-14 16:01:57,413 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1887650327] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:01:57,413 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:01:57,413 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:01:57,413 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1996591848] [2022-07-14 16:01:57,413 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:01:57,413 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:01:57,413 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:01:57,413 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:01:57,414 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:01:57,414 INFO L87 Difference]: Start difference. First operand 117 states and 180 transitions. cyclomatic complexity: 64 Second operand has 3 states, 3 states have (on average 11.333333333333334) internal successors, (34), 3 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:01:57,423 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:01:57,423 INFO L93 Difference]: Finished difference Result 117 states and 179 transitions. [2022-07-14 16:01:57,423 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:01:57,423 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 179 transitions. [2022-07-14 16:01:57,424 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2022-07-14 16:01:57,424 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 179 transitions. [2022-07-14 16:01:57,425 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2022-07-14 16:01:57,425 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2022-07-14 16:01:57,425 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 179 transitions. [2022-07-14 16:01:57,425 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:01:57,425 INFO L369 hiAutomatonCegarLoop]: Abstraction has 117 states and 179 transitions. [2022-07-14 16:01:57,425 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 179 transitions. [2022-07-14 16:01:57,428 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2022-07-14 16:01:57,428 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.5299145299145298) internal successors, (179), 116 states have internal predecessors, (179), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:01:57,428 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 179 transitions. [2022-07-14 16:01:57,428 INFO L392 hiAutomatonCegarLoop]: Abstraction has 117 states and 179 transitions. [2022-07-14 16:01:57,428 INFO L374 stractBuchiCegarLoop]: Abstraction has 117 states and 179 transitions. [2022-07-14 16:01:57,428 INFO L287 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-07-14 16:01:57,429 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 179 transitions. [2022-07-14 16:01:57,429 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2022-07-14 16:01:57,429 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:01:57,429 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:01:57,430 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:01:57,430 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:01:57,430 INFO L752 eck$LassoCheckResult]: Stem: 1347#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 1295#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 1257#L490 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1258#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 1320#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 1321#L137-2 ~b0_req_up~0 := 0; 1315#L145 assume { :end_inline_update_b0 } true; 1316#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 1276#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 1277#L152-2 ~b1_req_up~0 := 0; 1339#L160 assume { :end_inline_update_b1 } true; 1338#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 1260#L167 assume !(~d0_val~0 != ~d0_val_t~0); 1261#L167-2 ~d0_req_up~0 := 0; 1238#L175 assume { :end_inline_update_d0 } true; 1239#L226-1 assume !(1 == ~d1_req_up~0); 1297#L233-1 assume !(1 == ~z_req_up~0); 1325#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1253#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 1254#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1326#L321 assume !(0 == ~b0_ev~0); 1327#L321-2 assume !(0 == ~b1_ev~0); 1270#L326-1 assume !(0 == ~d0_ev~0); 1271#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 1242#L336-1 assume !(0 == ~z_ev~0); 1243#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1349#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1263#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1310#L130 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1311#L390 assume !(0 != activate_threads_~tmp~1#1); 1340#L390-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1309#L354 assume !(1 == ~b0_ev~0); 1290#L354-2 assume !(1 == ~b1_ev~0); 1291#L359-1 assume !(1 == ~d0_ev~0); 1293#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 1294#L369-1 assume !(1 == ~z_ev~0); 1299#L374-1 assume { :end_inline_reset_delta_events } true; 1282#L432-2 [2022-07-14 16:01:57,430 INFO L754 eck$LassoCheckResult]: Loop: 1282#L432-2 assume !false; 1283#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 1240#L295 assume !false; 1241#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1267#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1268#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1233#L276 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1234#L290 assume !(0 != eval_~tmp___0~0#1); 1300#L311 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1301#L212-3 assume !(1 == ~b0_req_up~0); 1329#L212-5 assume !(1 == ~b1_req_up~0); 1285#L219-3 assume !(1 == ~d0_req_up~0); 1235#L226-3 assume !(1 == ~d1_req_up~0); 1236#L233-3 assume !(1 == ~z_req_up~0); 1255#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1256#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 1322#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 1323#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 1305#L331-3 assume !(0 == ~d1_ev~0); 1249#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 1250#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1259#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1275#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1298#L130-1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1244#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 1245#L390-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1269#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 1279#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 1343#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 1337#L364-3 assume !(1 == ~d1_ev~0); 1336#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 1302#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1303#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1330#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1292#L276-1 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 1251#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1252#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1344#L415 start_simulation_#t~ret8#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 1331#L449 assume !(0 != start_simulation_~tmp~3#1); 1282#L432-2 [2022-07-14 16:01:57,430 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:01:57,431 INFO L85 PathProgramCache]: Analyzing trace with hash -2115080082, now seen corresponding path program 1 times [2022-07-14 16:01:57,431 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:01:57,431 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1081107127] [2022-07-14 16:01:57,431 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:01:57,431 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:01:57,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:01:57,475 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:01:57,476 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:01:57,476 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1081107127] [2022-07-14 16:01:57,476 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1081107127] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:01:57,476 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:01:57,476 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-07-14 16:01:57,476 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [286555162] [2022-07-14 16:01:57,476 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:01:57,476 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:01:57,476 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:01:57,477 INFO L85 PathProgramCache]: Analyzing trace with hash 1200633539, now seen corresponding path program 5 times [2022-07-14 16:01:57,477 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:01:57,477 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [100416935] [2022-07-14 16:01:57,477 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:01:57,477 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:01:57,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:01:57,517 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:01:57,517 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:01:57,517 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [100416935] [2022-07-14 16:01:57,517 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [100416935] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:01:57,517 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:01:57,517 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:01:57,518 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [73983182] [2022-07-14 16:01:57,518 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:01:57,518 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:01:57,518 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:01:57,518 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:01:57,518 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:01:57,519 INFO L87 Difference]: Start difference. First operand 117 states and 179 transitions. cyclomatic complexity: 63 Second operand has 4 states, 4 states have (on average 9.25) internal successors, (37), 4 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:01:57,546 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:01:57,546 INFO L93 Difference]: Finished difference Result 117 states and 178 transitions. [2022-07-14 16:01:57,548 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-07-14 16:01:57,549 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 178 transitions. [2022-07-14 16:01:57,549 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2022-07-14 16:01:57,550 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 178 transitions. [2022-07-14 16:01:57,550 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2022-07-14 16:01:57,550 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2022-07-14 16:01:57,550 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 178 transitions. [2022-07-14 16:01:57,551 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:01:57,551 INFO L369 hiAutomatonCegarLoop]: Abstraction has 117 states and 178 transitions. [2022-07-14 16:01:57,551 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 178 transitions. [2022-07-14 16:01:57,553 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2022-07-14 16:01:57,553 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.5213675213675213) internal successors, (178), 116 states have internal predecessors, (178), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:01:57,554 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 178 transitions. [2022-07-14 16:01:57,554 INFO L392 hiAutomatonCegarLoop]: Abstraction has 117 states and 178 transitions. [2022-07-14 16:01:57,554 INFO L374 stractBuchiCegarLoop]: Abstraction has 117 states and 178 transitions. [2022-07-14 16:01:57,554 INFO L287 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-07-14 16:01:57,554 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 178 transitions. [2022-07-14 16:01:57,554 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2022-07-14 16:01:57,554 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:01:57,554 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:01:57,555 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:01:57,555 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:01:57,556 INFO L752 eck$LassoCheckResult]: Stem: 1593#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 1541#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 1503#L490 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1504#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 1566#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 1567#L137-2 ~b0_req_up~0 := 0; 1561#L145 assume { :end_inline_update_b0 } true; 1562#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 1522#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 1523#L152-2 ~b1_req_up~0 := 0; 1585#L160 assume { :end_inline_update_b1 } true; 1584#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 1506#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 1507#L167-2 ~d0_req_up~0 := 0; 1484#L175 assume { :end_inline_update_d0 } true; 1485#L226-1 assume !(1 == ~d1_req_up~0); 1543#L233-1 assume !(1 == ~z_req_up~0); 1571#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1499#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 1500#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1572#L321 assume !(0 == ~b0_ev~0); 1573#L321-2 assume !(0 == ~b1_ev~0); 1516#L326-1 assume !(0 == ~d0_ev~0); 1517#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 1488#L336-1 assume !(0 == ~z_ev~0); 1489#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1595#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1509#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1556#L130 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1557#L390 assume !(0 != activate_threads_~tmp~1#1); 1586#L390-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1555#L354 assume !(1 == ~b0_ev~0); 1536#L354-2 assume !(1 == ~b1_ev~0); 1537#L359-1 assume !(1 == ~d0_ev~0); 1539#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 1540#L369-1 assume !(1 == ~z_ev~0); 1545#L374-1 assume { :end_inline_reset_delta_events } true; 1528#L432-2 [2022-07-14 16:01:57,556 INFO L754 eck$LassoCheckResult]: Loop: 1528#L432-2 assume !false; 1529#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 1486#L295 assume !false; 1487#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1513#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1514#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1479#L276 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1480#L290 assume !(0 != eval_~tmp___0~0#1); 1546#L311 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1547#L212-3 assume !(1 == ~b0_req_up~0); 1575#L212-5 assume !(1 == ~b1_req_up~0); 1531#L219-3 assume !(1 == ~d0_req_up~0); 1481#L226-3 assume !(1 == ~d1_req_up~0); 1482#L233-3 assume !(1 == ~z_req_up~0); 1501#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1502#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 1568#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 1569#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 1551#L331-3 assume !(0 == ~d1_ev~0); 1495#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 1496#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1505#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1521#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1544#L130-1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1490#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 1491#L390-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1515#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 1525#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 1589#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 1583#L364-3 assume !(1 == ~d1_ev~0); 1582#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 1548#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1549#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1576#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1538#L276-1 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 1497#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1498#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1590#L415 start_simulation_#t~ret8#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 1577#L449 assume !(0 != start_simulation_~tmp~3#1); 1528#L432-2 [2022-07-14 16:01:57,556 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:01:57,556 INFO L85 PathProgramCache]: Analyzing trace with hash 2039338604, now seen corresponding path program 1 times [2022-07-14 16:01:57,556 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:01:57,556 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1080839399] [2022-07-14 16:01:57,556 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:01:57,556 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:01:57,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:01:57,613 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:01:57,613 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:01:57,613 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1080839399] [2022-07-14 16:01:57,613 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1080839399] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:01:57,613 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:01:57,613 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:01:57,614 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [387768855] [2022-07-14 16:01:57,614 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:01:57,614 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:01:57,614 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:01:57,614 INFO L85 PathProgramCache]: Analyzing trace with hash 1200633539, now seen corresponding path program 6 times [2022-07-14 16:01:57,614 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:01:57,614 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [706787303] [2022-07-14 16:01:57,614 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:01:57,614 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:01:57,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:01:57,638 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:01:57,638 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:01:57,639 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [706787303] [2022-07-14 16:01:57,639 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [706787303] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:01:57,639 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:01:57,639 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:01:57,639 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1094787376] [2022-07-14 16:01:57,639 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:01:57,639 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:01:57,639 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:01:57,639 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:01:57,640 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:01:57,640 INFO L87 Difference]: Start difference. First operand 117 states and 178 transitions. cyclomatic complexity: 62 Second operand has 3 states, 3 states have (on average 12.333333333333334) internal successors, (37), 3 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:01:57,652 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:01:57,653 INFO L93 Difference]: Finished difference Result 117 states and 177 transitions. [2022-07-14 16:01:57,653 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:01:57,654 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 177 transitions. [2022-07-14 16:01:57,655 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2022-07-14 16:01:57,656 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 177 transitions. [2022-07-14 16:01:57,656 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2022-07-14 16:01:57,656 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2022-07-14 16:01:57,656 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 177 transitions. [2022-07-14 16:01:57,656 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:01:57,656 INFO L369 hiAutomatonCegarLoop]: Abstraction has 117 states and 177 transitions. [2022-07-14 16:01:57,656 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 177 transitions. [2022-07-14 16:01:57,658 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2022-07-14 16:01:57,658 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.5128205128205128) internal successors, (177), 116 states have internal predecessors, (177), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:01:57,659 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 177 transitions. [2022-07-14 16:01:57,659 INFO L392 hiAutomatonCegarLoop]: Abstraction has 117 states and 177 transitions. [2022-07-14 16:01:57,669 INFO L374 stractBuchiCegarLoop]: Abstraction has 117 states and 177 transitions. [2022-07-14 16:01:57,675 INFO L287 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-07-14 16:01:57,675 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 177 transitions. [2022-07-14 16:01:57,676 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2022-07-14 16:01:57,676 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:01:57,676 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:01:57,677 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:01:57,677 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:01:57,677 INFO L752 eck$LassoCheckResult]: Stem: 1836#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 1784#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 1746#L490 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1747#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 1809#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 1810#L137-2 ~b0_req_up~0 := 0; 1803#L145 assume { :end_inline_update_b0 } true; 1804#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 1765#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 1766#L152-2 ~b1_req_up~0 := 0; 1828#L160 assume { :end_inline_update_b1 } true; 1827#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 1749#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 1750#L167-2 ~d0_req_up~0 := 0; 1727#L175 assume { :end_inline_update_d0 } true; 1728#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 1785#L182 assume !(~d1_val~0 != ~d1_val_t~0); 1754#L182-2 ~d1_req_up~0 := 0; 1755#L190 assume { :end_inline_update_d1 } true; 1808#L233-1 assume !(1 == ~z_req_up~0); 1814#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1742#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 1743#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1815#L321 assume !(0 == ~b0_ev~0); 1816#L321-2 assume !(0 == ~b1_ev~0); 1759#L326-1 assume !(0 == ~d0_ev~0); 1760#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 1731#L336-1 assume !(0 == ~z_ev~0); 1732#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1838#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1752#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1798#L130 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1799#L390 assume !(0 != activate_threads_~tmp~1#1); 1829#L390-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1797#L354 assume !(1 == ~b0_ev~0); 1779#L354-2 assume !(1 == ~b1_ev~0); 1780#L359-1 assume !(1 == ~d0_ev~0); 1782#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 1783#L369-1 assume !(1 == ~z_ev~0); 1787#L374-1 assume { :end_inline_reset_delta_events } true; 1771#L432-2 [2022-07-14 16:01:57,677 INFO L754 eck$LassoCheckResult]: Loop: 1771#L432-2 assume !false; 1772#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 1729#L295 assume !false; 1730#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1756#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1757#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1722#L276 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1723#L290 assume !(0 != eval_~tmp___0~0#1); 1788#L311 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1789#L212-3 assume !(1 == ~b0_req_up~0); 1818#L212-5 assume !(1 == ~b1_req_up~0); 1774#L219-3 assume !(1 == ~d0_req_up~0); 1724#L226-3 assume !(1 == ~d1_req_up~0); 1725#L233-3 assume !(1 == ~z_req_up~0); 1744#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1745#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 1811#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 1812#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 1793#L331-3 assume !(0 == ~d1_ev~0); 1738#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 1739#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1748#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1764#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1786#L130-1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1733#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 1734#L390-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1758#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 1768#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 1832#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 1826#L364-3 assume !(1 == ~d1_ev~0); 1825#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 1790#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1791#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1819#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1781#L276-1 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 1740#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1741#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1833#L415 start_simulation_#t~ret8#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 1820#L449 assume !(0 != start_simulation_~tmp~3#1); 1771#L432-2 [2022-07-14 16:01:57,677 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:01:57,677 INFO L85 PathProgramCache]: Analyzing trace with hash -525437980, now seen corresponding path program 1 times [2022-07-14 16:01:57,678 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:01:57,678 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2140856149] [2022-07-14 16:01:57,678 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:01:57,678 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:01:57,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:01:57,711 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:01:57,711 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:01:57,711 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2140856149] [2022-07-14 16:01:57,712 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2140856149] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:01:57,712 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:01:57,712 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-07-14 16:01:57,712 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1674782880] [2022-07-14 16:01:57,712 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:01:57,712 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:01:57,712 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:01:57,712 INFO L85 PathProgramCache]: Analyzing trace with hash 1200633539, now seen corresponding path program 7 times [2022-07-14 16:01:57,712 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:01:57,713 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1006441848] [2022-07-14 16:01:57,713 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:01:57,713 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:01:57,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:01:57,731 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:01:57,732 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:01:57,732 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1006441848] [2022-07-14 16:01:57,732 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1006441848] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:01:57,732 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:01:57,732 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:01:57,732 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1413283847] [2022-07-14 16:01:57,733 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:01:57,733 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:01:57,733 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:01:57,733 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-07-14 16:01:57,733 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-07-14 16:01:57,734 INFO L87 Difference]: Start difference. First operand 117 states and 177 transitions. cyclomatic complexity: 61 Second operand has 5 states, 5 states have (on average 7.8) internal successors, (39), 5 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:01:57,768 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:01:57,769 INFO L93 Difference]: Finished difference Result 151 states and 225 transitions. [2022-07-14 16:01:57,769 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-07-14 16:01:57,770 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 151 states and 225 transitions. [2022-07-14 16:01:57,771 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 105 [2022-07-14 16:01:57,771 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 151 states to 151 states and 225 transitions. [2022-07-14 16:01:57,772 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 151 [2022-07-14 16:01:57,772 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 151 [2022-07-14 16:01:57,772 INFO L73 IsDeterministic]: Start isDeterministic. Operand 151 states and 225 transitions. [2022-07-14 16:01:57,772 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:01:57,772 INFO L369 hiAutomatonCegarLoop]: Abstraction has 151 states and 225 transitions. [2022-07-14 16:01:57,773 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 151 states and 225 transitions. [2022-07-14 16:01:57,775 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 151 to 120. [2022-07-14 16:01:57,775 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 120 states, 120 states have (on average 1.5) internal successors, (180), 119 states have internal predecessors, (180), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:01:57,775 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 120 states to 120 states and 180 transitions. [2022-07-14 16:01:57,776 INFO L392 hiAutomatonCegarLoop]: Abstraction has 120 states and 180 transitions. [2022-07-14 16:01:57,776 INFO L374 stractBuchiCegarLoop]: Abstraction has 120 states and 180 transitions. [2022-07-14 16:01:57,776 INFO L287 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-07-14 16:01:57,776 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 120 states and 180 transitions. [2022-07-14 16:01:57,777 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 74 [2022-07-14 16:01:57,777 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:01:57,777 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:01:57,778 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:01:57,778 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:01:57,778 INFO L752 eck$LassoCheckResult]: Stem: 2123#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 2071#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 2032#L490 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2033#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 2096#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 2097#L137-2 ~b0_req_up~0 := 0; 2090#L145 assume { :end_inline_update_b0 } true; 2091#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 2052#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 2053#L152-2 ~b1_req_up~0 := 0; 2115#L160 assume { :end_inline_update_b1 } true; 2114#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 2035#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 2036#L167-2 ~d0_req_up~0 := 0; 2013#L175 assume { :end_inline_update_d0 } true; 2014#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 2072#L182 assume !(~d1_val~0 != ~d1_val_t~0); 2040#L182-2 ~d1_req_up~0 := 0; 2041#L190 assume { :end_inline_update_d1 } true; 2095#L233-1 assume !(1 == ~z_req_up~0); 2101#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2028#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 2029#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2102#L321 assume !(0 == ~b0_ev~0); 2103#L321-2 assume !(0 == ~b1_ev~0); 2046#L326-1 assume !(0 == ~d0_ev~0); 2047#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 2017#L336-1 assume !(0 == ~z_ev~0); 2018#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 2125#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 2038#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 2085#L130 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 2086#L390 assume !(0 != activate_threads_~tmp~1#1); 2116#L390-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2084#L354 assume !(1 == ~b0_ev~0); 2066#L354-2 assume !(1 == ~b1_ev~0); 2067#L359-1 assume !(1 == ~d0_ev~0); 2069#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 2070#L369-1 assume !(1 == ~z_ev~0); 2074#L374-1 assume { :end_inline_reset_delta_events } true; 2058#L432-2 [2022-07-14 16:01:57,778 INFO L754 eck$LassoCheckResult]: Loop: 2058#L432-2 assume !false; 2059#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 2015#L295 assume !false; 2016#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 2042#L268 assume !(0 == ~comp_m1_st~0);exists_runnable_thread_~__retres1~1#1 := 0; 2044#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 2127#L276 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2126#L290 assume !(0 != eval_~tmp___0~0#1); 2075#L311 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2076#L212-3 assume !(1 == ~b0_req_up~0); 2105#L212-5 assume !(1 == ~b1_req_up~0); 2061#L219-3 assume !(1 == ~d0_req_up~0); 2010#L226-3 assume !(1 == ~d1_req_up~0); 2011#L233-3 assume !(1 == ~z_req_up~0); 2030#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2031#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 2098#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 2099#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 2080#L331-3 assume !(0 == ~d1_ev~0); 2024#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 2025#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 2034#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 2051#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 2073#L130-1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 2019#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 2020#L390-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2045#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 2055#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 2119#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 2113#L364-3 assume !(1 == ~d1_ev~0); 2112#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 2077#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 2078#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 2106#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 2068#L276-1 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 2026#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2027#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2120#L415 start_simulation_#t~ret8#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 2107#L449 assume !(0 != start_simulation_~tmp~3#1); 2058#L432-2 [2022-07-14 16:01:57,778 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:01:57,779 INFO L85 PathProgramCache]: Analyzing trace with hash -525437980, now seen corresponding path program 2 times [2022-07-14 16:01:57,779 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:01:57,779 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1993158133] [2022-07-14 16:01:57,779 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:01:57,779 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:01:57,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:01:57,800 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:01:57,800 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:01:57,801 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1993158133] [2022-07-14 16:01:57,801 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1993158133] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:01:57,801 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:01:57,801 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-07-14 16:01:57,801 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1033037560] [2022-07-14 16:01:57,801 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:01:57,802 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:01:57,802 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:01:57,802 INFO L85 PathProgramCache]: Analyzing trace with hash 356628037, now seen corresponding path program 1 times [2022-07-14 16:01:57,802 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:01:57,802 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [120292054] [2022-07-14 16:01:57,802 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:01:57,803 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:01:57,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:01:57,808 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:01:57,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:01:57,826 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:01:58,136 INFO L210 LassoAnalysis]: Preferences: [2022-07-14 16:01:58,136 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-07-14 16:01:58,136 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-07-14 16:01:58,136 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-07-14 16:01:58,137 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2022-07-14 16:01:58,137 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 16:01:58,137 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-07-14 16:01:58,137 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-07-14 16:01:58,137 INFO L133 ssoRankerPreferences]: Filename of dumped script: bist_cell.cil.c_Iteration9_Loop [2022-07-14 16:01:58,137 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-07-14 16:01:58,137 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-07-14 16:01:58,157 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,174 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,188 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,191 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,195 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,200 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,202 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,205 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,206 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,208 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,210 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,212 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,214 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,218 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,221 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,225 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,227 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,229 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,230 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,234 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,236 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,240 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,242 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,423 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-07-14 16:01:58,423 INFO L404 LassoAnalysis]: Checking for nontermination... [2022-07-14 16:01:58,425 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 16:01:58,425 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 16:01:58,426 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-14 16:01:58,428 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2022-07-14 16:01:58,428 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-07-14 16:01:58,440 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2022-07-14 16:01:58,440 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_~kernel_st~0#1=3} Honda state: {ULTIMATE.start_start_simulation_~kernel_st~0#1=3} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2022-07-14 16:01:58,447 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2022-07-14 16:01:58,456 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2022-07-14 16:01:58,456 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 16:01:58,456 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 16:01:58,457 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-14 16:01:58,473 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2022-07-14 16:01:58,473 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2022-07-14 16:01:58,474 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-07-14 16:01:58,489 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2022-07-14 16:01:58,489 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~d1_ev~0=-7} Honda state: {~d1_ev~0=-7} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2022-07-14 16:01:58,507 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2022-07-14 16:01:58,507 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 16:01:58,507 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 16:01:58,517 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-14 16:01:58,551 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2022-07-14 16:01:58,567 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2022-07-14 16:01:58,567 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-07-14 16:01:58,616 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2022-07-14 16:01:58,616 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 16:01:58,617 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 16:01:58,618 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-14 16:01:58,618 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2022-07-14 16:01:58,619 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2022-07-14 16:01:58,620 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-07-14 16:01:58,641 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2022-07-14 16:01:58,657 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2022-07-14 16:01:58,657 INFO L210 LassoAnalysis]: Preferences: [2022-07-14 16:01:58,657 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-07-14 16:01:58,657 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-07-14 16:01:58,657 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-07-14 16:01:58,657 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2022-07-14 16:01:58,657 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 16:01:58,657 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-07-14 16:01:58,657 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-07-14 16:01:58,657 INFO L133 ssoRankerPreferences]: Filename of dumped script: bist_cell.cil.c_Iteration9_Loop [2022-07-14 16:01:58,657 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-07-14 16:01:58,657 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-07-14 16:01:58,662 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,667 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,671 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,683 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,686 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,695 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,698 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,701 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,708 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,710 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,721 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,724 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,735 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,737 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,747 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,750 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,752 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,756 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,758 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,759 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,773 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,775 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,781 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:58,989 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-07-14 16:01:58,992 INFO L490 LassoAnalysis]: Using template 'affine'. [2022-07-14 16:01:58,993 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 16:01:58,993 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 16:01:58,996 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-14 16:01:59,010 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-07-14 16:01:59,016 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-07-14 16:01:59,016 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-07-14 16:01:59,017 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-07-14 16:01:59,017 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2022-07-14 16:01:59,017 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-07-14 16:01:59,019 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2022-07-14 16:01:59,019 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-07-14 16:01:59,023 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2022-07-14 16:01:59,032 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-07-14 16:01:59,049 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2022-07-14 16:01:59,049 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 16:01:59,049 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 16:01:59,051 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-14 16:01:59,053 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2022-07-14 16:01:59,068 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-07-14 16:01:59,074 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-07-14 16:01:59,074 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-07-14 16:01:59,074 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-07-14 16:01:59,074 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-07-14 16:01:59,074 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-07-14 16:01:59,075 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-07-14 16:01:59,075 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-07-14 16:01:59,076 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2022-07-14 16:01:59,079 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2022-07-14 16:01:59,079 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2022-07-14 16:01:59,080 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 16:01:59,080 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 16:01:59,108 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-14 16:01:59,109 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2022-07-14 16:01:59,110 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2022-07-14 16:01:59,110 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2022-07-14 16:01:59,110 INFO L513 LassoAnalysis]: Proved termination. [2022-07-14 16:01:59,111 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(~b0_ev~0) = -1*~b0_ev~0 + 1 Supporting invariants [] [2022-07-14 16:01:59,127 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2022-07-14 16:01:59,129 INFO L293 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2022-07-14 16:01:59,146 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:01:59,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:01:59,191 INFO L263 TraceCheckSpWp]: Trace formula consists of 183 conjuncts, 2 conjunts are in the unsatisfiable core [2022-07-14 16:01:59,194 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 16:01:59,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:01:59,273 INFO L263 TraceCheckSpWp]: Trace formula consists of 90 conjuncts, 4 conjunts are in the unsatisfiable core [2022-07-14 16:01:59,274 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 16:01:59,363 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:01:59,366 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2022-07-14 16:01:59,366 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 120 states and 180 transitions. cyclomatic complexity: 61 Second operand has 5 states, 5 states have (on average 15.8) internal successors, (79), 5 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:01:59,404 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 120 states and 180 transitions. cyclomatic complexity: 61. Second operand has 5 states, 5 states have (on average 15.8) internal successors, (79), 5 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 274 states and 422 transitions. Complement of second has 5 states. [2022-07-14 16:01:59,405 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2022-07-14 16:01:59,406 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 15.8) internal successors, (79), 5 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:01:59,406 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 181 transitions. [2022-07-14 16:01:59,407 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 181 transitions. Stem has 40 letters. Loop has 39 letters. [2022-07-14 16:01:59,408 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-07-14 16:01:59,408 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 181 transitions. Stem has 79 letters. Loop has 39 letters. [2022-07-14 16:01:59,409 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-07-14 16:01:59,409 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 181 transitions. Stem has 40 letters. Loop has 78 letters. [2022-07-14 16:01:59,410 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-07-14 16:01:59,410 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 274 states and 422 transitions. [2022-07-14 16:01:59,412 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 148 [2022-07-14 16:01:59,413 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 274 states to 274 states and 422 transitions. [2022-07-14 16:01:59,413 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 195 [2022-07-14 16:01:59,413 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 198 [2022-07-14 16:01:59,413 INFO L73 IsDeterministic]: Start isDeterministic. Operand 274 states and 422 transitions. [2022-07-14 16:01:59,413 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-07-14 16:01:59,413 INFO L369 hiAutomatonCegarLoop]: Abstraction has 274 states and 422 transitions. [2022-07-14 16:01:59,413 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 274 states and 422 transitions. [2022-07-14 16:01:59,417 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 274 to 271. [2022-07-14 16:01:59,417 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 271 states, 271 states have (on average 1.5387453874538746) internal successors, (417), 270 states have internal predecessors, (417), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:01:59,418 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 271 states to 271 states and 417 transitions. [2022-07-14 16:01:59,418 INFO L392 hiAutomatonCegarLoop]: Abstraction has 271 states and 417 transitions. [2022-07-14 16:01:59,418 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:01:59,418 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:01:59,418 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:01:59,418 INFO L87 Difference]: Start difference. First operand 271 states and 417 transitions. Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:01:59,435 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:01:59,435 INFO L93 Difference]: Finished difference Result 271 states and 416 transitions. [2022-07-14 16:01:59,436 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-07-14 16:01:59,436 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 271 states and 416 transitions. [2022-07-14 16:01:59,437 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 148 [2022-07-14 16:01:59,438 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 271 states to 271 states and 416 transitions. [2022-07-14 16:01:59,438 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 195 [2022-07-14 16:01:59,438 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 195 [2022-07-14 16:01:59,438 INFO L73 IsDeterministic]: Start isDeterministic. Operand 271 states and 416 transitions. [2022-07-14 16:01:59,438 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-07-14 16:01:59,438 INFO L369 hiAutomatonCegarLoop]: Abstraction has 271 states and 416 transitions. [2022-07-14 16:01:59,439 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 271 states and 416 transitions. [2022-07-14 16:01:59,441 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 271 to 271. [2022-07-14 16:01:59,442 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 271 states, 271 states have (on average 1.5350553505535056) internal successors, (416), 270 states have internal predecessors, (416), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:01:59,442 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 271 states to 271 states and 416 transitions. [2022-07-14 16:01:59,442 INFO L392 hiAutomatonCegarLoop]: Abstraction has 271 states and 416 transitions. [2022-07-14 16:01:59,442 INFO L374 stractBuchiCegarLoop]: Abstraction has 271 states and 416 transitions. [2022-07-14 16:01:59,442 INFO L287 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-07-14 16:01:59,442 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 271 states and 416 transitions. [2022-07-14 16:01:59,443 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 148 [2022-07-14 16:01:59,443 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:01:59,443 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:01:59,444 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:01:59,444 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:01:59,444 INFO L752 eck$LassoCheckResult]: Stem: 3403#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 3311#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 3247#L490 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3248#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 3351#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 3352#L137-2 ~b0_req_up~0 := 0; 3342#L145 assume { :end_inline_update_b0 } true; 3343#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 3277#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 3278#L152-2 ~b1_req_up~0 := 0; 3385#L160 assume { :end_inline_update_b1 } true; 3383#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 3251#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 3252#L167-2 ~d0_req_up~0 := 0; 3215#L175 assume { :end_inline_update_d0 } true; 3216#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 3314#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 3262#L182-2 ~d1_req_up~0 := 0; 3263#L190 assume { :end_inline_update_d1 } true; 3350#L233-1 assume !(1 == ~z_req_up~0); 3358#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3245#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 3246#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3359#L321 assume !(0 == ~b0_ev~0); 3360#L321-2 assume !(0 == ~b1_ev~0); 3271#L326-1 assume !(0 == ~d0_ev~0); 3272#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 3225#L336-1 assume !(0 == ~z_ev~0); 3226#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 3406#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 3254#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 3339#L130 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 3340#L390 assume !(0 != activate_threads_~tmp~1#1); 3388#L390-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3334#L354 assume !(1 == ~b0_ev~0); 3307#L354-2 assume !(1 == ~b1_ev~0); 3308#L359-1 assume !(1 == ~d0_ev~0); 3309#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 3310#L369-1 assume !(1 == ~z_ev~0); 3319#L374-1 assume { :end_inline_reset_delta_events } true; 3391#L432-2 assume !false; 3290#L433 [2022-07-14 16:01:59,444 INFO L754 eck$LassoCheckResult]: Loop: 3290#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 3217#L295 assume !false; 3218#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 3256#L268 assume !(0 == ~comp_m1_st~0);exists_runnable_thread_~__retres1~1#1 := 0; 3258#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 3465#L276 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3464#L290 assume !(0 != eval_~tmp___0~0#1); 3315#L311 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3316#L212-3 assume !(1 == ~b0_req_up~0); 3362#L212-5 assume !(1 == ~b1_req_up~0); 3421#L219-3 assume !(1 == ~d0_req_up~0); 3209#L226-3 assume !(1 == ~d1_req_up~0); 3210#L233-3 assume !(1 == ~z_req_up~0); 3241#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3242#L321-3 assume !(0 == ~b0_ev~0); 3378#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 3430#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 3475#L331-3 assume !(0 == ~d1_ev~0); 3474#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 3473#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 3472#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 3468#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 3467#L130-1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 3466#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 3264#L390-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3265#L354-3 assume !(1 == ~b0_ev~0); 3458#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 3429#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 3455#L364-3 assume !(1 == ~d1_ev~0); 3376#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 3320#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 3321#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 3365#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 3305#L276-1 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 3237#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3238#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3396#L415 start_simulation_#t~ret8#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 3367#L449 assume !(0 != start_simulation_~tmp~3#1); 3289#L432-2 assume !false; 3290#L433 [2022-07-14 16:01:59,444 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:01:59,444 INFO L85 PathProgramCache]: Analyzing trace with hash 750743388, now seen corresponding path program 1 times [2022-07-14 16:01:59,444 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:01:59,444 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [189433452] [2022-07-14 16:01:59,445 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:01:59,445 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:01:59,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:01:59,458 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:01:59,458 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:01:59,459 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [189433452] [2022-07-14 16:01:59,459 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [189433452] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:01:59,459 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:01:59,459 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:01:59,459 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1806250491] [2022-07-14 16:01:59,459 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:01:59,459 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:01:59,459 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:01:59,459 INFO L85 PathProgramCache]: Analyzing trace with hash 618560829, now seen corresponding path program 1 times [2022-07-14 16:01:59,459 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:01:59,459 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2127910345] [2022-07-14 16:01:59,459 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:01:59,460 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:01:59,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:01:59,468 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:01:59,469 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:01:59,469 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2127910345] [2022-07-14 16:01:59,469 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2127910345] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:01:59,469 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:01:59,469 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:01:59,469 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1751816535] [2022-07-14 16:01:59,469 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:01:59,469 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:01:59,469 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:01:59,469 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:01:59,469 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:01:59,470 INFO L87 Difference]: Start difference. First operand 271 states and 416 transitions. cyclomatic complexity: 148 Second operand has 3 states, 3 states have (on average 13.0) internal successors, (39), 3 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:01:59,488 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:01:59,488 INFO L93 Difference]: Finished difference Result 313 states and 475 transitions. [2022-07-14 16:01:59,488 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:01:59,489 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 313 states and 475 transitions. [2022-07-14 16:01:59,490 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 159 [2022-07-14 16:01:59,491 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 313 states to 303 states and 459 transitions. [2022-07-14 16:01:59,492 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 217 [2022-07-14 16:01:59,492 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 217 [2022-07-14 16:01:59,492 INFO L73 IsDeterministic]: Start isDeterministic. Operand 303 states and 459 transitions. [2022-07-14 16:01:59,492 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-07-14 16:01:59,492 INFO L369 hiAutomatonCegarLoop]: Abstraction has 303 states and 459 transitions. [2022-07-14 16:01:59,492 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 303 states and 459 transitions. [2022-07-14 16:01:59,495 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 303 to 303. [2022-07-14 16:01:59,495 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 303 states, 303 states have (on average 1.5148514851485149) internal successors, (459), 302 states have internal predecessors, (459), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:01:59,496 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 303 states to 303 states and 459 transitions. [2022-07-14 16:01:59,496 INFO L392 hiAutomatonCegarLoop]: Abstraction has 303 states and 459 transitions. [2022-07-14 16:01:59,496 INFO L374 stractBuchiCegarLoop]: Abstraction has 303 states and 459 transitions. [2022-07-14 16:01:59,496 INFO L287 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-07-14 16:01:59,496 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 303 states and 459 transitions. [2022-07-14 16:01:59,497 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 159 [2022-07-14 16:01:59,497 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:01:59,497 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:01:59,497 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:01:59,497 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:01:59,498 INFO L752 eck$LassoCheckResult]: Stem: 3995#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 3900#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 3839#L490 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3840#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 3943#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 3944#L137-2 ~b0_req_up~0 := 0; 3933#L145 assume { :end_inline_update_b0 } true; 3934#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 3868#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 3869#L152-2 ~b1_req_up~0 := 0; 3976#L160 assume { :end_inline_update_b1 } true; 3974#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 3843#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 3844#L167-2 ~d0_req_up~0 := 0; 3806#L175 assume { :end_inline_update_d0 } true; 3807#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 3904#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 3854#L182-2 ~d1_req_up~0 := 0; 3855#L190 assume { :end_inline_update_d1 } true; 3942#L233-1 assume !(1 == ~z_req_up~0); 3950#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3837#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 3838#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3951#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 3952#L321-2 assume !(0 == ~b1_ev~0); 3862#L326-1 assume !(0 == ~d0_ev~0); 3863#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 3816#L336-1 assume !(0 == ~z_ev~0); 3817#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 3999#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 3991#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 3930#L130 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 3931#L390 assume !(0 != activate_threads_~tmp~1#1); 3977#L390-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3925#L354 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 3896#L354-2 assume !(1 == ~b1_ev~0); 3897#L359-1 assume !(1 == ~d0_ev~0); 3898#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 3899#L369-1 assume !(1 == ~z_ev~0); 3909#L374-1 assume { :end_inline_reset_delta_events } true; 3981#L432-2 assume !false; 3879#L433 [2022-07-14 16:01:59,498 INFO L754 eck$LassoCheckResult]: Loop: 3879#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 3808#L295 assume !false; 3809#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 3848#L268 assume !(0 == ~comp_m1_st~0);exists_runnable_thread_~__retres1~1#1 := 0; 3850#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 4061#L276 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4060#L290 assume !(0 != eval_~tmp___0~0#1); 3905#L311 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3906#L212-3 assume !(1 == ~b0_req_up~0); 3955#L212-5 assume !(1 == ~b1_req_up~0); 3883#L219-3 assume !(1 == ~d0_req_up~0); 4047#L226-3 assume !(1 == ~d1_req_up~0); 4045#L233-3 assume !(1 == ~z_req_up~0); 4043#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4042#L321-3 assume !(0 == ~b0_ev~0); 4041#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 4040#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 4039#L331-3 assume !(0 == ~d1_ev~0); 4038#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 4037#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 4018#L107-1 assume !(1 == ~b0_ev~0); 3989#L111-1 assume 1 == ~b1_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 3865#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 3901#L130-1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 3812#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 3813#L390-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3856#L354-3 assume !(1 == ~b0_ev~0); 3872#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 3984#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 3972#L364-3 assume !(1 == ~d1_ev~0); 3968#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 3910#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 3911#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 3958#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 3894#L276-1 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 3829#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3830#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3987#L415 start_simulation_#t~ret8#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 3960#L449 assume !(0 != start_simulation_~tmp~3#1); 3878#L432-2 assume !false; 3879#L433 [2022-07-14 16:01:59,498 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:01:59,498 INFO L85 PathProgramCache]: Analyzing trace with hash 969880732, now seen corresponding path program 1 times [2022-07-14 16:01:59,498 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:01:59,498 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [616617977] [2022-07-14 16:01:59,498 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:01:59,498 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:01:59,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:01:59,510 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:01:59,510 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:01:59,510 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [616617977] [2022-07-14 16:01:59,510 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [616617977] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:01:59,510 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:01:59,511 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:01:59,511 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [498546080] [2022-07-14 16:01:59,511 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:01:59,511 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:01:59,511 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:01:59,511 INFO L85 PathProgramCache]: Analyzing trace with hash 571541896, now seen corresponding path program 1 times [2022-07-14 16:01:59,511 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:01:59,511 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1728475968] [2022-07-14 16:01:59,511 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:01:59,511 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:01:59,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:01:59,516 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:01:59,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:01:59,521 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:01:59,609 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2022-07-14 16:01:59,787 INFO L210 LassoAnalysis]: Preferences: [2022-07-14 16:01:59,787 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-07-14 16:01:59,787 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-07-14 16:01:59,787 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-07-14 16:01:59,787 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2022-07-14 16:01:59,787 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 16:01:59,787 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-07-14 16:01:59,787 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-07-14 16:01:59,787 INFO L133 ssoRankerPreferences]: Filename of dumped script: bist_cell.cil.c_Iteration11_Loop [2022-07-14 16:01:59,787 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-07-14 16:01:59,787 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-07-14 16:01:59,788 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:59,791 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:59,792 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:59,796 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:59,797 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:59,798 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:59,802 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:59,804 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:59,806 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:59,807 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:59,810 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:59,812 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:59,813 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:59,815 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:59,816 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:59,817 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:59,820 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:59,821 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:59,825 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:59,828 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:59,829 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:59,833 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:01:59,836 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:02:00,004 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-07-14 16:02:00,004 INFO L404 LassoAnalysis]: Checking for nontermination... [2022-07-14 16:02:00,004 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 16:02:00,004 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 16:02:00,005 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-14 16:02:00,017 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2022-07-14 16:02:00,017 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-07-14 16:02:00,026 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2022-07-14 16:02:00,035 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2022-07-14 16:02:00,035 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Honda state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2022-07-14 16:02:00,052 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2022-07-14 16:02:00,052 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 16:02:00,053 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 16:02:00,068 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-14 16:02:00,069 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2022-07-14 16:02:00,070 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2022-07-14 16:02:00,070 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-07-14 16:02:00,091 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2022-07-14 16:02:00,091 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_#t~ret7#1=0} Honda state: {ULTIMATE.start_stop_simulation_#t~ret7#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2022-07-14 16:02:00,108 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Forceful destruction successful, exit code 0 [2022-07-14 16:02:00,109 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 16:02:00,109 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 16:02:00,124 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-14 16:02:00,129 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2022-07-14 16:02:00,129 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-07-14 16:02:00,138 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2022-07-14 16:02:00,164 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2022-07-14 16:02:00,164 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 16:02:00,164 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 16:02:00,165 INFO L229 MonitoredProcess]: Starting monitored process 12 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-14 16:02:00,182 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2022-07-14 16:02:00,182 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-07-14 16:02:00,191 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2022-07-14 16:02:00,211 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2022-07-14 16:02:00,251 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2022-07-14 16:02:00,251 INFO L210 LassoAnalysis]: Preferences: [2022-07-14 16:02:00,251 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-07-14 16:02:00,251 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-07-14 16:02:00,251 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-07-14 16:02:00,251 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2022-07-14 16:02:00,251 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 16:02:00,251 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-07-14 16:02:00,252 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-07-14 16:02:00,252 INFO L133 ssoRankerPreferences]: Filename of dumped script: bist_cell.cil.c_Iteration11_Loop [2022-07-14 16:02:00,252 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-07-14 16:02:00,252 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-07-14 16:02:00,253 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:02:00,256 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:02:00,258 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:02:00,260 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:02:00,261 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:02:00,264 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:02:00,267 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:02:00,269 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:02:00,271 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:02:00,272 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:02:00,277 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:02:00,278 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:02:00,280 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:02:00,282 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:02:00,284 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:02:00,286 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:02:00,290 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:02:00,292 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:02:00,294 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:02:00,297 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:02:00,299 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:02:00,303 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:02:00,308 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 16:02:00,477 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-07-14 16:02:00,477 INFO L490 LassoAnalysis]: Using template 'affine'. [2022-07-14 16:02:00,477 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 16:02:00,477 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 16:02:00,478 INFO L229 MonitoredProcess]: Starting monitored process 13 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-14 16:02:00,500 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2022-07-14 16:02:00,501 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-07-14 16:02:00,507 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-07-14 16:02:00,507 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-07-14 16:02:00,507 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-07-14 16:02:00,507 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-07-14 16:02:00,507 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-07-14 16:02:00,508 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-07-14 16:02:00,508 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-07-14 16:02:00,522 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2022-07-14 16:02:00,523 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2022-07-14 16:02:00,523 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2022-07-14 16:02:00,524 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 16:02:00,524 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 16:02:00,525 INFO L229 MonitoredProcess]: Starting monitored process 14 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-14 16:02:00,527 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2022-07-14 16:02:00,529 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2022-07-14 16:02:00,529 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2022-07-14 16:02:00,529 INFO L513 LassoAnalysis]: Proved termination. [2022-07-14 16:02:00,529 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(~d0_ev~0) = -1*~d0_ev~0 + 1 Supporting invariants [] [2022-07-14 16:02:00,580 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Forceful destruction successful, exit code 0 [2022-07-14 16:02:00,581 INFO L293 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2022-07-14 16:02:00,600 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:00,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:00,620 INFO L263 TraceCheckSpWp]: Trace formula consists of 193 conjuncts, 2 conjunts are in the unsatisfiable core [2022-07-14 16:02:00,621 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 16:02:00,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:00,666 INFO L263 TraceCheckSpWp]: Trace formula consists of 85 conjuncts, 4 conjunts are in the unsatisfiable core [2022-07-14 16:02:00,666 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 16:02:00,727 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:00,728 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2022-07-14 16:02:00,728 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 303 states and 459 transitions. cyclomatic complexity: 159 Second operand has 5 states, 5 states have (on average 16.2) internal successors, (81), 5 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:00,750 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 303 states and 459 transitions. cyclomatic complexity: 159. Second operand has 5 states, 5 states have (on average 16.2) internal successors, (81), 5 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 810 states and 1251 transitions. Complement of second has 5 states. [2022-07-14 16:02:00,750 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2022-07-14 16:02:00,751 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 16.2) internal successors, (81), 5 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:00,751 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 181 transitions. [2022-07-14 16:02:00,751 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 181 transitions. Stem has 41 letters. Loop has 40 letters. [2022-07-14 16:02:00,752 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-07-14 16:02:00,752 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 181 transitions. Stem has 81 letters. Loop has 40 letters. [2022-07-14 16:02:00,752 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-07-14 16:02:00,752 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 181 transitions. Stem has 41 letters. Loop has 80 letters. [2022-07-14 16:02:00,753 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-07-14 16:02:00,753 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 810 states and 1251 transitions. [2022-07-14 16:02:00,757 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 318 [2022-07-14 16:02:00,774 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 810 states to 810 states and 1251 transitions. [2022-07-14 16:02:00,774 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 378 [2022-07-14 16:02:00,774 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 384 [2022-07-14 16:02:00,775 INFO L73 IsDeterministic]: Start isDeterministic. Operand 810 states and 1251 transitions. [2022-07-14 16:02:00,775 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-07-14 16:02:00,775 INFO L369 hiAutomatonCegarLoop]: Abstraction has 810 states and 1251 transitions. [2022-07-14 16:02:00,775 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 810 states and 1251 transitions. [2022-07-14 16:02:00,785 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 810 to 804. [2022-07-14 16:02:00,786 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 804 states, 804 states have (on average 1.5422885572139304) internal successors, (1240), 803 states have internal predecessors, (1240), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:00,790 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 804 states to 804 states and 1240 transitions. [2022-07-14 16:02:00,790 INFO L392 hiAutomatonCegarLoop]: Abstraction has 804 states and 1240 transitions. [2022-07-14 16:02:00,790 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:00,790 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:02:00,790 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:02:00,790 INFO L87 Difference]: Start difference. First operand 804 states and 1240 transitions. Second operand has 3 states, 3 states have (on average 13.666666666666666) internal successors, (41), 3 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:00,807 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:00,807 INFO L93 Difference]: Finished difference Result 963 states and 1454 transitions. [2022-07-14 16:02:00,807 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:02:00,808 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 963 states and 1454 transitions. [2022-07-14 16:02:00,813 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Forceful destruction successful, exit code 0 [2022-07-14 16:02:00,817 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 388 [2022-07-14 16:02:00,820 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 963 states to 963 states and 1454 transitions. [2022-07-14 16:02:00,820 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 448 [2022-07-14 16:02:00,821 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 448 [2022-07-14 16:02:00,821 INFO L73 IsDeterministic]: Start isDeterministic. Operand 963 states and 1454 transitions. [2022-07-14 16:02:00,821 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-07-14 16:02:00,821 INFO L369 hiAutomatonCegarLoop]: Abstraction has 963 states and 1454 transitions. [2022-07-14 16:02:00,821 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 963 states and 1454 transitions. [2022-07-14 16:02:00,829 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 963 to 963. [2022-07-14 16:02:00,830 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 963 states, 963 states have (on average 1.509865005192108) internal successors, (1454), 962 states have internal predecessors, (1454), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:00,832 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 963 states to 963 states and 1454 transitions. [2022-07-14 16:02:00,832 INFO L392 hiAutomatonCegarLoop]: Abstraction has 963 states and 1454 transitions. [2022-07-14 16:02:00,832 INFO L374 stractBuchiCegarLoop]: Abstraction has 963 states and 1454 transitions. [2022-07-14 16:02:00,832 INFO L287 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-07-14 16:02:00,832 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 963 states and 1454 transitions. [2022-07-14 16:02:00,835 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 388 [2022-07-14 16:02:00,835 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:00,835 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:00,835 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:00,835 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:00,836 INFO L752 eck$LassoCheckResult]: Stem: 7154#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 7047#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 6982#L490 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6983#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 7091#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 7092#L137-2 ~b0_req_up~0 := 0; 7081#L145 assume { :end_inline_update_b0 } true; 7082#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 7014#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 7015#L152-2 ~b1_req_up~0 := 0; 7129#L160 assume { :end_inline_update_b1 } true; 7127#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 6987#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 6988#L167-2 ~d0_req_up~0 := 0; 6950#L175 assume { :end_inline_update_d0 } true; 6951#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 7051#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 6998#L182-2 ~d1_req_up~0 := 0; 6999#L190 assume { :end_inline_update_d1 } true; 7090#L233-1 assume !(1 == ~z_req_up~0); 7098#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6980#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 6981#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7099#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 7100#L321-2 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 7166#L326-1 assume !(0 == ~d0_ev~0); 7009#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 6960#L336-1 assume !(0 == ~z_ev~0); 6961#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 7158#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 7149#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 7078#L130 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 7079#L390 assume !(0 != activate_threads_~tmp~1#1); 7130#L390-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7072#L354 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 7043#L354-2 assume !(1 == ~b1_ev~0); 7044#L359-1 assume !(1 == ~d0_ev~0); 7045#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 7046#L369-1 assume !(1 == ~z_ev~0); 7056#L374-1 assume { :end_inline_reset_delta_events } true; 7134#L432-2 assume !false; 7325#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 6952#L295 [2022-07-14 16:02:00,836 INFO L754 eck$LassoCheckResult]: Loop: 6952#L295 assume !false; 6953#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 7128#L268 assume !(0 == ~comp_m1_st~0);exists_runnable_thread_~__retres1~1#1 := 0; 7713#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 7708#L276 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7706#L290 assume 0 != eval_~tmp___0~0#1; 7152#L290-1 assume !(0 == ~comp_m1_st~0); 6952#L295 [2022-07-14 16:02:00,836 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:00,836 INFO L85 PathProgramCache]: Analyzing trace with hash 1995676522, now seen corresponding path program 1 times [2022-07-14 16:02:00,836 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:00,836 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [891855741] [2022-07-14 16:02:00,836 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:00,836 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:00,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:00,850 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:00,850 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:00,850 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [891855741] [2022-07-14 16:02:00,850 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [891855741] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:00,850 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:00,850 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:00,852 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [501993907] [2022-07-14 16:02:00,852 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:00,853 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:00,853 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:00,853 INFO L85 PathProgramCache]: Analyzing trace with hash 831114558, now seen corresponding path program 1 times [2022-07-14 16:02:00,853 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:00,854 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [825283701] [2022-07-14 16:02:00,854 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:00,854 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:00,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:00,892 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:00,892 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:00,893 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [825283701] [2022-07-14 16:02:00,893 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [825283701] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:00,893 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:00,893 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:02:00,893 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2015362384] [2022-07-14 16:02:00,893 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:00,893 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:00,893 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:00,894 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-07-14 16:02:00,894 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-07-14 16:02:00,895 INFO L87 Difference]: Start difference. First operand 963 states and 1454 transitions. cyclomatic complexity: 500 Second operand has 5 states, 5 states have (on average 1.4) internal successors, (7), 5 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:00,935 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:00,936 INFO L93 Difference]: Finished difference Result 1053 states and 1544 transitions. [2022-07-14 16:02:00,936 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-07-14 16:02:00,936 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1053 states and 1544 transitions. [2022-07-14 16:02:00,941 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 428 [2022-07-14 16:02:00,946 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1053 states to 1053 states and 1544 transitions. [2022-07-14 16:02:00,946 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 488 [2022-07-14 16:02:00,946 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 488 [2022-07-14 16:02:00,946 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1053 states and 1544 transitions. [2022-07-14 16:02:00,946 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-07-14 16:02:00,946 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1053 states and 1544 transitions. [2022-07-14 16:02:00,951 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1053 states and 1544 transitions. [2022-07-14 16:02:00,958 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1053 to 963. [2022-07-14 16:02:00,959 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 963 states, 963 states have (on average 1.5005192107995846) internal successors, (1445), 962 states have internal predecessors, (1445), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:00,961 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 963 states to 963 states and 1445 transitions. [2022-07-14 16:02:00,962 INFO L392 hiAutomatonCegarLoop]: Abstraction has 963 states and 1445 transitions. [2022-07-14 16:02:00,962 INFO L374 stractBuchiCegarLoop]: Abstraction has 963 states and 1445 transitions. [2022-07-14 16:02:00,962 INFO L287 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-07-14 16:02:00,962 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 963 states and 1445 transitions. [2022-07-14 16:02:00,965 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 388 [2022-07-14 16:02:00,965 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:00,965 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:00,966 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:00,966 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:00,967 INFO L752 eck$LassoCheckResult]: Stem: 9189#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 9078#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 9014#L490 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9015#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 9120#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 9121#L137-2 ~b0_req_up~0 := 0; 9111#L145 assume { :end_inline_update_b0 } true; 9112#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 9045#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 9046#L152-2 ~b1_req_up~0 := 0; 9162#L160 assume { :end_inline_update_b1 } true; 9159#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 9019#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 9020#L167-2 ~d0_req_up~0 := 0; 8982#L175 assume { :end_inline_update_d0 } true; 8983#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 9082#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 9030#L182-2 ~d1_req_up~0 := 0; 9031#L190 assume { :end_inline_update_d1 } true; 9119#L233-1 assume !(1 == ~z_req_up~0); 9127#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9012#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 9013#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9128#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 9129#L321-2 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 9202#L326-1 assume !(0 == ~d0_ev~0); 9040#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 8992#L336-1 assume !(0 == ~z_ev~0); 8993#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 9194#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 9185#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 9108#L130 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 9109#L390 assume !(0 != activate_threads_~tmp~1#1); 9163#L390-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9103#L354 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 9074#L354-2 assume !(1 == ~b1_ev~0); 9075#L359-1 assume !(1 == ~d0_ev~0); 9076#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 9077#L369-1 assume !(1 == ~z_ev~0); 9087#L374-1 assume { :end_inline_reset_delta_events } true; 9168#L432-2 assume !false; 9608#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 9521#L295 [2022-07-14 16:02:00,967 INFO L754 eck$LassoCheckResult]: Loop: 9521#L295 assume !false; 9426#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 9420#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 9179#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 8978#L276 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8979#L290 assume 0 != eval_~tmp___0~0#1; 9195#L290-1 assume !(0 == ~comp_m1_st~0); 9521#L295 [2022-07-14 16:02:00,967 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:00,967 INFO L85 PathProgramCache]: Analyzing trace with hash 1995676522, now seen corresponding path program 2 times [2022-07-14 16:02:00,967 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:00,967 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2109051149] [2022-07-14 16:02:00,968 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:00,968 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:00,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:00,989 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:00,990 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:00,990 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2109051149] [2022-07-14 16:02:00,990 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2109051149] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:00,990 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:00,990 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:00,990 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1771719203] [2022-07-14 16:02:00,991 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:00,991 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:00,991 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:00,991 INFO L85 PathProgramCache]: Analyzing trace with hash 829267516, now seen corresponding path program 1 times [2022-07-14 16:02:00,991 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:00,991 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1302413248] [2022-07-14 16:02:00,991 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:00,992 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:00,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:00,998 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:00,998 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:00,998 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1302413248] [2022-07-14 16:02:00,998 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1302413248] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:00,998 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:00,998 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-14 16:02:00,998 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1163426854] [2022-07-14 16:02:00,998 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:00,999 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:00,999 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:00,999 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:02:00,999 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:02:00,999 INFO L87 Difference]: Start difference. First operand 963 states and 1445 transitions. cyclomatic complexity: 491 Second operand has 3 states, 2 states have (on average 3.5) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:01,014 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:01,014 INFO L93 Difference]: Finished difference Result 1188 states and 1749 transitions. [2022-07-14 16:02:01,015 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:02:01,015 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1188 states and 1749 transitions. [2022-07-14 16:02:01,020 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 468 [2022-07-14 16:02:01,024 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1188 states to 1188 states and 1749 transitions. [2022-07-14 16:02:01,024 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 563 [2022-07-14 16:02:01,025 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 563 [2022-07-14 16:02:01,025 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1188 states and 1749 transitions. [2022-07-14 16:02:01,025 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-07-14 16:02:01,025 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1188 states and 1749 transitions. [2022-07-14 16:02:01,026 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1188 states and 1749 transitions. [2022-07-14 16:02:01,035 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1188 to 1188. [2022-07-14 16:02:01,037 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1188 states, 1188 states have (on average 1.4722222222222223) internal successors, (1749), 1187 states have internal predecessors, (1749), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:01,039 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1188 states to 1188 states and 1749 transitions. [2022-07-14 16:02:01,039 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1188 states and 1749 transitions. [2022-07-14 16:02:01,039 INFO L374 stractBuchiCegarLoop]: Abstraction has 1188 states and 1749 transitions. [2022-07-14 16:02:01,040 INFO L287 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-07-14 16:02:01,040 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1188 states and 1749 transitions. [2022-07-14 16:02:01,043 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 468 [2022-07-14 16:02:01,043 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:01,043 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:01,045 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:01,045 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:01,045 INFO L752 eck$LassoCheckResult]: Stem: 11349#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 11237#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 11175#L490 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11176#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 11283#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 11284#L137-2 ~b0_req_up~0 := 0; 11273#L145 assume { :end_inline_update_b0 } true; 11274#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 11203#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 11204#L152-2 ~b1_req_up~0 := 0; 11323#L160 assume { :end_inline_update_b1 } true; 11317#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 11179#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 11180#L167-2 ~d0_req_up~0 := 0; 11140#L175 assume { :end_inline_update_d0 } true; 11141#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 11241#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 11188#L182-2 ~d1_req_up~0 := 0; 11189#L190 assume { :end_inline_update_d1 } true; 11282#L233-1 assume !(1 == ~z_req_up~0); 11290#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11172#L255 assume 1 == ~comp_m1_i~0;~comp_m1_st~0 := 0; 11173#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11909#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 11910#L321-2 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 11914#L326-1 assume !(0 == ~d0_ev~0); 11913#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 11912#L336-1 assume !(0 == ~z_ev~0); 11911#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 11901#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 11900#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 11899#L130 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 11898#L390 assume !(0 != activate_threads_~tmp~1#1); 11325#L390-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11897#L354 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 11895#L354-2 assume !(1 == ~b1_ev~0); 11894#L359-1 assume !(1 == ~d0_ev~0); 11893#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 11892#L369-1 assume !(1 == ~z_ev~0); 11891#L374-1 assume { :end_inline_reset_delta_events } true; 11889#L432-2 assume !false; 11793#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 11636#L295 [2022-07-14 16:02:01,045 INFO L754 eck$LassoCheckResult]: Loop: 11636#L295 assume !false; 11644#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 11643#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 11381#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 11640#L276 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11638#L290 assume 0 != eval_~tmp___0~0#1; 11637#L290-1 assume 0 == ~comp_m1_st~0;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 11635#L299 assume !(0 != eval_~tmp~0#1); 11636#L295 [2022-07-14 16:02:01,046 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:01,046 INFO L85 PathProgramCache]: Analyzing trace with hash 1572974696, now seen corresponding path program 1 times [2022-07-14 16:02:01,046 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:01,046 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2096219295] [2022-07-14 16:02:01,047 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:01,047 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:01,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:01,069 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:01,069 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:01,070 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2096219295] [2022-07-14 16:02:01,070 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2096219295] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:01,070 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:01,071 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-07-14 16:02:01,071 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1449071605] [2022-07-14 16:02:01,071 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:01,073 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:01,073 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:01,073 INFO L85 PathProgramCache]: Analyzing trace with hash -62512628, now seen corresponding path program 1 times [2022-07-14 16:02:01,073 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:01,073 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2118045908] [2022-07-14 16:02:01,073 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:01,073 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:01,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:01,076 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:02:01,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:01,080 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:02:01,105 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:01,106 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:02:01,106 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:02:01,106 INFO L87 Difference]: Start difference. First operand 1188 states and 1749 transitions. cyclomatic complexity: 570 Second operand has 4 states, 4 states have (on average 10.5) internal successors, (42), 4 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:01,122 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:01,123 INFO L93 Difference]: Finished difference Result 1165 states and 1712 transitions. [2022-07-14 16:02:01,123 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:02:01,123 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1165 states and 1712 transitions. [2022-07-14 16:02:01,127 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 468 [2022-07-14 16:02:01,131 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1165 states to 1165 states and 1712 transitions. [2022-07-14 16:02:01,131 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 540 [2022-07-14 16:02:01,132 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 540 [2022-07-14 16:02:01,132 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1165 states and 1712 transitions. [2022-07-14 16:02:01,132 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-07-14 16:02:01,132 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1165 states and 1712 transitions. [2022-07-14 16:02:01,132 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1165 states and 1712 transitions. [2022-07-14 16:02:01,141 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1165 to 1165. [2022-07-14 16:02:01,142 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1165 states, 1165 states have (on average 1.4695278969957082) internal successors, (1712), 1164 states have internal predecessors, (1712), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:01,145 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1165 states to 1165 states and 1712 transitions. [2022-07-14 16:02:01,145 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1165 states and 1712 transitions. [2022-07-14 16:02:01,145 INFO L374 stractBuchiCegarLoop]: Abstraction has 1165 states and 1712 transitions. [2022-07-14 16:02:01,145 INFO L287 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-07-14 16:02:01,145 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1165 states and 1712 transitions. [2022-07-14 16:02:01,148 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 468 [2022-07-14 16:02:01,148 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:01,148 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:01,149 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:01,149 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:01,149 INFO L752 eck$LassoCheckResult]: Stem: 13723#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 13601#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 13536#L490 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13537#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 13646#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 13647#L137-2 ~b0_req_up~0 := 0; 13636#L145 assume { :end_inline_update_b0 } true; 13637#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 13566#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 13567#L152-2 ~b1_req_up~0 := 0; 13682#L160 assume { :end_inline_update_b1 } true; 13680#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 13540#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 13541#L167-2 ~d0_req_up~0 := 0; 13502#L175 assume { :end_inline_update_d0 } true; 13503#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 13602#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 13545#L182-2 ~d1_req_up~0 := 0; 13546#L190 assume { :end_inline_update_d1 } true; 13645#L233-1 assume !(1 == ~z_req_up~0); 13653#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13530#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 13531#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13654#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 13655#L321-2 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 13554#L326-1 assume !(0 == ~d0_ev~0); 13555#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 13508#L336-1 assume !(0 == ~z_ev~0); 13509#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 13730#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 13716#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 13717#L130 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 13686#L390 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 13687#L390-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13628#L354 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 13594#L354-2 assume !(1 == ~b1_ev~0); 13595#L359-1 assume !(1 == ~d0_ev~0); 13599#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 13600#L369-1 assume !(1 == ~z_ev~0); 13606#L374-1 assume { :end_inline_reset_delta_events } true; 14219#L432-2 assume !false; 14220#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 14050#L295 [2022-07-14 16:02:01,149 INFO L754 eck$LassoCheckResult]: Loop: 14050#L295 assume !false; 14055#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 14054#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 13946#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 14053#L276 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 14052#L290 assume 0 != eval_~tmp___0~0#1; 14051#L290-1 assume 0 == ~comp_m1_st~0;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 14049#L299 assume !(0 != eval_~tmp~0#1); 14050#L295 [2022-07-14 16:02:01,149 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:01,149 INFO L85 PathProgramCache]: Analyzing trace with hash -1906263764, now seen corresponding path program 1 times [2022-07-14 16:02:01,149 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:01,150 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [602915856] [2022-07-14 16:02:01,150 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:01,150 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:01,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:01,161 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:01,161 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:01,161 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [602915856] [2022-07-14 16:02:01,161 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [602915856] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:01,161 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:01,161 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:01,161 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [704295589] [2022-07-14 16:02:01,162 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:01,162 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:01,162 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:01,162 INFO L85 PathProgramCache]: Analyzing trace with hash -62512628, now seen corresponding path program 2 times [2022-07-14 16:02:01,162 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:01,162 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2076290077] [2022-07-14 16:02:01,162 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:01,163 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:01,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:01,165 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:02:01,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:01,167 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:02:01,190 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:01,191 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:02:01,191 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:02:01,191 INFO L87 Difference]: Start difference. First operand 1165 states and 1712 transitions. cyclomatic complexity: 556 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:01,217 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:01,217 INFO L93 Difference]: Finished difference Result 1252 states and 1830 transitions. [2022-07-14 16:02:01,217 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:02:01,218 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1252 states and 1830 transitions. [2022-07-14 16:02:01,223 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 525 [2022-07-14 16:02:01,226 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1252 states to 1252 states and 1830 transitions. [2022-07-14 16:02:01,227 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 597 [2022-07-14 16:02:01,227 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 597 [2022-07-14 16:02:01,227 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1252 states and 1830 transitions. [2022-07-14 16:02:01,227 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-07-14 16:02:01,227 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1252 states and 1830 transitions. [2022-07-14 16:02:01,228 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1252 states and 1830 transitions. [2022-07-14 16:02:01,238 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1252 to 1252. [2022-07-14 16:02:01,239 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1252 states, 1252 states have (on average 1.461661341853035) internal successors, (1830), 1251 states have internal predecessors, (1830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:01,242 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1252 states to 1252 states and 1830 transitions. [2022-07-14 16:02:01,242 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1252 states and 1830 transitions. [2022-07-14 16:02:01,242 INFO L374 stractBuchiCegarLoop]: Abstraction has 1252 states and 1830 transitions. [2022-07-14 16:02:01,242 INFO L287 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-07-14 16:02:01,242 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1252 states and 1830 transitions. [2022-07-14 16:02:01,245 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 525 [2022-07-14 16:02:01,245 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:01,246 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:01,246 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:01,246 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:01,246 INFO L752 eck$LassoCheckResult]: Stem: 16145#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 16026#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 15960#L490 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15961#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 16073#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 16074#L137-2 ~b0_req_up~0 := 0; 16064#L145 assume { :end_inline_update_b0 } true; 16065#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 15992#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 15993#L152-2 ~b1_req_up~0 := 0; 16109#L160 assume { :end_inline_update_b1 } true; 16108#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 15965#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 15966#L167-2 ~d0_req_up~0 := 0; 15925#L175 assume { :end_inline_update_d0 } true; 15926#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 16027#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 15970#L182-2 ~d1_req_up~0 := 0; 15971#L190 assume { :end_inline_update_d1 } true; 16072#L233-1 assume !(1 == ~z_req_up~0); 16080#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15954#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 15955#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16081#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 16082#L321-2 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 15980#L326-1 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 15981#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 15931#L336-1 assume !(0 == ~z_ev~0); 15932#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 16149#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 16137#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 16138#L130 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 16114#L390 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 16115#L390-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16144#L354 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 16020#L354-2 assume !(1 == ~b1_ev~0); 16021#L359-1 assume !(1 == ~d0_ev~0); 16024#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 16025#L369-1 assume !(1 == ~z_ev~0); 16119#L374-1 assume { :end_inline_reset_delta_events } true; 16120#L432-2 assume !false; 16784#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 16619#L295 [2022-07-14 16:02:01,246 INFO L754 eck$LassoCheckResult]: Loop: 16619#L295 assume !false; 16624#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 16623#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 16416#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 16622#L276 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 16621#L290 assume 0 != eval_~tmp___0~0#1; 16620#L290-1 assume 0 == ~comp_m1_st~0;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 16618#L299 assume !(0 != eval_~tmp~0#1); 16619#L295 [2022-07-14 16:02:01,247 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:01,247 INFO L85 PathProgramCache]: Analyzing trace with hash -317915862, now seen corresponding path program 1 times [2022-07-14 16:02:01,247 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:01,247 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [774815174] [2022-07-14 16:02:01,247 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:01,247 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:01,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:01,267 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:01,267 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:01,267 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [774815174] [2022-07-14 16:02:01,267 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [774815174] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:01,268 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:01,268 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:01,269 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1829365843] [2022-07-14 16:02:01,269 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:01,269 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:01,269 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:01,270 INFO L85 PathProgramCache]: Analyzing trace with hash -62512628, now seen corresponding path program 3 times [2022-07-14 16:02:01,270 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:01,270 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [885588083] [2022-07-14 16:02:01,270 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:01,270 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:01,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:01,273 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:02:01,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:01,278 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:02:01,303 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:01,304 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:02:01,304 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:02:01,304 INFO L87 Difference]: Start difference. First operand 1252 states and 1830 transitions. cyclomatic complexity: 587 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:01,320 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:01,320 INFO L93 Difference]: Finished difference Result 1473 states and 2140 transitions. [2022-07-14 16:02:01,321 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:02:01,321 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1473 states and 2140 transitions. [2022-07-14 16:02:01,327 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 612 [2022-07-14 16:02:01,333 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1473 states to 1473 states and 2140 transitions. [2022-07-14 16:02:01,333 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 682 [2022-07-14 16:02:01,333 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 682 [2022-07-14 16:02:01,333 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1473 states and 2140 transitions. [2022-07-14 16:02:01,334 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-07-14 16:02:01,334 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1473 states and 2140 transitions. [2022-07-14 16:02:01,334 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1473 states and 2140 transitions. [2022-07-14 16:02:01,347 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1473 to 1473. [2022-07-14 16:02:01,348 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1473 states, 1473 states have (on average 1.4528173794976238) internal successors, (2140), 1472 states have internal predecessors, (2140), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:01,352 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1473 states to 1473 states and 2140 transitions. [2022-07-14 16:02:01,352 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1473 states and 2140 transitions. [2022-07-14 16:02:01,353 INFO L374 stractBuchiCegarLoop]: Abstraction has 1473 states and 2140 transitions. [2022-07-14 16:02:01,353 INFO L287 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-07-14 16:02:01,353 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1473 states and 2140 transitions. [2022-07-14 16:02:01,358 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 612 [2022-07-14 16:02:01,358 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:01,358 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:01,361 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:01,361 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:01,362 INFO L752 eck$LassoCheckResult]: Stem: 18895#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 18754#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 18691#L490 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18692#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 18802#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 18803#L137-2 ~b0_req_up~0 := 0; 18793#L145 assume { :end_inline_update_b0 } true; 18794#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 18720#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 18721#L152-2 ~b1_req_up~0 := 0; 18849#L160 assume { :end_inline_update_b1 } true; 18842#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 18695#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 18696#L167-2 ~d0_req_up~0 := 0; 18656#L175 assume { :end_inline_update_d0 } true; 18657#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 18755#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 18699#L182-2 ~d1_req_up~0 := 0; 18700#L190 assume { :end_inline_update_d1 } true; 18801#L233-1 assume !(1 == ~z_req_up~0); 18809#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18689#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 18690#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18810#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 18811#L321-2 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 18712#L326-1 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 18713#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 18662#L336-1 assume !(0 == ~z_ev~0); 18663#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 18899#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 18886#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 18887#L130 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 18852#L390 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 18853#L390-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18894#L354 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 18747#L354-2 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 18748#L359-1 assume !(1 == ~d0_ev~0); 18752#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 18753#L369-1 assume !(1 == ~z_ev~0); 18865#L374-1 assume { :end_inline_reset_delta_events } true; 18866#L432-2 assume !false; 19046#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 19047#L295 [2022-07-14 16:02:01,362 INFO L754 eck$LassoCheckResult]: Loop: 19047#L295 assume !false; 19866#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 19865#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 19833#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 19864#L276 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 19863#L290 assume 0 != eval_~tmp___0~0#1; 19862#L290-1 assume 0 == ~comp_m1_st~0;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 19861#L299 assume !(0 != eval_~tmp~0#1); 19047#L295 [2022-07-14 16:02:01,363 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:01,364 INFO L85 PathProgramCache]: Analyzing trace with hash -2092923224, now seen corresponding path program 1 times [2022-07-14 16:02:01,364 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:01,364 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [707748974] [2022-07-14 16:02:01,364 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:01,364 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:01,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:01,375 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:01,376 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:01,376 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [707748974] [2022-07-14 16:02:01,376 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [707748974] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:01,376 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:01,376 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:01,376 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [223763958] [2022-07-14 16:02:01,378 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:01,378 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:01,378 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:01,378 INFO L85 PathProgramCache]: Analyzing trace with hash -62512628, now seen corresponding path program 4 times [2022-07-14 16:02:01,378 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:01,378 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1221728082] [2022-07-14 16:02:01,378 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:01,378 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:01,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:01,380 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:02:01,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:01,385 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:02:01,409 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:01,409 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:02:01,409 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:02:01,409 INFO L87 Difference]: Start difference. First operand 1473 states and 2140 transitions. cyclomatic complexity: 676 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:01,424 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:01,425 INFO L93 Difference]: Finished difference Result 1878 states and 2694 transitions. [2022-07-14 16:02:01,425 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:02:01,425 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1878 states and 2694 transitions. [2022-07-14 16:02:01,430 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 696 [2022-07-14 16:02:01,435 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1878 states to 1747 states and 2497 transitions. [2022-07-14 16:02:01,436 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 768 [2022-07-14 16:02:01,436 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 768 [2022-07-14 16:02:01,436 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1747 states and 2497 transitions. [2022-07-14 16:02:01,437 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-07-14 16:02:01,437 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1747 states and 2497 transitions. [2022-07-14 16:02:01,437 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1747 states and 2497 transitions. [2022-07-14 16:02:01,450 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1747 to 1747. [2022-07-14 16:02:01,452 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1747 states, 1747 states have (on average 1.4293073840870063) internal successors, (2497), 1746 states have internal predecessors, (2497), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:01,455 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1747 states to 1747 states and 2497 transitions. [2022-07-14 16:02:01,455 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1747 states and 2497 transitions. [2022-07-14 16:02:01,455 INFO L374 stractBuchiCegarLoop]: Abstraction has 1747 states and 2497 transitions. [2022-07-14 16:02:01,455 INFO L287 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-07-14 16:02:01,455 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1747 states and 2497 transitions. [2022-07-14 16:02:01,459 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 696 [2022-07-14 16:02:01,459 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:01,459 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:01,459 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:01,459 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:01,459 INFO L752 eck$LassoCheckResult]: Stem: 22252#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 22112#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 22047#L490 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22048#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 22163#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 22164#L137-2 ~b0_req_up~0 := 0; 22152#L145 assume { :end_inline_update_b0 } true; 22153#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 22077#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 22078#L152-2 ~b1_req_up~0 := 0; 22211#L160 assume { :end_inline_update_b1 } true; 22204#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 22051#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 22052#L167-2 ~d0_req_up~0 := 0; 22013#L175 assume { :end_inline_update_d0 } true; 22014#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 22117#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 22059#L182-2 ~d1_req_up~0 := 0; 22060#L190 assume { :end_inline_update_d1 } true; 22162#L233-1 assume !(1 == ~z_req_up~0); 22170#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22045#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 22046#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22171#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 22172#L321-2 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 22069#L326-1 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 22070#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 22025#L336-1 assume !(0 == ~z_ev~0); 22026#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 22258#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 22243#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 22244#L130 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 22214#L390 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 22215#L390-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22143#L354 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 22144#L354-2 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 22212#L359-1 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 22213#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 22122#L369-1 assume !(1 == ~z_ev~0); 22123#L374-1 assume { :end_inline_reset_delta_events } true; 22440#L432-2 assume !false; 23361#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 22429#L295 [2022-07-14 16:02:01,460 INFO L754 eck$LassoCheckResult]: Loop: 22429#L295 assume !false; 22430#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 22422#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 22423#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 22419#L276 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 22420#L290 assume 0 != eval_~tmp___0~0#1; 22415#L290-1 assume 0 == ~comp_m1_st~0;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 22416#L299 assume !(0 != eval_~tmp~0#1); 22429#L295 [2022-07-14 16:02:01,460 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:01,460 INFO L85 PathProgramCache]: Analyzing trace with hash 2144785770, now seen corresponding path program 1 times [2022-07-14 16:02:01,460 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:01,460 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [411066105] [2022-07-14 16:02:01,460 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:01,460 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:01,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:01,465 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:02:01,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:01,476 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:02:01,476 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:01,476 INFO L85 PathProgramCache]: Analyzing trace with hash -62512628, now seen corresponding path program 5 times [2022-07-14 16:02:01,476 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:01,477 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1509047308] [2022-07-14 16:02:01,477 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:01,477 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:01,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:01,482 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:02:01,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:01,484 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:02:01,484 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:01,484 INFO L85 PathProgramCache]: Analyzing trace with hash 109674101, now seen corresponding path program 1 times [2022-07-14 16:02:01,484 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:01,484 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [21519803] [2022-07-14 16:02:01,484 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:01,484 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:01,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:01,489 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:02:01,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:01,511 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:02:02,154 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 14.07 04:02:02 BoogieIcfgContainer [2022-07-14 16:02:02,154 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-07-14 16:02:02,154 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-07-14 16:02:02,154 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-07-14 16:02:02,154 INFO L275 PluginConnector]: Witness Printer initialized [2022-07-14 16:02:02,155 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.07 04:01:56" (3/4) ... [2022-07-14 16:02:02,156 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-07-14 16:02:02,183 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2022-07-14 16:02:02,183 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-07-14 16:02:02,184 INFO L158 Benchmark]: Toolchain (without parser) took 6385.21ms. Allocated memory was 142.6MB in the beginning and 213.9MB in the end (delta: 71.3MB). Free memory was 112.0MB in the beginning and 126.6MB in the end (delta: -14.6MB). Peak memory consumption was 56.6MB. Max. memory is 16.1GB. [2022-07-14 16:02:02,184 INFO L158 Benchmark]: CDTParser took 0.13ms. Allocated memory is still 86.0MB. Free memory was 45.2MB in the beginning and 45.2MB in the end (delta: 76.9kB). There was no memory consumed. Max. memory is 16.1GB. [2022-07-14 16:02:02,184 INFO L158 Benchmark]: CACSL2BoogieTranslator took 319.30ms. Allocated memory is still 142.6MB. Free memory was 111.8MB in the beginning and 115.3MB in the end (delta: -3.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2022-07-14 16:02:02,184 INFO L158 Benchmark]: Boogie Procedure Inliner took 53.53ms. Allocated memory is still 142.6MB. Free memory was 115.3MB in the beginning and 112.8MB in the end (delta: 2.6MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-07-14 16:02:02,184 INFO L158 Benchmark]: Boogie Preprocessor took 19.34ms. Allocated memory is still 142.6MB. Free memory was 112.8MB in the beginning and 111.1MB in the end (delta: 1.7MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-07-14 16:02:02,184 INFO L158 Benchmark]: RCFGBuilder took 395.20ms. Allocated memory is still 142.6MB. Free memory was 111.1MB in the beginning and 92.8MB in the end (delta: 18.3MB). Peak memory consumption was 18.9MB. Max. memory is 16.1GB. [2022-07-14 16:02:02,185 INFO L158 Benchmark]: BuchiAutomizer took 5564.10ms. Allocated memory was 142.6MB in the beginning and 213.9MB in the end (delta: 71.3MB). Free memory was 92.8MB in the beginning and 130.8MB in the end (delta: -37.9MB). Peak memory consumption was 108.2MB. Max. memory is 16.1GB. [2022-07-14 16:02:02,185 INFO L158 Benchmark]: Witness Printer took 28.96ms. Allocated memory is still 213.9MB. Free memory was 130.8MB in the beginning and 126.6MB in the end (delta: 4.2MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-07-14 16:02:02,186 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.13ms. Allocated memory is still 86.0MB. Free memory was 45.2MB in the beginning and 45.2MB in the end (delta: 76.9kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 319.30ms. Allocated memory is still 142.6MB. Free memory was 111.8MB in the beginning and 115.3MB in the end (delta: -3.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 53.53ms. Allocated memory is still 142.6MB. Free memory was 115.3MB in the beginning and 112.8MB in the end (delta: 2.6MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 19.34ms. Allocated memory is still 142.6MB. Free memory was 112.8MB in the beginning and 111.1MB in the end (delta: 1.7MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 395.20ms. Allocated memory is still 142.6MB. Free memory was 111.1MB in the beginning and 92.8MB in the end (delta: 18.3MB). Peak memory consumption was 18.9MB. Max. memory is 16.1GB. * BuchiAutomizer took 5564.10ms. Allocated memory was 142.6MB in the beginning and 213.9MB in the end (delta: 71.3MB). Free memory was 92.8MB in the beginning and 130.8MB in the end (delta: -37.9MB). Peak memory consumption was 108.2MB. Max. memory is 16.1GB. * Witness Printer took 28.96ms. Allocated memory is still 213.9MB. Free memory was 130.8MB in the beginning and 126.6MB in the end (delta: 4.2MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 19 terminating modules (17 trivial, 2 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function -1 * b0_ev + 1 and consists of 3 locations. One deterministic module has affine ranking function -1 * d0_ev + 1 and consists of 3 locations. 17 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 1747 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 5.5s and 18 iterations. TraceHistogramMax:1. Analysis of lassos took 4.2s. Construction of modules took 0.1s. Büchi inclusion checks took 0.6s. Highest rank in rank-based complementation 3. Minimization of det autom 8. Minimization of nondet autom 11. Automata minimization 0.2s AutomataMinimizationTime, 19 MinimizatonAttempts, 130 StatesRemovedByMinimization, 4 NontrivialMinimizations. Non-live state removal took 0.1s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [2, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 1085 SdHoareTripleChecker+Valid, 0.2s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 1083 mSDsluCounter, 7434 SdHoareTripleChecker+Invalid, 0.2s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 4054 mSDsCounter, 49 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 260 IncrementalHoareTripleChecker+Invalid, 309 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 49 mSolverCounterUnsat, 3380 mSDtfsCounter, 260 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI0 SFLT0 conc0 concLT0 SILN4 SILU0 SILI11 SILT2 lasso0 LassoPreprocessingBenchmarks: Lassos: inital95 mio100 ax100 hnf100 lsp11 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq209 hnf86 smp100 dnf189 smp63 tf108 neg92 sie116 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 38ms VariablesStem: 0 VariablesLoop: 1 DisjunctsStem: 1 DisjunctsLoop: 2 SupportingInvariants: 0 MotzkinApplications: 4 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 4 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 2 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.3s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 285]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=1} State at position 1 is {b1_val_t=1, NULL=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4c0053ef=0, d0_val=1, NULL=1, tmp=1, __retres1=0, z_val=0, b0_val_t=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@159affa1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2a30aedb=0, d1_ev=2, comp_m1_i=0, tmp=0, b1_val=1, d1_req_up=0, z_val_t=0, b1_req_up=0, d0_ev=2, __retres1=1, z_ev=2, b1_ev=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6530d0f5=0, comp_m1_st=0, tmp=0, b0_req_up=0, tmp___0=1, \result=0, z_req_up=0, d1_val=1, b0_ev=2, NULL=0, d0_val_t=1, kernel_st=1, d1_val_t=1, __retres1=1, b0_val=1, \result=1, d0_req_up=0, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 285]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int b0_val ; [L25] int b0_val_t ; [L26] int b0_ev ; [L27] int b0_req_up ; [L28] int b1_val ; [L29] int b1_val_t ; [L30] int b1_ev ; [L31] int b1_req_up ; [L32] int d0_val ; [L33] int d0_val_t ; [L34] int d0_ev ; [L35] int d0_req_up ; [L36] int d1_val ; [L37] int d1_val_t ; [L38] int d1_ev ; [L39] int d1_req_up ; [L40] int z_val ; [L41] int z_val_t ; [L42] int z_ev ; [L43] int z_req_up ; [L44] int comp_m1_st ; [L45] int comp_m1_i ; [L494] int __retres1 ; [L498] CALL init_model() [L465] b0_val = 0 [L466] b0_ev = 2 [L467] b0_req_up = 0 [L468] b1_val = 0 [L469] b1_ev = 2 [L470] b1_req_up = 0 [L471] d0_val = 0 [L472] d0_ev = 2 [L473] d0_req_up = 0 [L474] d1_val = 0 [L475] d1_ev = 2 [L476] d1_req_up = 0 [L477] z_val = 0 [L478] z_ev = 2 [L479] z_req_up = 0 [L480] b0_val_t = 1 [L481] b0_req_up = 1 [L482] b1_val_t = 1 [L483] b1_req_up = 1 [L484] d0_val_t = 1 [L485] d0_req_up = 1 [L486] d1_val_t = 1 [L487] d1_req_up = 1 [L488] comp_m1_i = 0 [L498] RET init_model() [L499] CALL start_simulation() [L419] int kernel_st ; [L420] int tmp ; [L424] kernel_st = 0 [L425] CALL update_channels() [L212] COND TRUE (int )b0_req_up == 1 [L214] CALL update_b0() [L137] COND TRUE (int )b0_val != (int )b0_val_t [L138] b0_val = b0_val_t [L139] b0_ev = 0 [L143] b0_req_up = 0 [L214] RET update_b0() [L219] COND TRUE (int )b1_req_up == 1 [L221] CALL update_b1() [L152] COND TRUE (int )b1_val != (int )b1_val_t [L153] b1_val = b1_val_t [L154] b1_ev = 0 [L158] b1_req_up = 0 [L221] RET update_b1() [L226] COND TRUE (int )d0_req_up == 1 [L228] CALL update_d0() [L167] COND TRUE (int )d0_val != (int )d0_val_t [L168] d0_val = d0_val_t [L169] d0_ev = 0 [L173] d0_req_up = 0 [L228] RET update_d0() [L233] COND TRUE (int )d1_req_up == 1 [L235] CALL update_d1() [L182] COND TRUE (int )d1_val != (int )d1_val_t [L183] d1_val = d1_val_t [L184] d1_ev = 0 [L188] d1_req_up = 0 [L235] RET update_d1() [L240] COND FALSE !((int )z_req_up == 1) [L425] RET update_channels() [L426] CALL init_threads() [L255] COND FALSE !((int )comp_m1_i == 1) [L258] comp_m1_st = 2 [L426] RET init_threads() [L427] CALL fire_delta_events() [L321] COND TRUE (int )b0_ev == 0 [L322] b0_ev = 1 [L326] COND TRUE (int )b1_ev == 0 [L327] b1_ev = 1 [L331] COND TRUE (int )d0_ev == 0 [L332] d0_ev = 1 [L336] COND TRUE (int )d1_ev == 0 [L337] d1_ev = 1 [L341] COND FALSE !((int )z_ev == 0) [L427] RET fire_delta_events() [L428] CALL activate_threads() [L384] int tmp ; [L388] CALL, EXPR is_method1_triggered() [L104] int __retres1 ; [L107] COND TRUE (int )b0_ev == 1 [L108] __retres1 = 1 [L130] return (__retres1); [L388] RET, EXPR is_method1_triggered() [L388] tmp = is_method1_triggered() [L390] COND TRUE \read(tmp) [L391] comp_m1_st = 0 [L428] RET activate_threads() [L429] CALL reset_delta_events() [L354] COND TRUE (int )b0_ev == 1 [L355] b0_ev = 2 [L359] COND TRUE (int )b1_ev == 1 [L360] b1_ev = 2 [L364] COND TRUE (int )d0_ev == 1 [L365] d0_ev = 2 [L369] COND TRUE (int )d1_ev == 1 [L370] d1_ev = 2 [L374] COND FALSE !((int )z_ev == 1) [L429] RET reset_delta_events() [L432] COND TRUE 1 [L435] kernel_st = 1 [L436] CALL eval() [L280] int tmp ; [L281] int tmp___0 ; Loop: [L285] COND TRUE 1 [L288] CALL, EXPR exists_runnable_thread() [L265] int __retres1 ; [L268] COND TRUE (int )comp_m1_st == 0 [L269] __retres1 = 1 [L276] return (__retres1); [L288] RET, EXPR exists_runnable_thread() [L288] tmp___0 = exists_runnable_thread() [L290] COND TRUE \read(tmp___0) [L295] COND TRUE (int )comp_m1_st == 0 [L297] tmp = __VERIFIER_nondet_int() [L299] COND FALSE !(\read(tmp)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-07-14 16:02:02,230 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)