./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/kundu.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version f4b24e32 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/kundu.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 941010afb19994aa6e2e07f5c4b80f87a4c5e60b4e0ef3217e91339d9dc3aacb --- Real Ultimate output --- This is Ultimate 0.2.2-?-f4b24e3 [2022-07-14 16:01:56,056 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-07-14 16:01:56,058 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-07-14 16:01:56,085 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-07-14 16:01:56,085 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-07-14 16:01:56,086 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-07-14 16:01:56,088 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-07-14 16:01:56,089 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-07-14 16:01:56,091 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-07-14 16:01:56,092 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-07-14 16:01:56,092 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-07-14 16:01:56,093 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-07-14 16:01:56,094 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-07-14 16:01:56,095 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-07-14 16:01:56,096 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-07-14 16:01:56,097 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-07-14 16:01:56,097 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-07-14 16:01:56,098 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-07-14 16:01:56,100 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-07-14 16:01:56,101 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-07-14 16:01:56,103 INFO L181 SettingsManager]: Resetting HornVerifier preferences to default values [2022-07-14 16:01:56,104 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-07-14 16:01:56,105 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-07-14 16:01:56,106 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-07-14 16:01:56,106 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-07-14 16:01:56,109 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-07-14 16:01:56,110 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-07-14 16:01:56,110 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-07-14 16:01:56,111 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-07-14 16:01:56,111 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-07-14 16:01:56,112 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-07-14 16:01:56,112 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-07-14 16:01:56,113 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-07-14 16:01:56,114 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-07-14 16:01:56,114 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-07-14 16:01:56,115 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-07-14 16:01:56,115 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-07-14 16:01:56,116 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-07-14 16:01:56,116 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-07-14 16:01:56,116 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-07-14 16:01:56,117 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-07-14 16:01:56,118 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-07-14 16:01:56,119 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-07-14 16:01:56,141 INFO L113 SettingsManager]: Loading preferences was successful [2022-07-14 16:01:56,141 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-07-14 16:01:56,142 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-07-14 16:01:56,142 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-07-14 16:01:56,143 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-07-14 16:01:56,143 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-07-14 16:01:56,144 INFO L138 SettingsManager]: * Use SBE=true [2022-07-14 16:01:56,144 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-07-14 16:01:56,144 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-07-14 16:01:56,145 INFO L138 SettingsManager]: * Use old map elimination=false [2022-07-14 16:01:56,145 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-07-14 16:01:56,145 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-07-14 16:01:56,145 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-07-14 16:01:56,146 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-07-14 16:01:56,146 INFO L138 SettingsManager]: * sizeof long=4 [2022-07-14 16:01:56,146 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-07-14 16:01:56,146 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-07-14 16:01:56,148 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-07-14 16:01:56,148 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-07-14 16:01:56,148 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-07-14 16:01:56,148 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-07-14 16:01:56,148 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-07-14 16:01:56,149 INFO L138 SettingsManager]: * sizeof long double=12 [2022-07-14 16:01:56,149 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-07-14 16:01:56,149 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-07-14 16:01:56,149 INFO L138 SettingsManager]: * Use constant arrays=true [2022-07-14 16:01:56,149 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-07-14 16:01:56,150 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-07-14 16:01:56,150 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-07-14 16:01:56,150 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-07-14 16:01:56,150 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-07-14 16:01:56,151 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-07-14 16:01:56,151 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 941010afb19994aa6e2e07f5c4b80f87a4c5e60b4e0ef3217e91339d9dc3aacb [2022-07-14 16:01:56,389 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-07-14 16:01:56,411 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-07-14 16:01:56,414 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-07-14 16:01:56,415 INFO L271 PluginConnector]: Initializing CDTParser... [2022-07-14 16:01:56,415 INFO L275 PluginConnector]: CDTParser initialized [2022-07-14 16:01:56,417 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/kundu.cil.c [2022-07-14 16:01:56,471 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/3850aa616/84766c495f364dec9845ec305cef2c6b/FLAG440d45b3d [2022-07-14 16:01:56,832 INFO L306 CDTParser]: Found 1 translation units. [2022-07-14 16:01:56,832 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/kundu.cil.c [2022-07-14 16:01:56,846 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/3850aa616/84766c495f364dec9845ec305cef2c6b/FLAG440d45b3d [2022-07-14 16:01:57,238 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/3850aa616/84766c495f364dec9845ec305cef2c6b [2022-07-14 16:01:57,243 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-07-14 16:01:57,245 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-07-14 16:01:57,246 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-07-14 16:01:57,246 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-07-14 16:01:57,248 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-07-14 16:01:57,249 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.07 04:01:57" (1/1) ... [2022-07-14 16:01:57,249 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@400864f1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:01:57, skipping insertion in model container [2022-07-14 16:01:57,250 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.07 04:01:57" (1/1) ... [2022-07-14 16:01:57,255 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-07-14 16:01:57,290 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-07-14 16:01:57,425 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/kundu.cil.c[635,648] [2022-07-14 16:01:57,473 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-14 16:01:57,480 INFO L203 MainTranslator]: Completed pre-run [2022-07-14 16:01:57,495 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/kundu.cil.c[635,648] [2022-07-14 16:01:57,536 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-14 16:01:57,557 INFO L208 MainTranslator]: Completed translation [2022-07-14 16:01:57,558 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:01:57 WrapperNode [2022-07-14 16:01:57,558 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-07-14 16:01:57,559 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-07-14 16:01:57,559 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-07-14 16:01:57,559 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-07-14 16:01:57,566 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:01:57" (1/1) ... [2022-07-14 16:01:57,584 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:01:57" (1/1) ... [2022-07-14 16:01:57,612 INFO L137 Inliner]: procedures = 34, calls = 40, calls flagged for inlining = 35, calls inlined = 45, statements flattened = 534 [2022-07-14 16:01:57,613 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-07-14 16:01:57,613 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-07-14 16:01:57,613 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-07-14 16:01:57,614 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-07-14 16:01:57,620 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:01:57" (1/1) ... [2022-07-14 16:01:57,620 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:01:57" (1/1) ... [2022-07-14 16:01:57,623 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:01:57" (1/1) ... [2022-07-14 16:01:57,623 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:01:57" (1/1) ... [2022-07-14 16:01:57,630 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:01:57" (1/1) ... [2022-07-14 16:01:57,637 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:01:57" (1/1) ... [2022-07-14 16:01:57,639 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:01:57" (1/1) ... [2022-07-14 16:01:57,642 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-07-14 16:01:57,643 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-07-14 16:01:57,643 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-07-14 16:01:57,644 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-07-14 16:01:57,653 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:01:57" (1/1) ... [2022-07-14 16:01:57,659 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 16:01:57,666 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 16:01:57,676 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-14 16:01:57,680 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-07-14 16:01:57,704 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-07-14 16:01:57,704 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-07-14 16:01:57,705 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-07-14 16:01:57,705 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-07-14 16:01:57,766 INFO L234 CfgBuilder]: Building ICFG [2022-07-14 16:01:57,768 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-07-14 16:01:58,211 INFO L275 CfgBuilder]: Performing block encoding [2022-07-14 16:01:58,219 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-07-14 16:01:58,219 INFO L299 CfgBuilder]: Removed 5 assume(true) statements. [2022-07-14 16:01:58,221 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.07 04:01:58 BoogieIcfgContainer [2022-07-14 16:01:58,222 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-07-14 16:01:58,223 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-07-14 16:01:58,223 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-07-14 16:01:58,227 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-07-14 16:01:58,228 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-14 16:01:58,228 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 14.07 04:01:57" (1/3) ... [2022-07-14 16:01:58,229 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@f341860 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 14.07 04:01:58, skipping insertion in model container [2022-07-14 16:01:58,229 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-14 16:01:58,229 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:01:57" (2/3) ... [2022-07-14 16:01:58,229 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@f341860 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 14.07 04:01:58, skipping insertion in model container [2022-07-14 16:01:58,229 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-14 16:01:58,229 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.07 04:01:58" (3/3) ... [2022-07-14 16:01:58,230 INFO L354 chiAutomizerObserver]: Analyzing ICFG kundu.cil.c [2022-07-14 16:01:58,277 INFO L255 stractBuchiCegarLoop]: Interprodecural is true [2022-07-14 16:01:58,277 INFO L256 stractBuchiCegarLoop]: Hoare is false [2022-07-14 16:01:58,277 INFO L257 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-07-14 16:01:58,277 INFO L258 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-07-14 16:01:58,277 INFO L259 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-07-14 16:01:58,278 INFO L260 stractBuchiCegarLoop]: Difference is false [2022-07-14 16:01:58,278 INFO L261 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-07-14 16:01:58,278 INFO L265 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-07-14 16:01:58,282 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 191 states, 190 states have (on average 1.5052631578947369) internal successors, (286), 190 states have internal predecessors, (286), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:01:58,310 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 154 [2022-07-14 16:01:58,311 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:01:58,311 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:01:58,319 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:01:58,319 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:01:58,319 INFO L287 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-07-14 16:01:58,321 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 191 states, 190 states have (on average 1.5052631578947369) internal successors, (286), 190 states have internal predecessors, (286), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:01:58,331 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 154 [2022-07-14 16:01:58,331 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:01:58,331 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:01:58,333 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:01:58,333 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:01:58,339 INFO L752 eck$LassoCheckResult]: Stem: 171#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 70#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 68#L613true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 55#L298true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 95#L305true assume !(1 == ~P_1_i~0);~P_1_st~0 := 2; 165#L305-2true assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 112#L310-1true assume !(1 == ~C_1_i~0);~C_1_st~0 := 2; 169#L315-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 157#L424true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 133#L118true assume !(1 == ~P_1_pc~0); 88#L118-2true is_P_1_triggered_~__retres1~0#1 := 0; 160#L129true is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 91#L130true activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 6#L491true assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 166#L491-2true assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 99#L186true assume 1 == ~P_2_pc~0; 175#L187true assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 107#L197true is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 105#L198true activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 73#L499true assume !(0 != activate_threads_~tmp___0~1#1); 81#L499-2true assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 37#L268true assume 1 == ~C_1_pc~0; 96#L269true assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 64#L289true is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 185#L290true activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 38#L507true assume !(0 != activate_threads_~tmp___1~1#1); 49#L507-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 125#L432true assume { :end_inline_reset_delta_events } true; 69#L561-2true [2022-07-14 16:01:58,340 INFO L754 eck$LassoCheckResult]: Loop: 69#L561-2true assume !false; 118#L562true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 178#L397true assume !true; 179#L413true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 76#L298-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 176#L424-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 161#L118-6true assume !(1 == ~P_1_pc~0); 8#L118-8true is_P_1_triggered_~__retres1~0#1 := 0; 24#L129-2true is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 89#L130-2true activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 141#L491-6true assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 47#L491-8true assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 98#L186-6true assume !(1 == ~P_2_pc~0); 48#L186-8true is_P_2_triggered_~__retres1~1#1 := 0; 153#L197-2true is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 111#L198-2true activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 56#L499-6true assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 53#L499-8true assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 20#L268-6true assume 1 == ~C_1_pc~0; 182#L269-2true assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 28#L289-2true is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 152#L290-2true activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 36#L507-6true assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 127#L507-8true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 106#L432-1true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 109#L328-1true assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 116#L345-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 42#L346-1true start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 3#L580true assume !(0 == start_simulation_~tmp~3#1); 22#L580-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 104#L328-2true assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 162#L345-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 25#L346-2true stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 123#L535true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12#L542true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 79#L543true start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 110#L593true assume !(0 != start_simulation_~tmp___0~2#1); 69#L561-2true [2022-07-14 16:01:58,344 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:01:58,345 INFO L85 PathProgramCache]: Analyzing trace with hash 1332213672, now seen corresponding path program 1 times [2022-07-14 16:01:58,353 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:01:58,353 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2140392444] [2022-07-14 16:01:58,354 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:01:58,355 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:01:58,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:01:58,531 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:01:58,532 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:01:58,533 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2140392444] [2022-07-14 16:01:58,534 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2140392444] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:01:58,534 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:01:58,535 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:01:58,536 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1537157483] [2022-07-14 16:01:58,537 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:01:58,541 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:01:58,544 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:01:58,545 INFO L85 PathProgramCache]: Analyzing trace with hash -1462313658, now seen corresponding path program 1 times [2022-07-14 16:01:58,545 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:01:58,546 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [914229995] [2022-07-14 16:01:58,546 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:01:58,546 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:01:58,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:01:58,579 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:01:58,583 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:01:58,583 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [914229995] [2022-07-14 16:01:58,583 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [914229995] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:01:58,583 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:01:58,583 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-14 16:01:58,584 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1315549628] [2022-07-14 16:01:58,584 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:01:58,585 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:01:58,586 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:01:58,625 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:01:58,626 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:01:58,629 INFO L87 Difference]: Start difference. First operand has 191 states, 190 states have (on average 1.5052631578947369) internal successors, (286), 190 states have internal predecessors, (286), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:01:58,673 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:01:58,675 INFO L93 Difference]: Finished difference Result 187 states and 270 transitions. [2022-07-14 16:01:58,677 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:01:58,683 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 187 states and 270 transitions. [2022-07-14 16:01:58,696 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 146 [2022-07-14 16:01:58,700 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 187 states to 179 states and 262 transitions. [2022-07-14 16:01:58,701 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 179 [2022-07-14 16:01:58,703 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 179 [2022-07-14 16:01:58,704 INFO L73 IsDeterministic]: Start isDeterministic. Operand 179 states and 262 transitions. [2022-07-14 16:01:58,705 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:01:58,706 INFO L369 hiAutomatonCegarLoop]: Abstraction has 179 states and 262 transitions. [2022-07-14 16:01:58,720 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179 states and 262 transitions. [2022-07-14 16:01:58,742 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179 to 179. [2022-07-14 16:01:58,744 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 179 states, 179 states have (on average 1.4636871508379887) internal successors, (262), 178 states have internal predecessors, (262), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:01:58,745 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 179 states to 179 states and 262 transitions. [2022-07-14 16:01:58,746 INFO L392 hiAutomatonCegarLoop]: Abstraction has 179 states and 262 transitions. [2022-07-14 16:01:58,747 INFO L374 stractBuchiCegarLoop]: Abstraction has 179 states and 262 transitions. [2022-07-14 16:01:58,747 INFO L287 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-07-14 16:01:58,747 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 179 states and 262 transitions. [2022-07-14 16:01:58,749 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 146 [2022-07-14 16:01:58,749 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:01:58,749 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:01:58,752 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:01:58,752 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:01:58,753 INFO L752 eck$LassoCheckResult]: Stem: 564#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 506#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 502#L613 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 487#L298 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 488#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 533#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 544#L310-1 assume !(1 == ~C_1_i~0);~C_1_st~0 := 2; 545#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 562#L424 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 551#L118 assume !(1 == ~P_1_pc~0); 525#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 526#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 529#L130 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 396#L491 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 397#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 535#L186 assume 1 == ~P_2_pc~0; 536#L187 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 418#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 539#L198 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 509#L499 assume !(0 != activate_threads_~tmp___0~1#1); 510#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 459#L268 assume 1 == ~C_1_pc~0; 461#L269 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 498#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 499#L290 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 462#L507 assume !(0 != activate_threads_~tmp___1~1#1); 463#L507-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 479#L432 assume { :end_inline_reset_delta_events } true; 503#L561-2 [2022-07-14 16:01:58,757 INFO L754 eck$LassoCheckResult]: Loop: 503#L561-2 assume !false; 504#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 421#L397 assume !false; 438#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 439#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 481#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 511#L346 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 512#L362 assume !(0 != eval_~tmp___2~0#1); 565#L413 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 513#L298-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 514#L424-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 563#L118-6 assume 1 == ~P_1_pc~0; 508#L119-2 assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1; 399#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 433#L130-2 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 524#L491-6 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 473#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 474#L186-6 assume 1 == ~P_2_pc~0; 534#L187-2 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 476#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 543#L198-2 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 489#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 486#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 424#L268-6 assume 1 == ~C_1_pc~0; 425#L269-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 440#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 441#L290-2 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 455#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 456#L507-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 540#L432-1 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 541#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 401#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 466#L346-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 387#L580 assume !(0 == start_simulation_~tmp~3#1); 389#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 430#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 537#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 434#L346-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 435#L535 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 407#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 408#L543 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 517#L593 assume !(0 != start_simulation_~tmp___0~2#1); 503#L561-2 [2022-07-14 16:01:58,758 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:01:58,758 INFO L85 PathProgramCache]: Analyzing trace with hash 1466227178, now seen corresponding path program 1 times [2022-07-14 16:01:58,758 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:01:58,759 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1687728993] [2022-07-14 16:01:58,759 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:01:58,759 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:01:58,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:01:58,812 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:01:58,812 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:01:58,812 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1687728993] [2022-07-14 16:01:58,812 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1687728993] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:01:58,814 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:01:58,814 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:01:58,815 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [977006181] [2022-07-14 16:01:58,815 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:01:58,815 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:01:58,816 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:01:58,816 INFO L85 PathProgramCache]: Analyzing trace with hash 1194162143, now seen corresponding path program 1 times [2022-07-14 16:01:58,816 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:01:58,816 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1579877707] [2022-07-14 16:01:58,816 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:01:58,817 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:01:58,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:01:58,909 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:01:58,910 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:01:58,911 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1579877707] [2022-07-14 16:01:58,911 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1579877707] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:01:58,911 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:01:58,912 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:01:58,912 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1174472890] [2022-07-14 16:01:58,912 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:01:58,914 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:01:58,914 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:01:58,915 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:01:58,915 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:01:58,915 INFO L87 Difference]: Start difference. First operand 179 states and 262 transitions. cyclomatic complexity: 84 Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:01:58,938 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:01:58,941 INFO L93 Difference]: Finished difference Result 179 states and 261 transitions. [2022-07-14 16:01:58,941 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:01:58,942 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 179 states and 261 transitions. [2022-07-14 16:01:58,944 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 146 [2022-07-14 16:01:58,947 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 179 states to 179 states and 261 transitions. [2022-07-14 16:01:58,947 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 179 [2022-07-14 16:01:58,949 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 179 [2022-07-14 16:01:58,949 INFO L73 IsDeterministic]: Start isDeterministic. Operand 179 states and 261 transitions. [2022-07-14 16:01:58,952 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:01:58,953 INFO L369 hiAutomatonCegarLoop]: Abstraction has 179 states and 261 transitions. [2022-07-14 16:01:58,953 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179 states and 261 transitions. [2022-07-14 16:01:58,960 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179 to 179. [2022-07-14 16:01:58,961 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 179 states, 179 states have (on average 1.458100558659218) internal successors, (261), 178 states have internal predecessors, (261), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:01:58,962 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 179 states to 179 states and 261 transitions. [2022-07-14 16:01:58,962 INFO L392 hiAutomatonCegarLoop]: Abstraction has 179 states and 261 transitions. [2022-07-14 16:01:58,962 INFO L374 stractBuchiCegarLoop]: Abstraction has 179 states and 261 transitions. [2022-07-14 16:01:58,962 INFO L287 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-07-14 16:01:58,962 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 179 states and 261 transitions. [2022-07-14 16:01:58,965 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 146 [2022-07-14 16:01:58,966 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:01:58,966 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:01:58,970 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:01:58,970 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:01:58,970 INFO L752 eck$LassoCheckResult]: Stem: 931#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 872#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 869#L613 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 854#L298 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 855#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 900#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 911#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 912#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 929#L424 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 918#L118 assume !(1 == ~P_1_pc~0); 891#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 892#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 896#L130 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 761#L491 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 762#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 902#L186 assume 1 == ~P_2_pc~0; 903#L187 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 783#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 906#L198 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 875#L499 assume !(0 != activate_threads_~tmp___0~1#1); 876#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 824#L268 assume 1 == ~C_1_pc~0; 826#L269 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 865#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 866#L290 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 827#L507 assume !(0 != activate_threads_~tmp___1~1#1); 828#L507-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 844#L432 assume { :end_inline_reset_delta_events } true; 870#L561-2 [2022-07-14 16:01:58,970 INFO L754 eck$LassoCheckResult]: Loop: 870#L561-2 assume !false; 871#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 786#L397 assume !false; 803#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 804#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 846#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 878#L346 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 879#L362 assume !(0 != eval_~tmp___2~0#1); 932#L413 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 880#L298-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 881#L424-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 930#L118-6 assume !(1 == ~P_1_pc~0); 765#L118-8 is_P_1_triggered_~__retres1~0#1 := 0; 766#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 800#L130-2 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 893#L491-6 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 840#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 841#L186-6 assume 1 == ~P_2_pc~0; 901#L187-2 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 843#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 910#L198-2 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 856#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 853#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 791#L268-6 assume 1 == ~C_1_pc~0; 792#L269-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 807#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 808#L290-2 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 822#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 823#L507-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 907#L432-1 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 908#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 768#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 833#L346-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 754#L580 assume !(0 == start_simulation_~tmp~3#1); 756#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 797#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 904#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 801#L346-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 802#L535 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 774#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 775#L543 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 884#L593 assume !(0 != start_simulation_~tmp___0~2#1); 870#L561-2 [2022-07-14 16:01:58,971 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:01:58,971 INFO L85 PathProgramCache]: Analyzing trace with hash 1247372460, now seen corresponding path program 1 times [2022-07-14 16:01:58,971 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:01:58,971 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1487456224] [2022-07-14 16:01:58,971 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:01:58,972 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:01:58,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:01:59,047 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:01:59,047 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:01:59,048 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1487456224] [2022-07-14 16:01:59,048 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1487456224] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:01:59,048 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:01:59,048 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:01:59,049 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1403991140] [2022-07-14 16:01:59,049 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:01:59,050 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:01:59,050 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:01:59,051 INFO L85 PathProgramCache]: Analyzing trace with hash -577308832, now seen corresponding path program 1 times [2022-07-14 16:01:59,051 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:01:59,051 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [552451117] [2022-07-14 16:01:59,051 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:01:59,051 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:01:59,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:01:59,118 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:01:59,119 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:01:59,120 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [552451117] [2022-07-14 16:01:59,120 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [552451117] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:01:59,120 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:01:59,121 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:01:59,121 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [825033449] [2022-07-14 16:01:59,121 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:01:59,121 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:01:59,121 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:01:59,122 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-07-14 16:01:59,122 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-07-14 16:01:59,123 INFO L87 Difference]: Start difference. First operand 179 states and 261 transitions. cyclomatic complexity: 83 Second operand has 5 states, 5 states have (on average 5.6) internal successors, (28), 5 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:01:59,231 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:01:59,231 INFO L93 Difference]: Finished difference Result 483 states and 703 transitions. [2022-07-14 16:01:59,231 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-07-14 16:01:59,233 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 483 states and 703 transitions. [2022-07-14 16:01:59,237 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 411 [2022-07-14 16:01:59,240 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 483 states to 483 states and 703 transitions. [2022-07-14 16:01:59,240 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 483 [2022-07-14 16:01:59,241 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 483 [2022-07-14 16:01:59,241 INFO L73 IsDeterministic]: Start isDeterministic. Operand 483 states and 703 transitions. [2022-07-14 16:01:59,243 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:01:59,243 INFO L369 hiAutomatonCegarLoop]: Abstraction has 483 states and 703 transitions. [2022-07-14 16:01:59,244 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 483 states and 703 transitions. [2022-07-14 16:01:59,253 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 483 to 191. [2022-07-14 16:01:59,253 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 191 states, 191 states have (on average 1.4293193717277486) internal successors, (273), 190 states have internal predecessors, (273), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:01:59,254 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 191 states to 191 states and 273 transitions. [2022-07-14 16:01:59,254 INFO L392 hiAutomatonCegarLoop]: Abstraction has 191 states and 273 transitions. [2022-07-14 16:01:59,254 INFO L374 stractBuchiCegarLoop]: Abstraction has 191 states and 273 transitions. [2022-07-14 16:01:59,254 INFO L287 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-07-14 16:01:59,255 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 191 states and 273 transitions. [2022-07-14 16:01:59,256 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 155 [2022-07-14 16:01:59,256 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:01:59,256 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:01:59,256 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:01:59,256 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:01:59,257 INFO L752 eck$LassoCheckResult]: Stem: 1617#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 1552#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 1548#L613 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1531#L298 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1532#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 1582#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 1593#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 1594#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1614#L424 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 1600#L118 assume !(1 == ~P_1_pc~0); 1573#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 1574#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 1616#L130 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1440#L491 assume !(0 != activate_threads_~tmp~1#1); 1441#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 1584#L186 assume 1 == ~P_2_pc~0; 1585#L187 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 1465#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 1588#L198 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1556#L499 assume !(0 != activate_threads_~tmp___0~1#1); 1557#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 1503#L268 assume 1 == ~C_1_pc~0; 1505#L269 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 1543#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 1544#L290 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1506#L507 assume !(0 != activate_threads_~tmp___1~1#1); 1507#L507-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1526#L432 assume { :end_inline_reset_delta_events } true; 1549#L561-2 [2022-07-14 16:01:59,257 INFO L754 eck$LassoCheckResult]: Loop: 1549#L561-2 assume !false; 1550#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 1461#L397 assume !false; 1480#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1481#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1522#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1558#L346 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1559#L362 assume !(0 != eval_~tmp___2~0#1); 1619#L413 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1560#L298-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1561#L424-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 1615#L118-6 assume 1 == ~P_1_pc~0; 1554#L119-2 assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1; 1555#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 1571#L130-2 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1572#L491-6 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 1517#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 1518#L186-6 assume 1 == ~P_2_pc~0; 1583#L187-2 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 1520#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 1592#L198-2 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1533#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 1530#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 1468#L268-6 assume 1 == ~C_1_pc~0; 1469#L269-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 1484#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 1485#L290-2 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1499#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 1500#L507-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1589#L432-1 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1590#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1445#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1510#L346-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1431#L580 assume !(0 == start_simulation_~tmp~3#1); 1433#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1474#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1586#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1478#L346-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 1479#L535 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1451#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1452#L543 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1564#L593 assume !(0 != start_simulation_~tmp___0~2#1); 1549#L561-2 [2022-07-14 16:01:59,257 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:01:59,257 INFO L85 PathProgramCache]: Analyzing trace with hash -32491218, now seen corresponding path program 1 times [2022-07-14 16:01:59,257 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:01:59,258 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1359915791] [2022-07-14 16:01:59,258 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:01:59,258 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:01:59,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:01:59,285 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:01:59,286 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:01:59,286 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1359915791] [2022-07-14 16:01:59,286 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1359915791] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:01:59,286 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:01:59,286 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-07-14 16:01:59,286 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1451001908] [2022-07-14 16:01:59,286 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:01:59,287 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:01:59,287 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:01:59,287 INFO L85 PathProgramCache]: Analyzing trace with hash 1194162143, now seen corresponding path program 2 times [2022-07-14 16:01:59,287 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:01:59,287 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1914193868] [2022-07-14 16:01:59,287 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:01:59,288 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:01:59,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:01:59,314 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:01:59,314 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:01:59,314 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1914193868] [2022-07-14 16:01:59,314 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1914193868] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:01:59,314 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:01:59,314 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:01:59,315 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1488751668] [2022-07-14 16:01:59,315 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:01:59,315 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:01:59,315 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:01:59,315 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:01:59,316 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:01:59,316 INFO L87 Difference]: Start difference. First operand 191 states and 273 transitions. cyclomatic complexity: 83 Second operand has 4 states, 4 states have (on average 7.0) internal successors, (28), 4 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:01:59,381 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:01:59,382 INFO L93 Difference]: Finished difference Result 478 states and 671 transitions. [2022-07-14 16:01:59,382 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:01:59,383 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 478 states and 671 transitions. [2022-07-14 16:01:59,387 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 415 [2022-07-14 16:01:59,390 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 478 states to 478 states and 671 transitions. [2022-07-14 16:01:59,390 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 478 [2022-07-14 16:01:59,391 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 478 [2022-07-14 16:01:59,391 INFO L73 IsDeterministic]: Start isDeterministic. Operand 478 states and 671 transitions. [2022-07-14 16:01:59,391 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:01:59,392 INFO L369 hiAutomatonCegarLoop]: Abstraction has 478 states and 671 transitions. [2022-07-14 16:01:59,392 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 478 states and 671 transitions. [2022-07-14 16:01:59,408 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 478 to 436. [2022-07-14 16:01:59,409 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 436 states, 436 states have (on average 1.4128440366972477) internal successors, (616), 435 states have internal predecessors, (616), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:01:59,411 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 436 states to 436 states and 616 transitions. [2022-07-14 16:01:59,411 INFO L392 hiAutomatonCegarLoop]: Abstraction has 436 states and 616 transitions. [2022-07-14 16:01:59,411 INFO L374 stractBuchiCegarLoop]: Abstraction has 436 states and 616 transitions. [2022-07-14 16:01:59,411 INFO L287 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-07-14 16:01:59,411 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 436 states and 616 transitions. [2022-07-14 16:01:59,413 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 399 [2022-07-14 16:01:59,413 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:01:59,413 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:01:59,414 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:01:59,414 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:01:59,420 INFO L752 eck$LassoCheckResult]: Stem: 2300#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 2236#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 2234#L613 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2216#L298 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2217#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 2265#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 2277#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 2278#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2298#L424 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 2286#L118 assume !(1 == ~P_1_pc~0); 2256#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 2257#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 2261#L130 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2120#L491 assume !(0 != activate_threads_~tmp~1#1); 2121#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 2267#L186 assume !(1 == ~P_2_pc~0); 2141#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 2142#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 2271#L198 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2238#L499 assume !(0 != activate_threads_~tmp___0~1#1); 2239#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 2183#L268 assume 1 == ~C_1_pc~0; 2185#L269 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 2228#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 2229#L290 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2186#L507 assume !(0 != activate_threads_~tmp___1~1#1); 2187#L507-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2203#L432 assume { :end_inline_reset_delta_events } true; 2232#L561-2 [2022-07-14 16:01:59,420 INFO L754 eck$LassoCheckResult]: Loop: 2232#L561-2 assume !false; 2233#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 2302#L397 assume !false; 2163#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2164#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2205#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2243#L346 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2244#L362 assume !(0 != eval_~tmp___2~0#1); 2303#L413 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2245#L298-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2246#L424-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 2299#L118-6 assume !(1 == ~P_1_pc~0); 2124#L118-8 is_P_1_triggered_~__retres1~0#1 := 0; 2125#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 2162#L130-2 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2258#L491-6 assume !(0 != activate_threads_~tmp~1#1); 2199#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 2200#L186-6 assume !(1 == ~P_2_pc~0); 2266#L186-8 is_P_2_triggered_~__retres1~1#1 := 0; 2505#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 2504#L198-2 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2433#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 2432#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 2150#L268-6 assume 1 == ~C_1_pc~0; 2151#L269-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 2167#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 2168#L290-2 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2181#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 2182#L507-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2272#L432-1 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2273#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2130#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2192#L346-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 2113#L580 assume !(0 == start_simulation_~tmp~3#1); 2115#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2528#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2526#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2525#L346-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 2524#L535 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2523#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2522#L543 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 2274#L593 assume !(0 != start_simulation_~tmp___0~2#1); 2232#L561-2 [2022-07-14 16:01:59,421 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:01:59,421 INFO L85 PathProgramCache]: Analyzing trace with hash -1311815953, now seen corresponding path program 1 times [2022-07-14 16:01:59,421 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:01:59,421 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1423754006] [2022-07-14 16:01:59,421 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:01:59,421 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:01:59,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:01:59,473 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:01:59,474 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:01:59,474 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1423754006] [2022-07-14 16:01:59,474 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1423754006] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:01:59,474 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:01:59,474 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-07-14 16:01:59,474 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1145077935] [2022-07-14 16:01:59,474 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:01:59,475 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:01:59,475 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:01:59,475 INFO L85 PathProgramCache]: Analyzing trace with hash -711684829, now seen corresponding path program 1 times [2022-07-14 16:01:59,475 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:01:59,475 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [942725730] [2022-07-14 16:01:59,475 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:01:59,476 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:01:59,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:01:59,507 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:01:59,507 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:01:59,508 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [942725730] [2022-07-14 16:01:59,508 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [942725730] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:01:59,508 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:01:59,508 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:01:59,508 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [829177777] [2022-07-14 16:01:59,508 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:01:59,509 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:01:59,509 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:01:59,509 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:01:59,510 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:01:59,510 INFO L87 Difference]: Start difference. First operand 436 states and 616 transitions. cyclomatic complexity: 182 Second operand has 4 states, 4 states have (on average 7.0) internal successors, (28), 4 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:01:59,603 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:01:59,603 INFO L93 Difference]: Finished difference Result 1188 states and 1642 transitions. [2022-07-14 16:01:59,603 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:01:59,606 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1188 states and 1642 transitions. [2022-07-14 16:01:59,613 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1108 [2022-07-14 16:01:59,620 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1188 states to 1188 states and 1642 transitions. [2022-07-14 16:01:59,620 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1188 [2022-07-14 16:01:59,621 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1188 [2022-07-14 16:01:59,621 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1188 states and 1642 transitions. [2022-07-14 16:01:59,622 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:01:59,622 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1188 states and 1642 transitions. [2022-07-14 16:01:59,623 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1188 states and 1642 transitions. [2022-07-14 16:01:59,636 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1188 to 1129. [2022-07-14 16:01:59,638 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1129 states, 1129 states have (on average 1.3906111603188662) internal successors, (1570), 1128 states have internal predecessors, (1570), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:01:59,640 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1129 states to 1129 states and 1570 transitions. [2022-07-14 16:01:59,641 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1129 states and 1570 transitions. [2022-07-14 16:01:59,641 INFO L374 stractBuchiCegarLoop]: Abstraction has 1129 states and 1570 transitions. [2022-07-14 16:01:59,641 INFO L287 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-07-14 16:01:59,641 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1129 states and 1570 transitions. [2022-07-14 16:01:59,645 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1087 [2022-07-14 16:01:59,645 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:01:59,645 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:01:59,647 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:01:59,647 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:01:59,647 INFO L752 eck$LassoCheckResult]: Stem: 3954#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 3874#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 3871#L613 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3853#L298 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3854#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 3907#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 3921#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 3922#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3951#L424 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 3933#L118 assume !(1 == ~P_1_pc~0); 3898#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 3899#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 3903#L130 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3757#L491 assume !(0 != activate_threads_~tmp~1#1); 3758#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 3908#L186 assume !(1 == ~P_2_pc~0); 3778#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 3779#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 3915#L198 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3877#L499 assume !(0 != activate_threads_~tmp___0~1#1); 3878#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 3821#L268 assume !(1 == ~C_1_pc~0); 3822#L268-2 assume 2 == ~C_1_pc~0; 3893#L279 assume 1 == ~C_1_ev~0;is_C_1_triggered_~__retres1~2#1 := 1; 3867#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 3868#L290 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3823#L507 assume !(0 != activate_threads_~tmp___1~1#1); 3824#L507-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3841#L432 assume { :end_inline_reset_delta_events } true; 3928#L561-2 [2022-07-14 16:01:59,648 INFO L754 eck$LassoCheckResult]: Loop: 3928#L561-2 assume !false; 4614#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 4608#L397 assume !false; 4604#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4599#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4594#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4590#L346 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4587#L362 assume !(0 != eval_~tmp___2~0#1); 4588#L413 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4783#L298-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4781#L424-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 4779#L118-6 assume !(1 == ~P_1_pc~0); 4777#L118-8 is_P_1_triggered_~__retres1~0#1 := 0; 4775#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 4773#L130-2 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4771#L491-6 assume !(0 != activate_threads_~tmp~1#1); 4769#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 4764#L186-6 assume !(1 == ~P_2_pc~0); 4761#L186-8 is_P_2_triggered_~__retres1~1#1 := 0; 4755#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 4751#L198-2 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4747#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 4744#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 4690#L268-6 assume !(1 == ~C_1_pc~0); 4688#L268-8 assume 2 == ~C_1_pc~0; 4684#L279-2 assume 1 == ~C_1_ev~0;is_C_1_triggered_~__retres1~2#1 := 1; 4681#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 4677#L290-2 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4674#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 4671#L507-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4668#L432-1 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4665#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4660#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4657#L346-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 4652#L580 assume !(0 == start_simulation_~tmp~3#1); 4648#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4645#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4642#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4640#L346-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 4638#L535 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4635#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4632#L543 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 4627#L593 assume !(0 != start_simulation_~tmp___0~2#1); 3928#L561-2 [2022-07-14 16:01:59,649 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:01:59,649 INFO L85 PathProgramCache]: Analyzing trace with hash -122788309, now seen corresponding path program 1 times [2022-07-14 16:01:59,649 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:01:59,649 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1481922378] [2022-07-14 16:01:59,649 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:01:59,649 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:01:59,662 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:01:59,691 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:01:59,691 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:01:59,691 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1481922378] [2022-07-14 16:01:59,691 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1481922378] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:01:59,691 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:01:59,692 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:01:59,694 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [444904163] [2022-07-14 16:01:59,694 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:01:59,694 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:01:59,695 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:01:59,695 INFO L85 PathProgramCache]: Analyzing trace with hash 1040752634, now seen corresponding path program 1 times [2022-07-14 16:01:59,695 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:01:59,695 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [100094242] [2022-07-14 16:01:59,695 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:01:59,695 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:01:59,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:01:59,734 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:01:59,735 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:01:59,735 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [100094242] [2022-07-14 16:01:59,737 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [100094242] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:01:59,737 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:01:59,738 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:01:59,738 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [694104487] [2022-07-14 16:01:59,738 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:01:59,739 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:01:59,739 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:01:59,740 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:01:59,740 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:01:59,740 INFO L87 Difference]: Start difference. First operand 1129 states and 1570 transitions. cyclomatic complexity: 445 Second operand has 3 states, 3 states have (on average 9.666666666666666) internal successors, (29), 3 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:01:59,782 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:01:59,782 INFO L93 Difference]: Finished difference Result 1500 states and 2055 transitions. [2022-07-14 16:01:59,782 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:01:59,783 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1500 states and 2055 transitions. [2022-07-14 16:01:59,795 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1453 [2022-07-14 16:01:59,803 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1500 states to 1500 states and 2055 transitions. [2022-07-14 16:01:59,803 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1500 [2022-07-14 16:01:59,804 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1500 [2022-07-14 16:01:59,804 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1500 states and 2055 transitions. [2022-07-14 16:01:59,806 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:01:59,806 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1500 states and 2055 transitions. [2022-07-14 16:01:59,807 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1500 states and 2055 transitions. [2022-07-14 16:01:59,833 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1500 to 1476. [2022-07-14 16:01:59,835 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.3719512195121952) internal successors, (2025), 1475 states have internal predecessors, (2025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:01:59,839 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2025 transitions. [2022-07-14 16:01:59,839 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2025 transitions. [2022-07-14 16:01:59,839 INFO L374 stractBuchiCegarLoop]: Abstraction has 1476 states and 2025 transitions. [2022-07-14 16:01:59,839 INFO L287 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-07-14 16:01:59,839 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2025 transitions. [2022-07-14 16:01:59,845 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1429 [2022-07-14 16:01:59,845 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:01:59,845 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:01:59,846 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:01:59,846 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:01:59,846 INFO L752 eck$LassoCheckResult]: Stem: 6589#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 6510#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 6508#L613 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6489#L298 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6490#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 6544#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 6555#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 6556#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6584#L424 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 6566#L118 assume !(1 == ~P_1_pc~0); 6535#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 6536#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 6540#L130 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 6395#L491 assume !(0 != activate_threads_~tmp~1#1); 6396#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 6545#L186 assume !(1 == ~P_2_pc~0); 6415#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 6416#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 6550#L198 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 6512#L499 assume !(0 != activate_threads_~tmp___0~1#1); 6513#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 6457#L268 assume !(1 == ~C_1_pc~0); 6458#L268-2 assume !(2 == ~C_1_pc~0); 6573#L278-1 is_C_1_triggered_~__retres1~2#1 := 0; 6502#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 6503#L290 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6459#L507 assume !(0 != activate_threads_~tmp___1~1#1); 6460#L507-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6477#L432 assume { :end_inline_reset_delta_events } true; 6561#L561-2 [2022-07-14 16:01:59,847 INFO L754 eck$LassoCheckResult]: Loop: 6561#L561-2 assume !false; 7792#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 7788#L397 assume !false; 7785#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7782#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7779#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7777#L346 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7773#L362 assume !(0 != eval_~tmp___2~0#1); 7774#L413 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7860#L298-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7859#L424-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 7857#L118-6 assume !(1 == ~P_1_pc~0); 7855#L118-8 is_P_1_triggered_~__retres1~0#1 := 0; 7853#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 7851#L130-2 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 7849#L491-6 assume !(0 != activate_threads_~tmp~1#1); 7847#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 7845#L186-6 assume !(1 == ~P_2_pc~0); 7843#L186-8 is_P_2_triggered_~__retres1~1#1 := 0; 7841#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 7839#L198-2 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7837#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 7835#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 7833#L268-6 assume !(1 == ~C_1_pc~0); 7831#L268-8 assume !(2 == ~C_1_pc~0); 7829#L278-5 is_C_1_triggered_~__retres1~2#1 := 0; 7827#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 7825#L290-2 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7823#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 7821#L507-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7819#L432-1 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7817#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7813#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7811#L346-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 7809#L580 assume !(0 == start_simulation_~tmp~3#1); 7807#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7805#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7803#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7801#L346-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 7800#L535 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7799#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7798#L543 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 7797#L593 assume !(0 != start_simulation_~tmp___0~2#1); 6561#L561-2 [2022-07-14 16:01:59,847 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:01:59,847 INFO L85 PathProgramCache]: Analyzing trace with hash 1966545068, now seen corresponding path program 1 times [2022-07-14 16:01:59,847 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:01:59,848 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [937833816] [2022-07-14 16:01:59,848 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:01:59,848 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:01:59,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:01:59,855 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:01:59,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:01:59,883 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:01:59,884 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:01:59,884 INFO L85 PathProgramCache]: Analyzing trace with hash 2031917307, now seen corresponding path program 1 times [2022-07-14 16:01:59,884 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:01:59,884 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [421401746] [2022-07-14 16:01:59,885 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:01:59,885 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:01:59,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:01:59,909 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:01:59,909 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:01:59,909 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [421401746] [2022-07-14 16:01:59,909 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [421401746] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:01:59,909 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:01:59,910 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:01:59,910 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1337150597] [2022-07-14 16:01:59,910 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:01:59,910 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:01:59,910 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:01:59,911 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-07-14 16:01:59,911 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-07-14 16:01:59,911 INFO L87 Difference]: Start difference. First operand 1476 states and 2025 transitions. cyclomatic complexity: 553 Second operand has 5 states, 5 states have (on average 8.6) internal successors, (43), 5 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:01:59,986 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:01:59,986 INFO L93 Difference]: Finished difference Result 2613 states and 3559 transitions. [2022-07-14 16:01:59,987 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-07-14 16:01:59,987 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2613 states and 3559 transitions. [2022-07-14 16:02:00,001 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2548 [2022-07-14 16:02:00,014 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2613 states to 2613 states and 3559 transitions. [2022-07-14 16:02:00,014 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2613 [2022-07-14 16:02:00,017 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2613 [2022-07-14 16:02:00,017 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2613 states and 3559 transitions. [2022-07-14 16:02:00,020 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:00,021 INFO L369 hiAutomatonCegarLoop]: Abstraction has 2613 states and 3559 transitions. [2022-07-14 16:02:00,022 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2613 states and 3559 transitions. [2022-07-14 16:02:00,041 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2613 to 1512. [2022-07-14 16:02:00,044 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1512 states, 1512 states have (on average 1.3630952380952381) internal successors, (2061), 1511 states have internal predecessors, (2061), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:00,048 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1512 states to 1512 states and 2061 transitions. [2022-07-14 16:02:00,048 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1512 states and 2061 transitions. [2022-07-14 16:02:00,048 INFO L374 stractBuchiCegarLoop]: Abstraction has 1512 states and 2061 transitions. [2022-07-14 16:02:00,048 INFO L287 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-07-14 16:02:00,066 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1512 states and 2061 transitions. [2022-07-14 16:02:00,072 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1465 [2022-07-14 16:02:00,073 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:00,073 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:00,073 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:00,073 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:00,074 INFO L752 eck$LassoCheckResult]: Stem: 10708#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 10616#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 10614#L613 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10593#L298 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10594#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 10649#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 10662#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 10663#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10703#L424 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 10677#L118 assume !(1 == ~P_1_pc~0); 10642#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 10643#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 10646#L130 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 10502#L491 assume !(0 != activate_threads_~tmp~1#1); 10503#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 10650#L186 assume !(1 == ~P_2_pc~0); 10525#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 10526#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 10655#L198 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 10621#L499 assume !(0 != activate_threads_~tmp___0~1#1); 10622#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 10565#L268 assume !(1 == ~C_1_pc~0); 10566#L268-2 assume !(2 == ~C_1_pc~0); 10683#L278-1 is_C_1_triggered_~__retres1~2#1 := 0; 10608#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 10609#L290 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 10567#L507 assume !(0 != activate_threads_~tmp___1~1#1); 10568#L507-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10587#L432 assume { :end_inline_reset_delta_events } true; 10673#L561-2 [2022-07-14 16:02:00,074 INFO L754 eck$LassoCheckResult]: Loop: 10673#L561-2 assume !false; 11966#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 11914#L397 assume !false; 11964#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 11957#L328 assume !(0 == ~P_1_st~0); 11958#L332 assume !(0 == ~P_2_st~0); 11956#L336 assume !(0 == ~C_1_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 11954#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 11953#L346 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 11752#L362 assume !(0 != eval_~tmp___2~0#1); 11753#L413 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10625#L298-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10626#L424-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 10705#L118-6 assume !(1 == ~P_1_pc~0); 10706#L118-8 is_P_1_triggered_~__retres1~0#1 := 0; 10536#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 10537#L130-2 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 10641#L491-6 assume !(0 != activate_threads_~tmp~1#1); 11986#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 11985#L186-6 assume !(1 == ~P_2_pc~0); 11984#L186-8 is_P_2_triggered_~__retres1~1#1 := 0; 10698#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 10699#L198-2 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 10595#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 10596#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 11983#L268-6 assume !(1 == ~C_1_pc~0); 10666#L268-8 assume !(2 == ~C_1_pc~0); 10667#L278-5 is_C_1_triggered_~__retres1~2#1 := 0; 10544#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 10545#L290-2 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 10559#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 10560#L507-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10656#L432-1 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 10657#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 11979#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 11977#L346-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 11976#L580 assume !(0 == start_simulation_~tmp~3#1); 11974#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 10652#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 10653#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 11971#L346-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 11970#L535 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11969#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11968#L543 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 11967#L593 assume !(0 != start_simulation_~tmp___0~2#1); 10673#L561-2 [2022-07-14 16:02:00,074 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:00,075 INFO L85 PathProgramCache]: Analyzing trace with hash 1966545068, now seen corresponding path program 2 times [2022-07-14 16:02:00,075 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:00,075 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [601638895] [2022-07-14 16:02:00,075 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:00,075 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:00,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:00,124 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:02:00,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:00,141 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:02:00,142 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:00,142 INFO L85 PathProgramCache]: Analyzing trace with hash -1502717854, now seen corresponding path program 1 times [2022-07-14 16:02:00,142 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:00,143 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [396313295] [2022-07-14 16:02:00,143 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:00,143 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:00,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:00,191 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:00,191 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:00,191 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [396313295] [2022-07-14 16:02:00,192 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [396313295] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:00,192 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:00,192 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:00,192 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [60347077] [2022-07-14 16:02:00,192 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:00,193 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:00,193 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:00,193 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:02:00,193 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:02:00,193 INFO L87 Difference]: Start difference. First operand 1512 states and 2061 transitions. cyclomatic complexity: 553 Second operand has 3 states, 3 states have (on average 15.0) internal successors, (45), 3 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:00,234 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:00,235 INFO L93 Difference]: Finished difference Result 2343 states and 3154 transitions. [2022-07-14 16:02:00,235 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:02:00,237 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2343 states and 3154 transitions. [2022-07-14 16:02:00,253 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2246 [2022-07-14 16:02:00,268 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2343 states to 2343 states and 3154 transitions. [2022-07-14 16:02:00,268 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2343 [2022-07-14 16:02:00,270 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2343 [2022-07-14 16:02:00,270 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2343 states and 3154 transitions. [2022-07-14 16:02:00,273 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:00,273 INFO L369 hiAutomatonCegarLoop]: Abstraction has 2343 states and 3154 transitions. [2022-07-14 16:02:00,275 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2343 states and 3154 transitions. [2022-07-14 16:02:00,299 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2343 to 2343. [2022-07-14 16:02:00,302 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2343 states, 2343 states have (on average 1.3461374306444729) internal successors, (3154), 2342 states have internal predecessors, (3154), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:00,309 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2343 states to 2343 states and 3154 transitions. [2022-07-14 16:02:00,309 INFO L392 hiAutomatonCegarLoop]: Abstraction has 2343 states and 3154 transitions. [2022-07-14 16:02:00,309 INFO L374 stractBuchiCegarLoop]: Abstraction has 2343 states and 3154 transitions. [2022-07-14 16:02:00,311 INFO L287 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-07-14 16:02:00,311 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2343 states and 3154 transitions. [2022-07-14 16:02:00,320 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2246 [2022-07-14 16:02:00,321 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:00,321 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:00,322 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:00,323 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:00,323 INFO L752 eck$LassoCheckResult]: Stem: 14565#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 14477#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 14474#L613 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14454#L298 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14455#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 14511#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 14524#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 14525#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14562#L424 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 14543#L118 assume !(1 == ~P_1_pc~0); 14503#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 14504#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 14507#L130 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 14363#L491 assume !(0 != activate_threads_~tmp~1#1); 14364#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 14514#L186 assume !(1 == ~P_2_pc~0); 14386#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 14387#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 14517#L198 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 14482#L499 assume !(0 != activate_threads_~tmp___0~1#1); 14483#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 14427#L268 assume !(1 == ~C_1_pc~0); 14428#L268-2 assume !(2 == ~C_1_pc~0); 14549#L278-1 is_C_1_triggered_~__retres1~2#1 := 0; 14468#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 14469#L290 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 14429#L507 assume !(0 != activate_threads_~tmp___1~1#1); 14430#L507-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14448#L432 assume { :end_inline_reset_delta_events } true; 14538#L561-2 assume !false; 15716#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 15268#L397 [2022-07-14 16:02:00,323 INFO L754 eck$LassoCheckResult]: Loop: 15268#L397 assume !false; 15714#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 15712#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 15709#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 15705#L346 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 15703#L362 assume 0 != eval_~tmp___2~0#1; 15701#L362-1 assume 0 == ~P_1_st~0;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 15699#L371 assume !(0 != eval_~tmp~0#1); 15697#L367 assume !(0 == ~P_2_st~0); 15692#L382 assume !(0 == ~C_1_st~0); 15268#L397 [2022-07-14 16:02:00,324 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:00,324 INFO L85 PathProgramCache]: Analyzing trace with hash 64203950, now seen corresponding path program 1 times [2022-07-14 16:02:00,325 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:00,325 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [403853007] [2022-07-14 16:02:00,325 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:00,325 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:00,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:00,331 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:02:00,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:00,339 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:02:00,340 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:00,340 INFO L85 PathProgramCache]: Analyzing trace with hash -658300295, now seen corresponding path program 1 times [2022-07-14 16:02:00,340 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:00,340 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [275064279] [2022-07-14 16:02:00,340 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:00,340 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:00,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:00,343 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:02:00,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:00,346 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:02:00,347 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:00,347 INFO L85 PathProgramCache]: Analyzing trace with hash -1216570650, now seen corresponding path program 1 times [2022-07-14 16:02:00,347 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:00,347 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [466769829] [2022-07-14 16:02:00,347 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:00,347 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:00,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:00,364 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:00,364 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:00,364 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [466769829] [2022-07-14 16:02:00,364 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [466769829] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:00,364 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:00,364 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:00,365 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [189234528] [2022-07-14 16:02:00,365 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:00,450 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:00,450 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:02:00,450 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:02:00,450 INFO L87 Difference]: Start difference. First operand 2343 states and 3154 transitions. cyclomatic complexity: 818 Second operand has 3 states, 3 states have (on average 13.666666666666666) internal successors, (41), 3 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:00,494 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:00,494 INFO L93 Difference]: Finished difference Result 3913 states and 5192 transitions. [2022-07-14 16:02:00,495 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:02:00,496 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3913 states and 5192 transitions. [2022-07-14 16:02:00,518 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3761 [2022-07-14 16:02:00,536 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3913 states to 3913 states and 5192 transitions. [2022-07-14 16:02:00,536 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3913 [2022-07-14 16:02:00,539 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3913 [2022-07-14 16:02:00,539 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3913 states and 5192 transitions. [2022-07-14 16:02:00,544 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:00,544 INFO L369 hiAutomatonCegarLoop]: Abstraction has 3913 states and 5192 transitions. [2022-07-14 16:02:00,546 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3913 states and 5192 transitions. [2022-07-14 16:02:00,590 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3913 to 3829. [2022-07-14 16:02:00,596 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3829 states, 3829 states have (on average 1.329328806476887) internal successors, (5090), 3828 states have internal predecessors, (5090), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:00,605 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3829 states to 3829 states and 5090 transitions. [2022-07-14 16:02:00,605 INFO L392 hiAutomatonCegarLoop]: Abstraction has 3829 states and 5090 transitions. [2022-07-14 16:02:00,605 INFO L374 stractBuchiCegarLoop]: Abstraction has 3829 states and 5090 transitions. [2022-07-14 16:02:00,605 INFO L287 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-07-14 16:02:00,605 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3829 states and 5090 transitions. [2022-07-14 16:02:00,616 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3677 [2022-07-14 16:02:00,616 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:00,617 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:00,618 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:00,618 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:00,618 INFO L752 eck$LassoCheckResult]: Stem: 20865#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 20743#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 20740#L613 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20722#L298 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20723#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 20782#L305-2 assume !(1 == ~P_2_i~0);~P_2_st~0 := 2; 20800#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 20801#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20848#L424 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 20849#L118 assume !(1 == ~P_1_pc~0); 20771#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 20772#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 20776#L130 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 20777#L491 assume !(0 != activate_threads_~tmp~1#1); 20857#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 20858#L186 assume !(1 == ~P_2_pc~0); 20645#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 20646#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 20790#L198 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 20791#L499 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 20748#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 20686#L268 assume !(1 == ~C_1_pc~0); 20687#L268-2 assume !(2 == ~C_1_pc~0); 20833#L278-1 is_C_1_triggered_~__retres1~2#1 := 0; 20834#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 20880#L290 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 20881#L507 assume !(0 != activate_threads_~tmp___1~1#1); 20709#L507-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20710#L432 assume { :end_inline_reset_delta_events } true; 22816#L561-2 assume !false; 22815#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 22809#L397 [2022-07-14 16:02:00,618 INFO L754 eck$LassoCheckResult]: Loop: 22809#L397 assume !false; 22810#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 22802#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 22803#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 22795#L346 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 22796#L362 assume 0 != eval_~tmp___2~0#1; 22759#L362-1 assume 0 == ~P_1_st~0;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 22760#L371 assume !(0 != eval_~tmp~0#1); 23645#L367 assume 0 == ~P_2_st~0;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 23639#L386 assume !(0 != eval_~tmp___0~0#1); 23630#L382 assume !(0 == ~C_1_st~0); 22809#L397 [2022-07-14 16:02:00,619 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:00,619 INFO L85 PathProgramCache]: Analyzing trace with hash -131921874, now seen corresponding path program 1 times [2022-07-14 16:02:00,619 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:00,619 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [12164929] [2022-07-14 16:02:00,619 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:00,619 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:00,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:00,632 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:00,632 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:00,632 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [12164929] [2022-07-14 16:02:00,632 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [12164929] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:00,632 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:00,633 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:00,633 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1517457582] [2022-07-14 16:02:00,633 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:00,633 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:00,634 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:00,634 INFO L85 PathProgramCache]: Analyzing trace with hash 1067386761, now seen corresponding path program 1 times [2022-07-14 16:02:00,634 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:00,634 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [960946405] [2022-07-14 16:02:00,634 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:00,634 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:00,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:00,637 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:02:00,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:00,640 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:02:00,729 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:00,729 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:02:00,730 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:02:00,730 INFO L87 Difference]: Start difference. First operand 3829 states and 5090 transitions. cyclomatic complexity: 1268 Second operand has 3 states, 3 states have (on average 10.333333333333334) internal successors, (31), 3 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:00,768 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:00,768 INFO L93 Difference]: Finished difference Result 3804 states and 5062 transitions. [2022-07-14 16:02:00,769 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:02:00,769 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3804 states and 5062 transitions. [2022-07-14 16:02:00,785 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3677 [2022-07-14 16:02:00,803 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3804 states to 3804 states and 5062 transitions. [2022-07-14 16:02:00,804 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3804 [2022-07-14 16:02:00,806 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3804 [2022-07-14 16:02:00,806 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3804 states and 5062 transitions. [2022-07-14 16:02:00,811 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:00,811 INFO L369 hiAutomatonCegarLoop]: Abstraction has 3804 states and 5062 transitions. [2022-07-14 16:02:00,813 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3804 states and 5062 transitions. [2022-07-14 16:02:00,853 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3804 to 3804. [2022-07-14 16:02:00,858 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3804 states, 3804 states have (on average 1.3307045215562565) internal successors, (5062), 3803 states have internal predecessors, (5062), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:00,866 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3804 states to 3804 states and 5062 transitions. [2022-07-14 16:02:00,866 INFO L392 hiAutomatonCegarLoop]: Abstraction has 3804 states and 5062 transitions. [2022-07-14 16:02:00,866 INFO L374 stractBuchiCegarLoop]: Abstraction has 3804 states and 5062 transitions. [2022-07-14 16:02:00,866 INFO L287 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-07-14 16:02:00,866 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3804 states and 5062 transitions. [2022-07-14 16:02:00,876 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3677 [2022-07-14 16:02:00,876 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:00,876 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:00,876 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:00,877 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:00,877 INFO L752 eck$LassoCheckResult]: Stem: 28470#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 28378#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 28376#L613 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28355#L298 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28356#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 28410#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 28425#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 28426#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28463#L424 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 28442#L118 assume !(1 == ~P_1_pc~0); 28403#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 28404#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 28407#L130 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 28266#L491 assume !(0 != activate_threads_~tmp~1#1); 28267#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 28414#L186 assume !(1 == ~P_2_pc~0); 28289#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 28290#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 28418#L198 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 28383#L499 assume !(0 != activate_threads_~tmp___0~1#1); 28384#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 28327#L268 assume !(1 == ~C_1_pc~0); 28328#L268-2 assume !(2 == ~C_1_pc~0); 28448#L278-1 is_C_1_triggered_~__retres1~2#1 := 0; 28369#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 28370#L290 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 28329#L507 assume !(0 != activate_threads_~tmp___1~1#1); 28330#L507-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28348#L432 assume { :end_inline_reset_delta_events } true; 28438#L561-2 assume !false; 31464#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 31368#L397 [2022-07-14 16:02:00,877 INFO L754 eck$LassoCheckResult]: Loop: 31368#L397 assume !false; 31459#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 31456#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 31453#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 31450#L346 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 31447#L362 assume 0 != eval_~tmp___2~0#1; 31444#L362-1 assume 0 == ~P_1_st~0;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 31440#L371 assume !(0 != eval_~tmp~0#1); 30733#L367 assume 0 == ~P_2_st~0;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 30603#L386 assume !(0 != eval_~tmp___0~0#1); 30604#L382 assume !(0 == ~C_1_st~0); 31368#L397 [2022-07-14 16:02:00,877 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:00,877 INFO L85 PathProgramCache]: Analyzing trace with hash 64203950, now seen corresponding path program 2 times [2022-07-14 16:02:00,877 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:00,877 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [443921143] [2022-07-14 16:02:00,878 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:00,878 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:00,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:00,883 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:02:00,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:00,891 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:02:00,891 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:00,891 INFO L85 PathProgramCache]: Analyzing trace with hash 1067386761, now seen corresponding path program 2 times [2022-07-14 16:02:00,891 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:00,891 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [894120318] [2022-07-14 16:02:00,892 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:00,892 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:00,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:00,894 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:02:00,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:00,897 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:02:00,898 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:00,898 INFO L85 PathProgramCache]: Analyzing trace with hash 940874940, now seen corresponding path program 1 times [2022-07-14 16:02:00,898 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:00,898 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1503273324] [2022-07-14 16:02:00,898 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:00,898 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:00,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:00,932 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:00,932 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:00,933 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1503273324] [2022-07-14 16:02:00,933 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1503273324] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:00,933 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:00,933 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-14 16:02:00,933 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1275722926] [2022-07-14 16:02:00,933 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:00,994 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:00,995 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:02:00,995 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:02:00,995 INFO L87 Difference]: Start difference. First operand 3804 states and 5062 transitions. cyclomatic complexity: 1265 Second operand has 3 states, 2 states have (on average 21.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:01,044 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:01,044 INFO L93 Difference]: Finished difference Result 6650 states and 8776 transitions. [2022-07-14 16:02:01,045 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:02:01,045 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6650 states and 8776 transitions. [2022-07-14 16:02:01,075 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 6427 [2022-07-14 16:02:01,106 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6650 states to 6650 states and 8776 transitions. [2022-07-14 16:02:01,106 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6650 [2022-07-14 16:02:01,110 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6650 [2022-07-14 16:02:01,110 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6650 states and 8776 transitions. [2022-07-14 16:02:01,119 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:01,119 INFO L369 hiAutomatonCegarLoop]: Abstraction has 6650 states and 8776 transitions. [2022-07-14 16:02:01,123 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6650 states and 8776 transitions. [2022-07-14 16:02:01,231 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6650 to 6650. [2022-07-14 16:02:01,242 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6650 states, 6650 states have (on average 1.3196992481203007) internal successors, (8776), 6649 states have internal predecessors, (8776), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:01,257 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6650 states to 6650 states and 8776 transitions. [2022-07-14 16:02:01,257 INFO L392 hiAutomatonCegarLoop]: Abstraction has 6650 states and 8776 transitions. [2022-07-14 16:02:01,257 INFO L374 stractBuchiCegarLoop]: Abstraction has 6650 states and 8776 transitions. [2022-07-14 16:02:01,257 INFO L287 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-07-14 16:02:01,257 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6650 states and 8776 transitions. [2022-07-14 16:02:01,283 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 6427 [2022-07-14 16:02:01,284 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:01,284 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:01,284 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:01,284 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:01,284 INFO L752 eck$LassoCheckResult]: Stem: 38948#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 38848#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 38846#L613 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38822#L298 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38823#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 38881#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 38897#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 38898#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38941#L424 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 38919#L118 assume !(1 == ~P_1_pc~0); 38873#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 38874#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 38877#L130 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 38728#L491 assume !(0 != activate_threads_~tmp~1#1); 38729#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 38885#L186 assume !(1 == ~P_2_pc~0); 38751#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 38752#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 38890#L198 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 38853#L499 assume !(0 != activate_threads_~tmp___0~1#1); 38854#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 38794#L268 assume !(1 == ~C_1_pc~0); 38795#L268-2 assume !(2 == ~C_1_pc~0); 38927#L278-1 is_C_1_triggered_~__retres1~2#1 := 0; 38837#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 38838#L290 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 38796#L507 assume !(0 != activate_threads_~tmp___1~1#1); 38797#L507-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38815#L432 assume { :end_inline_reset_delta_events } true; 38913#L561-2 assume !false; 39770#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 39771#L397 [2022-07-14 16:02:01,285 INFO L754 eck$LassoCheckResult]: Loop: 39771#L397 assume !false; 40138#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 40137#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 40136#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 40135#L346 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 40134#L362 assume 0 != eval_~tmp___2~0#1; 40133#L362-1 assume 0 == ~P_1_st~0;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 40131#L371 assume !(0 != eval_~tmp~0#1); 40130#L367 assume 0 == ~P_2_st~0;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 39766#L386 assume !(0 != eval_~tmp___0~0#1); 40129#L382 assume 0 == ~C_1_st~0;eval_~tmp___1~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 40139#L401 assume !(0 != eval_~tmp___1~0#1); 39771#L397 [2022-07-14 16:02:01,285 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:01,285 INFO L85 PathProgramCache]: Analyzing trace with hash 64203950, now seen corresponding path program 3 times [2022-07-14 16:02:01,285 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:01,285 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1350847273] [2022-07-14 16:02:01,285 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:01,286 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:01,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:01,291 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:02:01,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:01,299 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:02:01,299 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:01,299 INFO L85 PathProgramCache]: Analyzing trace with hash -1270750753, now seen corresponding path program 1 times [2022-07-14 16:02:01,300 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:01,300 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1294680221] [2022-07-14 16:02:01,300 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:01,300 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:01,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:01,303 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:02:01,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:01,306 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:02:01,306 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:01,306 INFO L85 PathProgramCache]: Analyzing trace with hash -897649908, now seen corresponding path program 1 times [2022-07-14 16:02:01,306 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:01,307 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [553623523] [2022-07-14 16:02:01,307 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:01,307 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:01,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:01,313 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:02:01,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:01,320 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:02:02,227 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 14.07 04:02:02 BoogieIcfgContainer [2022-07-14 16:02:02,227 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-07-14 16:02:02,228 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-07-14 16:02:02,228 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-07-14 16:02:02,228 INFO L275 PluginConnector]: Witness Printer initialized [2022-07-14 16:02:02,228 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.07 04:01:58" (3/4) ... [2022-07-14 16:02:02,230 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-07-14 16:02:02,264 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2022-07-14 16:02:02,264 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-07-14 16:02:02,264 INFO L158 Benchmark]: Toolchain (without parser) took 5019.30ms. Allocated memory was 88.1MB in the beginning and 169.9MB in the end (delta: 81.8MB). Free memory was 66.0MB in the beginning and 97.3MB in the end (delta: -31.3MB). Peak memory consumption was 49.9MB. Max. memory is 16.1GB. [2022-07-14 16:02:02,264 INFO L158 Benchmark]: CDTParser took 0.19ms. Allocated memory is still 88.1MB. Free memory was 66.4MB in the beginning and 66.3MB in the end (delta: 39.8kB). There was no memory consumed. Max. memory is 16.1GB. [2022-07-14 16:02:02,265 INFO L158 Benchmark]: CACSL2BoogieTranslator took 312.10ms. Allocated memory is still 88.1MB. Free memory was 65.8MB in the beginning and 61.4MB in the end (delta: 4.3MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2022-07-14 16:02:02,265 INFO L158 Benchmark]: Boogie Procedure Inliner took 54.03ms. Allocated memory is still 88.1MB. Free memory was 61.4MB in the beginning and 58.6MB in the end (delta: 2.8MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-07-14 16:02:02,265 INFO L158 Benchmark]: Boogie Preprocessor took 29.13ms. Allocated memory is still 88.1MB. Free memory was 58.6MB in the beginning and 56.4MB in the end (delta: 2.3MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-07-14 16:02:02,265 INFO L158 Benchmark]: RCFGBuilder took 578.65ms. Allocated memory was 88.1MB in the beginning and 107.0MB in the end (delta: 18.9MB). Free memory was 56.4MB in the beginning and 76.9MB in the end (delta: -20.5MB). Peak memory consumption was 18.7MB. Max. memory is 16.1GB. [2022-07-14 16:02:02,266 INFO L158 Benchmark]: BuchiAutomizer took 4004.67ms. Allocated memory was 107.0MB in the beginning and 169.9MB in the end (delta: 62.9MB). Free memory was 76.9MB in the beginning and 100.5MB in the end (delta: -23.6MB). Peak memory consumption was 104.1MB. Max. memory is 16.1GB. [2022-07-14 16:02:02,266 INFO L158 Benchmark]: Witness Printer took 36.06ms. Allocated memory is still 169.9MB. Free memory was 100.5MB in the beginning and 97.3MB in the end (delta: 3.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-07-14 16:02:02,267 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.19ms. Allocated memory is still 88.1MB. Free memory was 66.4MB in the beginning and 66.3MB in the end (delta: 39.8kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 312.10ms. Allocated memory is still 88.1MB. Free memory was 65.8MB in the beginning and 61.4MB in the end (delta: 4.3MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 54.03ms. Allocated memory is still 88.1MB. Free memory was 61.4MB in the beginning and 58.6MB in the end (delta: 2.8MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 29.13ms. Allocated memory is still 88.1MB. Free memory was 58.6MB in the beginning and 56.4MB in the end (delta: 2.3MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 578.65ms. Allocated memory was 88.1MB in the beginning and 107.0MB in the end (delta: 18.9MB). Free memory was 56.4MB in the beginning and 76.9MB in the end (delta: -20.5MB). Peak memory consumption was 18.7MB. Max. memory is 16.1GB. * BuchiAutomizer took 4004.67ms. Allocated memory was 107.0MB in the beginning and 169.9MB in the end (delta: 62.9MB). Free memory was 76.9MB in the beginning and 100.5MB in the end (delta: -23.6MB). Peak memory consumption was 104.1MB. Max. memory is 16.1GB. * Witness Printer took 36.06ms. Allocated memory is still 169.9MB. Free memory was 100.5MB in the beginning and 97.3MB in the end (delta: 3.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 11 terminating modules (11 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.11 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 6650 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 3.9s and 12 iterations. TraceHistogramMax:1. Analysis of lassos took 2.2s. Construction of modules took 0.2s. Büchi inclusion checks took 0.4s. Highest rank in rank-based complementation 0. Minimization of det autom 11. Minimization of nondet autom 0. Automata minimization 0.4s AutomataMinimizationTime, 11 MinimizatonAttempts, 1602 StatesRemovedByMinimization, 6 NontrivialMinimizations. Non-live state removal took 0.2s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 3995 SdHoareTripleChecker+Valid, 0.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 3995 mSDsluCounter, 6145 SdHoareTripleChecker+Invalid, 0.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 3372 mSDsCounter, 115 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 282 IncrementalHoareTripleChecker+Invalid, 397 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 115 mSolverCounterUnsat, 2773 mSDtfsCounter, 282 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI2 SFLT0 conc2 concLT0 SILN1 SILU0 SILI6 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 357]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=1} State at position 1 is {NULL=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4cf2315b=0, __retres1=0, P_1_pc=0, NULL=1, tmp___1=0, tmp=0, C_1_i=1, C_1_st=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@163f4fdf=0, data_0=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1444f0e7=0, __retres2=0, tmp___0=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1d64d9a6=0, __retres1=1, tmp=0, i=0, tmp___0=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7534ea5e=0, \result=0, P_1_i=1, e=0, \result=0, P_2_pc=0, clk=0, num=0, NULL=0, P_1_ev=0, C_1_pc=0, P_2_st=0, P_2_i=1, \result=1, tmp___2=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@db4dc7b=0, tmp=0, count=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@498ea868=0, data_1=0, tmp___1=0, max_loop=8, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@d387e28=0, C_1_pr=0, P_1_st=0, P_2_ev=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3c52e25a=0, C_1_ev=0, __retres1=0, timer=0, \result=0, kernel_st=1, tmp___0=0, \result=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 357]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int max_loop ; [L26] int clk ; [L27] int num ; [L28] int i ; [L29] int e ; [L30] int timer ; [L31] char data_0 ; [L32] char data_1 ; [L75] int P_1_pc; [L76] int P_1_st ; [L77] int P_1_i ; [L78] int P_1_ev ; [L133] int P_2_pc ; [L134] int P_2_st ; [L135] int P_2_i ; [L136] int P_2_ev ; [L201] int C_1_pc ; [L202] int C_1_st ; [L203] int C_1_i ; [L204] int C_1_ev ; [L205] int C_1_pr ; [L617] int count ; [L618] int __retres2 ; [L622] num = 0 [L623] i = 0 [L624] clk = 0 [L625] max_loop = 8 [L627] timer = 0 [L628] P_1_pc = 0 [L629] P_2_pc = 0 [L630] C_1_pc = 0 [L632] count = 0 [L633] CALL init_model() [L609] P_1_i = 1 [L610] P_2_i = 1 [L611] C_1_i = 1 [L633] RET init_model() [L634] CALL start_simulation() [L547] int kernel_st ; [L548] int tmp ; [L549] int tmp___0 ; [L553] kernel_st = 0 [L554] FCALL update_channels() [L555] CALL init_threads() [L305] COND TRUE (int )P_1_i == 1 [L306] P_1_st = 0 [L310] COND TRUE (int )P_2_i == 1 [L311] P_2_st = 0 [L315] COND TRUE (int )C_1_i == 1 [L316] C_1_st = 0 [L555] RET init_threads() [L556] FCALL fire_delta_events() [L557] CALL activate_threads() [L483] int tmp ; [L484] int tmp___0 ; [L485] int tmp___1 ; [L489] CALL, EXPR is_P_1_triggered() [L115] int __retres1 ; [L118] COND FALSE !((int )P_1_pc == 1) [L128] __retres1 = 0 [L130] return (__retres1); [L489] RET, EXPR is_P_1_triggered() [L489] tmp = is_P_1_triggered() [L491] COND FALSE !(\read(tmp)) [L497] CALL, EXPR is_P_2_triggered() [L183] int __retres1 ; [L186] COND FALSE !((int )P_2_pc == 1) [L196] __retres1 = 0 [L198] return (__retres1); [L497] RET, EXPR is_P_2_triggered() [L497] tmp___0 = is_P_2_triggered() [L499] COND FALSE !(\read(tmp___0)) [L505] CALL, EXPR is_C_1_triggered() [L265] int __retres1 ; [L268] COND FALSE !((int )C_1_pc == 1) [L278] COND FALSE !((int )C_1_pc == 2) [L288] __retres1 = 0 [L290] return (__retres1); [L505] RET, EXPR is_C_1_triggered() [L505] tmp___1 = is_C_1_triggered() [L507] COND FALSE !(\read(tmp___1)) [L557] RET activate_threads() [L558] FCALL reset_delta_events() [L561] COND TRUE 1 [L564] kernel_st = 1 [L565] CALL eval() [L350] int tmp ; [L351] int tmp___0 ; [L352] int tmp___1 ; [L353] int tmp___2 ; Loop: [L357] COND TRUE 1 [L360] CALL, EXPR exists_runnable_thread() [L325] int __retres1 ; [L328] COND TRUE (int )P_1_st == 0 [L329] __retres1 = 1 [L346] return (__retres1); [L360] RET, EXPR exists_runnable_thread() [L360] tmp___2 = exists_runnable_thread() [L362] COND TRUE \read(tmp___2) [L367] COND TRUE (int )P_1_st == 0 [L369] tmp = __VERIFIER_nondet_int() [L371] COND FALSE !(\read(tmp)) [L382] COND TRUE (int )P_2_st == 0 [L384] tmp___0 = __VERIFIER_nondet_int() [L386] COND FALSE !(\read(tmp___0)) [L397] COND TRUE (int )C_1_st == 0 [L399] tmp___1 = __VERIFIER_nondet_int() [L401] COND FALSE !(\read(tmp___1)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-07-14 16:02:02,307 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)