./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/pc_sfifo_2.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version f4b24e32 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/pc_sfifo_2.cil-2.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 5adc3402a12b42bc2aef7c382784898827eb467d1d3955bed162b3bd231708de --- Real Ultimate output --- This is Ultimate 0.2.2-?-f4b24e3 [2022-07-14 16:02:05,376 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-07-14 16:02:05,378 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-07-14 16:02:05,430 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-07-14 16:02:05,430 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-07-14 16:02:05,432 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-07-14 16:02:05,433 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-07-14 16:02:05,435 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-07-14 16:02:05,437 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-07-14 16:02:05,441 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-07-14 16:02:05,442 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-07-14 16:02:05,444 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-07-14 16:02:05,444 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-07-14 16:02:05,446 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-07-14 16:02:05,446 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-07-14 16:02:05,449 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-07-14 16:02:05,450 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-07-14 16:02:05,452 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-07-14 16:02:05,453 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-07-14 16:02:05,458 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-07-14 16:02:05,460 INFO L181 SettingsManager]: Resetting HornVerifier preferences to default values [2022-07-14 16:02:05,460 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-07-14 16:02:05,461 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-07-14 16:02:05,462 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-07-14 16:02:05,463 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-07-14 16:02:05,470 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-07-14 16:02:05,470 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-07-14 16:02:05,471 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-07-14 16:02:05,472 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-07-14 16:02:05,472 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-07-14 16:02:05,473 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-07-14 16:02:05,474 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-07-14 16:02:05,475 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-07-14 16:02:05,476 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-07-14 16:02:05,476 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-07-14 16:02:05,478 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-07-14 16:02:05,478 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-07-14 16:02:05,479 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-07-14 16:02:05,479 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-07-14 16:02:05,479 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-07-14 16:02:05,480 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-07-14 16:02:05,482 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-07-14 16:02:05,483 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-07-14 16:02:05,511 INFO L113 SettingsManager]: Loading preferences was successful [2022-07-14 16:02:05,511 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-07-14 16:02:05,512 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-07-14 16:02:05,512 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-07-14 16:02:05,514 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-07-14 16:02:05,514 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-07-14 16:02:05,514 INFO L138 SettingsManager]: * Use SBE=true [2022-07-14 16:02:05,514 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-07-14 16:02:05,514 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-07-14 16:02:05,515 INFO L138 SettingsManager]: * Use old map elimination=false [2022-07-14 16:02:05,515 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-07-14 16:02:05,516 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-07-14 16:02:05,516 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-07-14 16:02:05,516 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-07-14 16:02:05,516 INFO L138 SettingsManager]: * sizeof long=4 [2022-07-14 16:02:05,516 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-07-14 16:02:05,517 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-07-14 16:02:05,517 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-07-14 16:02:05,517 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-07-14 16:02:05,517 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-07-14 16:02:05,517 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-07-14 16:02:05,517 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-07-14 16:02:05,518 INFO L138 SettingsManager]: * sizeof long double=12 [2022-07-14 16:02:05,518 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-07-14 16:02:05,518 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-07-14 16:02:05,518 INFO L138 SettingsManager]: * Use constant arrays=true [2022-07-14 16:02:05,518 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-07-14 16:02:05,519 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-07-14 16:02:05,519 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-07-14 16:02:05,519 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-07-14 16:02:05,519 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-07-14 16:02:05,520 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-07-14 16:02:05,520 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 5adc3402a12b42bc2aef7c382784898827eb467d1d3955bed162b3bd231708de [2022-07-14 16:02:05,731 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-07-14 16:02:05,754 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-07-14 16:02:05,756 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-07-14 16:02:05,757 INFO L271 PluginConnector]: Initializing CDTParser... [2022-07-14 16:02:05,758 INFO L275 PluginConnector]: CDTParser initialized [2022-07-14 16:02:05,759 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/pc_sfifo_2.cil-2.c [2022-07-14 16:02:05,827 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/b292ab1ce/a5711ca3a7ba4d95a59ffe3d8c2d830b/FLAG003cfb5ba [2022-07-14 16:02:06,274 INFO L306 CDTParser]: Found 1 translation units. [2022-07-14 16:02:06,274 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_2.cil-2.c [2022-07-14 16:02:06,283 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/b292ab1ce/a5711ca3a7ba4d95a59ffe3d8c2d830b/FLAG003cfb5ba [2022-07-14 16:02:06,664 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/b292ab1ce/a5711ca3a7ba4d95a59ffe3d8c2d830b [2022-07-14 16:02:06,666 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-07-14 16:02:06,667 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-07-14 16:02:06,669 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-07-14 16:02:06,669 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-07-14 16:02:06,671 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-07-14 16:02:06,672 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.07 04:02:06" (1/1) ... [2022-07-14 16:02:06,673 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2c649f6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:06, skipping insertion in model container [2022-07-14 16:02:06,673 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.07 04:02:06" (1/1) ... [2022-07-14 16:02:06,679 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-07-14 16:02:06,704 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-07-14 16:02:06,838 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_2.cil-2.c[643,656] [2022-07-14 16:02:06,872 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-14 16:02:06,881 INFO L203 MainTranslator]: Completed pre-run [2022-07-14 16:02:06,890 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_2.cil-2.c[643,656] [2022-07-14 16:02:06,909 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-14 16:02:06,929 INFO L208 MainTranslator]: Completed translation [2022-07-14 16:02:06,930 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:06 WrapperNode [2022-07-14 16:02:06,930 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-07-14 16:02:06,930 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-07-14 16:02:06,931 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-07-14 16:02:06,931 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-07-14 16:02:06,936 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:06" (1/1) ... [2022-07-14 16:02:06,943 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:06" (1/1) ... [2022-07-14 16:02:06,970 INFO L137 Inliner]: procedures = 29, calls = 32, calls flagged for inlining = 27, calls inlined = 28, statements flattened = 308 [2022-07-14 16:02:06,971 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-07-14 16:02:06,971 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-07-14 16:02:06,972 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-07-14 16:02:06,972 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-07-14 16:02:06,979 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:06" (1/1) ... [2022-07-14 16:02:06,980 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:06" (1/1) ... [2022-07-14 16:02:06,982 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:06" (1/1) ... [2022-07-14 16:02:06,982 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:06" (1/1) ... [2022-07-14 16:02:06,986 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:06" (1/1) ... [2022-07-14 16:02:06,991 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:06" (1/1) ... [2022-07-14 16:02:06,993 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:06" (1/1) ... [2022-07-14 16:02:06,996 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-07-14 16:02:06,996 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-07-14 16:02:06,997 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-07-14 16:02:06,997 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-07-14 16:02:06,998 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:06" (1/1) ... [2022-07-14 16:02:07,008 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 16:02:07,029 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 16:02:07,045 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-14 16:02:07,075 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-07-14 16:02:07,099 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-07-14 16:02:07,099 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-07-14 16:02:07,099 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-07-14 16:02:07,099 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-07-14 16:02:07,184 INFO L234 CfgBuilder]: Building ICFG [2022-07-14 16:02:07,185 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-07-14 16:02:07,570 INFO L275 CfgBuilder]: Performing block encoding [2022-07-14 16:02:07,582 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-07-14 16:02:07,582 INFO L299 CfgBuilder]: Removed 4 assume(true) statements. [2022-07-14 16:02:07,584 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.07 04:02:07 BoogieIcfgContainer [2022-07-14 16:02:07,584 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-07-14 16:02:07,585 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-07-14 16:02:07,585 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-07-14 16:02:07,589 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-07-14 16:02:07,589 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-14 16:02:07,590 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 14.07 04:02:06" (1/3) ... [2022-07-14 16:02:07,591 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5ef7c374 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 14.07 04:02:07, skipping insertion in model container [2022-07-14 16:02:07,591 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-14 16:02:07,591 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:06" (2/3) ... [2022-07-14 16:02:07,591 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5ef7c374 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 14.07 04:02:07, skipping insertion in model container [2022-07-14 16:02:07,592 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-14 16:02:07,592 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.07 04:02:07" (3/3) ... [2022-07-14 16:02:07,593 INFO L354 chiAutomizerObserver]: Analyzing ICFG pc_sfifo_2.cil-2.c [2022-07-14 16:02:07,661 INFO L255 stractBuchiCegarLoop]: Interprodecural is true [2022-07-14 16:02:07,661 INFO L256 stractBuchiCegarLoop]: Hoare is false [2022-07-14 16:02:07,661 INFO L257 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-07-14 16:02:07,661 INFO L258 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-07-14 16:02:07,661 INFO L259 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-07-14 16:02:07,662 INFO L260 stractBuchiCegarLoop]: Difference is false [2022-07-14 16:02:07,662 INFO L261 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-07-14 16:02:07,662 INFO L265 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-07-14 16:02:07,666 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 105 states, 104 states have (on average 1.5288461538461537) internal successors, (159), 104 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:07,696 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 69 [2022-07-14 16:02:07,696 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:07,696 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:07,703 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:07,703 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:07,704 INFO L287 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-07-14 16:02:07,705 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 105 states, 104 states have (on average 1.5288461538461537) internal successors, (159), 104 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:07,717 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 69 [2022-07-14 16:02:07,718 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:07,718 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:07,721 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:07,721 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:07,727 INFO L752 eck$LassoCheckResult]: Stem: 100#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 29#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 64#L462true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 68#L222true assume !(1 == ~q_req_up~0); 9#L222-2true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 80#L237true assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 30#L237-2true assume !(1 == ~c_dr_i~0);~c_dr_st~0 := 2; 36#L242-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 86#L275true assume !(0 == ~q_read_ev~0); 94#L275-2true assume !(0 == ~q_write_ev~0); 22#L280-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 106#L65true assume !(1 == ~p_dw_pc~0); 28#L65-2true is_do_write_p_triggered_~__retres1~0#1 := 0; 53#L76true is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 63#L77true activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 33#L315true assume !(0 != activate_threads_~tmp~1#1); 65#L315-2true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 98#L84true assume 1 == ~c_dr_pc~0; 24#L85true assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 71#L95true is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 90#L96true activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4#L323true assume !(0 != activate_threads_~tmp___0~1#1); 46#L323-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 99#L293true assume !(1 == ~q_read_ev~0); 2#L293-2true assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 34#L298-1true assume { :end_inline_reset_delta_events } true; 10#L419-2true [2022-07-14 16:02:07,729 INFO L754 eck$LassoCheckResult]: Loop: 10#L419-2true assume !false; 26#L420true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 102#L364true assume !true; 60#L380true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 82#L222-3true assume !(1 == ~q_req_up~0); 31#L222-5true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 79#L275-3true assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 38#L275-5true assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 52#L280-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 61#L65-3true assume !(1 == ~p_dw_pc~0); 17#L65-5true is_do_write_p_triggered_~__retres1~0#1 := 0; 95#L76-1true is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 72#L77-1true activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 39#L315-3true assume !(0 != activate_threads_~tmp~1#1); 83#L315-5true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 57#L84-3true assume !(1 == ~c_dr_pc~0); 88#L84-5true is_do_read_c_triggered_~__retres1~1#1 := 0; 78#L95-1true is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 58#L96-1true activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 104#L323-3true assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 77#L323-5true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 91#L293-3true assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 5#L293-5true assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 51#L298-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 23#L255-1true assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 25#L267-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 55#L268-1true stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 11#L394true assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 7#L401true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 70#L402true start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 27#L436true assume !(0 != start_simulation_~tmp~4#1); 10#L419-2true [2022-07-14 16:02:07,744 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:07,745 INFO L85 PathProgramCache]: Analyzing trace with hash -239976594, now seen corresponding path program 1 times [2022-07-14 16:02:07,754 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:07,755 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1678767996] [2022-07-14 16:02:07,755 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:07,756 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:07,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:07,910 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:07,911 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:07,912 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1678767996] [2022-07-14 16:02:07,913 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1678767996] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:07,913 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:07,914 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:07,915 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1543556800] [2022-07-14 16:02:07,916 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:07,920 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:07,922 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:07,922 INFO L85 PathProgramCache]: Analyzing trace with hash 603406639, now seen corresponding path program 1 times [2022-07-14 16:02:07,923 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:07,923 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1281863961] [2022-07-14 16:02:07,924 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:07,924 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:07,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:07,953 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:07,953 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:07,953 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1281863961] [2022-07-14 16:02:07,954 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1281863961] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:07,954 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:07,954 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-14 16:02:07,954 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1373633549] [2022-07-14 16:02:07,954 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:07,955 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:07,956 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:07,983 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:02:07,984 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:02:07,986 INFO L87 Difference]: Start difference. First operand has 105 states, 104 states have (on average 1.5288461538461537) internal successors, (159), 104 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:08,015 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:08,015 INFO L93 Difference]: Finished difference Result 102 states and 144 transitions. [2022-07-14 16:02:08,016 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:02:08,021 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 102 states and 144 transitions. [2022-07-14 16:02:08,023 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 63 [2022-07-14 16:02:08,026 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 102 states to 95 states and 137 transitions. [2022-07-14 16:02:08,027 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 95 [2022-07-14 16:02:08,027 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 95 [2022-07-14 16:02:08,028 INFO L73 IsDeterministic]: Start isDeterministic. Operand 95 states and 137 transitions. [2022-07-14 16:02:08,028 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:08,029 INFO L369 hiAutomatonCegarLoop]: Abstraction has 95 states and 137 transitions. [2022-07-14 16:02:08,042 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 95 states and 137 transitions. [2022-07-14 16:02:08,051 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 95 to 95. [2022-07-14 16:02:08,052 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 95 states, 95 states have (on average 1.4421052631578948) internal successors, (137), 94 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:08,053 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95 states to 95 states and 137 transitions. [2022-07-14 16:02:08,054 INFO L392 hiAutomatonCegarLoop]: Abstraction has 95 states and 137 transitions. [2022-07-14 16:02:08,054 INFO L374 stractBuchiCegarLoop]: Abstraction has 95 states and 137 transitions. [2022-07-14 16:02:08,054 INFO L287 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-07-14 16:02:08,054 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 95 states and 137 transitions. [2022-07-14 16:02:08,055 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 63 [2022-07-14 16:02:08,056 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:08,056 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:08,057 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:08,057 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:08,057 INFO L752 eck$LassoCheckResult]: Stem: 310#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 298#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 252#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 253#L222 assume !(1 == ~q_req_up~0); 248#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 249#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 284#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 303#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 301#L275 assume !(0 == ~q_read_ev~0); 302#L275-2 assume !(0 == ~q_write_ev~0); 288#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 289#L65 assume !(1 == ~p_dw_pc~0); 287#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 286#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 244#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 245#L315 assume !(0 != activate_threads_~tmp~1#1); 254#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 255#L84 assume 1 == ~c_dr_pc~0; 294#L85 assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 265#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 266#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 227#L323 assume !(0 != activate_threads_~tmp___0~1#1); 228#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 309#L293 assume !(1 == ~q_read_ev~0); 216#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 217#L298-1 assume { :end_inline_reset_delta_events } true; 250#L419-2 [2022-07-14 16:02:08,058 INFO L754 eck$LassoCheckResult]: Loop: 250#L419-2 assume !false; 251#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 239#L364 assume !false; 290#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 262#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 221#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 269#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 270#L344 assume !(0 != eval_~tmp___1~0#1); 233#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 234#L222-3 assume !(1 == ~q_req_up~0); 295#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 282#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 283#L275-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 308#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 235#L65-3 assume !(1 == ~p_dw_pc~0); 236#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 273#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 267#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 268#L315-3 assume !(0 != activate_threads_~tmp~1#1); 296#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 222#L84-3 assume !(1 == ~c_dr_pc~0); 224#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 281#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 225#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 226#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 279#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 280#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 231#L293-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 232#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 291#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 292#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 218#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 219#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 242#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 243#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 264#L436 assume !(0 != start_simulation_~tmp~4#1); 250#L419-2 [2022-07-14 16:02:08,058 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:08,058 INFO L85 PathProgramCache]: Analyzing trace with hash 577671856, now seen corresponding path program 1 times [2022-07-14 16:02:08,059 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:08,059 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2068511659] [2022-07-14 16:02:08,059 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:08,059 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:08,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:08,115 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:08,116 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:08,116 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2068511659] [2022-07-14 16:02:08,116 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2068511659] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:08,117 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:08,117 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-07-14 16:02:08,117 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1967160392] [2022-07-14 16:02:08,117 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:08,118 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:08,118 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:08,118 INFO L85 PathProgramCache]: Analyzing trace with hash -631754702, now seen corresponding path program 1 times [2022-07-14 16:02:08,118 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:08,119 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [876409327] [2022-07-14 16:02:08,119 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:08,119 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:08,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:08,180 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:08,181 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:08,181 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [876409327] [2022-07-14 16:02:08,181 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [876409327] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:08,181 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:08,181 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:02:08,182 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [502401291] [2022-07-14 16:02:08,182 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:08,182 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:08,182 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:08,183 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-07-14 16:02:08,183 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-07-14 16:02:08,183 INFO L87 Difference]: Start difference. First operand 95 states and 137 transitions. cyclomatic complexity: 43 Second operand has 5 states, 5 states have (on average 5.2) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:08,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:08,338 INFO L93 Difference]: Finished difference Result 312 states and 441 transitions. [2022-07-14 16:02:08,338 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-07-14 16:02:08,339 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 312 states and 441 transitions. [2022-07-14 16:02:08,343 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 283 [2022-07-14 16:02:08,345 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 312 states to 312 states and 441 transitions. [2022-07-14 16:02:08,345 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 312 [2022-07-14 16:02:08,346 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 312 [2022-07-14 16:02:08,346 INFO L73 IsDeterministic]: Start isDeterministic. Operand 312 states and 441 transitions. [2022-07-14 16:02:08,348 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:08,348 INFO L369 hiAutomatonCegarLoop]: Abstraction has 312 states and 441 transitions. [2022-07-14 16:02:08,349 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 312 states and 441 transitions. [2022-07-14 16:02:08,361 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 312 to 298. [2022-07-14 16:02:08,362 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 298 states, 298 states have (on average 1.4261744966442953) internal successors, (425), 297 states have internal predecessors, (425), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:08,363 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 298 states to 298 states and 425 transitions. [2022-07-14 16:02:08,364 INFO L392 hiAutomatonCegarLoop]: Abstraction has 298 states and 425 transitions. [2022-07-14 16:02:08,364 INFO L374 stractBuchiCegarLoop]: Abstraction has 298 states and 425 transitions. [2022-07-14 16:02:08,364 INFO L287 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-07-14 16:02:08,364 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 298 states and 425 transitions. [2022-07-14 16:02:08,366 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 270 [2022-07-14 16:02:08,366 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:08,366 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:08,367 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:08,367 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:08,367 INFO L752 eck$LassoCheckResult]: Stem: 730#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 716#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 673#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 674#L222 assume !(1 == ~q_req_up~0); 669#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 670#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 703#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 721#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 719#L275 assume !(0 == ~q_read_ev~0); 720#L275-2 assume !(0 == ~q_write_ev~0); 708#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 709#L65 assume !(1 == ~p_dw_pc~0); 706#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 705#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 665#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 666#L315 assume !(0 != activate_threads_~tmp~1#1); 675#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 676#L84 assume !(1 == ~c_dr_pc~0); 692#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 685#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 686#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 648#L323 assume !(0 != activate_threads_~tmp___0~1#1); 649#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 729#L293 assume !(1 == ~q_read_ev~0); 640#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 641#L298-1 assume { :end_inline_reset_delta_events } true; 671#L419-2 [2022-07-14 16:02:08,368 INFO L754 eck$LassoCheckResult]: Loop: 671#L419-2 assume !false; 672#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 680#L364 assume !false; 707#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 679#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 647#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 687#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 688#L344 assume !(0 != eval_~tmp___1~0#1); 654#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 655#L222-3 assume !(1 == ~q_req_up~0); 713#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 701#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 702#L275-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 728#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 656#L65-3 assume !(1 == ~p_dw_pc~0); 657#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 691#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 683#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 684#L315-3 assume !(0 != activate_threads_~tmp~1#1); 714#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 642#L84-3 assume !(1 == ~c_dr_pc~0); 643#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 700#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 644#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 645#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 698#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 699#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 650#L293-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 651#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 710#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 711#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 638#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 639#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 661#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 662#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 682#L436 assume !(0 != start_simulation_~tmp~4#1); 671#L419-2 [2022-07-14 16:02:08,368 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:08,368 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647375, now seen corresponding path program 1 times [2022-07-14 16:02:08,369 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:08,369 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [978463532] [2022-07-14 16:02:08,369 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:08,369 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:08,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:08,410 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:08,410 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:08,410 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [978463532] [2022-07-14 16:02:08,410 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [978463532] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:08,411 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:08,411 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-07-14 16:02:08,411 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [54365708] [2022-07-14 16:02:08,411 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:08,412 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:08,412 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:08,412 INFO L85 PathProgramCache]: Analyzing trace with hash -631754702, now seen corresponding path program 2 times [2022-07-14 16:02:08,412 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:08,413 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [614714938] [2022-07-14 16:02:08,413 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:08,413 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:08,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:08,445 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:08,446 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:08,446 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [614714938] [2022-07-14 16:02:08,446 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [614714938] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:08,446 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:08,447 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:02:08,447 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1274012828] [2022-07-14 16:02:08,447 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:08,447 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:08,448 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:08,448 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:02:08,448 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:02:08,448 INFO L87 Difference]: Start difference. First operand 298 states and 425 transitions. cyclomatic complexity: 129 Second operand has 4 states, 4 states have (on average 6.5) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:08,523 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:08,523 INFO L93 Difference]: Finished difference Result 683 states and 947 transitions. [2022-07-14 16:02:08,523 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:02:08,524 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 683 states and 947 transitions. [2022-07-14 16:02:08,529 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 620 [2022-07-14 16:02:08,534 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 683 states to 683 states and 947 transitions. [2022-07-14 16:02:08,535 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 683 [2022-07-14 16:02:08,536 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 683 [2022-07-14 16:02:08,536 INFO L73 IsDeterministic]: Start isDeterministic. Operand 683 states and 947 transitions. [2022-07-14 16:02:08,542 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:08,542 INFO L369 hiAutomatonCegarLoop]: Abstraction has 683 states and 947 transitions. [2022-07-14 16:02:08,543 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 683 states and 947 transitions. [2022-07-14 16:02:08,565 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 683 to 683. [2022-07-14 16:02:08,572 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 683 states, 683 states have (on average 1.3865300146412884) internal successors, (947), 682 states have internal predecessors, (947), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:08,577 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 683 states to 683 states and 947 transitions. [2022-07-14 16:02:08,579 INFO L392 hiAutomatonCegarLoop]: Abstraction has 683 states and 947 transitions. [2022-07-14 16:02:08,579 INFO L374 stractBuchiCegarLoop]: Abstraction has 683 states and 947 transitions. [2022-07-14 16:02:08,579 INFO L287 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-07-14 16:02:08,579 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 683 states and 947 transitions. [2022-07-14 16:02:08,587 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 620 [2022-07-14 16:02:08,587 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:08,587 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:08,588 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:08,588 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:08,588 INFO L752 eck$LassoCheckResult]: Stem: 1750#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 1721#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 1668#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1669#L222 assume !(1 == ~q_req_up~0); 1664#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1665#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 1704#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 1728#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1723#L275 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 1724#L275-2 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 1740#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 1780#L65 assume !(1 == ~p_dw_pc~0); 1778#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 1777#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 1776#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1775#L315 assume !(0 != activate_threads_~tmp~1#1); 1774#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 1773#L84 assume !(1 == ~c_dr_pc~0); 1772#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 1771#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 1770#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1769#L323 assume !(0 != activate_threads_~tmp___0~1#1); 1768#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1767#L293 assume !(1 == ~q_read_ev~0); 1765#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 1766#L298-1 assume { :end_inline_reset_delta_events } true; 2073#L419-2 [2022-07-14 16:02:08,589 INFO L754 eck$LassoCheckResult]: Loop: 2073#L419-2 assume !false; 2071#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 1675#L364 assume !false; 1707#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1674#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1637#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1682#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 1683#L344 assume !(0 != eval_~tmp___1~0#1); 1648#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1649#L222-3 assume !(1 == ~q_req_up~0); 1714#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1702#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 1703#L275-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 1742#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 2313#L65-3 assume 1 == ~p_dw_pc~0; 2309#L66-1 assume 1 == ~q_read_ev~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 2308#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 2306#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1744#L315-3 assume !(0 != activate_threads_~tmp~1#1); 1716#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 1717#L84-3 assume !(1 == ~c_dr_pc~0); 2303#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 2302#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 1640#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1641#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 2300#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2299#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 2298#L293-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 1647#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1710#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1711#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1981#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 1979#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 1977#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1973#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1974#L436 assume !(0 != start_simulation_~tmp~4#1); 2073#L419-2 [2022-07-14 16:02:08,589 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:08,589 INFO L85 PathProgramCache]: Analyzing trace with hash 1964845233, now seen corresponding path program 1 times [2022-07-14 16:02:08,590 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:08,590 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [226984371] [2022-07-14 16:02:08,590 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:08,590 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:08,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:08,615 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:08,615 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:08,615 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [226984371] [2022-07-14 16:02:08,616 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [226984371] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:08,616 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:08,616 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:08,616 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1596357421] [2022-07-14 16:02:08,616 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:08,617 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:08,617 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:08,617 INFO L85 PathProgramCache]: Analyzing trace with hash -518368045, now seen corresponding path program 1 times [2022-07-14 16:02:08,618 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:08,618 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1363727369] [2022-07-14 16:02:08,618 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:08,618 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:08,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:08,649 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:08,649 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:08,650 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1363727369] [2022-07-14 16:02:08,650 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1363727369] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:08,650 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:08,650 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:02:08,650 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [523988739] [2022-07-14 16:02:08,651 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:08,651 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:08,651 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:08,652 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:02:08,652 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:02:08,652 INFO L87 Difference]: Start difference. First operand 683 states and 947 transitions. cyclomatic complexity: 268 Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:08,675 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:08,675 INFO L93 Difference]: Finished difference Result 952 states and 1297 transitions. [2022-07-14 16:02:08,676 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:02:08,676 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 952 states and 1297 transitions. [2022-07-14 16:02:08,682 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 906 [2022-07-14 16:02:08,687 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 952 states to 952 states and 1297 transitions. [2022-07-14 16:02:08,687 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 952 [2022-07-14 16:02:08,688 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 952 [2022-07-14 16:02:08,688 INFO L73 IsDeterministic]: Start isDeterministic. Operand 952 states and 1297 transitions. [2022-07-14 16:02:08,689 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:08,690 INFO L369 hiAutomatonCegarLoop]: Abstraction has 952 states and 1297 transitions. [2022-07-14 16:02:08,690 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 952 states and 1297 transitions. [2022-07-14 16:02:08,699 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 952 to 680. [2022-07-14 16:02:08,700 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 680 states, 680 states have (on average 1.3661764705882353) internal successors, (929), 679 states have internal predecessors, (929), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:08,702 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 680 states to 680 states and 929 transitions. [2022-07-14 16:02:08,702 INFO L392 hiAutomatonCegarLoop]: Abstraction has 680 states and 929 transitions. [2022-07-14 16:02:08,702 INFO L374 stractBuchiCegarLoop]: Abstraction has 680 states and 929 transitions. [2022-07-14 16:02:08,702 INFO L287 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-07-14 16:02:08,703 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 680 states and 929 transitions. [2022-07-14 16:02:08,706 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 636 [2022-07-14 16:02:08,706 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:08,706 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:08,707 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:08,707 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:08,707 INFO L752 eck$LassoCheckResult]: Stem: 3383#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 3359#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 3309#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3310#L222 assume !(1 == ~q_req_up~0); 3307#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3308#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 3345#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 3367#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3363#L275 assume !(0 == ~q_read_ev~0); 3364#L275-2 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 3376#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 3397#L65 assume !(1 == ~p_dw_pc~0); 3347#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 3395#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 3396#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3374#L315 assume !(0 != activate_threads_~tmp~1#1); 3375#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 3379#L84 assume !(1 == ~c_dr_pc~0); 3380#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 3322#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 3323#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3286#L323 assume !(0 != activate_threads_~tmp___0~1#1); 3287#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3381#L293 assume !(1 == ~q_read_ev~0); 3382#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 3277#L298-1 assume { :end_inline_reset_delta_events } true; 3311#L419-2 [2022-07-14 16:02:08,708 INFO L754 eck$LassoCheckResult]: Loop: 3311#L419-2 assume !false; 3312#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 3319#L364 assume !false; 3350#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3318#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3281#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3326#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 3327#L344 assume !(0 != eval_~tmp___1~0#1); 3292#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3293#L222-3 assume !(1 == ~q_req_up~0); 3355#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3343#L275-3 assume !(0 == ~q_read_ev~0); 3344#L275-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 3377#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 3934#L65-3 assume !(1 == ~p_dw_pc~0); 3932#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 3931#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 3930#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3929#L315-3 assume !(0 != activate_threads_~tmp~1#1); 3928#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 3927#L84-3 assume !(1 == ~c_dr_pc~0); 3926#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 3925#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 3924#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3923#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 3922#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3921#L293-3 assume !(1 == ~q_read_ev~0); 3920#L293-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 3291#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3351#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3352#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3871#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 3315#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 3301#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3302#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 3321#L436 assume !(0 != start_simulation_~tmp~4#1); 3311#L419-2 [2022-07-14 16:02:08,708 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:08,708 INFO L85 PathProgramCache]: Analyzing trace with hash -29299473, now seen corresponding path program 1 times [2022-07-14 16:02:08,708 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:08,709 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [922773007] [2022-07-14 16:02:08,709 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:08,709 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:08,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:08,769 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:08,772 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:08,772 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [922773007] [2022-07-14 16:02:08,772 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [922773007] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:08,773 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:08,773 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-07-14 16:02:08,773 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [690428115] [2022-07-14 16:02:08,773 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:08,774 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:08,774 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:08,774 INFO L85 PathProgramCache]: Analyzing trace with hash -884233102, now seen corresponding path program 1 times [2022-07-14 16:02:08,775 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:08,785 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1205616075] [2022-07-14 16:02:08,786 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:08,786 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:08,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:08,827 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:08,827 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:08,827 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1205616075] [2022-07-14 16:02:08,827 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1205616075] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:08,827 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:08,828 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:02:08,828 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1039169723] [2022-07-14 16:02:08,828 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:08,828 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:08,828 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:08,829 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:02:08,829 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:02:08,829 INFO L87 Difference]: Start difference. First operand 680 states and 929 transitions. cyclomatic complexity: 251 Second operand has 4 states, 4 states have (on average 6.5) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:08,878 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:08,878 INFO L93 Difference]: Finished difference Result 830 states and 1123 transitions. [2022-07-14 16:02:08,878 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-07-14 16:02:08,881 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 830 states and 1123 transitions. [2022-07-14 16:02:08,886 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 802 [2022-07-14 16:02:08,890 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 830 states to 830 states and 1123 transitions. [2022-07-14 16:02:08,890 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 830 [2022-07-14 16:02:08,891 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 830 [2022-07-14 16:02:08,891 INFO L73 IsDeterministic]: Start isDeterministic. Operand 830 states and 1123 transitions. [2022-07-14 16:02:08,892 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:08,892 INFO L369 hiAutomatonCegarLoop]: Abstraction has 830 states and 1123 transitions. [2022-07-14 16:02:08,893 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 830 states and 1123 transitions. [2022-07-14 16:02:08,901 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 830 to 608. [2022-07-14 16:02:08,902 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 608 states, 608 states have (on average 1.356907894736842) internal successors, (825), 607 states have internal predecessors, (825), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:08,904 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 608 states to 608 states and 825 transitions. [2022-07-14 16:02:08,904 INFO L392 hiAutomatonCegarLoop]: Abstraction has 608 states and 825 transitions. [2022-07-14 16:02:08,904 INFO L374 stractBuchiCegarLoop]: Abstraction has 608 states and 825 transitions. [2022-07-14 16:02:08,905 INFO L287 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-07-14 16:02:08,905 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 608 states and 825 transitions. [2022-07-14 16:02:08,907 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 580 [2022-07-14 16:02:08,908 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:08,908 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:08,910 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:08,910 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:08,910 INFO L752 eck$LassoCheckResult]: Stem: 4895#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 4878#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 4834#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4835#L222 assume !(1 == ~q_req_up~0); 4830#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4831#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 4865#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 4885#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4881#L275 assume !(0 == ~q_read_ev~0); 4882#L275-2 assume !(0 == ~q_write_ev~0); 4869#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 4870#L65 assume !(1 == ~p_dw_pc~0); 4867#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 4875#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 4828#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 4829#L315 assume !(0 != activate_threads_~tmp~1#1); 4836#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 4837#L84 assume !(1 == ~c_dr_pc~0); 4853#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 4846#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 4847#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4808#L323 assume !(0 != activate_threads_~tmp___0~1#1); 4809#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4892#L293 assume !(1 == ~q_read_ev~0); 4800#L293-2 assume !(1 == ~q_write_ev~0); 4801#L298-1 assume { :end_inline_reset_delta_events } true; 4890#L419-2 [2022-07-14 16:02:08,911 INFO L754 eck$LassoCheckResult]: Loop: 4890#L419-2 assume !false; 5156#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 4841#L364 assume !false; 5116#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5115#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5113#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5095#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 4857#L344 assume !(0 != eval_~tmp___1~0#1); 4859#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5223#L222-3 assume !(1 == ~q_req_up~0); 5221#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5219#L275-3 assume !(0 == ~q_read_ev~0); 5216#L275-5 assume !(0 == ~q_write_ev~0); 5214#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 5212#L65-3 assume !(1 == ~p_dw_pc~0); 5209#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 5207#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 5206#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 5205#L315-3 assume !(0 != activate_threads_~tmp~1#1); 5204#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 5201#L84-3 assume !(1 == ~c_dr_pc~0); 5198#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 5195#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 5192#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5189#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 5186#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5181#L293-3 assume !(1 == ~q_read_ev~0); 5178#L293-5 assume !(1 == ~q_write_ev~0); 5176#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5173#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5170#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5168#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 5166#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 5164#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5162#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 5160#L436 assume !(0 != start_simulation_~tmp~4#1); 4890#L419-2 [2022-07-14 16:02:08,912 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:08,912 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 1 times [2022-07-14 16:02:08,912 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:08,912 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [159957710] [2022-07-14 16:02:08,913 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:08,913 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:08,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:08,922 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:02:08,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:08,959 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:02:08,960 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:08,960 INFO L85 PathProgramCache]: Analyzing trace with hash -338188238, now seen corresponding path program 1 times [2022-07-14 16:02:08,961 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:08,961 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1573779249] [2022-07-14 16:02:08,961 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:08,961 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:08,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:08,990 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:08,990 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:08,993 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1573779249] [2022-07-14 16:02:08,994 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1573779249] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:08,994 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:08,995 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:02:08,995 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1596345459] [2022-07-14 16:02:08,995 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:08,995 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:08,999 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:08,999 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-07-14 16:02:09,000 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-07-14 16:02:09,000 INFO L87 Difference]: Start difference. First operand 608 states and 825 transitions. cyclomatic complexity: 219 Second operand has 5 states, 5 states have (on average 7.2) internal successors, (36), 5 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:09,054 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:09,054 INFO L93 Difference]: Finished difference Result 919 states and 1233 transitions. [2022-07-14 16:02:09,055 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-07-14 16:02:09,056 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 919 states and 1233 transitions. [2022-07-14 16:02:09,063 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 890 [2022-07-14 16:02:09,067 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 919 states to 919 states and 1233 transitions. [2022-07-14 16:02:09,067 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 919 [2022-07-14 16:02:09,068 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 919 [2022-07-14 16:02:09,068 INFO L73 IsDeterministic]: Start isDeterministic. Operand 919 states and 1233 transitions. [2022-07-14 16:02:09,069 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:09,069 INFO L369 hiAutomatonCegarLoop]: Abstraction has 919 states and 1233 transitions. [2022-07-14 16:02:09,070 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 919 states and 1233 transitions. [2022-07-14 16:02:09,077 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 919 to 635. [2022-07-14 16:02:09,079 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 635 states, 635 states have (on average 1.3417322834645669) internal successors, (852), 634 states have internal predecessors, (852), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:09,080 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 635 states to 635 states and 852 transitions. [2022-07-14 16:02:09,081 INFO L392 hiAutomatonCegarLoop]: Abstraction has 635 states and 852 transitions. [2022-07-14 16:02:09,081 INFO L374 stractBuchiCegarLoop]: Abstraction has 635 states and 852 transitions. [2022-07-14 16:02:09,081 INFO L287 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-07-14 16:02:09,081 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 635 states and 852 transitions. [2022-07-14 16:02:09,086 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 607 [2022-07-14 16:02:09,086 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:09,086 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:09,087 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:09,087 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:09,087 INFO L752 eck$LassoCheckResult]: Stem: 6451#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 6426#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 6378#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6379#L222 assume !(1 == ~q_req_up~0); 6374#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6375#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 6411#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 6432#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6428#L275 assume !(0 == ~q_read_ev~0); 6429#L275-2 assume !(0 == ~q_write_ev~0); 6415#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 6416#L65 assume !(1 == ~p_dw_pc~0); 6413#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 6422#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 6372#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 6373#L315 assume !(0 != activate_threads_~tmp~1#1); 6380#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 6381#L84 assume !(1 == ~c_dr_pc~0); 6399#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 6390#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 6391#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6352#L323 assume !(0 != activate_threads_~tmp___0~1#1); 6353#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6449#L293 assume !(1 == ~q_read_ev~0); 6343#L293-2 assume !(1 == ~q_write_ev~0); 6344#L298-1 assume { :end_inline_reset_delta_events } true; 6441#L419-2 [2022-07-14 16:02:09,089 INFO L754 eck$LassoCheckResult]: Loop: 6441#L419-2 assume !false; 6963#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 6385#L364 assume !false; 6414#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6384#L255 assume !(0 == ~p_dw_st~0); 6345#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 6347#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 6881#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 6863#L344 assume !(0 != eval_~tmp___1~0#1); 6358#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6359#L222-3 assume !(1 == ~q_req_up~0); 6420#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6409#L275-3 assume !(0 == ~q_read_ev~0); 6410#L275-5 assume !(0 == ~q_write_ev~0); 6444#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 6360#L65-3 assume !(1 == ~p_dw_pc~0); 6361#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 6442#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 6443#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 6445#L315-3 assume !(0 != activate_threads_~tmp~1#1); 6446#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 6348#L84-3 assume !(1 == ~c_dr_pc~0); 6349#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 6407#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 6408#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6462#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 6463#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6439#L293-3 assume !(1 == ~q_read_ev~0); 6440#L293-5 assume !(1 == ~q_write_ev~0); 6460#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6461#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 6969#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 6968#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 6967#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 6966#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6965#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 6964#L436 assume !(0 != start_simulation_~tmp~4#1); 6441#L419-2 [2022-07-14 16:02:09,089 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:09,089 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 2 times [2022-07-14 16:02:09,090 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:09,090 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [307000194] [2022-07-14 16:02:09,090 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:09,090 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:09,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:09,108 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:02:09,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:09,118 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:02:09,119 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:09,119 INFO L85 PathProgramCache]: Analyzing trace with hash 22665520, now seen corresponding path program 1 times [2022-07-14 16:02:09,119 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:09,119 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [736077447] [2022-07-14 16:02:09,119 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:09,120 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:09,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:09,136 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:09,136 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:09,136 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [736077447] [2022-07-14 16:02:09,136 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [736077447] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:09,137 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:09,137 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:09,137 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1382187012] [2022-07-14 16:02:09,137 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:09,137 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:09,138 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:09,138 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:02:09,138 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:02:09,138 INFO L87 Difference]: Start difference. First operand 635 states and 852 transitions. cyclomatic complexity: 219 Second operand has 3 states, 3 states have (on average 12.333333333333334) internal successors, (37), 3 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:09,157 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:09,157 INFO L93 Difference]: Finished difference Result 930 states and 1190 transitions. [2022-07-14 16:02:09,158 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:02:09,158 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 930 states and 1190 transitions. [2022-07-14 16:02:09,164 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 881 [2022-07-14 16:02:09,168 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 930 states to 930 states and 1190 transitions. [2022-07-14 16:02:09,168 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 930 [2022-07-14 16:02:09,169 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 930 [2022-07-14 16:02:09,169 INFO L73 IsDeterministic]: Start isDeterministic. Operand 930 states and 1190 transitions. [2022-07-14 16:02:09,170 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:09,170 INFO L369 hiAutomatonCegarLoop]: Abstraction has 930 states and 1190 transitions. [2022-07-14 16:02:09,171 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 930 states and 1190 transitions. [2022-07-14 16:02:09,192 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 930 to 930. [2022-07-14 16:02:09,194 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 930 states, 930 states have (on average 1.2795698924731183) internal successors, (1190), 929 states have internal predecessors, (1190), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:09,197 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 930 states to 930 states and 1190 transitions. [2022-07-14 16:02:09,197 INFO L392 hiAutomatonCegarLoop]: Abstraction has 930 states and 1190 transitions. [2022-07-14 16:02:09,197 INFO L374 stractBuchiCegarLoop]: Abstraction has 930 states and 1190 transitions. [2022-07-14 16:02:09,197 INFO L287 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-07-14 16:02:09,197 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 930 states and 1190 transitions. [2022-07-14 16:02:09,202 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 881 [2022-07-14 16:02:09,202 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:09,203 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:09,203 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:09,204 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:09,204 INFO L752 eck$LassoCheckResult]: Stem: 8036#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 8002#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 7947#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7948#L222 assume !(1 == ~q_req_up~0); 7945#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7946#L237 assume !(1 == ~p_dw_i~0);~p_dw_st~0 := 2; 7983#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 8024#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8025#L275 assume !(0 == ~q_read_ev~0); 8026#L275-2 assume !(0 == ~q_write_ev~0); 8027#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 8049#L65 assume !(1 == ~p_dw_pc~0); 7986#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 8047#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 8048#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 8018#L315 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 7951#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 7952#L84 assume !(1 == ~c_dr_pc~0); 7971#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 7972#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 8012#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 8013#L323 assume !(0 != activate_threads_~tmp___0~1#1); 8042#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8043#L293 assume !(1 == ~q_read_ev~0); 7912#L293-2 assume !(1 == ~q_write_ev~0); 7913#L298-1 assume { :end_inline_reset_delta_events } true; 8102#L419-2 [2022-07-14 16:02:09,204 INFO L754 eck$LassoCheckResult]: Loop: 8102#L419-2 assume !false; 8101#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 8100#L364 assume !false; 8099#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 8097#L255 assume !(0 == ~p_dw_st~0); 8098#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 8137#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 8136#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 8135#L344 assume !(0 != eval_~tmp___1~0#1); 8134#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8133#L222-3 assume !(1 == ~q_req_up~0); 8132#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8131#L275-3 assume !(0 == ~q_read_ev~0); 8130#L275-5 assume !(0 == ~q_write_ev~0); 8129#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 8128#L65-3 assume !(1 == ~p_dw_pc~0); 8126#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 8125#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 8124#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 8122#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 8121#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 8120#L84-3 assume !(1 == ~c_dr_pc~0); 8119#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 8117#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 8116#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 8115#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 8114#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8113#L293-3 assume !(1 == ~q_read_ev~0); 8112#L293-5 assume !(1 == ~q_write_ev~0); 8111#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 8109#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 8108#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 8107#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 8106#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 8105#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8104#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 8103#L436 assume !(0 != start_simulation_~tmp~4#1); 8102#L419-2 [2022-07-14 16:02:09,204 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:09,205 INFO L85 PathProgramCache]: Analyzing trace with hash -1896010065, now seen corresponding path program 1 times [2022-07-14 16:02:09,205 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:09,205 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [383548330] [2022-07-14 16:02:09,205 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:09,205 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:09,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:09,230 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:09,231 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:09,231 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [383548330] [2022-07-14 16:02:09,232 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [383548330] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:09,232 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:09,232 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:09,232 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [755819684] [2022-07-14 16:02:09,232 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:09,233 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:09,233 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:09,233 INFO L85 PathProgramCache]: Analyzing trace with hash 2016810226, now seen corresponding path program 1 times [2022-07-14 16:02:09,234 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:09,234 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [832101965] [2022-07-14 16:02:09,234 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:09,234 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:09,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:09,311 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:09,311 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:09,312 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [832101965] [2022-07-14 16:02:09,313 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [832101965] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:09,313 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:09,313 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:02:09,318 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2024470361] [2022-07-14 16:02:09,318 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:09,319 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:09,321 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:09,324 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:02:09,325 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:02:09,325 INFO L87 Difference]: Start difference. First operand 930 states and 1190 transitions. cyclomatic complexity: 262 Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:09,333 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:09,333 INFO L93 Difference]: Finished difference Result 909 states and 1165 transitions. [2022-07-14 16:02:09,333 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:02:09,335 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 909 states and 1165 transitions. [2022-07-14 16:02:09,340 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 881 [2022-07-14 16:02:09,344 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 909 states to 909 states and 1165 transitions. [2022-07-14 16:02:09,346 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 909 [2022-07-14 16:02:09,347 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 909 [2022-07-14 16:02:09,347 INFO L73 IsDeterministic]: Start isDeterministic. Operand 909 states and 1165 transitions. [2022-07-14 16:02:09,348 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:09,348 INFO L369 hiAutomatonCegarLoop]: Abstraction has 909 states and 1165 transitions. [2022-07-14 16:02:09,348 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 909 states and 1165 transitions. [2022-07-14 16:02:09,358 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 909 to 909. [2022-07-14 16:02:09,360 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 909 states, 909 states have (on average 1.2816281628162816) internal successors, (1165), 908 states have internal predecessors, (1165), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:09,362 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 909 states to 909 states and 1165 transitions. [2022-07-14 16:02:09,362 INFO L392 hiAutomatonCegarLoop]: Abstraction has 909 states and 1165 transitions. [2022-07-14 16:02:09,362 INFO L374 stractBuchiCegarLoop]: Abstraction has 909 states and 1165 transitions. [2022-07-14 16:02:09,362 INFO L287 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-07-14 16:02:09,362 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 909 states and 1165 transitions. [2022-07-14 16:02:09,366 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 881 [2022-07-14 16:02:09,366 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:09,366 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:09,368 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:09,368 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:09,369 INFO L752 eck$LassoCheckResult]: Stem: 9865#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 9846#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 9795#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9796#L222 assume !(1 == ~q_req_up~0); 9793#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9794#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 9830#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 9852#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9849#L275 assume !(0 == ~q_read_ev~0); 9850#L275-2 assume !(0 == ~q_write_ev~0); 9833#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 9834#L65 assume !(1 == ~p_dw_pc~0); 9832#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 9843#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 9788#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 9789#L315 assume !(0 != activate_threads_~tmp~1#1); 9799#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 9800#L84 assume !(1 == ~c_dr_pc~0); 9818#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 9808#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 9809#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 9771#L323 assume !(0 != activate_threads_~tmp___0~1#1); 9772#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9864#L293 assume !(1 == ~q_read_ev~0); 9760#L293-2 assume !(1 == ~q_write_ev~0); 9761#L298-1 assume { :end_inline_reset_delta_events } true; 9859#L419-2 [2022-07-14 16:02:09,370 INFO L754 eck$LassoCheckResult]: Loop: 9859#L419-2 assume !false; 9923#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 9922#L364 assume !false; 9921#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 9919#L255 assume !(0 == ~p_dw_st~0); 9920#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 9957#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 9956#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 9955#L344 assume !(0 != eval_~tmp___1~0#1); 9954#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9953#L222-3 assume !(1 == ~q_req_up~0); 9952#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9951#L275-3 assume !(0 == ~q_read_ev~0); 9950#L275-5 assume !(0 == ~q_write_ev~0); 9949#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 9948#L65-3 assume !(1 == ~p_dw_pc~0); 9946#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 9945#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 9944#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 9942#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 9941#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 9940#L84-3 assume !(1 == ~c_dr_pc~0); 9939#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 9938#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 9937#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 9936#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 9935#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9934#L293-3 assume !(1 == ~q_read_ev~0); 9933#L293-5 assume !(1 == ~q_write_ev~0); 9932#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 9930#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 9929#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 9928#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 9927#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 9926#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9925#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 9924#L436 assume !(0 != start_simulation_~tmp~4#1); 9859#L419-2 [2022-07-14 16:02:09,373 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:09,373 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 3 times [2022-07-14 16:02:09,374 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:09,374 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1489915654] [2022-07-14 16:02:09,374 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:09,375 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:09,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:09,388 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:02:09,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:09,403 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:02:09,404 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:09,404 INFO L85 PathProgramCache]: Analyzing trace with hash 2016810226, now seen corresponding path program 2 times [2022-07-14 16:02:09,404 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:09,404 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1680186360] [2022-07-14 16:02:09,404 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:09,404 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:09,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:09,439 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:09,440 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:09,440 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1680186360] [2022-07-14 16:02:09,440 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1680186360] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:09,440 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:09,440 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:02:09,441 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [322741786] [2022-07-14 16:02:09,441 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:09,441 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:09,441 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:09,442 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-07-14 16:02:09,442 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-07-14 16:02:09,442 INFO L87 Difference]: Start difference. First operand 909 states and 1165 transitions. cyclomatic complexity: 258 Second operand has 5 states, 5 states have (on average 7.4) internal successors, (37), 5 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:09,495 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:09,495 INFO L93 Difference]: Finished difference Result 1550 states and 1986 transitions. [2022-07-14 16:02:09,496 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-07-14 16:02:09,496 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1550 states and 1986 transitions. [2022-07-14 16:02:09,505 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1506 [2022-07-14 16:02:09,512 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1550 states to 1550 states and 1986 transitions. [2022-07-14 16:02:09,512 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1550 [2022-07-14 16:02:09,513 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1550 [2022-07-14 16:02:09,513 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1550 states and 1986 transitions. [2022-07-14 16:02:09,515 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:09,515 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1550 states and 1986 transitions. [2022-07-14 16:02:09,516 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1550 states and 1986 transitions. [2022-07-14 16:02:09,527 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1550 to 860. [2022-07-14 16:02:09,528 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 860 states, 860 states have (on average 1.2732558139534884) internal successors, (1095), 859 states have internal predecessors, (1095), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:09,530 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 860 states to 860 states and 1095 transitions. [2022-07-14 16:02:09,531 INFO L392 hiAutomatonCegarLoop]: Abstraction has 860 states and 1095 transitions. [2022-07-14 16:02:09,531 INFO L374 stractBuchiCegarLoop]: Abstraction has 860 states and 1095 transitions. [2022-07-14 16:02:09,531 INFO L287 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-07-14 16:02:09,531 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 860 states and 1095 transitions. [2022-07-14 16:02:09,534 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 817 [2022-07-14 16:02:09,535 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:09,535 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:09,535 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:09,535 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:09,536 INFO L752 eck$LassoCheckResult]: Stem: 12335#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 12315#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 12267#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12268#L222 assume !(1 == ~q_req_up~0); 12265#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12266#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 12301#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 12321#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12318#L275 assume !(0 == ~q_read_ev~0); 12319#L275-2 assume !(0 == ~q_write_ev~0); 12304#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 12305#L65 assume !(1 == ~p_dw_pc~0); 12303#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 12312#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 12260#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 12261#L315 assume !(0 != activate_threads_~tmp~1#1); 12271#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 12272#L84 assume !(1 == ~c_dr_pc~0); 12290#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 12281#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 12282#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 12243#L323 assume !(0 != activate_threads_~tmp___0~1#1); 12244#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12334#L293 assume !(1 == ~q_read_ev~0); 12232#L293-2 assume !(1 == ~q_write_ev~0); 12233#L298-1 assume { :end_inline_reset_delta_events } true; 12328#L419-2 assume !false; 13001#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 13000#L364 assume !false; 12999#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 12997#L255 assume !(0 == ~p_dw_st~0); 12998#L259 [2022-07-14 16:02:09,536 INFO L754 eck$LassoCheckResult]: Loop: 12998#L259 assume 0 == ~c_dr_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 13005#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 13006#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 13002#L344 assume 0 != eval_~tmp___1~0#1; 12320#L344-1 assume !(0 == ~p_dw_st~0); 12275#L349 assume !(0 == ~c_dr_st~0); 12277#L364 assume !false; 13009#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 13008#L255 assume !(0 == ~p_dw_st~0); 12998#L259 [2022-07-14 16:02:09,536 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:09,536 INFO L85 PathProgramCache]: Analyzing trace with hash -1220673252, now seen corresponding path program 1 times [2022-07-14 16:02:09,537 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:09,537 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [689822613] [2022-07-14 16:02:09,537 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:09,537 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:09,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:09,553 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:09,553 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:09,553 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [689822613] [2022-07-14 16:02:09,553 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [689822613] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:09,554 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:09,554 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-14 16:02:09,554 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1213706956] [2022-07-14 16:02:09,554 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:09,572 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:09,573 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:09,573 INFO L85 PathProgramCache]: Analyzing trace with hash -565706813, now seen corresponding path program 1 times [2022-07-14 16:02:09,573 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:09,573 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [14820384] [2022-07-14 16:02:09,574 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:09,574 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:09,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:09,583 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:09,583 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:09,583 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [14820384] [2022-07-14 16:02:09,583 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [14820384] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:09,583 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:09,583 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-14 16:02:09,584 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1954045810] [2022-07-14 16:02:09,584 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:09,584 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:09,584 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:09,585 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:02:09,585 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:02:09,585 INFO L87 Difference]: Start difference. First operand 860 states and 1095 transitions. cyclomatic complexity: 237 Second operand has 3 states, 3 states have (on average 3.0) internal successors, (9), 2 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:09,605 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:09,606 INFO L93 Difference]: Finished difference Result 1209 states and 1521 transitions. [2022-07-14 16:02:09,606 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:02:09,607 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1209 states and 1521 transitions. [2022-07-14 16:02:09,613 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1166 [2022-07-14 16:02:09,619 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1209 states to 1209 states and 1521 transitions. [2022-07-14 16:02:09,620 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1209 [2022-07-14 16:02:09,620 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1209 [2022-07-14 16:02:09,621 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1209 states and 1521 transitions. [2022-07-14 16:02:09,622 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:09,622 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1209 states and 1521 transitions. [2022-07-14 16:02:09,623 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1209 states and 1521 transitions. [2022-07-14 16:02:09,636 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1209 to 1209. [2022-07-14 16:02:09,638 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1209 states, 1209 states have (on average 1.2580645161290323) internal successors, (1521), 1208 states have internal predecessors, (1521), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:09,640 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1209 states to 1209 states and 1521 transitions. [2022-07-14 16:02:09,641 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1209 states and 1521 transitions. [2022-07-14 16:02:09,641 INFO L374 stractBuchiCegarLoop]: Abstraction has 1209 states and 1521 transitions. [2022-07-14 16:02:09,641 INFO L287 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-07-14 16:02:09,641 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1209 states and 1521 transitions. [2022-07-14 16:02:09,646 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1166 [2022-07-14 16:02:09,646 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:09,646 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:09,647 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:09,647 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:09,647 INFO L752 eck$LassoCheckResult]: Stem: 14412#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 14391#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 14342#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14343#L222 assume !(1 == ~q_req_up~0); 14340#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14341#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 14376#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 14398#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14395#L275 assume !(0 == ~q_read_ev~0); 14396#L275-2 assume !(0 == ~q_write_ev~0); 14379#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 14380#L65 assume !(1 == ~p_dw_pc~0); 14378#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 14389#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 14335#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 14336#L315 assume !(0 != activate_threads_~tmp~1#1); 14346#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 14347#L84 assume !(1 == ~c_dr_pc~0); 14364#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 14355#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 14356#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 14318#L323 assume !(0 != activate_threads_~tmp___0~1#1); 14319#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14411#L293 assume !(1 == ~q_read_ev~0); 14308#L293-2 assume !(1 == ~q_write_ev~0); 14309#L298-1 assume { :end_inline_reset_delta_events } true; 14405#L419-2 assume !false; 14492#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 14491#L364 assume !false; 14489#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 14487#L255 assume !(0 == ~p_dw_st~0); 14486#L259 [2022-07-14 16:02:09,647 INFO L754 eck$LassoCheckResult]: Loop: 14486#L259 assume 0 == ~c_dr_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 14484#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 14482#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 14480#L344 assume 0 != eval_~tmp___1~0#1; 14470#L344-1 assume !(0 == ~p_dw_st~0); 14352#L349 assume 0 == ~c_dr_st~0;eval_~tmp___0~2#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 14353#L368 assume !(0 != eval_~tmp___0~2#1); 14393#L364 assume !false; 14490#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 14488#L255 assume !(0 == ~p_dw_st~0); 14486#L259 [2022-07-14 16:02:09,647 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:09,648 INFO L85 PathProgramCache]: Analyzing trace with hash -1220673252, now seen corresponding path program 2 times [2022-07-14 16:02:09,648 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:09,648 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1588624120] [2022-07-14 16:02:09,648 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:09,648 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:09,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:09,664 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:09,664 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:09,664 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1588624120] [2022-07-14 16:02:09,664 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1588624120] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:09,664 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:09,664 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-14 16:02:09,665 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1259813760] [2022-07-14 16:02:09,665 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:09,665 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:09,665 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:09,666 INFO L85 PathProgramCache]: Analyzing trace with hash -410340052, now seen corresponding path program 1 times [2022-07-14 16:02:09,666 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:09,666 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [824881146] [2022-07-14 16:02:09,666 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:09,666 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:09,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:09,669 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:02:09,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:09,672 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:02:09,739 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:09,740 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:02:09,741 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:02:09,741 INFO L87 Difference]: Start difference. First operand 1209 states and 1521 transitions. cyclomatic complexity: 314 Second operand has 3 states, 2 states have (on average 15.5) internal successors, (31), 3 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:09,774 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:09,774 INFO L93 Difference]: Finished difference Result 1209 states and 1471 transitions. [2022-07-14 16:02:09,774 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:02:09,775 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1209 states and 1471 transitions. [2022-07-14 16:02:09,781 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1166 [2022-07-14 16:02:09,786 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1209 states to 1209 states and 1471 transitions. [2022-07-14 16:02:09,799 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1209 [2022-07-14 16:02:09,800 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1209 [2022-07-14 16:02:09,800 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1209 states and 1471 transitions. [2022-07-14 16:02:09,801 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:09,801 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1209 states and 1471 transitions. [2022-07-14 16:02:09,802 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1209 states and 1471 transitions. [2022-07-14 16:02:09,811 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1209 to 1209. [2022-07-14 16:02:09,828 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1209 states, 1209 states have (on average 1.216708023159636) internal successors, (1471), 1208 states have internal predecessors, (1471), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:09,831 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1209 states to 1209 states and 1471 transitions. [2022-07-14 16:02:09,831 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1209 states and 1471 transitions. [2022-07-14 16:02:09,831 INFO L374 stractBuchiCegarLoop]: Abstraction has 1209 states and 1471 transitions. [2022-07-14 16:02:09,831 INFO L287 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-07-14 16:02:09,832 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1209 states and 1471 transitions. [2022-07-14 16:02:09,836 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1166 [2022-07-14 16:02:09,836 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:09,836 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:09,837 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:09,837 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-07-14 16:02:09,837 INFO L752 eck$LassoCheckResult]: Stem: 16834#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 16812#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 16768#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16769#L222 assume !(1 == ~q_req_up~0); 16764#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16765#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 16799#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 16819#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16817#L275 assume !(0 == ~q_read_ev~0); 16818#L275-2 assume !(0 == ~q_write_ev~0); 16803#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 16804#L65 assume !(1 == ~p_dw_pc~0); 16801#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 16810#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 16762#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 16763#L315 assume !(0 != activate_threads_~tmp~1#1); 16770#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 16771#L84 assume !(1 == ~c_dr_pc~0); 16788#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 16781#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 16782#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 16742#L323 assume !(0 != activate_threads_~tmp___0~1#1); 16743#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16832#L293 assume !(1 == ~q_read_ev~0); 16734#L293-2 assume !(1 == ~q_write_ev~0); 16735#L298-1 assume { :end_inline_reset_delta_events } true; 16826#L419-2 assume !false; 16880#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 16879#L364 assume !false; 16878#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 16877#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 16876#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 16875#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 16873#L344 assume 0 != eval_~tmp___1~0#1; 16871#L344-1 assume 0 == ~p_dw_st~0;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 16869#L353 assume 0 != eval_~tmp~2#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1; 16866#L128 assume !(0 == ~p_dw_pc~0); 16867#L131 assume 1 == ~p_dw_pc~0; 16824#L141 [2022-07-14 16:02:09,837 INFO L754 eck$LassoCheckResult]: Loop: 16824#L141 ~q_buf_0~0 := do_write_p_#t~nondet6#1;havoc do_write_p_#t~nondet6#1;~p_last_write~0 := ~q_buf_0~0;~p_num_write~0 := 1 + ~p_num_write~0;~q_free~0 := 0;~q_req_up~0 := 1; 16827#L139-1 assume !false; 16837#L140 assume !(0 == ~q_free~0); 16824#L141 [2022-07-14 16:02:09,838 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:09,838 INFO L85 PathProgramCache]: Analyzing trace with hash -1071076411, now seen corresponding path program 1 times [2022-07-14 16:02:09,838 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:09,838 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2095954487] [2022-07-14 16:02:09,838 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:09,839 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:09,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:09,870 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:09,870 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:09,871 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2095954487] [2022-07-14 16:02:09,871 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2095954487] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:09,871 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:09,871 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:09,871 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1663148298] [2022-07-14 16:02:09,871 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:09,871 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:09,872 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:09,872 INFO L85 PathProgramCache]: Analyzing trace with hash 220166, now seen corresponding path program 1 times [2022-07-14 16:02:09,872 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:09,872 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [899074250] [2022-07-14 16:02:09,872 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:09,872 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:09,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:09,880 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:09,880 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:09,880 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [899074250] [2022-07-14 16:02:09,880 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [899074250] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:09,880 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:09,880 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2022-07-14 16:02:09,881 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [253519713] [2022-07-14 16:02:09,881 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:09,881 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:09,881 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:09,881 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:02:09,881 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:02:09,882 INFO L87 Difference]: Start difference. First operand 1209 states and 1471 transitions. cyclomatic complexity: 264 Second operand has 3 states, 2 states have (on average 1.5) internal successors, (3), 2 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:09,908 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:09,908 INFO L93 Difference]: Finished difference Result 2195 states and 2627 transitions. [2022-07-14 16:02:09,908 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:02:09,909 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2195 states and 2627 transitions. [2022-07-14 16:02:09,921 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2152 [2022-07-14 16:02:09,929 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2195 states to 2195 states and 2627 transitions. [2022-07-14 16:02:09,930 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2195 [2022-07-14 16:02:09,931 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2195 [2022-07-14 16:02:09,931 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2195 states and 2627 transitions. [2022-07-14 16:02:09,933 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:09,933 INFO L369 hiAutomatonCegarLoop]: Abstraction has 2195 states and 2627 transitions. [2022-07-14 16:02:09,934 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2195 states and 2627 transitions. [2022-07-14 16:02:09,954 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2195 to 1879. [2022-07-14 16:02:09,956 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1879 states, 1879 states have (on average 1.204364023416711) internal successors, (2263), 1878 states have internal predecessors, (2263), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:09,985 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1879 states to 1879 states and 2263 transitions. [2022-07-14 16:02:09,985 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1879 states and 2263 transitions. [2022-07-14 16:02:09,985 INFO L374 stractBuchiCegarLoop]: Abstraction has 1879 states and 2263 transitions. [2022-07-14 16:02:09,985 INFO L287 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-07-14 16:02:09,985 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1879 states and 2263 transitions. [2022-07-14 16:02:09,991 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1836 [2022-07-14 16:02:09,991 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:09,991 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:09,992 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:09,992 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:09,993 INFO L752 eck$LassoCheckResult]: Stem: 20250#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 20224#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 20176#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20177#L222 assume !(1 == ~q_req_up~0); 20174#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20175#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 20210#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 20231#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20229#L275 assume !(0 == ~q_read_ev~0); 20230#L275-2 assume !(0 == ~q_write_ev~0); 20213#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 20214#L65 assume !(1 == ~p_dw_pc~0); 20212#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 20222#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 20170#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 20171#L315 assume !(0 != activate_threads_~tmp~1#1); 20180#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 20181#L84 assume !(1 == ~c_dr_pc~0); 20198#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 20189#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 20190#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 20153#L323 assume !(0 != activate_threads_~tmp___0~1#1); 20154#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20249#L293 assume !(1 == ~q_read_ev~0); 20143#L293-2 assume !(1 == ~q_write_ev~0); 20144#L298-1 assume { :end_inline_reset_delta_events } true; 20239#L419-2 assume !false; 20328#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 20327#L364 assume !false; 20326#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 20325#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 20324#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 20323#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 20321#L344 assume 0 != eval_~tmp___1~0#1; 20319#L344-1 assume 0 == ~p_dw_st~0;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 20317#L353 assume 0 != eval_~tmp~2#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1; 20314#L128 assume !(0 == ~p_dw_pc~0); 20315#L131 assume 1 == ~p_dw_pc~0; 20240#L141 [2022-07-14 16:02:09,993 INFO L754 eck$LassoCheckResult]: Loop: 20240#L141 ~q_buf_0~0 := do_write_p_#t~nondet6#1;havoc do_write_p_#t~nondet6#1;~p_last_write~0 := ~q_buf_0~0;~p_num_write~0 := 1 + ~p_num_write~0;~q_free~0 := 0;~q_req_up~0 := 1; 20166#L139-1 assume !false; 20167#L140 assume 0 == ~q_free~0;~p_dw_st~0 := 2;~p_dw_pc~0 := 1; 20182#L158 assume { :end_inline_do_write_p } true; 20183#L349 assume 0 == ~c_dr_st~0;eval_~tmp___0~2#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 20329#L368 assume 0 != eval_~tmp___0~2#1;~c_dr_st~0 := 1;assume { :begin_inline_do_read_c } true;havoc do_read_c_~a~0#1;havoc do_read_c_~a~0#1; 20330#L169 assume 0 == ~c_dr_pc~0; 20261#L198-1 assume !false; 20199#L181 assume !(1 == ~q_free~0); 20200#L182-1 do_read_c_~a~0#1 := ~q_buf_0~0;~c_last_read~0 := do_read_c_~a~0#1;~c_num_read~0 := 1 + ~c_num_read~0;~q_free~0 := 1;~q_req_up~0 := 1; 20155#L198 assume ~p_last_write~0 == ~c_last_read~0; 20156#L199 assume ~p_num_write~0 == ~c_num_read~0; 20248#L198-1 assume !false; 20269#L181 assume 1 == ~q_free~0;~c_dr_st~0 := 2;~c_dr_pc~0 := 1;~a_t~0 := do_read_c_~a~0#1; 20270#L212 assume { :end_inline_do_read_c } true; 21256#L364 assume !false; 21255#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 21254#L255 assume !(0 == ~p_dw_st~0); 21252#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 21251#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 20368#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 20341#L344 assume !(0 != eval_~tmp___1~0#1); 20159#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20160#L222-3 assume 1 == ~q_req_up~0;assume { :begin_inline_update_fifo_q } true; 20274#L35-3 assume !(0 == ~q_free~0); 20277#L35-5 assume 1 == ~q_free~0;~q_read_ev~0 := 0; 20343#L40-3 ~q_ev~0 := 0;~q_req_up~0 := 0; 20814#L48-1 assume { :end_inline_update_fifo_q } true; 20813#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20660#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 20661#L275-5 assume !(0 == ~q_write_ev~0); 20652#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 20653#L65-3 assume 1 == ~p_dw_pc~0; 20641#L66-1 assume 1 == ~q_read_ev~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 20642#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 20633#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 20634#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 20625#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 20626#L84-3 assume !(1 == ~c_dr_pc~0); 20609#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 20606#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 20603#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 20600#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 20599#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21936#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 21933#L293-5 assume !(1 == ~q_write_ev~0); 21930#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 21927#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 21924#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 21921#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 21918#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 21915#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21912#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 21909#L436 assume !(0 != start_simulation_~tmp~4#1); 21906#L419-2 assume !false; 21903#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 21900#L364 assume !false; 21897#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 21894#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 21891#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 21888#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 21885#L344 assume 0 != eval_~tmp___1~0#1; 21882#L344-1 assume 0 == ~p_dw_st~0;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 21881#L353 assume 0 != eval_~tmp~2#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1; 21877#L128 assume !(0 == ~p_dw_pc~0); 21878#L131 assume 1 == ~p_dw_pc~0; 20240#L141 [2022-07-14 16:02:09,994 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:09,994 INFO L85 PathProgramCache]: Analyzing trace with hash -1071076411, now seen corresponding path program 2 times [2022-07-14 16:02:09,994 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:09,994 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1184040981] [2022-07-14 16:02:09,994 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:09,994 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:09,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:10,010 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:10,011 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:10,011 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1184040981] [2022-07-14 16:02:10,011 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1184040981] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:10,011 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:10,012 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:10,012 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1142310294] [2022-07-14 16:02:10,012 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:10,012 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:10,012 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:10,013 INFO L85 PathProgramCache]: Analyzing trace with hash -1533797676, now seen corresponding path program 1 times [2022-07-14 16:02:10,013 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:10,013 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [588820220] [2022-07-14 16:02:10,013 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:10,013 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:10,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:10,031 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-07-14 16:02:10,031 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:10,032 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [588820220] [2022-07-14 16:02:10,032 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [588820220] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:10,032 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:10,032 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:10,032 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [601093089] [2022-07-14 16:02:10,032 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:10,033 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:10,033 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:10,033 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:02:10,033 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:02:10,034 INFO L87 Difference]: Start difference. First operand 1879 states and 2263 transitions. cyclomatic complexity: 386 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:10,051 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:10,051 INFO L93 Difference]: Finished difference Result 1933 states and 2326 transitions. [2022-07-14 16:02:10,051 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:02:10,052 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1933 states and 2326 transitions. [2022-07-14 16:02:10,059 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1892 [2022-07-14 16:02:10,067 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1933 states to 1933 states and 2326 transitions. [2022-07-14 16:02:10,067 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1933 [2022-07-14 16:02:10,068 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1933 [2022-07-14 16:02:10,068 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1933 states and 2326 transitions. [2022-07-14 16:02:10,070 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:10,070 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1933 states and 2326 transitions. [2022-07-14 16:02:10,071 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1933 states and 2326 transitions. [2022-07-14 16:02:10,091 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1933 to 1877. [2022-07-14 16:02:10,094 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1877 states, 1877 states have (on average 1.202983484283431) internal successors, (2258), 1876 states have internal predecessors, (2258), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:10,098 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1877 states to 1877 states and 2258 transitions. [2022-07-14 16:02:10,098 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1877 states and 2258 transitions. [2022-07-14 16:02:10,098 INFO L374 stractBuchiCegarLoop]: Abstraction has 1877 states and 2258 transitions. [2022-07-14 16:02:10,099 INFO L287 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-07-14 16:02:10,099 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1877 states and 2258 transitions. [2022-07-14 16:02:10,103 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1836 [2022-07-14 16:02:10,104 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:10,104 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:10,105 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:10,105 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:10,105 INFO L752 eck$LassoCheckResult]: Stem: 24073#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 24047#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 23995#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23996#L222 assume !(1 == ~q_req_up~0); 23993#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23994#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 24033#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 24056#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24053#L275 assume !(0 == ~q_read_ev~0); 24054#L275-2 assume !(0 == ~q_write_ev~0); 24034#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 24035#L65 assume !(1 == ~p_dw_pc~0); 24043#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 24044#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 23989#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 23990#L315 assume !(0 != activate_threads_~tmp~1#1); 23999#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 24000#L84 assume !(1 == ~c_dr_pc~0); 24022#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 24010#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 24011#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 23972#L323 assume !(0 != activate_threads_~tmp___0~1#1); 23973#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24072#L293 assume !(1 == ~q_read_ev~0); 23962#L293-2 assume !(1 == ~q_write_ev~0); 23963#L298-1 assume { :end_inline_reset_delta_events } true; 24065#L419-2 assume !false; 24132#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 24131#L364 assume !false; 24130#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 24129#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 24128#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 24127#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 24125#L344 assume 0 != eval_~tmp___1~0#1; 24123#L344-1 assume 0 == ~p_dw_st~0;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 24121#L353 assume 0 != eval_~tmp~2#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1; 24119#L128 assume 0 == ~p_dw_pc~0; 24117#L139-1 assume !false; 24115#L140 assume !(0 == ~q_free~0); 24063#L141 [2022-07-14 16:02:10,106 INFO L754 eck$LassoCheckResult]: Loop: 24063#L141 ~q_buf_0~0 := do_write_p_#t~nondet6#1;havoc do_write_p_#t~nondet6#1;~p_last_write~0 := ~q_buf_0~0;~p_num_write~0 := 1 + ~p_num_write~0;~q_free~0 := 0;~q_req_up~0 := 1; 24064#L139-1 assume !false; 24209#L140 assume 0 == ~q_free~0;~p_dw_st~0 := 2;~p_dw_pc~0 := 1; 24210#L158 assume { :end_inline_do_write_p } true; 24108#L349 assume 0 == ~c_dr_st~0;eval_~tmp___0~2#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 24106#L368 assume 0 != eval_~tmp___0~2#1;~c_dr_st~0 := 1;assume { :begin_inline_do_read_c } true;havoc do_read_c_~a~0#1;havoc do_read_c_~a~0#1; 24104#L169 assume 0 == ~c_dr_pc~0; 24101#L198-1 assume !false; 24023#L181 assume !(1 == ~q_free~0); 24024#L182-1 do_read_c_~a~0#1 := ~q_buf_0~0;~c_last_read~0 := do_read_c_~a~0#1;~c_num_read~0 := 1 + ~c_num_read~0;~q_free~0 := 1;~q_req_up~0 := 1; 23974#L198 assume ~p_last_write~0 == ~c_last_read~0; 23975#L199 assume ~p_num_write~0 == ~c_num_read~0; 24344#L198-1 assume !false; 24340#L181 assume 1 == ~q_free~0;~c_dr_st~0 := 2;~c_dr_pc~0 := 1;~a_t~0 := do_read_c_~a~0#1; 24335#L212 assume { :end_inline_do_read_c } true; 24331#L364 assume !false; 24329#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 24327#L255 assume !(0 == ~p_dw_st~0); 24323#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 24321#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 24319#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 24314#L344 assume !(0 != eval_~tmp___1~0#1); 24299#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 24300#L222-3 assume 1 == ~q_req_up~0;assume { :begin_inline_update_fifo_q } true; 24518#L35-3 assume !(0 == ~q_free~0); 24998#L35-5 assume 1 == ~q_free~0;~q_read_ev~0 := 0; 24999#L40-3 ~q_ev~0 := 0;~q_req_up~0 := 0; 25032#L48-1 assume { :end_inline_update_fifo_q } true; 25031#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25030#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 25029#L275-5 assume !(0 == ~q_write_ev~0); 25028#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 25027#L65-3 assume 1 == ~p_dw_pc~0; 25024#L66-1 assume 1 == ~q_read_ev~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 25025#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 24994#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 24995#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 25370#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 25371#L84-3 assume !(1 == ~c_dr_pc~0); 23969#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 25368#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 25366#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 25364#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 25308#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25803#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 25804#L293-5 assume !(1 == ~q_write_ev~0); 25824#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 25823#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 25822#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 25821#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 25820#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 25819#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25818#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 25817#L436 assume !(0 != start_simulation_~tmp~4#1); 25816#L419-2 assume !false; 25815#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 25814#L364 assume !false; 25813#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 25812#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 25811#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 25810#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 25809#L344 assume 0 != eval_~tmp___1~0#1; 25808#L344-1 assume 0 == ~p_dw_st~0;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 25807#L353 assume 0 != eval_~tmp~2#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1; 25805#L128 assume !(0 == ~p_dw_pc~0); 25806#L131 assume 1 == ~p_dw_pc~0; 24063#L141 [2022-07-14 16:02:10,106 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:10,106 INFO L85 PathProgramCache]: Analyzing trace with hash 1156368236, now seen corresponding path program 1 times [2022-07-14 16:02:10,106 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:10,106 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1181286332] [2022-07-14 16:02:10,107 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:10,107 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:10,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:10,112 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:02:10,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:10,121 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:02:10,122 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:10,122 INFO L85 PathProgramCache]: Analyzing trace with hash -1533797676, now seen corresponding path program 2 times [2022-07-14 16:02:10,122 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:10,122 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [654971891] [2022-07-14 16:02:10,122 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:10,122 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:10,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:10,139 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-07-14 16:02:10,139 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:10,139 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [654971891] [2022-07-14 16:02:10,139 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [654971891] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:10,140 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:10,140 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:10,140 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [61932745] [2022-07-14 16:02:10,140 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:10,140 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:10,141 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:10,141 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:02:10,141 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:02:10,141 INFO L87 Difference]: Start difference. First operand 1877 states and 2258 transitions. cyclomatic complexity: 383 Second operand has 3 states, 3 states have (on average 21.666666666666668) internal successors, (65), 3 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:10,155 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:10,155 INFO L93 Difference]: Finished difference Result 995 states and 1175 transitions. [2022-07-14 16:02:10,155 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:02:10,156 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 995 states and 1175 transitions. [2022-07-14 16:02:10,160 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 946 [2022-07-14 16:02:10,163 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 995 states to 995 states and 1175 transitions. [2022-07-14 16:02:10,163 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 995 [2022-07-14 16:02:10,164 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 995 [2022-07-14 16:02:10,164 INFO L73 IsDeterministic]: Start isDeterministic. Operand 995 states and 1175 transitions. [2022-07-14 16:02:10,165 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:10,165 INFO L369 hiAutomatonCegarLoop]: Abstraction has 995 states and 1175 transitions. [2022-07-14 16:02:10,166 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 995 states and 1175 transitions. [2022-07-14 16:02:10,173 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 995 to 844. [2022-07-14 16:02:10,174 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 844 states, 844 states have (on average 1.1919431279620853) internal successors, (1006), 843 states have internal predecessors, (1006), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:10,176 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 844 states to 844 states and 1006 transitions. [2022-07-14 16:02:10,176 INFO L392 hiAutomatonCegarLoop]: Abstraction has 844 states and 1006 transitions. [2022-07-14 16:02:10,176 INFO L374 stractBuchiCegarLoop]: Abstraction has 844 states and 1006 transitions. [2022-07-14 16:02:10,176 INFO L287 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-07-14 16:02:10,176 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 844 states and 1006 transitions. [2022-07-14 16:02:10,178 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 795 [2022-07-14 16:02:10,179 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:10,179 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:10,179 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:10,179 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:10,179 INFO L752 eck$LassoCheckResult]: Stem: 26943#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 26923#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 26875#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26876#L222 assume !(1 == ~q_req_up~0); 26871#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26872#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 26907#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 26931#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26928#L275 assume !(0 == ~q_read_ev~0); 26929#L275-2 assume !(0 == ~q_write_ev~0); 26910#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 26911#L65 assume !(1 == ~p_dw_pc~0); 26920#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 26921#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 26867#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 26868#L315 assume !(0 != activate_threads_~tmp~1#1); 26877#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 26878#L84 assume !(1 == ~c_dr_pc~0); 26896#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 26887#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 26888#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 26850#L323 assume !(0 != activate_threads_~tmp___0~1#1); 26851#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26942#L293 assume !(1 == ~q_read_ev~0); 26842#L293-2 assume !(1 == ~q_write_ev~0); 26843#L298-1 assume { :end_inline_reset_delta_events } true; 26939#L419-2 assume !false; 26992#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 26991#L364 assume !false; 26990#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 26989#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 26988#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 26987#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 26984#L344 assume 0 != eval_~tmp___1~0#1; 26981#L344-1 assume 0 == ~p_dw_st~0;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 26978#L353 assume 0 != eval_~tmp~2#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1; 26975#L128 assume 0 == ~p_dw_pc~0; 26971#L139-1 assume !false; 26966#L140 assume 0 == ~q_free~0;~p_dw_st~0 := 2;~p_dw_pc~0 := 1; 26962#L158 assume { :end_inline_do_write_p } true; 26960#L349 [2022-07-14 16:02:10,180 INFO L754 eck$LassoCheckResult]: Loop: 26960#L349 assume 0 == ~c_dr_st~0;eval_~tmp___0~2#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 26956#L368 assume !(0 != eval_~tmp___0~2#1); 26957#L364 assume !false; 26985#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 26982#L255 assume !(0 == ~p_dw_st~0); 26979#L259 assume 0 == ~c_dr_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 26976#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 26972#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 26968#L344 assume 0 != eval_~tmp___1~0#1; 26963#L344-1 assume !(0 == ~p_dw_st~0); 26960#L349 [2022-07-14 16:02:10,180 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:10,180 INFO L85 PathProgramCache]: Analyzing trace with hash 1487677052, now seen corresponding path program 1 times [2022-07-14 16:02:10,180 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:10,180 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2126251155] [2022-07-14 16:02:10,181 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:10,181 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:10,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:10,207 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:10,207 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:10,207 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2126251155] [2022-07-14 16:02:10,207 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2126251155] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:10,208 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:10,208 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-07-14 16:02:10,208 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1012583098] [2022-07-14 16:02:10,208 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:10,208 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:10,209 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:10,209 INFO L85 PathProgramCache]: Analyzing trace with hash 1964822518, now seen corresponding path program 2 times [2022-07-14 16:02:10,209 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:10,209 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [785245773] [2022-07-14 16:02:10,209 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:10,209 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:10,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:10,212 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:02:10,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:10,215 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:02:10,275 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:10,276 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-07-14 16:02:10,276 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-07-14 16:02:10,276 INFO L87 Difference]: Start difference. First operand 844 states and 1006 transitions. cyclomatic complexity: 165 Second operand has 5 states, 5 states have (on average 8.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:10,352 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:10,353 INFO L93 Difference]: Finished difference Result 1152 states and 1340 transitions. [2022-07-14 16:02:10,353 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-07-14 16:02:10,353 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1152 states and 1340 transitions. [2022-07-14 16:02:10,358 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1105 [2022-07-14 16:02:10,375 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1152 states to 1152 states and 1340 transitions. [2022-07-14 16:02:10,375 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1152 [2022-07-14 16:02:10,376 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1152 [2022-07-14 16:02:10,376 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1152 states and 1340 transitions. [2022-07-14 16:02:10,377 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:10,377 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1152 states and 1340 transitions. [2022-07-14 16:02:10,378 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1152 states and 1340 transitions. [2022-07-14 16:02:10,385 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1152 to 777. [2022-07-14 16:02:10,386 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 777 states, 777 states have (on average 1.1853281853281854) internal successors, (921), 776 states have internal predecessors, (921), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:10,388 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 777 states to 777 states and 921 transitions. [2022-07-14 16:02:10,388 INFO L392 hiAutomatonCegarLoop]: Abstraction has 777 states and 921 transitions. [2022-07-14 16:02:10,388 INFO L374 stractBuchiCegarLoop]: Abstraction has 777 states and 921 transitions. [2022-07-14 16:02:10,388 INFO L287 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-07-14 16:02:10,388 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 777 states and 921 transitions. [2022-07-14 16:02:10,390 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 730 [2022-07-14 16:02:10,391 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:10,391 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:10,391 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:10,391 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:10,391 INFO L752 eck$LassoCheckResult]: Stem: 28943#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 28925#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 28879#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28880#L222 assume !(1 == ~q_req_up~0); 28877#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28878#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 28912#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 28930#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28928#L275 assume !(0 == ~q_read_ev~0); 28929#L275-2 assume !(0 == ~q_write_ev~0); 28914#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 28915#L65 assume !(1 == ~p_dw_pc~0); 28920#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 28921#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 28873#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 28874#L315 assume !(0 != activate_threads_~tmp~1#1); 28883#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 28884#L84 assume !(1 == ~c_dr_pc~0); 28900#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 28891#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 28892#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 28856#L323 assume !(0 != activate_threads_~tmp___0~1#1); 28857#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28942#L293 assume !(1 == ~q_read_ev~0); 28846#L293-2 assume !(1 == ~q_write_ev~0); 28847#L298-1 assume { :end_inline_reset_delta_events } true; 28937#L419-2 assume !false; 28982#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 28981#L364 assume !false; 28980#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 28979#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 28978#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 28977#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 28976#L344 assume 0 != eval_~tmp___1~0#1; 28975#L344-1 assume 0 == ~p_dw_st~0;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 28974#L353 assume 0 != eval_~tmp~2#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1; 28972#L128 assume 0 == ~p_dw_pc~0; 28970#L139-1 assume !false; 28968#L140 assume !(0 == ~q_free~0); 28966#L141 ~q_buf_0~0 := do_write_p_#t~nondet6#1;havoc do_write_p_#t~nondet6#1;~p_last_write~0 := ~q_buf_0~0;~p_num_write~0 := 1 + ~p_num_write~0;~q_free~0 := 0;~q_req_up~0 := 1; 28964#L139-1 assume !false; 28962#L140 assume 0 == ~q_free~0;~p_dw_st~0 := 2;~p_dw_pc~0 := 1; 28960#L158 assume { :end_inline_do_write_p } true; 28959#L349 [2022-07-14 16:02:10,391 INFO L754 eck$LassoCheckResult]: Loop: 28959#L349 assume 0 == ~c_dr_st~0;eval_~tmp___0~2#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 28957#L368 assume !(0 != eval_~tmp___0~2#1); 28958#L364 assume !false; 28973#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 28971#L255 assume !(0 == ~p_dw_st~0); 28969#L259 assume 0 == ~c_dr_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 28967#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 28965#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 28963#L344 assume 0 != eval_~tmp___1~0#1; 28961#L344-1 assume !(0 == ~p_dw_st~0); 28959#L349 [2022-07-14 16:02:10,392 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:10,392 INFO L85 PathProgramCache]: Analyzing trace with hash -377667827, now seen corresponding path program 1 times [2022-07-14 16:02:10,392 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:10,392 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [562988876] [2022-07-14 16:02:10,392 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:10,392 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:10,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:10,398 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:02:10,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:10,406 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:02:10,407 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:10,407 INFO L85 PathProgramCache]: Analyzing trace with hash 1964822518, now seen corresponding path program 3 times [2022-07-14 16:02:10,407 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:10,407 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2079761851] [2022-07-14 16:02:10,407 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:10,407 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:10,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:10,409 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:02:10,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:10,412 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:02:10,412 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:10,412 INFO L85 PathProgramCache]: Analyzing trace with hash -1458589694, now seen corresponding path program 1 times [2022-07-14 16:02:10,412 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:10,413 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [837738869] [2022-07-14 16:02:10,413 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:10,413 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:10,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:10,419 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:02:10,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:10,427 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:02:11,320 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 14.07 04:02:11 BoogieIcfgContainer [2022-07-14 16:02:11,320 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-07-14 16:02:11,321 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-07-14 16:02:11,321 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-07-14 16:02:11,321 INFO L275 PluginConnector]: Witness Printer initialized [2022-07-14 16:02:11,321 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.07 04:02:07" (3/4) ... [2022-07-14 16:02:11,323 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-07-14 16:02:11,358 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2022-07-14 16:02:11,358 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-07-14 16:02:11,359 INFO L158 Benchmark]: Toolchain (without parser) took 4691.74ms. Allocated memory was 90.2MB in the beginning and 148.9MB in the end (delta: 58.7MB). Free memory was 57.5MB in the beginning and 97.0MB in the end (delta: -39.5MB). Peak memory consumption was 18.3MB. Max. memory is 16.1GB. [2022-07-14 16:02:11,359 INFO L158 Benchmark]: CDTParser took 0.19ms. Allocated memory is still 90.2MB. Free memory was 46.5MB in the beginning and 46.4MB in the end (delta: 47.1kB). There was no memory consumed. Max. memory is 16.1GB. [2022-07-14 16:02:11,359 INFO L158 Benchmark]: CACSL2BoogieTranslator took 261.25ms. Allocated memory was 90.2MB in the beginning and 117.4MB in the end (delta: 27.3MB). Free memory was 57.3MB in the beginning and 91.2MB in the end (delta: -33.9MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2022-07-14 16:02:11,359 INFO L158 Benchmark]: Boogie Procedure Inliner took 40.19ms. Allocated memory is still 117.4MB. Free memory was 91.2MB in the beginning and 89.1MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-07-14 16:02:11,360 INFO L158 Benchmark]: Boogie Preprocessor took 24.22ms. Allocated memory is still 117.4MB. Free memory was 89.1MB in the beginning and 87.6MB in the end (delta: 1.4MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-07-14 16:02:11,360 INFO L158 Benchmark]: RCFGBuilder took 588.13ms. Allocated memory is still 117.4MB. Free memory was 87.6MB in the beginning and 72.1MB in the end (delta: 15.5MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. [2022-07-14 16:02:11,360 INFO L158 Benchmark]: BuchiAutomizer took 3734.80ms. Allocated memory was 117.4MB in the beginning and 148.9MB in the end (delta: 31.5MB). Free memory was 71.5MB in the beginning and 100.1MB in the end (delta: -28.6MB). Peak memory consumption was 61.1MB. Max. memory is 16.1GB. [2022-07-14 16:02:11,361 INFO L158 Benchmark]: Witness Printer took 37.53ms. Allocated memory is still 148.9MB. Free memory was 100.1MB in the beginning and 97.0MB in the end (delta: 3.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-07-14 16:02:11,362 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.19ms. Allocated memory is still 90.2MB. Free memory was 46.5MB in the beginning and 46.4MB in the end (delta: 47.1kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 261.25ms. Allocated memory was 90.2MB in the beginning and 117.4MB in the end (delta: 27.3MB). Free memory was 57.3MB in the beginning and 91.2MB in the end (delta: -33.9MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 40.19ms. Allocated memory is still 117.4MB. Free memory was 91.2MB in the beginning and 89.1MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 24.22ms. Allocated memory is still 117.4MB. Free memory was 89.1MB in the beginning and 87.6MB in the end (delta: 1.4MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 588.13ms. Allocated memory is still 117.4MB. Free memory was 87.6MB in the beginning and 72.1MB in the end (delta: 15.5MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. * BuchiAutomizer took 3734.80ms. Allocated memory was 117.4MB in the beginning and 148.9MB in the end (delta: 31.5MB). Free memory was 71.5MB in the beginning and 100.1MB in the end (delta: -28.6MB). Peak memory consumption was 61.1MB. Max. memory is 16.1GB. * Witness Printer took 37.53ms. Allocated memory is still 148.9MB. Free memory was 100.1MB in the beginning and 97.0MB in the end (delta: 3.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 15 terminating modules (15 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.15 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 777 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 3.6s and 16 iterations. TraceHistogramMax:2. Analysis of lassos took 2.2s. Construction of modules took 0.3s. Büchi inclusion checks took 0.3s. Highest rank in rank-based complementation 0. Minimization of det autom 15. Minimization of nondet autom 0. Automata minimization 0.3s AutomataMinimizationTime, 15 MinimizatonAttempts, 2380 StatesRemovedByMinimization, 9 NontrivialMinimizations. Non-live state removal took 0.1s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 2465 SdHoareTripleChecker+Valid, 0.4s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 2465 mSDsluCounter, 4346 SdHoareTripleChecker+Invalid, 0.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 2216 mSDsCounter, 92 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 298 IncrementalHoareTripleChecker+Invalid, 390 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 92 mSolverCounterUnsat, 2130 mSDtfsCounter, 298 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc0 concLT0 SILN2 SILU0 SILI9 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 364]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=1} State at position 1 is {p_last_write=4, c_dr_i=1, c_dr_pc=0, a_t=0, NULL=0, \result=0, NULL=1, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@74ff539f=0, __retres1=0, c_num_read=0, c_dr_st=0, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2e01c53a=0, q_read_ev=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@38862792=0, p_dw_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@17024093=0, q_req_up=1, q_write_ev=2, tmp___0=0, tmp___1=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@665be3a9=0, p_dw_pc=1, __retres1=1, q_free=0, \result=0, p_dw_st=2, __retres1=0, q_ev=0, tmp___0=0, tmp=5, c_last_read=0, NULL=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3622afd1=0, kernel_st=1, p_num_write=1, q_buf_0=4, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2939739a=0, __retres1=0, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 339]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int q_buf_0 ; [L26] int q_free ; [L27] int q_read_ev ; [L28] int q_write_ev ; [L29] int q_req_up ; [L30] int q_ev ; [L51] int p_num_write ; [L52] int p_last_write ; [L53] int p_dw_st ; [L54] int p_dw_pc ; [L55] int p_dw_i ; [L56] int c_num_read ; [L57] int c_last_read ; [L58] int c_dr_st ; [L59] int c_dr_pc ; [L60] int c_dr_i ; [L164] static int a_t ; [L466] int __retres1 ; [L470] CALL init_model() [L452] q_free = 1 [L453] q_write_ev = 2 [L454] q_read_ev = q_write_ev [L455] p_num_write = 0 [L456] p_dw_pc = 0 [L457] p_dw_i = 1 [L458] c_num_read = 0 [L459] c_dr_pc = 0 [L460] c_dr_i = 1 [L470] RET init_model() [L471] CALL start_simulation() [L406] int kernel_st ; [L407] int tmp ; [L411] kernel_st = 0 [L412] CALL update_channels() [L222] COND FALSE !((int )q_req_up == 1) [L412] RET update_channels() [L413] CALL init_threads() [L237] COND TRUE (int )p_dw_i == 1 [L238] p_dw_st = 0 [L242] COND TRUE (int )c_dr_i == 1 [L243] c_dr_st = 0 [L413] RET init_threads() [L414] CALL fire_delta_events() [L275] COND FALSE !((int )q_read_ev == 0) [L280] COND FALSE !((int )q_write_ev == 0) [L414] RET fire_delta_events() [L415] CALL activate_threads() [L308] int tmp ; [L309] int tmp___0 ; [L313] CALL, EXPR is_do_write_p_triggered() [L62] int __retres1 ; [L65] COND FALSE !((int )p_dw_pc == 1) [L75] __retres1 = 0 [L77] return (__retres1); [L313] RET, EXPR is_do_write_p_triggered() [L313] tmp = is_do_write_p_triggered() [L315] COND FALSE !(\read(tmp)) [L321] CALL, EXPR is_do_read_c_triggered() [L81] int __retres1 ; [L84] COND FALSE !((int )c_dr_pc == 1) [L94] __retres1 = 0 [L96] return (__retres1); [L321] RET, EXPR is_do_read_c_triggered() [L321] tmp___0 = is_do_read_c_triggered() [L323] COND FALSE !(\read(tmp___0)) [L415] RET activate_threads() [L416] CALL reset_delta_events() [L293] COND FALSE !((int )q_read_ev == 1) [L298] COND FALSE !((int )q_write_ev == 1) [L416] RET reset_delta_events() [L419] COND TRUE 1 [L422] kernel_st = 1 [L423] CALL eval() [L333] int tmp ; [L334] int tmp___0 ; [L335] int tmp___1 ; [L339] COND TRUE 1 [L342] CALL, EXPR exists_runnable_thread() [L252] int __retres1 ; [L255] COND TRUE (int )p_dw_st == 0 [L256] __retres1 = 1 [L268] return (__retres1); [L342] RET, EXPR exists_runnable_thread() [L342] tmp___1 = exists_runnable_thread() [L344] COND TRUE \read(tmp___1) [L349] COND TRUE (int )p_dw_st == 0 [L351] tmp = __VERIFIER_nondet_int() [L353] COND TRUE \read(tmp) [L355] p_dw_st = 1 [L356] CALL do_write_p() [L128] COND TRUE (int )p_dw_pc == 0 [L139] COND TRUE 1 [L141] COND FALSE !((int )q_free == 0) [L151] q_buf_0 = __VERIFIER_nondet_int() [L152] p_last_write = q_buf_0 [L153] p_num_write += 1 [L154] q_free = 0 [L155] q_req_up = 1 [L139] COND TRUE 1 [L141] COND TRUE (int )q_free == 0 [L142] p_dw_st = 2 [L143] p_dw_pc = 1 [L356] RET do_write_p() Loop: [L364] COND TRUE (int )c_dr_st == 0 [L366] tmp___0 = __VERIFIER_nondet_int() [L368] COND FALSE !(\read(tmp___0)) [L339] COND TRUE 1 [L342] CALL, EXPR exists_runnable_thread() [L252] int __retres1 ; [L255] COND FALSE !((int )p_dw_st == 0) [L259] COND TRUE (int )c_dr_st == 0 [L260] __retres1 = 1 [L268] return (__retres1); [L342] RET, EXPR exists_runnable_thread() [L342] tmp___1 = exists_runnable_thread() [L344] COND TRUE \read(tmp___1) [L349] COND FALSE !((int )p_dw_st == 0) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-07-14 16:02:11,404 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)