./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/pipeline.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version f4b24e32 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/pipeline.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 79bbe68806c3ba3852cd8c209d4ce80dca551636a131cc65daaf97524d927c63 --- Real Ultimate output --- This is Ultimate 0.2.2-?-f4b24e3 [2022-07-14 16:02:11,330 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-07-14 16:02:11,332 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-07-14 16:02:11,361 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-07-14 16:02:11,362 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-07-14 16:02:11,363 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-07-14 16:02:11,364 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-07-14 16:02:11,366 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-07-14 16:02:11,367 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-07-14 16:02:11,371 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-07-14 16:02:11,372 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-07-14 16:02:11,374 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-07-14 16:02:11,374 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-07-14 16:02:11,375 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-07-14 16:02:11,377 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-07-14 16:02:11,379 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-07-14 16:02:11,380 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-07-14 16:02:11,381 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-07-14 16:02:11,382 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-07-14 16:02:11,386 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-07-14 16:02:11,388 INFO L181 SettingsManager]: Resetting HornVerifier preferences to default values [2022-07-14 16:02:11,388 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-07-14 16:02:11,389 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-07-14 16:02:11,389 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-07-14 16:02:11,391 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-07-14 16:02:11,395 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-07-14 16:02:11,396 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-07-14 16:02:11,396 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-07-14 16:02:11,397 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-07-14 16:02:11,397 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-07-14 16:02:11,398 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-07-14 16:02:11,398 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-07-14 16:02:11,400 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-07-14 16:02:11,400 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-07-14 16:02:11,401 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-07-14 16:02:11,401 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-07-14 16:02:11,402 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-07-14 16:02:11,402 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-07-14 16:02:11,402 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-07-14 16:02:11,402 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-07-14 16:02:11,403 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-07-14 16:02:11,404 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-07-14 16:02:11,405 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-07-14 16:02:11,432 INFO L113 SettingsManager]: Loading preferences was successful [2022-07-14 16:02:11,432 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-07-14 16:02:11,433 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-07-14 16:02:11,433 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-07-14 16:02:11,434 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-07-14 16:02:11,434 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-07-14 16:02:11,434 INFO L138 SettingsManager]: * Use SBE=true [2022-07-14 16:02:11,434 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-07-14 16:02:11,435 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-07-14 16:02:11,435 INFO L138 SettingsManager]: * Use old map elimination=false [2022-07-14 16:02:11,435 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-07-14 16:02:11,436 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-07-14 16:02:11,436 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-07-14 16:02:11,436 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-07-14 16:02:11,436 INFO L138 SettingsManager]: * sizeof long=4 [2022-07-14 16:02:11,436 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-07-14 16:02:11,437 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-07-14 16:02:11,437 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-07-14 16:02:11,437 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-07-14 16:02:11,437 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-07-14 16:02:11,438 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-07-14 16:02:11,438 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-07-14 16:02:11,438 INFO L138 SettingsManager]: * sizeof long double=12 [2022-07-14 16:02:11,438 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-07-14 16:02:11,438 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-07-14 16:02:11,438 INFO L138 SettingsManager]: * Use constant arrays=true [2022-07-14 16:02:11,438 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-07-14 16:02:11,439 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-07-14 16:02:11,439 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-07-14 16:02:11,439 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-07-14 16:02:11,439 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-07-14 16:02:11,440 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-07-14 16:02:11,440 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 79bbe68806c3ba3852cd8c209d4ce80dca551636a131cc65daaf97524d927c63 [2022-07-14 16:02:11,626 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-07-14 16:02:11,644 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-07-14 16:02:11,646 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-07-14 16:02:11,647 INFO L271 PluginConnector]: Initializing CDTParser... [2022-07-14 16:02:11,647 INFO L275 PluginConnector]: CDTParser initialized [2022-07-14 16:02:11,648 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/pipeline.cil-1.c [2022-07-14 16:02:11,691 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/76ce825bb/cb251e100e68446eb0a76d59913a497d/FLAG19e8a7304 [2022-07-14 16:02:12,104 INFO L306 CDTParser]: Found 1 translation units. [2022-07-14 16:02:12,104 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/pipeline.cil-1.c [2022-07-14 16:02:12,129 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/76ce825bb/cb251e100e68446eb0a76d59913a497d/FLAG19e8a7304 [2022-07-14 16:02:12,151 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/76ce825bb/cb251e100e68446eb0a76d59913a497d [2022-07-14 16:02:12,153 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-07-14 16:02:12,154 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-07-14 16:02:12,157 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-07-14 16:02:12,157 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-07-14 16:02:12,162 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-07-14 16:02:12,167 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.07 04:02:12" (1/1) ... [2022-07-14 16:02:12,168 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5f5642ee and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:12, skipping insertion in model container [2022-07-14 16:02:12,169 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.07 04:02:12" (1/1) ... [2022-07-14 16:02:12,174 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-07-14 16:02:12,236 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-07-14 16:02:12,391 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/pipeline.cil-1.c[640,653] [2022-07-14 16:02:12,498 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-14 16:02:12,519 INFO L203 MainTranslator]: Completed pre-run [2022-07-14 16:02:12,540 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/pipeline.cil-1.c[640,653] [2022-07-14 16:02:12,593 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-14 16:02:12,611 INFO L208 MainTranslator]: Completed translation [2022-07-14 16:02:12,618 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:12 WrapperNode [2022-07-14 16:02:12,618 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-07-14 16:02:12,633 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-07-14 16:02:12,634 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-07-14 16:02:12,634 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-07-14 16:02:12,640 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:12" (1/1) ... [2022-07-14 16:02:12,664 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:12" (1/1) ... [2022-07-14 16:02:12,708 INFO L137 Inliner]: procedures = 20, calls = 17, calls flagged for inlining = 12, calls inlined = 24, statements flattened = 1037 [2022-07-14 16:02:12,733 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-07-14 16:02:12,734 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-07-14 16:02:12,734 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-07-14 16:02:12,734 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-07-14 16:02:12,740 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:12" (1/1) ... [2022-07-14 16:02:12,740 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:12" (1/1) ... [2022-07-14 16:02:12,749 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:12" (1/1) ... [2022-07-14 16:02:12,750 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:12" (1/1) ... [2022-07-14 16:02:12,766 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:12" (1/1) ... [2022-07-14 16:02:12,792 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:12" (1/1) ... [2022-07-14 16:02:12,829 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:12" (1/1) ... [2022-07-14 16:02:12,833 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-07-14 16:02:12,834 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-07-14 16:02:12,843 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-07-14 16:02:12,843 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-07-14 16:02:12,844 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:12" (1/1) ... [2022-07-14 16:02:12,857 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 16:02:12,865 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 16:02:12,896 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-14 16:02:12,899 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-07-14 16:02:12,948 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-07-14 16:02:12,948 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-07-14 16:02:12,948 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-07-14 16:02:12,948 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-07-14 16:02:13,010 INFO L234 CfgBuilder]: Building ICFG [2022-07-14 16:02:13,012 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-07-14 16:02:13,536 INFO L275 CfgBuilder]: Performing block encoding [2022-07-14 16:02:13,545 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-07-14 16:02:13,545 INFO L299 CfgBuilder]: Removed 7 assume(true) statements. [2022-07-14 16:02:13,548 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.07 04:02:13 BoogieIcfgContainer [2022-07-14 16:02:13,548 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-07-14 16:02:13,549 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-07-14 16:02:13,549 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-07-14 16:02:13,551 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-07-14 16:02:13,552 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-14 16:02:13,552 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 14.07 04:02:12" (1/3) ... [2022-07-14 16:02:13,553 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@427e3ff7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 14.07 04:02:13, skipping insertion in model container [2022-07-14 16:02:13,553 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-14 16:02:13,553 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:12" (2/3) ... [2022-07-14 16:02:13,553 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@427e3ff7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 14.07 04:02:13, skipping insertion in model container [2022-07-14 16:02:13,553 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-14 16:02:13,553 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.07 04:02:13" (3/3) ... [2022-07-14 16:02:13,554 INFO L354 chiAutomizerObserver]: Analyzing ICFG pipeline.cil-1.c [2022-07-14 16:02:13,596 INFO L255 stractBuchiCegarLoop]: Interprodecural is true [2022-07-14 16:02:13,596 INFO L256 stractBuchiCegarLoop]: Hoare is false [2022-07-14 16:02:13,596 INFO L257 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-07-14 16:02:13,596 INFO L258 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-07-14 16:02:13,597 INFO L259 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-07-14 16:02:13,597 INFO L260 stractBuchiCegarLoop]: Difference is false [2022-07-14 16:02:13,597 INFO L261 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-07-14 16:02:13,597 INFO L265 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-07-14 16:02:13,602 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 422 states, 421 states have (on average 1.814726840855107) internal successors, (764), 421 states have internal predecessors, (764), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:13,641 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 360 [2022-07-14 16:02:13,642 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:13,642 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:13,661 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:13,661 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:13,661 INFO L287 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-07-14 16:02:13,663 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 422 states, 421 states have (on average 1.814726840855107) internal successors, (764), 421 states have internal predecessors, (764), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:13,670 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 360 [2022-07-14 16:02:13,670 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:13,670 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:13,672 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:13,672 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:13,690 INFO L752 eck$LassoCheckResult]: Stem: 413#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 358#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 30#L256true assume !(1 == ~main_in1_req_up~0); 9#L256-2true assume !(1 == ~main_in2_req_up~0); 24#L267-1true assume !(1 == ~main_sum_req_up~0); 302#L278-1true assume !(1 == ~main_diff_req_up~0); 2#L289-1true assume !(1 == ~main_pres_req_up~0); 254#L300-1true assume !(1 == ~main_dbl_req_up~0); 148#L311-1true assume !(1 == ~main_zero_req_up~0); 327#L322-1true assume !(1 == ~main_clk_req_up~0); 193#L333-1true assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 124#L351-1true assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 18#L356-1true assume 1 == ~S2_presdbl_i~0;~S2_presdbl_st~0 := 0; 118#L361-1true assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 340#L366-1true assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 112#L371-1true assume !(0 == ~main_in1_ev~0); 43#L376-1true assume !(0 == ~main_in2_ev~0); 304#L381-1true assume !(0 == ~main_sum_ev~0); 132#L386-1true assume !(0 == ~main_diff_ev~0); 322#L391-1true assume !(0 == ~main_pres_ev~0); 228#L396-1true assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1; 80#L401-1true assume !(0 == ~main_zero_ev~0); 86#L406-1true assume !(0 == ~main_clk_ev~0); 353#L411-1true assume !(0 == ~main_clk_pos_edge~0); 337#L416-1true assume !(0 == ~main_clk_neg_edge~0); 393#L421-1true assume !(1 == ~main_clk_pos_edge~0); 290#L426-1true assume !(1 == ~main_clk_pos_edge~0); 105#L431-1true assume !(1 == ~main_clk_pos_edge~0); 233#L436-1true assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0; 94#L441-1true assume !(1 == ~main_clk_pos_edge~0); 385#L446-1true assume !(1 == ~main_in1_ev~0); 276#L451-1true assume !(1 == ~main_in2_ev~0); 394#L456-1true assume !(1 == ~main_sum_ev~0); 137#L461-1true assume !(1 == ~main_diff_ev~0); 380#L466-1true assume !(1 == ~main_pres_ev~0); 405#L471-1true assume !(1 == ~main_dbl_ev~0); 25#L476-1true assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 194#L481-1true assume !(1 == ~main_clk_ev~0); 91#L486-1true assume !(1 == ~main_clk_pos_edge~0); 27#L491-1true assume !(1 == ~main_clk_neg_edge~0); 249#L742-1true [2022-07-14 16:02:13,691 INFO L754 eck$LassoCheckResult]: Loop: 249#L742-1true assume !false; 375#L503true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 205#L229true assume false; 238#L245true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 255#L509true assume !(1 == ~main_in1_req_up~0); 172#L509-2true assume !(1 == ~main_in2_req_up~0); 338#L520-1true assume !(1 == ~main_sum_req_up~0); 219#L531-1true assume !(1 == ~main_diff_req_up~0); 143#L542-1true assume !(1 == ~main_pres_req_up~0); 392#L553-1true assume !(1 == ~main_dbl_req_up~0); 158#L564-1true assume !(1 == ~main_zero_req_up~0); 244#L575-1true assume !(1 == ~main_clk_req_up~0); 342#L586-1true start_simulation_~kernel_st~0#1 := 3; 368#L605true assume !(0 == ~main_in1_ev~0); 286#L605-2true assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 16#L610-1true assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 192#L615-1true assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 189#L620-1true assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 185#L625-1true assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1; 269#L630-1true assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 328#L635-1true assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 326#L640-1true assume !(0 == ~main_clk_pos_edge~0); 84#L645-1true assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 111#L650-1true assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0; 131#L655-1true assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0; 203#L660-1true assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0; 239#L665-1true assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0; 289#L670-1true assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0; 181#L675-1true assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 236#L680-1true assume !(1 == ~main_in2_ev~0); 311#L685-1true assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 214#L690-1true assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 404#L695-1true assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 274#L700-1true assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2; 267#L705-1true assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 374#L710-1true assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 177#L715-1true assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2; 134#L720-1true assume !(1 == ~main_clk_neg_edge~0); 164#L725-1true assume 0 == ~N_generate_st~0; 249#L742-1true [2022-07-14 16:02:13,695 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:13,695 INFO L85 PathProgramCache]: Analyzing trace with hash 1291793407, now seen corresponding path program 1 times [2022-07-14 16:02:13,701 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:13,703 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1645221066] [2022-07-14 16:02:13,704 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:13,704 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:13,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:13,888 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:13,888 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:13,889 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1645221066] [2022-07-14 16:02:13,890 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1645221066] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:13,890 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:13,891 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-07-14 16:02:13,892 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [160457293] [2022-07-14 16:02:13,893 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:13,897 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:13,898 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:13,899 INFO L85 PathProgramCache]: Analyzing trace with hash -727719859, now seen corresponding path program 1 times [2022-07-14 16:02:13,899 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:13,899 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1809891470] [2022-07-14 16:02:13,900 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:13,900 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:13,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:13,937 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:13,938 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:13,939 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1809891470] [2022-07-14 16:02:13,939 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1809891470] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:13,939 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:13,942 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-14 16:02:13,942 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [965909248] [2022-07-14 16:02:13,942 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:13,943 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:13,944 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:13,965 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-07-14 16:02:13,966 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-07-14 16:02:13,968 INFO L87 Difference]: Start difference. First operand has 422 states, 421 states have (on average 1.814726840855107) internal successors, (764), 421 states have internal predecessors, (764), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 19.5) internal successors, (39), 2 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:14,006 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:14,007 INFO L93 Difference]: Finished difference Result 417 states and 745 transitions. [2022-07-14 16:02:14,008 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-07-14 16:02:14,012 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 417 states and 745 transitions. [2022-07-14 16:02:14,024 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 358 [2022-07-14 16:02:14,035 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 417 states to 416 states and 744 transitions. [2022-07-14 16:02:14,035 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 416 [2022-07-14 16:02:14,036 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 416 [2022-07-14 16:02:14,037 INFO L73 IsDeterministic]: Start isDeterministic. Operand 416 states and 744 transitions. [2022-07-14 16:02:14,044 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:14,044 INFO L369 hiAutomatonCegarLoop]: Abstraction has 416 states and 744 transitions. [2022-07-14 16:02:14,058 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 416 states and 744 transitions. [2022-07-14 16:02:14,075 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 416 to 416. [2022-07-14 16:02:14,076 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 416 states, 416 states have (on average 1.7884615384615385) internal successors, (744), 415 states have internal predecessors, (744), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:14,077 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 416 states to 416 states and 744 transitions. [2022-07-14 16:02:14,078 INFO L392 hiAutomatonCegarLoop]: Abstraction has 416 states and 744 transitions. [2022-07-14 16:02:14,078 INFO L374 stractBuchiCegarLoop]: Abstraction has 416 states and 744 transitions. [2022-07-14 16:02:14,078 INFO L287 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-07-14 16:02:14,078 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 416 states and 744 transitions. [2022-07-14 16:02:14,080 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 358 [2022-07-14 16:02:14,080 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:14,080 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:14,081 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:14,081 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:14,082 INFO L752 eck$LassoCheckResult]: Stem: 1264#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 1256#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 909#L256 assume !(1 == ~main_in1_req_up~0); 866#L256-2 assume !(1 == ~main_in2_req_up~0); 868#L267-1 assume !(1 == ~main_sum_req_up~0); 897#L278-1 assume !(1 == ~main_diff_req_up~0); 849#L289-1 assume !(1 == ~main_pres_req_up~0); 850#L300-1 assume !(1 == ~main_dbl_req_up~0); 957#L311-1 assume !(1 == ~main_zero_req_up~0); 1102#L322-1 assume !(1 == ~main_clk_req_up~0); 1076#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 1067#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 886#L356-1 assume 1 == ~S2_presdbl_i~0;~S2_presdbl_st~0 := 0; 887#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 1061#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 1055#L371-1 assume !(0 == ~main_in1_ev~0); 937#L376-1 assume !(0 == ~main_in2_ev~0); 938#L381-1 assume !(0 == ~main_sum_ev~0); 1078#L386-1 assume !(0 == ~main_diff_ev~0); 1079#L391-1 assume !(0 == ~main_pres_ev~0); 1186#L396-1 assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1; 1006#L401-1 assume !(0 == ~main_zero_ev~0); 1007#L406-1 assume !(0 == ~main_clk_ev~0); 1016#L411-1 assume !(0 == ~main_clk_pos_edge~0); 1247#L416-1 assume !(0 == ~main_clk_neg_edge~0); 1248#L421-1 assume !(1 == ~main_clk_pos_edge~0); 1233#L426-1 assume !(1 == ~main_clk_pos_edge~0); 1044#L431-1 assume !(1 == ~main_clk_pos_edge~0); 1045#L436-1 assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0; 1025#L441-1 assume !(1 == ~main_clk_pos_edge~0); 1026#L446-1 assume !(1 == ~main_in1_ev~0); 1225#L451-1 assume !(1 == ~main_in2_ev~0); 1226#L456-1 assume !(1 == ~main_sum_ev~0); 1087#L461-1 assume !(1 == ~main_diff_ev~0); 1088#L466-1 assume !(1 == ~main_pres_ev~0); 1261#L471-1 assume !(1 == ~main_dbl_ev~0); 899#L476-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 900#L481-1 assume !(1 == ~main_clk_ev~0); 1023#L486-1 assume !(1 == ~main_clk_pos_edge~0); 904#L491-1 assume !(1 == ~main_clk_neg_edge~0); 905#L742-1 [2022-07-14 16:02:14,082 INFO L754 eck$LassoCheckResult]: Loop: 905#L742-1 assume !false; 1205#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 941#L229 assume !false; 1164#L147 assume !(0 == ~N_generate_st~0); 969#L151 assume !(0 == ~S1_addsub_st~0); 970#L154 assume !(0 == ~S2_presdbl_st~0); 859#L157 assume !(0 == ~S3_zero_st~0); 861#L160 assume !(0 == ~D_print_st~0); 1195#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 1196#L509 assume !(1 == ~main_in1_req_up~0); 863#L509-2 assume !(1 == ~main_in2_req_up~0); 1132#L520-1 assume !(1 == ~main_sum_req_up~0); 1178#L531-1 assume !(1 == ~main_diff_req_up~0); 1096#L542-1 assume !(1 == ~main_pres_req_up~0); 870#L553-1 assume !(1 == ~main_dbl_req_up~0); 1105#L564-1 assume !(1 == ~main_zero_req_up~0); 1115#L575-1 assume !(1 == ~main_clk_req_up~0); 1200#L586-1 start_simulation_~kernel_st~0#1 := 3; 1249#L605 assume !(0 == ~main_in1_ev~0); 1232#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 883#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 884#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 1155#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 1150#L625-1 assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1; 1151#L630-1 assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 1220#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 1243#L640-1 assume !(0 == ~main_clk_pos_edge~0); 1014#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 1015#L650-1 assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0; 1054#L655-1 assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0; 1077#L660-1 assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0; 1163#L665-1 assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0; 1197#L670-1 assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0; 1143#L675-1 assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 1144#L680-1 assume !(1 == ~main_in2_ev~0); 1193#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 1173#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 1174#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 1221#L700-1 assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2; 1218#L705-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 1219#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 1139#L715-1 assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2; 1083#L720-1 assume !(1 == ~main_clk_neg_edge~0); 1084#L725-1 assume 0 == ~N_generate_st~0; 905#L742-1 [2022-07-14 16:02:14,082 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:14,083 INFO L85 PathProgramCache]: Analyzing trace with hash 1291793407, now seen corresponding path program 2 times [2022-07-14 16:02:14,083 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:14,083 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1519762786] [2022-07-14 16:02:14,083 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:14,083 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:14,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:14,117 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:14,118 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:14,118 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1519762786] [2022-07-14 16:02:14,118 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1519762786] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:14,118 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:14,118 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-07-14 16:02:14,118 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1240107515] [2022-07-14 16:02:14,119 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:14,119 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:14,119 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:14,120 INFO L85 PathProgramCache]: Analyzing trace with hash 1802774254, now seen corresponding path program 1 times [2022-07-14 16:02:14,120 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:14,120 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [7081838] [2022-07-14 16:02:14,120 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:14,120 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:14,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:14,149 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:14,150 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:14,150 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [7081838] [2022-07-14 16:02:14,150 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [7081838] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:14,150 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:14,150 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:14,151 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [806174732] [2022-07-14 16:02:14,151 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:14,151 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:14,151 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:14,152 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:02:14,152 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:02:14,152 INFO L87 Difference]: Start difference. First operand 416 states and 744 transitions. cyclomatic complexity: 330 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:14,233 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:14,233 INFO L93 Difference]: Finished difference Result 760 states and 1352 transitions. [2022-07-14 16:02:14,233 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:02:14,234 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 760 states and 1352 transitions. [2022-07-14 16:02:14,241 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 703 [2022-07-14 16:02:14,244 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 760 states to 760 states and 1352 transitions. [2022-07-14 16:02:14,245 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 760 [2022-07-14 16:02:14,246 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 760 [2022-07-14 16:02:14,246 INFO L73 IsDeterministic]: Start isDeterministic. Operand 760 states and 1352 transitions. [2022-07-14 16:02:14,247 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:14,247 INFO L369 hiAutomatonCegarLoop]: Abstraction has 760 states and 1352 transitions. [2022-07-14 16:02:14,248 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 760 states and 1352 transitions. [2022-07-14 16:02:14,270 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 760 to 760. [2022-07-14 16:02:14,273 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 760 states, 760 states have (on average 1.7789473684210526) internal successors, (1352), 759 states have internal predecessors, (1352), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:14,275 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 760 states to 760 states and 1352 transitions. [2022-07-14 16:02:14,275 INFO L392 hiAutomatonCegarLoop]: Abstraction has 760 states and 1352 transitions. [2022-07-14 16:02:14,275 INFO L374 stractBuchiCegarLoop]: Abstraction has 760 states and 1352 transitions. [2022-07-14 16:02:14,276 INFO L287 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-07-14 16:02:14,276 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 760 states and 1352 transitions. [2022-07-14 16:02:14,278 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 703 [2022-07-14 16:02:14,279 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:14,279 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:14,285 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:14,285 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:14,286 INFO L752 eck$LassoCheckResult]: Stem: 2461#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 2453#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2096#L256 assume !(1 == ~main_in1_req_up~0); 2053#L256-2 assume !(1 == ~main_in2_req_up~0); 2055#L267-1 assume !(1 == ~main_sum_req_up~0); 2084#L278-1 assume !(1 == ~main_diff_req_up~0); 2036#L289-1 assume !(1 == ~main_pres_req_up~0); 2037#L300-1 assume !(1 == ~main_dbl_req_up~0); 2142#L311-1 assume !(1 == ~main_zero_req_up~0); 2290#L322-1 assume !(1 == ~main_clk_req_up~0); 2263#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2254#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2073#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2074#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 2248#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 2242#L371-1 assume !(0 == ~main_in1_ev~0); 2122#L376-1 assume !(0 == ~main_in2_ev~0); 2123#L381-1 assume !(0 == ~main_sum_ev~0); 2265#L386-1 assume !(0 == ~main_diff_ev~0); 2266#L391-1 assume !(0 == ~main_pres_ev~0); 2377#L396-1 assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1; 2193#L401-1 assume !(0 == ~main_zero_ev~0); 2194#L406-1 assume !(0 == ~main_clk_ev~0); 2203#L411-1 assume !(0 == ~main_clk_pos_edge~0); 2444#L416-1 assume !(0 == ~main_clk_neg_edge~0); 2445#L421-1 assume !(1 == ~main_clk_pos_edge~0); 2428#L426-1 assume !(1 == ~main_clk_pos_edge~0); 2231#L431-1 assume !(1 == ~main_clk_pos_edge~0); 2232#L436-1 assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0; 2211#L441-1 assume !(1 == ~main_clk_pos_edge~0); 2212#L446-1 assume !(1 == ~main_in1_ev~0); 2420#L451-1 assume !(1 == ~main_in2_ev~0); 2421#L456-1 assume !(1 == ~main_sum_ev~0); 2275#L461-1 assume !(1 == ~main_diff_ev~0); 2276#L466-1 assume !(1 == ~main_pres_ev~0); 2457#L471-1 assume !(1 == ~main_dbl_ev~0); 2086#L476-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 2087#L481-1 assume !(1 == ~main_clk_ev~0); 2210#L486-1 assume !(1 == ~main_clk_pos_edge~0); 2091#L491-1 assume !(1 == ~main_clk_neg_edge~0); 2092#L742-1 [2022-07-14 16:02:14,286 INFO L754 eck$LassoCheckResult]: Loop: 2092#L742-1 assume !false; 2744#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2739#L229 assume !false; 2737#L147 assume !(0 == ~N_generate_st~0); 2735#L151 assume !(0 == ~S1_addsub_st~0); 2733#L154 assume !(0 == ~S2_presdbl_st~0); 2046#L157 assume !(0 == ~S3_zero_st~0); 2048#L160 assume !(0 == ~D_print_st~0); 2387#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 2388#L509 assume !(1 == ~main_in1_req_up~0); 2321#L509-2 assume !(1 == ~main_in2_req_up~0); 2322#L520-1 assume !(1 == ~main_sum_req_up~0); 2369#L531-1 assume !(1 == ~main_diff_req_up~0); 2284#L542-1 assume !(1 == ~main_pres_req_up~0); 2057#L553-1 assume !(1 == ~main_dbl_req_up~0); 2293#L564-1 assume !(1 == ~main_zero_req_up~0); 2304#L575-1 assume !(1 == ~main_clk_req_up~0); 2393#L586-1 start_simulation_~kernel_st~0#1 := 3; 2446#L605 assume !(0 == ~main_in1_ev~0); 2427#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 2070#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2071#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 2346#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2340#L625-1 assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1; 2341#L630-1 assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 2415#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 2440#L640-1 assume !(0 == ~main_clk_pos_edge~0); 2201#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 2202#L650-1 assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0; 2241#L655-1 assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0; 2264#L660-1 assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0; 2354#L665-1 assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0; 2389#L670-1 assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0; 2333#L675-1 assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 2334#L680-1 assume !(1 == ~main_in2_ev~0); 2385#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 2364#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2365#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 2416#L700-1 assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2; 2413#L705-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 2414#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 2329#L715-1 assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2; 2270#L720-1 assume !(1 == ~main_clk_neg_edge~0); 2271#L725-1 assume 0 == ~N_generate_st~0; 2092#L742-1 [2022-07-14 16:02:14,289 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:14,290 INFO L85 PathProgramCache]: Analyzing trace with hash 782320317, now seen corresponding path program 1 times [2022-07-14 16:02:14,290 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:14,290 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1454607590] [2022-07-14 16:02:14,290 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:14,290 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:14,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:14,367 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:14,368 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:14,368 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1454607590] [2022-07-14 16:02:14,368 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1454607590] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:14,368 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:14,368 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-07-14 16:02:14,369 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [56661946] [2022-07-14 16:02:14,369 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:14,369 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:14,369 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:14,369 INFO L85 PathProgramCache]: Analyzing trace with hash 1802774254, now seen corresponding path program 2 times [2022-07-14 16:02:14,370 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:14,370 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [781556972] [2022-07-14 16:02:14,370 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:14,370 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:14,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:14,436 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:14,436 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:14,437 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [781556972] [2022-07-14 16:02:14,437 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [781556972] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:14,437 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:14,437 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:14,437 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [762960058] [2022-07-14 16:02:14,437 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:14,438 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:14,438 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:14,439 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:02:14,439 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:02:14,439 INFO L87 Difference]: Start difference. First operand 760 states and 1352 transitions. cyclomatic complexity: 596 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:14,569 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:14,569 INFO L93 Difference]: Finished difference Result 1669 states and 2937 transitions. [2022-07-14 16:02:14,570 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-07-14 16:02:14,571 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1669 states and 2937 transitions. [2022-07-14 16:02:14,580 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1572 [2022-07-14 16:02:14,586 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1669 states to 1669 states and 2937 transitions. [2022-07-14 16:02:14,586 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1669 [2022-07-14 16:02:14,588 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1669 [2022-07-14 16:02:14,588 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1669 states and 2937 transitions. [2022-07-14 16:02:14,589 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:14,589 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1669 states and 2937 transitions. [2022-07-14 16:02:14,590 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1669 states and 2937 transitions. [2022-07-14 16:02:14,606 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1669 to 1669. [2022-07-14 16:02:14,609 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1669 states, 1669 states have (on average 1.7597363690832835) internal successors, (2937), 1668 states have internal predecessors, (2937), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:14,613 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1669 states to 1669 states and 2937 transitions. [2022-07-14 16:02:14,613 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1669 states and 2937 transitions. [2022-07-14 16:02:14,613 INFO L374 stractBuchiCegarLoop]: Abstraction has 1669 states and 2937 transitions. [2022-07-14 16:02:14,613 INFO L287 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-07-14 16:02:14,613 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1669 states and 2937 transitions. [2022-07-14 16:02:14,618 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1572 [2022-07-14 16:02:14,619 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:14,619 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:14,619 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:14,619 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:14,620 INFO L752 eck$LassoCheckResult]: Stem: 4958#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 4937#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 4535#L256 assume !(1 == ~main_in1_req_up~0); 4492#L256-2 assume !(1 == ~main_in2_req_up~0); 4494#L267-1 assume !(1 == ~main_sum_req_up~0); 4523#L278-1 assume !(1 == ~main_diff_req_up~0); 4475#L289-1 assume !(1 == ~main_pres_req_up~0); 4476#L300-1 assume !(1 == ~main_dbl_req_up~0); 4745#L311-1 assume !(1 == ~main_zero_req_up~0); 4744#L322-1 assume !(1 == ~main_clk_req_up~0); 4972#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 4971#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 4512#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 4513#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 4697#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 4691#L371-1 assume !(0 == ~main_in1_ev~0); 4562#L376-1 assume !(0 == ~main_in2_ev~0); 4563#L381-1 assume !(0 == ~main_sum_ev~0); 4966#L386-1 assume !(0 == ~main_diff_ev~0); 4917#L391-1 assume !(0 == ~main_pres_ev~0); 4845#L396-1 assume !(0 == ~main_dbl_ev~0); 4846#L401-1 assume !(0 == ~main_zero_ev~0); 5814#L406-1 assume !(0 == ~main_clk_ev~0); 5813#L411-1 assume !(0 == ~main_clk_pos_edge~0); 5812#L416-1 assume !(0 == ~main_clk_neg_edge~0); 5811#L421-1 assume !(1 == ~main_clk_pos_edge~0); 5810#L426-1 assume !(1 == ~main_clk_pos_edge~0); 5809#L431-1 assume !(1 == ~main_clk_pos_edge~0); 5808#L436-1 assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0; 5804#L441-1 assume !(1 == ~main_clk_pos_edge~0); 5800#L446-1 assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 4889#L451-1 assume !(1 == ~main_in2_ev~0); 4890#L456-1 assume !(1 == ~main_sum_ev~0); 4725#L461-1 assume !(1 == ~main_diff_ev~0); 4726#L466-1 assume !(1 == ~main_pres_ev~0); 4946#L471-1 assume !(1 == ~main_dbl_ev~0); 4525#L476-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 4526#L481-1 assume !(1 == ~main_clk_ev~0); 4656#L486-1 assume !(1 == ~main_clk_pos_edge~0); 4530#L491-1 assume !(1 == ~main_clk_neg_edge~0); 4531#L742-1 [2022-07-14 16:02:14,620 INFO L754 eck$LassoCheckResult]: Loop: 4531#L742-1 assume !false; 4868#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 4566#L229 assume !false; 4817#L147 assume !(0 == ~N_generate_st~0); 4596#L151 assume !(0 == ~S1_addsub_st~0); 4597#L154 assume !(0 == ~S2_presdbl_st~0); 4485#L157 assume !(0 == ~S3_zero_st~0); 4487#L160 assume !(0 == ~D_print_st~0); 4856#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 4857#L509 assume !(1 == ~main_in1_req_up~0); 4777#L509-2 assume !(1 == ~main_in2_req_up~0); 4778#L520-1 assume !(1 == ~main_sum_req_up~0); 5113#L531-1 assume !(1 == ~main_diff_req_up~0); 5111#L542-1 assume !(1 == ~main_pres_req_up~0); 4952#L553-1 assume !(1 == ~main_dbl_req_up~0); 4953#L564-1 assume !(1 == ~main_zero_req_up~0); 5944#L575-1 assume !(1 == ~main_clk_req_up~0); 5942#L586-1 start_simulation_~kernel_st~0#1 := 3; 5941#L605 assume !(0 == ~main_in1_ev~0); 5940#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 5939#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 5938#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 5937#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 4799#L625-1 assume !(0 == ~main_dbl_ev~0); 4800#L630-1 assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 4884#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 4918#L640-1 assume !(0 == ~main_clk_pos_edge~0); 4643#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 4644#L650-1 assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0; 4690#L655-1 assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0; 4715#L660-1 assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0; 4816#L665-1 assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0; 4858#L670-1 assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0; 4792#L675-1 assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 4793#L680-1 assume !(1 == ~main_in2_ev~0); 4854#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 4829#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 4830#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 4885#L700-1 assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2; 4882#L705-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 4883#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 4786#L715-1 assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2; 4723#L720-1 assume !(1 == ~main_clk_neg_edge~0); 4724#L725-1 assume 0 == ~N_generate_st~0; 4531#L742-1 [2022-07-14 16:02:14,620 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:14,620 INFO L85 PathProgramCache]: Analyzing trace with hash 357698877, now seen corresponding path program 1 times [2022-07-14 16:02:14,621 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:14,621 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [582012487] [2022-07-14 16:02:14,621 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:14,621 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:14,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:14,648 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:14,648 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:14,648 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [582012487] [2022-07-14 16:02:14,649 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [582012487] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:14,649 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:14,649 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:14,649 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1281927904] [2022-07-14 16:02:14,649 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:14,649 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:14,650 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:14,650 INFO L85 PathProgramCache]: Analyzing trace with hash -2069491216, now seen corresponding path program 1 times [2022-07-14 16:02:14,650 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:14,650 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1930387812] [2022-07-14 16:02:14,650 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:14,651 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:14,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:14,675 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:14,675 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:14,675 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1930387812] [2022-07-14 16:02:14,675 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1930387812] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:14,676 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:14,676 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:14,676 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1262078240] [2022-07-14 16:02:14,676 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:14,676 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:14,676 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:14,677 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:02:14,677 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:02:14,677 INFO L87 Difference]: Start difference. First operand 1669 states and 2937 transitions. cyclomatic complexity: 1276 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:14,843 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:14,843 INFO L93 Difference]: Finished difference Result 1999 states and 3465 transitions. [2022-07-14 16:02:14,844 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:02:14,845 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1999 states and 3465 transitions. [2022-07-14 16:02:14,853 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1872 [2022-07-14 16:02:14,860 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1999 states to 1999 states and 3465 transitions. [2022-07-14 16:02:14,860 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1999 [2022-07-14 16:02:14,862 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1999 [2022-07-14 16:02:14,862 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1999 states and 3465 transitions. [2022-07-14 16:02:14,863 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:14,864 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1999 states and 3465 transitions. [2022-07-14 16:02:14,865 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1999 states and 3465 transitions. [2022-07-14 16:02:14,881 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1999 to 1999. [2022-07-14 16:02:14,883 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1999 states, 1999 states have (on average 1.7333666833416708) internal successors, (3465), 1998 states have internal predecessors, (3465), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:14,887 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1999 states to 1999 states and 3465 transitions. [2022-07-14 16:02:14,888 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1999 states and 3465 transitions. [2022-07-14 16:02:14,888 INFO L374 stractBuchiCegarLoop]: Abstraction has 1999 states and 3465 transitions. [2022-07-14 16:02:14,888 INFO L287 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-07-14 16:02:14,888 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1999 states and 3465 transitions. [2022-07-14 16:02:14,894 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1872 [2022-07-14 16:02:14,894 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:14,894 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:14,894 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:14,895 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:14,895 INFO L752 eck$LassoCheckResult]: Stem: 8642#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 8618#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 8211#L256 assume !(1 == ~main_in1_req_up~0); 8167#L256-2 assume !(1 == ~main_in2_req_up~0); 8169#L267-1 assume !(1 == ~main_sum_req_up~0); 8198#L278-1 assume !(1 == ~main_diff_req_up~0); 8150#L289-1 assume !(1 == ~main_pres_req_up~0); 8151#L300-1 assume !(1 == ~main_dbl_req_up~0); 8258#L311-1 assume !(1 == ~main_zero_req_up~0); 8598#L322-1 assume !(1 == ~main_clk_req_up~0); 8389#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 8378#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 8379#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 8653#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 8606#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 8366#L371-1 assume !(0 == ~main_in1_ev~0); 8238#L376-1 assume !(0 == ~main_in2_ev~0); 8239#L381-1 assume !(0 == ~main_sum_ev~0); 8650#L386-1 assume !(0 == ~main_diff_ev~0); 8595#L391-1 assume !(0 == ~main_pres_ev~0); 8520#L396-1 assume !(0 == ~main_dbl_ev~0); 8312#L401-1 assume !(0 == ~main_zero_ev~0); 8313#L406-1 assume !(0 == ~main_clk_ev~0); 8324#L411-1 assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1; 8614#L416-1 assume !(0 == ~main_clk_neg_edge~0); 10148#L421-1 assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0; 10122#L426-1 assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0; 10121#L431-1 assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0; 10120#L436-1 assume !(1 == ~main_clk_pos_edge~0); 8333#L441-1 assume !(1 == ~main_clk_pos_edge~0); 8334#L446-1 assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 9017#L451-1 assume !(1 == ~main_in2_ev~0); 10027#L456-1 assume !(1 == ~main_sum_ev~0); 10026#L461-1 assume !(1 == ~main_diff_ev~0); 10025#L466-1 assume !(1 == ~main_pres_ev~0); 10024#L471-1 assume !(1 == ~main_dbl_ev~0); 9006#L476-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 10023#L481-1 assume !(1 == ~main_clk_ev~0); 10022#L486-1 assume !(1 == ~main_clk_pos_edge~0); 10020#L491-1 assume !(1 == ~main_clk_neg_edge~0); 8293#L742-1 [2022-07-14 16:02:14,895 INFO L754 eck$LassoCheckResult]: Loop: 8293#L742-1 assume !false; 10019#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 10015#L229 assume !false; 10014#L147 assume !(0 == ~N_generate_st~0); 10013#L151 assume !(0 == ~S1_addsub_st~0); 10012#L154 assume !(0 == ~S2_presdbl_st~0); 10011#L157 assume !(0 == ~S3_zero_st~0); 10009#L160 assume !(0 == ~D_print_st~0); 10008#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 10007#L509 assume !(1 == ~main_in1_req_up~0); 10005#L509-2 assume !(1 == ~main_in2_req_up~0); 10002#L520-1 assume !(1 == ~main_sum_req_up~0); 9998#L531-1 assume !(1 == ~main_diff_req_up~0); 9994#L542-1 assume !(1 == ~main_pres_req_up~0); 9990#L553-1 assume !(1 == ~main_dbl_req_up~0); 9984#L564-1 assume !(1 == ~main_zero_req_up~0); 9978#L575-1 assume !(1 == ~main_clk_req_up~0); 9975#L586-1 start_simulation_~kernel_st~0#1 := 3; 9973#L605 assume !(0 == ~main_in1_ev~0); 9971#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 9969#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 9967#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 9965#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 9964#L625-1 assume !(0 == ~main_dbl_ev~0); 9962#L630-1 assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 9961#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 9959#L640-1 assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1; 9958#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 9957#L650-1 assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0; 9956#L655-1 assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0; 9954#L660-1 assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0; 9953#L665-1 assume !(1 == ~main_clk_pos_edge~0); 8532#L670-1 assume !(1 == ~main_clk_pos_edge~0); 8471#L675-1 assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 8472#L680-1 assume !(1 == ~main_in2_ev~0); 8528#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 8505#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 8506#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 8564#L700-1 assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2; 8560#L705-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 8561#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 8466#L715-1 assume !(1 == ~main_clk_pos_edge~0); 8397#L720-1 assume !(1 == ~main_clk_neg_edge~0); 8398#L725-1 assume 0 == ~N_generate_st~0; 8293#L742-1 [2022-07-14 16:02:14,897 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:14,897 INFO L85 PathProgramCache]: Analyzing trace with hash 787031863, now seen corresponding path program 1 times [2022-07-14 16:02:14,897 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:14,897 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1594818786] [2022-07-14 16:02:14,897 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:14,898 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:14,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:14,948 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:14,948 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:14,948 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1594818786] [2022-07-14 16:02:14,948 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1594818786] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:14,949 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:14,949 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-07-14 16:02:14,949 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [264372638] [2022-07-14 16:02:14,949 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:14,954 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:14,954 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:14,954 INFO L85 PathProgramCache]: Analyzing trace with hash -403985164, now seen corresponding path program 1 times [2022-07-14 16:02:14,954 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:14,954 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [8980651] [2022-07-14 16:02:14,954 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:14,955 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:14,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:14,977 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:14,977 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:14,977 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [8980651] [2022-07-14 16:02:14,977 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [8980651] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:14,978 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:14,978 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:14,978 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2089183557] [2022-07-14 16:02:14,978 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:14,978 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:14,978 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:14,979 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:02:14,979 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:02:14,979 INFO L87 Difference]: Start difference. First operand 1999 states and 3465 transitions. cyclomatic complexity: 1474 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:15,207 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:15,208 INFO L93 Difference]: Finished difference Result 4015 states and 6814 transitions. [2022-07-14 16:02:15,208 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-07-14 16:02:15,210 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4015 states and 6814 transitions. [2022-07-14 16:02:15,267 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 3762 [2022-07-14 16:02:15,281 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4015 states to 4015 states and 6814 transitions. [2022-07-14 16:02:15,281 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4015 [2022-07-14 16:02:15,284 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4015 [2022-07-14 16:02:15,284 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4015 states and 6814 transitions. [2022-07-14 16:02:15,288 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:15,288 INFO L369 hiAutomatonCegarLoop]: Abstraction has 4015 states and 6814 transitions. [2022-07-14 16:02:15,290 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4015 states and 6814 transitions. [2022-07-14 16:02:15,328 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4015 to 3985. [2022-07-14 16:02:15,333 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3985 states, 3985 states have (on average 1.6948557089084064) internal successors, (6754), 3984 states have internal predecessors, (6754), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:15,343 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3985 states to 3985 states and 6754 transitions. [2022-07-14 16:02:15,343 INFO L392 hiAutomatonCegarLoop]: Abstraction has 3985 states and 6754 transitions. [2022-07-14 16:02:15,343 INFO L374 stractBuchiCegarLoop]: Abstraction has 3985 states and 6754 transitions. [2022-07-14 16:02:15,344 INFO L287 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-07-14 16:02:15,344 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3985 states and 6754 transitions. [2022-07-14 16:02:15,358 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 3762 [2022-07-14 16:02:15,358 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:15,359 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:15,360 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:15,361 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:15,361 INFO L752 eck$LassoCheckResult]: Stem: 14698#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 14672#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 14235#L256 assume !(1 == ~main_in1_req_up~0); 14191#L256-2 assume !(1 == ~main_in2_req_up~0); 14193#L267-1 assume !(1 == ~main_sum_req_up~0); 14222#L278-1 assume !(1 == ~main_diff_req_up~0); 14174#L289-1 assume !(1 == ~main_pres_req_up~0); 14175#L300-1 assume !(1 == ~main_dbl_req_up~0); 14449#L311-1 assume !(1 == ~main_zero_req_up~0); 14446#L322-1 assume !(1 == ~main_clk_req_up~0); 14519#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 14405#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 14406#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 15390#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 14658#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 14391#L371-1 assume !(0 == ~main_in1_ev~0); 14392#L376-1 assume !(0 == ~main_in2_ev~0); 14785#L381-1 assume !(0 == ~main_sum_ev~0); 14786#L386-1 assume !(0 == ~main_diff_ev~0); 14645#L391-1 assume !(0 == ~main_pres_ev~0); 14557#L396-1 assume !(0 == ~main_dbl_ev~0); 14336#L401-1 assume !(0 == ~main_zero_ev~0); 14337#L406-1 assume !(0 == ~main_clk_ev~0); 14346#L411-1 assume !(0 == ~main_clk_pos_edge~0); 14655#L416-1 assume !(0 == ~main_clk_neg_edge~0); 14656#L421-1 assume !(1 == ~main_clk_pos_edge~0); 14623#L426-1 assume !(1 == ~main_clk_pos_edge~0); 14378#L431-1 assume !(1 == ~main_clk_pos_edge~0); 14379#L436-1 assume !(1 == ~main_clk_pos_edge~0); 14357#L441-1 assume !(1 == ~main_clk_pos_edge~0); 14358#L446-1 assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 14688#L451-1 assume !(1 == ~main_in2_ev~0); 15332#L456-1 assume !(1 == ~main_sum_ev~0); 15330#L461-1 assume !(1 == ~main_diff_ev~0); 15291#L466-1 assume !(1 == ~main_pres_ev~0); 15283#L471-1 assume !(1 == ~main_dbl_ev~0); 14224#L476-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 14225#L481-1 assume !(1 == ~main_clk_ev~0); 15093#L486-1 assume !(1 == ~main_clk_pos_edge~0); 15092#L491-1 assume !(1 == ~main_clk_neg_edge~0); 15213#L742-1 [2022-07-14 16:02:15,361 INFO L754 eck$LassoCheckResult]: Loop: 15213#L742-1 assume !false; 15212#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 15208#L229 assume !false; 15206#L147 assume !(0 == ~N_generate_st~0); 15202#L151 assume !(0 == ~S1_addsub_st~0); 15203#L154 assume !(0 == ~S2_presdbl_st~0); 15204#L157 assume !(0 == ~S3_zero_st~0); 15205#L160 assume !(0 == ~D_print_st~0); 15207#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 15416#L509 assume !(1 == ~main_in1_req_up~0); 15414#L509-2 assume !(1 == ~main_in2_req_up~0); 15411#L520-1 assume !(1 == ~main_sum_req_up~0); 15407#L531-1 assume !(1 == ~main_diff_req_up~0); 15397#L542-1 assume !(1 == ~main_pres_req_up~0); 15393#L553-1 assume !(1 == ~main_dbl_req_up~0); 15388#L564-1 assume !(1 == ~main_zero_req_up~0); 15382#L575-1 assume !(1 == ~main_clk_req_up~0); 15378#L586-1 start_simulation_~kernel_st~0#1 := 3; 15376#L605 assume !(0 == ~main_in1_ev~0); 15374#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 15371#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 15369#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 15366#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 15362#L625-1 assume !(0 == ~main_dbl_ev~0); 15356#L630-1 assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 15352#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 15350#L640-1 assume !(0 == ~main_clk_pos_edge~0); 15318#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 15344#L650-1 assume !(1 == ~main_clk_pos_edge~0); 15314#L655-1 assume !(1 == ~main_clk_pos_edge~0); 15312#L660-1 assume !(1 == ~main_clk_pos_edge~0); 15309#L665-1 assume !(1 == ~main_clk_pos_edge~0); 15303#L670-1 assume !(1 == ~main_clk_pos_edge~0); 15301#L675-1 assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 15300#L680-1 assume !(1 == ~main_in2_ev~0); 15298#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 15296#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 15295#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 15289#L700-1 assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2; 15282#L705-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 15280#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 15278#L715-1 assume !(1 == ~main_clk_pos_edge~0); 15276#L720-1 assume !(1 == ~main_clk_neg_edge~0); 15219#L725-1 assume 0 == ~N_generate_st~0; 15213#L742-1 [2022-07-14 16:02:15,362 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:15,362 INFO L85 PathProgramCache]: Analyzing trace with hash 615864315, now seen corresponding path program 1 times [2022-07-14 16:02:15,362 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:15,362 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1763098787] [2022-07-14 16:02:15,362 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:15,363 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:15,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:15,392 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:15,393 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:15,393 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1763098787] [2022-07-14 16:02:15,393 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1763098787] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:15,393 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:15,394 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-07-14 16:02:15,394 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [632192942] [2022-07-14 16:02:15,394 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:15,394 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:15,395 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:15,395 INFO L85 PathProgramCache]: Analyzing trace with hash -1415211856, now seen corresponding path program 1 times [2022-07-14 16:02:15,395 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:15,395 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [769835725] [2022-07-14 16:02:15,395 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:15,395 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:15,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:15,408 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:15,408 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:15,408 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [769835725] [2022-07-14 16:02:15,408 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [769835725] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:15,408 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:15,409 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:15,409 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1904801877] [2022-07-14 16:02:15,409 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:15,409 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:15,409 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:15,410 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:02:15,410 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:02:15,410 INFO L87 Difference]: Start difference. First operand 3985 states and 6754 transitions. cyclomatic complexity: 2785 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:15,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:15,608 INFO L93 Difference]: Finished difference Result 4445 states and 7522 transitions. [2022-07-14 16:02:15,609 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:02:15,610 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4445 states and 7522 transitions. [2022-07-14 16:02:15,625 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4162 [2022-07-14 16:02:15,670 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4445 states to 4445 states and 7522 transitions. [2022-07-14 16:02:15,670 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4445 [2022-07-14 16:02:15,673 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4445 [2022-07-14 16:02:15,673 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4445 states and 7522 transitions. [2022-07-14 16:02:15,677 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:15,677 INFO L369 hiAutomatonCegarLoop]: Abstraction has 4445 states and 7522 transitions. [2022-07-14 16:02:15,678 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4445 states and 7522 transitions. [2022-07-14 16:02:15,708 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4445 to 4415. [2022-07-14 16:02:15,713 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4415 states, 4415 states have (on average 1.6901472253680634) internal successors, (7462), 4414 states have internal predecessors, (7462), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:15,721 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4415 states to 4415 states and 7462 transitions. [2022-07-14 16:02:15,721 INFO L392 hiAutomatonCegarLoop]: Abstraction has 4415 states and 7462 transitions. [2022-07-14 16:02:15,721 INFO L374 stractBuchiCegarLoop]: Abstraction has 4415 states and 7462 transitions. [2022-07-14 16:02:15,722 INFO L287 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-07-14 16:02:15,722 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4415 states and 7462 transitions. [2022-07-14 16:02:15,730 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4162 [2022-07-14 16:02:15,730 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:15,730 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:15,731 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:15,731 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:15,731 INFO L752 eck$LassoCheckResult]: Stem: 23123#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 23090#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 22676#L256 assume !(1 == ~main_in1_req_up~0); 22632#L256-2 assume !(1 == ~main_in2_req_up~0); 22634#L267-1 assume !(1 == ~main_sum_req_up~0); 22663#L278-1 assume !(1 == ~main_diff_req_up~0); 22615#L289-1 assume !(1 == ~main_pres_req_up~0); 22616#L300-1 assume !(1 == ~main_dbl_req_up~0); 22723#L311-1 assume !(1 == ~main_zero_req_up~0); 23069#L322-1 assume !(1 == ~main_clk_req_up~0); 23071#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 24690#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 24688#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 24686#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 24684#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 24682#L371-1 assume !(0 == ~main_in1_ev~0); 24680#L376-1 assume !(0 == ~main_in2_ev~0); 24678#L381-1 assume !(0 == ~main_sum_ev~0); 24675#L386-1 assume !(0 == ~main_diff_ev~0); 24673#L391-1 assume !(0 == ~main_pres_ev~0); 24671#L396-1 assume !(0 == ~main_dbl_ev~0); 24669#L401-1 assume !(0 == ~main_zero_ev~0); 24667#L406-1 assume !(0 == ~main_clk_ev~0); 24664#L411-1 assume !(0 == ~main_clk_pos_edge~0); 24662#L416-1 assume !(0 == ~main_clk_neg_edge~0); 24660#L421-1 assume !(1 == ~main_clk_pos_edge~0); 24657#L426-1 assume !(1 == ~main_clk_pos_edge~0); 24655#L431-1 assume !(1 == ~main_clk_pos_edge~0); 24652#L436-1 assume !(1 == ~main_clk_pos_edge~0); 24649#L441-1 assume !(1 == ~main_clk_pos_edge~0); 24646#L446-1 assume !(1 == ~main_in1_ev~0); 24643#L451-1 assume !(1 == ~main_in2_ev~0); 24641#L456-1 assume !(1 == ~main_sum_ev~0); 24569#L461-1 assume !(1 == ~main_diff_ev~0); 24564#L466-1 assume !(1 == ~main_pres_ev~0); 24555#L471-1 assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2; 24556#L476-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 25389#L481-1 assume !(1 == ~main_clk_ev~0); 25387#L486-1 assume !(1 == ~main_clk_pos_edge~0); 25373#L491-1 assume !(1 == ~main_clk_neg_edge~0); 25369#L742-1 [2022-07-14 16:02:15,731 INFO L754 eck$LassoCheckResult]: Loop: 25369#L742-1 assume !false; 25368#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 25364#L229 assume !false; 25362#L147 assume !(0 == ~N_generate_st~0); 25358#L151 assume !(0 == ~S1_addsub_st~0); 25359#L154 assume !(0 == ~S2_presdbl_st~0); 25360#L157 assume !(0 == ~S3_zero_st~0); 25361#L160 assume !(0 == ~D_print_st~0); 25363#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 25459#L509 assume !(1 == ~main_in1_req_up~0); 25457#L509-2 assume !(1 == ~main_in2_req_up~0); 25454#L520-1 assume !(1 == ~main_sum_req_up~0); 25450#L531-1 assume !(1 == ~main_diff_req_up~0); 25448#L542-1 assume !(1 == ~main_pres_req_up~0); 25444#L553-1 assume !(1 == ~main_dbl_req_up~0); 25440#L564-1 assume !(1 == ~main_zero_req_up~0); 25436#L575-1 assume !(1 == ~main_clk_req_up~0); 25433#L586-1 start_simulation_~kernel_st~0#1 := 3; 25431#L605 assume !(0 == ~main_in1_ev~0); 25429#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 25427#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 25425#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 25423#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 25421#L625-1 assume !(0 == ~main_dbl_ev~0); 25418#L630-1 assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 25416#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 25414#L640-1 assume !(0 == ~main_clk_pos_edge~0); 25412#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 25410#L650-1 assume !(1 == ~main_clk_pos_edge~0); 25408#L655-1 assume !(1 == ~main_clk_pos_edge~0); 25406#L660-1 assume !(1 == ~main_clk_pos_edge~0); 25404#L665-1 assume !(1 == ~main_clk_pos_edge~0); 25402#L670-1 assume !(1 == ~main_clk_pos_edge~0); 25400#L675-1 assume !(1 == ~main_in1_ev~0); 25398#L680-1 assume !(1 == ~main_in2_ev~0); 25396#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 25394#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 25392#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 25390#L700-1 assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2; 24274#L705-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 25388#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 25386#L715-1 assume !(1 == ~main_clk_pos_edge~0); 25385#L720-1 assume !(1 == ~main_clk_neg_edge~0); 25376#L725-1 assume 0 == ~N_generate_st~0; 25369#L742-1 [2022-07-14 16:02:15,732 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:15,732 INFO L85 PathProgramCache]: Analyzing trace with hash 220990263, now seen corresponding path program 1 times [2022-07-14 16:02:15,732 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:15,732 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1409576796] [2022-07-14 16:02:15,732 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:15,732 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:15,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:15,754 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:15,754 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:15,754 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1409576796] [2022-07-14 16:02:15,755 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1409576796] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:15,755 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:15,755 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-07-14 16:02:15,755 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [768406359] [2022-07-14 16:02:15,755 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:15,756 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:15,756 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:15,756 INFO L85 PathProgramCache]: Analyzing trace with hash -714147278, now seen corresponding path program 1 times [2022-07-14 16:02:15,756 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:15,756 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2025563945] [2022-07-14 16:02:15,756 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:15,756 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:15,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:15,767 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:15,767 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:15,768 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2025563945] [2022-07-14 16:02:15,768 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2025563945] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:15,768 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:15,768 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:15,768 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [35852052] [2022-07-14 16:02:15,768 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:15,769 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:15,769 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:15,769 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:02:15,769 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:02:15,769 INFO L87 Difference]: Start difference. First operand 4415 states and 7462 transitions. cyclomatic complexity: 3063 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:15,923 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:15,923 INFO L93 Difference]: Finished difference Result 5574 states and 9318 transitions. [2022-07-14 16:02:15,923 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:02:15,924 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5574 states and 9318 transitions. [2022-07-14 16:02:15,939 INFO L131 ngComponentsAnalysis]: Automaton has 18 accepting balls. 5240 [2022-07-14 16:02:15,956 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5574 states to 5574 states and 9318 transitions. [2022-07-14 16:02:15,956 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5574 [2022-07-14 16:02:15,960 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5574 [2022-07-14 16:02:15,960 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5574 states and 9318 transitions. [2022-07-14 16:02:16,010 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:16,010 INFO L369 hiAutomatonCegarLoop]: Abstraction has 5574 states and 9318 transitions. [2022-07-14 16:02:16,012 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5574 states and 9318 transitions. [2022-07-14 16:02:16,055 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5574 to 5130. [2022-07-14 16:02:16,062 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5130 states, 5130 states have (on average 1.6754385964912282) internal successors, (8595), 5129 states have internal predecessors, (8595), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:16,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5130 states to 5130 states and 8595 transitions. [2022-07-14 16:02:16,071 INFO L392 hiAutomatonCegarLoop]: Abstraction has 5130 states and 8595 transitions. [2022-07-14 16:02:16,071 INFO L374 stractBuchiCegarLoop]: Abstraction has 5130 states and 8595 transitions. [2022-07-14 16:02:16,071 INFO L287 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-07-14 16:02:16,071 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5130 states and 8595 transitions. [2022-07-14 16:02:16,080 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4812 [2022-07-14 16:02:16,080 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:16,080 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:16,080 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:16,080 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:16,081 INFO L752 eck$LassoCheckResult]: Stem: 33094#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 33071#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 32676#L256 assume !(1 == ~main_in1_req_up~0); 32632#L256-2 assume !(1 == ~main_in2_req_up~0); 32634#L267-1 assume !(1 == ~main_sum_req_up~0); 32663#L278-1 assume !(1 == ~main_diff_req_up~0); 32615#L289-1 assume !(1 == ~main_pres_req_up~0); 32616#L300-1 assume !(1 == ~main_dbl_req_up~0); 32724#L311-1 assume !(1 == ~main_zero_req_up~0); 33048#L322-1 assume !(1 == ~main_clk_req_up~0); 33050#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 36466#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 36465#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 36464#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 36463#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 36462#L371-1 assume !(0 == ~main_in1_ev~0); 36461#L376-1 assume !(0 == ~main_in2_ev~0); 36460#L381-1 assume !(0 == ~main_sum_ev~0); 36459#L386-1 assume !(0 == ~main_diff_ev~0); 36458#L391-1 assume !(0 == ~main_pres_ev~0); 36397#L396-1 assume !(0 == ~main_dbl_ev~0); 35475#L401-1 assume !(0 == ~main_zero_ev~0); 35472#L406-1 assume !(0 == ~main_clk_ev~0); 35470#L411-1 assume !(0 == ~main_clk_pos_edge~0); 35468#L416-1 assume !(0 == ~main_clk_neg_edge~0); 35467#L421-1 assume !(1 == ~main_clk_pos_edge~0); 35465#L426-1 assume !(1 == ~main_clk_pos_edge~0); 35461#L431-1 assume !(1 == ~main_clk_pos_edge~0); 35457#L436-1 assume !(1 == ~main_clk_pos_edge~0); 35453#L441-1 assume !(1 == ~main_clk_pos_edge~0); 35452#L446-1 assume !(1 == ~main_in1_ev~0); 35451#L451-1 assume !(1 == ~main_in2_ev~0); 35450#L456-1 assume !(1 == ~main_sum_ev~0); 35449#L461-1 assume !(1 == ~main_diff_ev~0); 35448#L466-1 assume !(1 == ~main_pres_ev~0); 35447#L471-1 assume !(1 == ~main_dbl_ev~0); 35446#L476-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 35445#L481-1 assume !(1 == ~main_clk_ev~0); 35444#L486-1 assume !(1 == ~main_clk_pos_edge~0); 35443#L491-1 assume !(1 == ~main_clk_neg_edge~0); 35390#L742-1 [2022-07-14 16:02:16,081 INFO L754 eck$LassoCheckResult]: Loop: 35390#L742-1 assume !false; 35442#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 35438#L229 assume !false; 35437#L147 assume !(0 == ~N_generate_st~0); 35436#L151 assume !(0 == ~S1_addsub_st~0); 35435#L154 assume !(0 == ~S2_presdbl_st~0); 35434#L157 assume !(0 == ~S3_zero_st~0); 35432#L160 assume !(0 == ~D_print_st~0); 35431#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 35430#L509 assume !(1 == ~main_in1_req_up~0); 35429#L509-2 assume !(1 == ~main_in2_req_up~0); 35428#L520-1 assume !(1 == ~main_sum_req_up~0); 35425#L531-1 assume !(1 == ~main_diff_req_up~0); 35424#L542-1 assume !(1 == ~main_pres_req_up~0); 35423#L553-1 assume !(1 == ~main_dbl_req_up~0); 35422#L564-1 assume !(1 == ~main_zero_req_up~0); 35421#L575-1 assume !(1 == ~main_clk_req_up~0); 35420#L586-1 start_simulation_~kernel_st~0#1 := 3; 35419#L605 assume !(0 == ~main_in1_ev~0); 35418#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 35417#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 35416#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 35415#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 35414#L625-1 assume !(0 == ~main_dbl_ev~0); 35413#L630-1 assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 35412#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 35411#L640-1 assume !(0 == ~main_clk_pos_edge~0); 35410#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 35409#L650-1 assume !(1 == ~main_clk_pos_edge~0); 35408#L655-1 assume !(1 == ~main_clk_pos_edge~0); 35407#L660-1 assume !(1 == ~main_clk_pos_edge~0); 35406#L665-1 assume !(1 == ~main_clk_pos_edge~0); 35405#L670-1 assume !(1 == ~main_clk_pos_edge~0); 35404#L675-1 assume !(1 == ~main_in1_ev~0); 35403#L680-1 assume !(1 == ~main_in2_ev~0); 35402#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 35401#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 35400#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 35399#L700-1 assume !(1 == ~main_dbl_ev~0); 35398#L705-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 35397#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 35396#L715-1 assume !(1 == ~main_clk_pos_edge~0); 35395#L720-1 assume !(1 == ~main_clk_neg_edge~0); 35394#L725-1 assume 0 == ~N_generate_st~0; 35390#L742-1 [2022-07-14 16:02:16,081 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:16,081 INFO L85 PathProgramCache]: Analyzing trace with hash 222837305, now seen corresponding path program 1 times [2022-07-14 16:02:16,081 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:16,082 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [314553908] [2022-07-14 16:02:16,082 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:16,082 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:16,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:16,099 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:16,099 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:16,099 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [314553908] [2022-07-14 16:02:16,099 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [314553908] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:16,099 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:16,100 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-07-14 16:02:16,100 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1373937690] [2022-07-14 16:02:16,100 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:16,100 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:16,100 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:16,100 INFO L85 PathProgramCache]: Analyzing trace with hash -656888976, now seen corresponding path program 1 times [2022-07-14 16:02:16,101 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:16,101 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [180576121] [2022-07-14 16:02:16,101 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:16,101 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:16,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:16,111 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:16,111 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:16,111 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [180576121] [2022-07-14 16:02:16,111 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [180576121] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:16,111 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:16,111 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:16,111 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1720055832] [2022-07-14 16:02:16,111 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:16,112 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:16,112 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:16,112 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:02:16,112 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:02:16,112 INFO L87 Difference]: Start difference. First operand 5130 states and 8595 transitions. cyclomatic complexity: 3481 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:16,340 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:16,340 INFO L93 Difference]: Finished difference Result 9446 states and 15503 transitions. [2022-07-14 16:02:16,340 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:02:16,341 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9446 states and 15503 transitions. [2022-07-14 16:02:16,363 INFO L131 ngComponentsAnalysis]: Automaton has 26 accepting balls. 8840 [2022-07-14 16:02:16,384 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9446 states to 9446 states and 15503 transitions. [2022-07-14 16:02:16,384 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9446 [2022-07-14 16:02:16,388 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9446 [2022-07-14 16:02:16,388 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9446 states and 15503 transitions. [2022-07-14 16:02:16,396 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:16,396 INFO L369 hiAutomatonCegarLoop]: Abstraction has 9446 states and 15503 transitions. [2022-07-14 16:02:16,399 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9446 states and 15503 transitions. [2022-07-14 16:02:16,495 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9446 to 6978. [2022-07-14 16:02:16,502 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6978 states, 6978 states have (on average 1.65262252794497) internal successors, (11532), 6977 states have internal predecessors, (11532), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:16,514 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6978 states to 6978 states and 11532 transitions. [2022-07-14 16:02:16,514 INFO L392 hiAutomatonCegarLoop]: Abstraction has 6978 states and 11532 transitions. [2022-07-14 16:02:16,514 INFO L374 stractBuchiCegarLoop]: Abstraction has 6978 states and 11532 transitions. [2022-07-14 16:02:16,514 INFO L287 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-07-14 16:02:16,514 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6978 states and 11532 transitions. [2022-07-14 16:02:16,527 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6492 [2022-07-14 16:02:16,527 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:16,527 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:16,528 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:16,528 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:16,528 INFO L752 eck$LassoCheckResult]: Stem: 47732#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 47702#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 47263#L256 assume !(1 == ~main_in1_req_up~0); 47219#L256-2 assume !(1 == ~main_in2_req_up~0); 47221#L267-1 assume !(1 == ~main_sum_req_up~0); 47250#L278-1 assume !(1 == ~main_diff_req_up~0); 47202#L289-1 assume !(1 == ~main_pres_req_up~0); 47203#L300-1 assume !(1 == ~main_dbl_req_up~0); 47310#L311-1 assume !(1 == ~main_zero_req_up~0); 47678#L322-1 assume !(1 == ~main_clk_req_up~0); 47447#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 47435#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 47239#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 47240#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 47428#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 47962#L371-1 assume !(0 == ~main_in1_ev~0); 47290#L376-1 assume !(0 == ~main_in2_ev~0); 47291#L381-1 assume !(0 == ~main_sum_ev~0); 47960#L386-1 assume !(0 == ~main_diff_ev~0); 47674#L391-1 assume !(0 == ~main_pres_ev~0); 47587#L396-1 assume !(0 == ~main_dbl_ev~0); 47588#L401-1 assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 50722#L406-1 assume !(0 == ~main_clk_ev~0); 50721#L411-1 assume !(0 == ~main_clk_pos_edge~0); 50720#L416-1 assume !(0 == ~main_clk_neg_edge~0); 50719#L421-1 assume !(1 == ~main_clk_pos_edge~0); 50718#L426-1 assume !(1 == ~main_clk_pos_edge~0); 50717#L431-1 assume !(1 == ~main_clk_pos_edge~0); 50716#L436-1 assume !(1 == ~main_clk_pos_edge~0); 50715#L441-1 assume !(1 == ~main_clk_pos_edge~0); 50714#L446-1 assume !(1 == ~main_in1_ev~0); 50713#L451-1 assume !(1 == ~main_in2_ev~0); 50712#L456-1 assume !(1 == ~main_sum_ev~0); 50711#L461-1 assume !(1 == ~main_diff_ev~0); 50710#L466-1 assume !(1 == ~main_pres_ev~0); 50709#L471-1 assume !(1 == ~main_dbl_ev~0); 50707#L476-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 50686#L481-1 assume !(1 == ~main_clk_ev~0); 50679#L486-1 assume !(1 == ~main_clk_pos_edge~0); 50671#L491-1 assume !(1 == ~main_clk_neg_edge~0); 50476#L742-1 [2022-07-14 16:02:16,528 INFO L754 eck$LassoCheckResult]: Loop: 50476#L742-1 assume !false; 50656#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 50651#L229 assume !false; 50649#L147 assume !(0 == ~N_generate_st~0); 50647#L151 assume !(0 == ~S1_addsub_st~0); 50645#L154 assume !(0 == ~S2_presdbl_st~0); 50641#L157 assume !(0 == ~S3_zero_st~0); 50637#L160 assume !(0 == ~D_print_st~0); 50635#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 50633#L509 assume !(1 == ~main_in1_req_up~0); 50628#L509-2 assume !(1 == ~main_in2_req_up~0); 50621#L520-1 assume !(1 == ~main_sum_req_up~0); 50612#L531-1 assume !(1 == ~main_diff_req_up~0); 50604#L542-1 assume !(1 == ~main_pres_req_up~0); 50595#L553-1 assume !(1 == ~main_dbl_req_up~0); 50587#L564-1 assume !(1 == ~main_zero_req_up~0); 50579#L575-1 assume !(1 == ~main_clk_req_up~0); 50574#L586-1 start_simulation_~kernel_st~0#1 := 3; 50570#L605 assume !(0 == ~main_in1_ev~0); 50566#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 50562#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 50558#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 50554#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 50550#L625-1 assume !(0 == ~main_dbl_ev~0); 50529#L630-1 assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 50528#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 50527#L640-1 assume !(0 == ~main_clk_pos_edge~0); 50526#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 50525#L650-1 assume !(1 == ~main_clk_pos_edge~0); 50524#L655-1 assume !(1 == ~main_clk_pos_edge~0); 50523#L660-1 assume !(1 == ~main_clk_pos_edge~0); 50522#L665-1 assume !(1 == ~main_clk_pos_edge~0); 50521#L670-1 assume !(1 == ~main_clk_pos_edge~0); 50520#L675-1 assume !(1 == ~main_in1_ev~0); 50519#L680-1 assume !(1 == ~main_in2_ev~0); 50518#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 50517#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 50516#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 50515#L700-1 assume !(1 == ~main_dbl_ev~0); 50513#L705-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 50511#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 50509#L715-1 assume !(1 == ~main_clk_pos_edge~0); 50507#L720-1 assume !(1 == ~main_clk_neg_edge~0); 50503#L725-1 assume 0 == ~N_generate_st~0; 50476#L742-1 [2022-07-14 16:02:16,529 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:16,529 INFO L85 PathProgramCache]: Analyzing trace with hash 1911781047, now seen corresponding path program 1 times [2022-07-14 16:02:16,529 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:16,529 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1859708549] [2022-07-14 16:02:16,529 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:16,530 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:16,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:16,546 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:16,546 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:16,546 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1859708549] [2022-07-14 16:02:16,547 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1859708549] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:16,547 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:16,547 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-07-14 16:02:16,547 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [51806197] [2022-07-14 16:02:16,547 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:16,547 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:16,548 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:16,548 INFO L85 PathProgramCache]: Analyzing trace with hash -656888976, now seen corresponding path program 2 times [2022-07-14 16:02:16,548 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:16,548 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [260898706] [2022-07-14 16:02:16,548 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:16,548 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:16,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:16,560 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:16,560 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:16,560 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [260898706] [2022-07-14 16:02:16,560 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [260898706] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:16,560 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:16,560 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:16,560 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2092795246] [2022-07-14 16:02:16,561 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:16,561 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:16,561 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:16,561 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:02:16,561 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:02:16,562 INFO L87 Difference]: Start difference. First operand 6978 states and 11532 transitions. cyclomatic complexity: 4570 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:16,675 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:16,676 INFO L93 Difference]: Finished difference Result 12839 states and 21043 transitions. [2022-07-14 16:02:16,676 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-07-14 16:02:16,677 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12839 states and 21043 transitions. [2022-07-14 16:02:16,719 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 12108 [2022-07-14 16:02:16,746 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12839 states to 12839 states and 21043 transitions. [2022-07-14 16:02:16,747 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12839 [2022-07-14 16:02:16,752 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12839 [2022-07-14 16:02:16,753 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12839 states and 21043 transitions. [2022-07-14 16:02:16,816 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:16,816 INFO L369 hiAutomatonCegarLoop]: Abstraction has 12839 states and 21043 transitions. [2022-07-14 16:02:16,835 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12839 states and 21043 transitions. [2022-07-14 16:02:16,918 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12839 to 12839. [2022-07-14 16:02:16,931 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12839 states, 12839 states have (on average 1.6389905755899992) internal successors, (21043), 12838 states have internal predecessors, (21043), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:16,954 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12839 states to 12839 states and 21043 transitions. [2022-07-14 16:02:16,954 INFO L392 hiAutomatonCegarLoop]: Abstraction has 12839 states and 21043 transitions. [2022-07-14 16:02:16,955 INFO L374 stractBuchiCegarLoop]: Abstraction has 12839 states and 21043 transitions. [2022-07-14 16:02:16,955 INFO L287 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-07-14 16:02:16,955 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12839 states and 21043 transitions. [2022-07-14 16:02:16,984 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 12108 [2022-07-14 16:02:16,984 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:16,984 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:16,985 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:16,985 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:16,985 INFO L752 eck$LassoCheckResult]: Stem: 67576#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 67547#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 67091#L256 assume !(1 == ~main_in1_req_up~0); 67047#L256-2 assume !(1 == ~main_in2_req_up~0); 67049#L267-1 assume !(1 == ~main_sum_req_up~0); 67078#L278-1 assume !(1 == ~main_diff_req_up~0); 67029#L289-1 assume !(1 == ~main_pres_req_up~0); 67030#L300-1 assume !(1 == ~main_dbl_req_up~0); 67138#L311-1 assume !(1 == ~main_zero_req_up~0); 67522#L322-1 assume !(1 == ~main_clk_req_up~0); 67524#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 70263#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 70257#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 70256#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 70255#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 70254#L371-1 assume !(0 == ~main_in1_ev~0); 70253#L376-1 assume !(0 == ~main_in2_ev~0); 70252#L381-1 assume !(0 == ~main_sum_ev~0); 70251#L386-1 assume !(0 == ~main_diff_ev~0); 70250#L391-1 assume !(0 == ~main_pres_ev~0); 70249#L396-1 assume !(0 == ~main_dbl_ev~0); 70248#L401-1 assume !(0 == ~main_zero_ev~0); 70247#L406-1 assume !(0 == ~main_clk_ev~0); 70246#L411-1 assume !(0 == ~main_clk_pos_edge~0); 70243#L416-1 assume !(0 == ~main_clk_neg_edge~0); 70240#L421-1 assume !(1 == ~main_clk_pos_edge~0); 70238#L426-1 assume !(1 == ~main_clk_pos_edge~0); 70236#L431-1 assume !(1 == ~main_clk_pos_edge~0); 70234#L436-1 assume !(1 == ~main_clk_pos_edge~0); 70232#L441-1 assume !(1 == ~main_clk_pos_edge~0); 70230#L446-1 assume !(1 == ~main_in1_ev~0); 70228#L451-1 assume !(1 == ~main_in2_ev~0); 70226#L456-1 assume !(1 == ~main_sum_ev~0); 70224#L461-1 assume !(1 == ~main_diff_ev~0); 70222#L466-1 assume !(1 == ~main_pres_ev~0); 70220#L471-1 assume !(1 == ~main_dbl_ev~0); 70217#L476-1 assume !(1 == ~main_zero_ev~0); 70215#L481-1 assume !(1 == ~main_clk_ev~0); 70212#L486-1 assume !(1 == ~main_clk_pos_edge~0); 70170#L491-1 assume !(1 == ~main_clk_neg_edge~0); 70166#L742-1 [2022-07-14 16:02:16,985 INFO L754 eck$LassoCheckResult]: Loop: 70166#L742-1 assume !false; 70165#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 70161#L229 assume !false; 70159#L147 assume !(0 == ~N_generate_st~0); 70155#L151 assume !(0 == ~S1_addsub_st~0); 70156#L154 assume !(0 == ~S2_presdbl_st~0); 70157#L157 assume !(0 == ~S3_zero_st~0); 70158#L160 assume !(0 == ~D_print_st~0); 70160#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 70541#L509 assume !(1 == ~main_in1_req_up~0); 70538#L509-2 assume !(1 == ~main_in2_req_up~0); 70534#L520-1 assume !(1 == ~main_sum_req_up~0); 70522#L531-1 assume !(1 == ~main_diff_req_up~0); 70510#L542-1 assume !(1 == ~main_pres_req_up~0); 70506#L553-1 assume !(1 == ~main_dbl_req_up~0); 70502#L564-1 assume !(1 == ~main_zero_req_up~0); 70498#L575-1 assume !(1 == ~main_clk_req_up~0); 70494#L586-1 start_simulation_~kernel_st~0#1 := 3; 70493#L605 assume !(0 == ~main_in1_ev~0); 70491#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 70489#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 70487#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 70485#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 70483#L625-1 assume !(0 == ~main_dbl_ev~0); 70481#L630-1 assume !(0 == ~main_zero_ev~0); 70375#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 70339#L640-1 assume !(0 == ~main_clk_pos_edge~0); 70338#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 70337#L650-1 assume !(1 == ~main_clk_pos_edge~0); 70336#L655-1 assume !(1 == ~main_clk_pos_edge~0); 70335#L660-1 assume !(1 == ~main_clk_pos_edge~0); 70334#L665-1 assume !(1 == ~main_clk_pos_edge~0); 70333#L670-1 assume !(1 == ~main_clk_pos_edge~0); 70332#L675-1 assume !(1 == ~main_in1_ev~0); 70331#L680-1 assume !(1 == ~main_in2_ev~0); 70330#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 70329#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 70328#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 70327#L700-1 assume !(1 == ~main_dbl_ev~0); 70326#L705-1 assume !(1 == ~main_zero_ev~0); 70324#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 70320#L715-1 assume !(1 == ~main_clk_pos_edge~0); 70316#L720-1 assume !(1 == ~main_clk_neg_edge~0); 70173#L725-1 assume 0 == ~N_generate_st~0; 70166#L742-1 [2022-07-14 16:02:16,986 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:16,986 INFO L85 PathProgramCache]: Analyzing trace with hash 222896887, now seen corresponding path program 1 times [2022-07-14 16:02:16,986 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:16,986 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [488949420] [2022-07-14 16:02:16,986 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:16,987 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:16,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:16,992 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:02:17,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:17,128 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:02:17,129 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:17,130 INFO L85 PathProgramCache]: Analyzing trace with hash -1472690384, now seen corresponding path program 1 times [2022-07-14 16:02:17,130 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:17,131 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [262195116] [2022-07-14 16:02:17,131 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:17,131 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:17,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:17,159 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:17,159 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:17,159 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [262195116] [2022-07-14 16:02:17,160 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [262195116] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:17,160 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:17,160 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:17,160 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [362189335] [2022-07-14 16:02:17,160 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:17,160 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:17,160 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:17,160 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:02:17,161 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:02:17,161 INFO L87 Difference]: Start difference. First operand 12839 states and 21043 transitions. cyclomatic complexity: 8236 Second operand has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:17,291 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:17,291 INFO L93 Difference]: Finished difference Result 18429 states and 29722 transitions. [2022-07-14 16:02:17,291 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:02:17,292 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18429 states and 29722 transitions. [2022-07-14 16:02:17,417 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 17278 [2022-07-14 16:02:17,539 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18429 states to 18429 states and 29722 transitions. [2022-07-14 16:02:17,539 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18429 [2022-07-14 16:02:17,553 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18429 [2022-07-14 16:02:17,553 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18429 states and 29722 transitions. [2022-07-14 16:02:17,668 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:17,669 INFO L369 hiAutomatonCegarLoop]: Abstraction has 18429 states and 29722 transitions. [2022-07-14 16:02:17,677 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18429 states and 29722 transitions. [2022-07-14 16:02:17,975 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18429 to 18429. [2022-07-14 16:02:17,992 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18429 states, 18429 states have (on average 1.6127841988170817) internal successors, (29722), 18428 states have internal predecessors, (29722), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:18,026 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18429 states to 18429 states and 29722 transitions. [2022-07-14 16:02:18,026 INFO L392 hiAutomatonCegarLoop]: Abstraction has 18429 states and 29722 transitions. [2022-07-14 16:02:18,027 INFO L374 stractBuchiCegarLoop]: Abstraction has 18429 states and 29722 transitions. [2022-07-14 16:02:18,027 INFO L287 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-07-14 16:02:18,027 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18429 states and 29722 transitions. [2022-07-14 16:02:18,072 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 17278 [2022-07-14 16:02:18,072 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:18,072 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:18,073 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:18,073 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:18,073 INFO L752 eck$LassoCheckResult]: Stem: 98859#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 98826#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 98367#L256 assume !(1 == ~main_in1_req_up~0); 98321#L256-2 assume !(1 == ~main_in2_req_up~0); 98323#L267-1 assume !(1 == ~main_sum_req_up~0); 98353#L278-1 assume !(1 == ~main_diff_req_up~0); 98303#L289-1 assume !(1 == ~main_pres_req_up~0); 98304#L300-1 assume !(1 == ~main_dbl_req_up~0); 98415#L311-1 assume !(1 == ~main_zero_req_up~0); 98794#L322-1 assume !(1 == ~main_clk_req_up~0); 98557#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 99445#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 98342#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 98343#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 98538#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 99442#L371-1 assume !(0 == ~main_in1_ev~0); 98394#L376-1 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 98395#L381-1 assume !(0 == ~main_sum_ev~0); 98560#L386-1 assume !(0 == ~main_diff_ev~0); 98561#L391-1 assume !(0 == ~main_pres_ev~0); 98711#L396-1 assume !(0 == ~main_dbl_ev~0); 98472#L401-1 assume !(0 == ~main_zero_ev~0); 98473#L406-1 assume !(0 == ~main_clk_ev~0); 107850#L411-1 assume !(0 == ~main_clk_pos_edge~0); 107848#L416-1 assume !(0 == ~main_clk_neg_edge~0); 107844#L421-1 assume !(1 == ~main_clk_pos_edge~0); 107840#L426-1 assume !(1 == ~main_clk_pos_edge~0); 107837#L431-1 assume !(1 == ~main_clk_pos_edge~0); 107833#L436-1 assume !(1 == ~main_clk_pos_edge~0); 107796#L441-1 assume !(1 == ~main_clk_pos_edge~0); 107215#L446-1 assume !(1 == ~main_in1_ev~0); 101140#L451-1 assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2; 101132#L456-1 assume !(1 == ~main_sum_ev~0); 101032#L461-1 assume !(1 == ~main_diff_ev~0); 101029#L466-1 assume !(1 == ~main_pres_ev~0); 101027#L471-1 assume !(1 == ~main_dbl_ev~0); 101025#L476-1 assume !(1 == ~main_zero_ev~0); 101017#L481-1 assume !(1 == ~main_clk_ev~0); 100729#L486-1 assume !(1 == ~main_clk_pos_edge~0); 100724#L491-1 assume !(1 == ~main_clk_neg_edge~0); 100439#L742-1 [2022-07-14 16:02:18,073 INFO L754 eck$LassoCheckResult]: Loop: 100439#L742-1 assume !false; 102441#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 102437#L229 assume !false; 102435#L147 assume !(0 == ~N_generate_st~0); 100706#L151 assume !(0 == ~S1_addsub_st~0); 100705#L154 assume !(0 == ~S2_presdbl_st~0); 100704#L157 assume !(0 == ~S3_zero_st~0); 100702#L160 assume !(0 == ~D_print_st~0); 100700#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 100697#L509 assume !(1 == ~main_in1_req_up~0); 100693#L509-2 assume !(1 == ~main_in2_req_up~0); 100688#L520-1 assume !(1 == ~main_sum_req_up~0); 100679#L531-1 assume !(1 == ~main_diff_req_up~0); 100675#L542-1 assume !(1 == ~main_pres_req_up~0); 100674#L553-1 assume !(1 == ~main_dbl_req_up~0); 102207#L564-1 assume !(1 == ~main_zero_req_up~0); 100506#L575-1 assume !(1 == ~main_clk_req_up~0); 100507#L586-1 start_simulation_~kernel_st~0#1 := 3; 100817#L605 assume !(0 == ~main_in1_ev~0); 100814#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 100812#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 100811#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 100810#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 100809#L625-1 assume !(0 == ~main_dbl_ev~0); 100804#L630-1 assume !(0 == ~main_zero_ev~0); 100802#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 100800#L640-1 assume !(0 == ~main_clk_pos_edge~0); 100798#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 100796#L650-1 assume !(1 == ~main_clk_pos_edge~0); 100794#L655-1 assume !(1 == ~main_clk_pos_edge~0); 100792#L660-1 assume !(1 == ~main_clk_pos_edge~0); 100790#L665-1 assume !(1 == ~main_clk_pos_edge~0); 100787#L670-1 assume !(1 == ~main_clk_pos_edge~0); 100786#L675-1 assume !(1 == ~main_in1_ev~0); 100785#L680-1 assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2; 100783#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 100780#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 100778#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 100776#L700-1 assume !(1 == ~main_dbl_ev~0); 100773#L705-1 assume !(1 == ~main_zero_ev~0); 100770#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 100449#L715-1 assume !(1 == ~main_clk_pos_edge~0); 100446#L720-1 assume !(1 == ~main_clk_neg_edge~0); 100445#L725-1 assume 0 == ~N_generate_st~0; 100439#L742-1 [2022-07-14 16:02:18,074 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:18,074 INFO L85 PathProgramCache]: Analyzing trace with hash -323147977, now seen corresponding path program 1 times [2022-07-14 16:02:18,074 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:18,074 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [540712087] [2022-07-14 16:02:18,074 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:18,075 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:18,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:18,092 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:18,093 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:18,093 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [540712087] [2022-07-14 16:02:18,093 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [540712087] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:18,093 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:18,093 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-07-14 16:02:18,093 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1938361941] [2022-07-14 16:02:18,093 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:18,094 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:18,094 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:18,094 INFO L85 PathProgramCache]: Analyzing trace with hash -1079663374, now seen corresponding path program 1 times [2022-07-14 16:02:18,094 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:18,094 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1157995441] [2022-07-14 16:02:18,094 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:18,095 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:18,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:18,106 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:18,106 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:18,106 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1157995441] [2022-07-14 16:02:18,106 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1157995441] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:18,107 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:18,107 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:18,107 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2118446495] [2022-07-14 16:02:18,107 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:18,107 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:18,107 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:18,108 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:02:18,108 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:02:18,108 INFO L87 Difference]: Start difference. First operand 18429 states and 29722 transitions. cyclomatic complexity: 11325 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:18,336 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:18,336 INFO L93 Difference]: Finished difference Result 33519 states and 53550 transitions. [2022-07-14 16:02:18,350 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-07-14 16:02:18,351 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 33519 states and 53550 transitions. [2022-07-14 16:02:18,586 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 31728 [2022-07-14 16:02:18,685 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 33519 states to 33519 states and 53550 transitions. [2022-07-14 16:02:18,685 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 33519 [2022-07-14 16:02:18,708 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 33519 [2022-07-14 16:02:18,708 INFO L73 IsDeterministic]: Start isDeterministic. Operand 33519 states and 53550 transitions. [2022-07-14 16:02:18,731 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:18,732 INFO L369 hiAutomatonCegarLoop]: Abstraction has 33519 states and 53550 transitions. [2022-07-14 16:02:18,747 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33519 states and 53550 transitions. [2022-07-14 16:02:19,025 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33519 to 33519. [2022-07-14 16:02:19,057 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 33519 states, 33519 states have (on average 1.597601360422447) internal successors, (53550), 33518 states have internal predecessors, (53550), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:19,146 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33519 states to 33519 states and 53550 transitions. [2022-07-14 16:02:19,163 INFO L392 hiAutomatonCegarLoop]: Abstraction has 33519 states and 53550 transitions. [2022-07-14 16:02:19,163 INFO L374 stractBuchiCegarLoop]: Abstraction has 33519 states and 53550 transitions. [2022-07-14 16:02:19,163 INFO L287 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-07-14 16:02:19,164 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 33519 states and 53550 transitions. [2022-07-14 16:02:19,241 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 31728 [2022-07-14 16:02:19,242 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:19,242 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:19,242 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:19,243 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:19,243 INFO L752 eck$LassoCheckResult]: Stem: 150847#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 150803#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 150324#L256 assume !(1 == ~main_in1_req_up~0); 150280#L256-2 assume !(1 == ~main_in2_req_up~0); 150282#L267-1 assume !(1 == ~main_sum_req_up~0); 150311#L278-1 assume !(1 == ~main_diff_req_up~0); 150261#L289-1 assume !(1 == ~main_pres_req_up~0); 150262#L300-1 assume !(1 == ~main_dbl_req_up~0); 150376#L311-1 assume !(1 == ~main_zero_req_up~0); 150771#L322-1 assume !(1 == ~main_clk_req_up~0); 150517#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 154238#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 155631#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 155630#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 155629#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 155628#L371-1 assume !(0 == ~main_in1_ev~0); 155627#L376-1 assume !(0 == ~main_in2_ev~0); 155626#L381-1 assume !(0 == ~main_sum_ev~0); 155625#L386-1 assume !(0 == ~main_diff_ev~0); 155624#L391-1 assume !(0 == ~main_pres_ev~0); 155623#L396-1 assume !(0 == ~main_dbl_ev~0); 155622#L401-1 assume !(0 == ~main_zero_ev~0); 155621#L406-1 assume !(0 == ~main_clk_ev~0); 155620#L411-1 assume !(0 == ~main_clk_pos_edge~0); 155619#L416-1 assume !(0 == ~main_clk_neg_edge~0); 155618#L421-1 assume !(1 == ~main_clk_pos_edge~0); 155617#L426-1 assume !(1 == ~main_clk_pos_edge~0); 155616#L431-1 assume !(1 == ~main_clk_pos_edge~0); 155615#L436-1 assume !(1 == ~main_clk_pos_edge~0); 155614#L441-1 assume !(1 == ~main_clk_pos_edge~0); 155613#L446-1 assume !(1 == ~main_in1_ev~0); 155611#L451-1 assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2; 155612#L456-1 assume !(1 == ~main_sum_ev~0); 163148#L461-1 assume !(1 == ~main_diff_ev~0); 163147#L466-1 assume !(1 == ~main_pres_ev~0); 163146#L471-1 assume !(1 == ~main_dbl_ev~0); 162653#L476-1 assume !(1 == ~main_zero_ev~0); 162651#L481-1 assume !(1 == ~main_clk_ev~0); 162647#L486-1 assume !(1 == ~main_clk_pos_edge~0); 162643#L491-1 assume !(1 == ~main_clk_neg_edge~0); 156633#L742-1 [2022-07-14 16:02:19,243 INFO L754 eck$LassoCheckResult]: Loop: 156633#L742-1 assume !false; 162639#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 162635#L229 assume !false; 162632#L147 assume !(0 == ~N_generate_st~0); 162631#L151 assume !(0 == ~S1_addsub_st~0); 162630#L154 assume !(0 == ~S2_presdbl_st~0); 162626#L157 assume !(0 == ~S3_zero_st~0); 162621#L160 assume !(0 == ~D_print_st~0); 162617#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 162613#L509 assume !(1 == ~main_in1_req_up~0); 162609#L509-2 assume !(1 == ~main_in2_req_up~0); 162610#L520-1 assume !(1 == ~main_sum_req_up~0); 162627#L531-1 assume !(1 == ~main_diff_req_up~0); 162624#L542-1 assume !(1 == ~main_pres_req_up~0); 162619#L553-1 assume !(1 == ~main_dbl_req_up~0); 162615#L564-1 assume !(1 == ~main_zero_req_up~0); 162611#L575-1 assume !(1 == ~main_clk_req_up~0); 162612#L586-1 start_simulation_~kernel_st~0#1 := 3; 168713#L605 assume !(0 == ~main_in1_ev~0); 168712#L605-2 assume !(0 == ~main_in2_ev~0); 162448#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 168711#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 168710#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 168704#L625-1 assume !(0 == ~main_dbl_ev~0); 168703#L630-1 assume !(0 == ~main_zero_ev~0); 168682#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 168681#L640-1 assume !(0 == ~main_clk_pos_edge~0); 168678#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 168677#L650-1 assume !(1 == ~main_clk_pos_edge~0); 168675#L655-1 assume !(1 == ~main_clk_pos_edge~0); 166943#L660-1 assume !(1 == ~main_clk_pos_edge~0); 166940#L665-1 assume !(1 == ~main_clk_pos_edge~0); 166937#L670-1 assume !(1 == ~main_clk_pos_edge~0); 166934#L675-1 assume !(1 == ~main_in1_ev~0); 156664#L680-1 assume !(1 == ~main_in2_ev~0); 154198#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 156662#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 156658#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 156654#L700-1 assume !(1 == ~main_dbl_ev~0); 156652#L705-1 assume !(1 == ~main_zero_ev~0); 156650#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 156647#L715-1 assume !(1 == ~main_clk_pos_edge~0); 156643#L720-1 assume !(1 == ~main_clk_neg_edge~0); 156641#L725-1 assume 0 == ~N_generate_st~0; 156633#L742-1 [2022-07-14 16:02:19,243 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:19,243 INFO L85 PathProgramCache]: Analyzing trace with hash -457161483, now seen corresponding path program 1 times [2022-07-14 16:02:19,244 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:19,244 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2138962255] [2022-07-14 16:02:19,244 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:19,244 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:19,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:19,267 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:19,267 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:19,267 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2138962255] [2022-07-14 16:02:19,267 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2138962255] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:19,267 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:19,267 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-07-14 16:02:19,268 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [729963300] [2022-07-14 16:02:19,268 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:19,268 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:19,268 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:19,268 INFO L85 PathProgramCache]: Analyzing trace with hash -1332141774, now seen corresponding path program 1 times [2022-07-14 16:02:19,268 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:19,269 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1341042109] [2022-07-14 16:02:19,269 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:19,269 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:19,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:19,279 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:19,279 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:19,280 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1341042109] [2022-07-14 16:02:19,280 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1341042109] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:19,280 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:19,280 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:19,280 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1419594957] [2022-07-14 16:02:19,280 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:19,280 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:19,281 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:19,281 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:02:19,281 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:02:19,281 INFO L87 Difference]: Start difference. First operand 33519 states and 53550 transitions. cyclomatic complexity: 20095 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:19,663 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:19,663 INFO L93 Difference]: Finished difference Result 34717 states and 54842 transitions. [2022-07-14 16:02:19,663 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:02:19,664 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34717 states and 54842 transitions. [2022-07-14 16:02:19,777 INFO L131 ngComponentsAnalysis]: Automaton has 66 accepting balls. 32815 [2022-07-14 16:02:19,988 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34717 states to 34717 states and 54842 transitions. [2022-07-14 16:02:20,003 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 34717 [2022-07-14 16:02:20,042 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 34717 [2022-07-14 16:02:20,042 INFO L73 IsDeterministic]: Start isDeterministic. Operand 34717 states and 54842 transitions. [2022-07-14 16:02:20,086 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:20,097 INFO L369 hiAutomatonCegarLoop]: Abstraction has 34717 states and 54842 transitions. [2022-07-14 16:02:20,130 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34717 states and 54842 transitions. [2022-07-14 16:02:20,721 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34717 to 33519. [2022-07-14 16:02:20,750 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 33519 states, 33519 states have (on average 1.5798800680211222) internal successors, (52956), 33518 states have internal predecessors, (52956), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:20,803 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33519 states to 33519 states and 52956 transitions. [2022-07-14 16:02:20,804 INFO L392 hiAutomatonCegarLoop]: Abstraction has 33519 states and 52956 transitions. [2022-07-14 16:02:20,804 INFO L374 stractBuchiCegarLoop]: Abstraction has 33519 states and 52956 transitions. [2022-07-14 16:02:20,804 INFO L287 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-07-14 16:02:20,804 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 33519 states and 52956 transitions. [2022-07-14 16:02:20,882 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 31728 [2022-07-14 16:02:20,882 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:20,882 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:20,883 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:20,883 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:20,883 INFO L752 eck$LassoCheckResult]: Stem: 219031#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 219003#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 218571#L256 assume !(1 == ~main_in1_req_up~0); 218527#L256-2 assume !(1 == ~main_in2_req_up~0); 218529#L267-1 assume !(1 == ~main_sum_req_up~0); 218558#L278-1 assume !(1 == ~main_diff_req_up~0); 218508#L289-1 assume !(1 == ~main_pres_req_up~0); 218509#L300-1 assume !(1 == ~main_dbl_req_up~0); 218622#L311-1 assume !(1 == ~main_zero_req_up~0); 218981#L322-1 assume !(1 == ~main_clk_req_up~0); 218983#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 223895#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 223893#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 223891#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 223889#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 223887#L371-1 assume !(0 == ~main_in1_ev~0); 223885#L376-1 assume !(0 == ~main_in2_ev~0); 223883#L381-1 assume !(0 == ~main_sum_ev~0); 223881#L386-1 assume !(0 == ~main_diff_ev~0); 223879#L391-1 assume !(0 == ~main_pres_ev~0); 223877#L396-1 assume !(0 == ~main_dbl_ev~0); 223875#L401-1 assume !(0 == ~main_zero_ev~0); 223873#L406-1 assume !(0 == ~main_clk_ev~0); 223871#L411-1 assume !(0 == ~main_clk_pos_edge~0); 223869#L416-1 assume !(0 == ~main_clk_neg_edge~0); 223867#L421-1 assume !(1 == ~main_clk_pos_edge~0); 223865#L426-1 assume !(1 == ~main_clk_pos_edge~0); 223863#L431-1 assume !(1 == ~main_clk_pos_edge~0); 223861#L436-1 assume !(1 == ~main_clk_pos_edge~0); 223859#L441-1 assume !(1 == ~main_clk_pos_edge~0); 223857#L446-1 assume !(1 == ~main_in1_ev~0); 223845#L451-1 assume !(1 == ~main_in2_ev~0); 223839#L456-1 assume !(1 == ~main_sum_ev~0); 223833#L461-1 assume !(1 == ~main_diff_ev~0); 223830#L466-1 assume !(1 == ~main_pres_ev~0); 223827#L471-1 assume !(1 == ~main_dbl_ev~0); 223824#L476-1 assume !(1 == ~main_zero_ev~0); 223819#L481-1 assume !(1 == ~main_clk_ev~0); 223818#L486-1 assume !(1 == ~main_clk_pos_edge~0); 223804#L491-1 assume !(1 == ~main_clk_neg_edge~0); 223799#L742-1 [2022-07-14 16:02:20,883 INFO L754 eck$LassoCheckResult]: Loop: 223799#L742-1 assume !false; 223792#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 223785#L229 assume !false; 223784#L147 assume !(0 == ~N_generate_st~0); 223778#L151 assume !(0 == ~S1_addsub_st~0); 223772#L154 assume !(0 == ~S2_presdbl_st~0); 223765#L157 assume !(0 == ~S3_zero_st~0); 223755#L160 assume !(0 == ~D_print_st~0); 223750#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 223746#L509 assume !(1 == ~main_in1_req_up~0); 223740#L509-2 assume !(1 == ~main_in2_req_up~0); 223741#L520-1 assume !(1 == ~main_sum_req_up~0); 223974#L531-1 assume !(1 == ~main_diff_req_up~0); 223970#L542-1 assume !(1 == ~main_pres_req_up~0); 223947#L553-1 assume !(1 == ~main_dbl_req_up~0); 223900#L564-1 assume !(1 == ~main_zero_req_up~0); 223897#L575-1 assume !(1 == ~main_clk_req_up~0); 223894#L586-1 start_simulation_~kernel_st~0#1 := 3; 223892#L605 assume !(0 == ~main_in1_ev~0); 223890#L605-2 assume !(0 == ~main_in2_ev~0); 223888#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 223886#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 223884#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 223882#L625-1 assume !(0 == ~main_dbl_ev~0); 223880#L630-1 assume !(0 == ~main_zero_ev~0); 223878#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 223876#L640-1 assume !(0 == ~main_clk_pos_edge~0); 223874#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 223872#L650-1 assume !(1 == ~main_clk_pos_edge~0); 223870#L655-1 assume !(1 == ~main_clk_pos_edge~0); 223868#L660-1 assume !(1 == ~main_clk_pos_edge~0); 223866#L665-1 assume !(1 == ~main_clk_pos_edge~0); 223864#L670-1 assume !(1 == ~main_clk_pos_edge~0); 223862#L675-1 assume !(1 == ~main_in1_ev~0); 223860#L680-1 assume !(1 == ~main_in2_ev~0); 223858#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 223846#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 223840#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 223834#L700-1 assume !(1 == ~main_dbl_ev~0); 223831#L705-1 assume !(1 == ~main_zero_ev~0); 223828#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 223825#L715-1 assume !(1 == ~main_clk_pos_edge~0); 223820#L720-1 assume !(1 == ~main_clk_neg_edge~0); 223807#L725-1 assume 0 == ~N_generate_st~0; 223799#L742-1 [2022-07-14 16:02:20,883 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:20,883 INFO L85 PathProgramCache]: Analyzing trace with hash 222896887, now seen corresponding path program 2 times [2022-07-14 16:02:20,884 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:20,884 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2000981845] [2022-07-14 16:02:20,884 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:20,884 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:20,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:20,890 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:02:20,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:20,899 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:02:20,900 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:20,900 INFO L85 PathProgramCache]: Analyzing trace with hash -1332141774, now seen corresponding path program 2 times [2022-07-14 16:02:20,900 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:20,900 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [793808826] [2022-07-14 16:02:20,900 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:20,900 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:20,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:20,909 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:20,910 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:20,910 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [793808826] [2022-07-14 16:02:20,910 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [793808826] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:20,910 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:20,910 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:20,910 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1503287150] [2022-07-14 16:02:20,910 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:20,911 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:20,911 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:20,911 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:02:20,911 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:02:20,911 INFO L87 Difference]: Start difference. First operand 33519 states and 52956 transitions. cyclomatic complexity: 19501 Second operand has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:21,181 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:21,181 INFO L93 Difference]: Finished difference Result 44288 states and 68290 transitions. [2022-07-14 16:02:21,182 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:02:21,182 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 44288 states and 68290 transitions. [2022-07-14 16:02:21,529 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 41518 [2022-07-14 16:02:21,628 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 44288 states to 44288 states and 68290 transitions. [2022-07-14 16:02:21,628 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 44288 [2022-07-14 16:02:21,654 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 44288 [2022-07-14 16:02:21,654 INFO L73 IsDeterministic]: Start isDeterministic. Operand 44288 states and 68290 transitions. [2022-07-14 16:02:21,679 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:21,679 INFO L369 hiAutomatonCegarLoop]: Abstraction has 44288 states and 68290 transitions. [2022-07-14 16:02:21,699 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44288 states and 68290 transitions. [2022-07-14 16:02:22,265 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44288 to 44288. [2022-07-14 16:02:22,308 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44288 states, 44288 states have (on average 1.5419526734104045) internal successors, (68290), 44287 states have internal predecessors, (68290), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:22,376 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44288 states to 44288 states and 68290 transitions. [2022-07-14 16:02:22,376 INFO L392 hiAutomatonCegarLoop]: Abstraction has 44288 states and 68290 transitions. [2022-07-14 16:02:22,376 INFO L374 stractBuchiCegarLoop]: Abstraction has 44288 states and 68290 transitions. [2022-07-14 16:02:22,376 INFO L287 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-07-14 16:02:22,376 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44288 states and 68290 transitions. [2022-07-14 16:02:22,498 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 41518 [2022-07-14 16:02:22,499 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:22,499 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:22,499 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:22,500 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:22,500 INFO L752 eck$LassoCheckResult]: Stem: 296891#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 296845#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 296385#L256 assume !(1 == ~main_in1_req_up~0); 296340#L256-2 assume !(1 == ~main_in2_req_up~0); 296342#L267-1 assume !(1 == ~main_sum_req_up~0); 296372#L278-1 assume !(1 == ~main_diff_req_up~0); 296321#L289-1 assume !(1 == ~main_pres_req_up~0); 296322#L300-1 assume !(1 == ~main_dbl_req_up~0); 300482#L311-1 assume !(1 == ~main_zero_req_up~0); 300479#L322-1 assume !(1 == ~main_clk_req_up~0); 300480#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 304645#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 304644#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 304643#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 304642#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 304641#L371-1 assume !(0 == ~main_in1_ev~0); 304640#L376-1 assume !(0 == ~main_in2_ev~0); 304639#L381-1 assume !(0 == ~main_sum_ev~0); 304638#L386-1 assume !(0 == ~main_diff_ev~0); 304637#L391-1 assume !(0 == ~main_pres_ev~0); 304636#L396-1 assume !(0 == ~main_dbl_ev~0); 304635#L401-1 assume !(0 == ~main_zero_ev~0); 304634#L406-1 assume !(0 == ~main_clk_ev~0); 304633#L411-1 assume !(0 == ~main_clk_pos_edge~0); 304631#L416-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 304630#L421-1 assume !(1 == ~main_clk_pos_edge~0); 304629#L426-1 assume !(1 == ~main_clk_pos_edge~0); 304628#L431-1 assume !(1 == ~main_clk_pos_edge~0); 304627#L436-1 assume !(1 == ~main_clk_pos_edge~0); 304626#L441-1 assume !(1 == ~main_clk_pos_edge~0); 304625#L446-1 assume !(1 == ~main_in1_ev~0); 304624#L451-1 assume !(1 == ~main_in2_ev~0); 304623#L456-1 assume !(1 == ~main_sum_ev~0); 304622#L461-1 assume !(1 == ~main_diff_ev~0); 304621#L466-1 assume !(1 == ~main_pres_ev~0); 304620#L471-1 assume !(1 == ~main_dbl_ev~0); 304619#L476-1 assume !(1 == ~main_zero_ev~0); 304618#L481-1 assume !(1 == ~main_clk_ev~0); 304617#L486-1 assume !(1 == ~main_clk_pos_edge~0); 304546#L491-1 assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2; 304544#L742-1 [2022-07-14 16:02:22,500 INFO L754 eck$LassoCheckResult]: Loop: 304544#L742-1 assume !false; 304543#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 304539#L229 assume !false; 304538#L147 assume !(0 == ~N_generate_st~0); 304537#L151 assume !(0 == ~S1_addsub_st~0); 304536#L154 assume !(0 == ~S2_presdbl_st~0); 304535#L157 assume !(0 == ~S3_zero_st~0); 304533#L160 assume !(0 == ~D_print_st~0); 304532#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 304531#L509 assume !(1 == ~main_in1_req_up~0); 304529#L509-2 assume !(1 == ~main_in2_req_up~0); 304530#L520-1 assume !(1 == ~main_sum_req_up~0); 304592#L531-1 assume !(1 == ~main_diff_req_up~0); 300234#L542-1 assume !(1 == ~main_pres_req_up~0); 300233#L553-1 assume !(1 == ~main_dbl_req_up~0); 304584#L564-1 assume !(1 == ~main_zero_req_up~0); 304581#L575-1 assume !(1 == ~main_clk_req_up~0); 304579#L586-1 start_simulation_~kernel_st~0#1 := 3; 304578#L605 assume !(0 == ~main_in1_ev~0); 304577#L605-2 assume !(0 == ~main_in2_ev~0); 304576#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 304575#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 304574#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 304573#L625-1 assume !(0 == ~main_dbl_ev~0); 304572#L630-1 assume !(0 == ~main_zero_ev~0); 304571#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 304570#L640-1 assume !(0 == ~main_clk_pos_edge~0); 304568#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 304567#L650-1 assume !(1 == ~main_clk_pos_edge~0); 304566#L655-1 assume !(1 == ~main_clk_pos_edge~0); 304565#L660-1 assume !(1 == ~main_clk_pos_edge~0); 304564#L665-1 assume !(1 == ~main_clk_pos_edge~0); 304563#L670-1 assume !(1 == ~main_clk_pos_edge~0); 304562#L675-1 assume !(1 == ~main_in1_ev~0); 304561#L680-1 assume !(1 == ~main_in2_ev~0); 304560#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 304559#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 304558#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 304557#L700-1 assume !(1 == ~main_dbl_ev~0); 304556#L705-1 assume !(1 == ~main_zero_ev~0); 304555#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 304554#L715-1 assume !(1 == ~main_clk_pos_edge~0); 304553#L720-1 assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2; 304549#L725-1 assume 0 == ~N_generate_st~0; 304544#L742-1 [2022-07-14 16:02:22,500 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:22,501 INFO L85 PathProgramCache]: Analyzing trace with hash 1243965239, now seen corresponding path program 1 times [2022-07-14 16:02:22,501 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:22,501 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1927828401] [2022-07-14 16:02:22,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:22,501 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:22,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:22,517 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:22,518 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:22,518 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1927828401] [2022-07-14 16:02:22,518 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1927828401] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:22,518 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:22,518 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-07-14 16:02:22,518 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1803827244] [2022-07-14 16:02:22,518 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:22,519 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:22,519 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:22,519 INFO L85 PathProgramCache]: Analyzing trace with hash -1332141836, now seen corresponding path program 1 times [2022-07-14 16:02:22,519 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:22,519 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1803491492] [2022-07-14 16:02:22,519 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:22,519 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:22,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:22,530 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:22,530 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:22,530 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1803491492] [2022-07-14 16:02:22,530 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1803491492] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:22,530 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:22,530 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-14 16:02:22,531 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [838656117] [2022-07-14 16:02:22,531 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:22,531 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:22,531 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:22,531 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:02:22,532 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:02:22,532 INFO L87 Difference]: Start difference. First operand 44288 states and 68290 transitions. cyclomatic complexity: 24066 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:22,755 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:22,755 INFO L93 Difference]: Finished difference Result 53275 states and 81140 transitions. [2022-07-14 16:02:22,756 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-07-14 16:02:22,756 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 53275 states and 81140 transitions. [2022-07-14 16:02:23,333 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 50818 [2022-07-14 16:02:23,473 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 53275 states to 53275 states and 81140 transitions. [2022-07-14 16:02:23,474 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 53275 [2022-07-14 16:02:23,507 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 53275 [2022-07-14 16:02:23,507 INFO L73 IsDeterministic]: Start isDeterministic. Operand 53275 states and 81140 transitions. [2022-07-14 16:02:23,540 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:23,540 INFO L369 hiAutomatonCegarLoop]: Abstraction has 53275 states and 81140 transitions. [2022-07-14 16:02:23,569 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53275 states and 81140 transitions. [2022-07-14 16:02:24,178 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53275 to 41741. [2022-07-14 16:02:24,209 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41741 states, 41741 states have (on average 1.5255504180541912) internal successors, (63678), 41740 states have internal predecessors, (63678), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:24,271 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41741 states to 41741 states and 63678 transitions. [2022-07-14 16:02:24,271 INFO L392 hiAutomatonCegarLoop]: Abstraction has 41741 states and 63678 transitions. [2022-07-14 16:02:24,271 INFO L374 stractBuchiCegarLoop]: Abstraction has 41741 states and 63678 transitions. [2022-07-14 16:02:24,272 INFO L287 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-07-14 16:02:24,272 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41741 states and 63678 transitions. [2022-07-14 16:02:24,367 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 39570 [2022-07-14 16:02:24,367 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:24,367 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:24,368 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:24,368 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:24,368 INFO L752 eck$LassoCheckResult]: Stem: 394486#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 394442#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 393957#L256 assume !(1 == ~main_in1_req_up~0); 393913#L256-2 assume !(1 == ~main_in2_req_up~0); 393915#L267-1 assume !(1 == ~main_sum_req_up~0); 393944#L278-1 assume !(1 == ~main_diff_req_up~0); 393894#L289-1 assume !(1 == ~main_pres_req_up~0); 393895#L300-1 assume !(1 == ~main_dbl_req_up~0); 394006#L311-1 assume !(1 == ~main_zero_req_up~0); 394412#L322-1 assume !(1 == ~main_clk_req_up~0); 394414#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 398208#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 398207#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 398206#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 398205#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 398204#L371-1 assume !(0 == ~main_in1_ev~0); 398203#L376-1 assume !(0 == ~main_in2_ev~0); 398202#L381-1 assume !(0 == ~main_sum_ev~0); 398198#L386-1 assume !(0 == ~main_diff_ev~0); 396759#L391-1 assume !(0 == ~main_pres_ev~0); 396758#L396-1 assume !(0 == ~main_dbl_ev~0); 396756#L401-1 assume !(0 == ~main_zero_ev~0); 396757#L406-1 assume !(0 == ~main_clk_ev~0); 398188#L411-1 assume !(0 == ~main_clk_pos_edge~0); 396752#L416-1 assume !(0 == ~main_clk_neg_edge~0); 396751#L421-1 assume !(1 == ~main_clk_pos_edge~0); 396750#L426-1 assume !(1 == ~main_clk_pos_edge~0); 396749#L431-1 assume !(1 == ~main_clk_pos_edge~0); 396748#L436-1 assume !(1 == ~main_clk_pos_edge~0); 396747#L441-1 assume !(1 == ~main_clk_pos_edge~0); 396746#L446-1 assume !(1 == ~main_in1_ev~0); 396745#L451-1 assume !(1 == ~main_in2_ev~0); 396744#L456-1 assume !(1 == ~main_sum_ev~0); 396743#L461-1 assume !(1 == ~main_diff_ev~0); 396742#L466-1 assume !(1 == ~main_pres_ev~0); 396741#L471-1 assume !(1 == ~main_dbl_ev~0); 396740#L476-1 assume !(1 == ~main_zero_ev~0); 396738#L481-1 assume !(1 == ~main_clk_ev~0); 396739#L486-1 assume !(1 == ~main_clk_pos_edge~0); 396707#L491-1 assume !(1 == ~main_clk_neg_edge~0); 396702#L742-1 [2022-07-14 16:02:24,369 INFO L754 eck$LassoCheckResult]: Loop: 396702#L742-1 assume !false; 396701#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 396697#L229 assume !false; 396696#L147 assume !(0 == ~N_generate_st~0); 396692#L151 assume !(0 == ~S1_addsub_st~0); 396693#L154 assume !(0 == ~S2_presdbl_st~0); 396694#L157 assume !(0 == ~S3_zero_st~0); 396695#L160 assume !(0 == ~D_print_st~0); 394311#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 394312#L509 assume !(1 == ~main_in1_req_up~0); 394221#L509-2 assume !(1 == ~main_in2_req_up~0); 394222#L520-1 assume !(1 == ~main_sum_req_up~0); 401385#L531-1 assume !(1 == ~main_diff_req_up~0); 400988#L542-1 assume !(1 == ~main_pres_req_up~0); 400984#L553-1 assume !(1 == ~main_dbl_req_up~0); 400981#L564-1 assume !(1 == ~main_zero_req_up~0); 400982#L575-1 assume !(1 == ~main_clk_req_up~0); 401428#L586-1 start_simulation_~kernel_st~0#1 := 3; 403178#L605 assume !(0 == ~main_in1_ev~0); 403177#L605-2 assume !(0 == ~main_in2_ev~0); 403176#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 403175#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 403174#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 403173#L625-1 assume !(0 == ~main_dbl_ev~0); 403172#L630-1 assume !(0 == ~main_zero_ev~0); 403171#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 403170#L640-1 assume !(0 == ~main_clk_pos_edge~0); 403169#L645-1 assume !(0 == ~main_clk_neg_edge~0); 403168#L650-1 assume !(1 == ~main_clk_pos_edge~0); 403167#L655-1 assume !(1 == ~main_clk_pos_edge~0); 403166#L660-1 assume !(1 == ~main_clk_pos_edge~0); 403165#L665-1 assume !(1 == ~main_clk_pos_edge~0); 403164#L670-1 assume !(1 == ~main_clk_pos_edge~0); 403163#L675-1 assume !(1 == ~main_in1_ev~0); 403162#L680-1 assume !(1 == ~main_in2_ev~0); 403161#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 403160#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 403159#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 403158#L700-1 assume !(1 == ~main_dbl_ev~0); 403157#L705-1 assume !(1 == ~main_zero_ev~0); 403156#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 394233#L715-1 assume !(1 == ~main_clk_pos_edge~0); 394155#L720-1 assume !(1 == ~main_clk_neg_edge~0); 394156#L725-1 assume 0 == ~N_generate_st~0; 396702#L742-1 [2022-07-14 16:02:24,369 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:24,369 INFO L85 PathProgramCache]: Analyzing trace with hash 222896887, now seen corresponding path program 3 times [2022-07-14 16:02:24,369 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:24,369 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [551286267] [2022-07-14 16:02:24,370 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:24,370 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:24,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:24,378 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:02:24,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:24,396 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:02:24,397 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:24,397 INFO L85 PathProgramCache]: Analyzing trace with hash 1374477620, now seen corresponding path program 1 times [2022-07-14 16:02:24,397 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:24,397 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1219316389] [2022-07-14 16:02:24,397 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:24,398 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:24,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:24,410 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:24,411 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:24,411 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1219316389] [2022-07-14 16:02:24,411 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1219316389] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:24,411 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:24,411 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-14 16:02:24,411 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [301391397] [2022-07-14 16:02:24,411 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:24,411 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:24,412 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:24,412 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:02:24,412 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:02:24,412 INFO L87 Difference]: Start difference. First operand 41741 states and 63678 transitions. cyclomatic complexity: 22001 Second operand has 3 states, 2 states have (on average 22.0) internal successors, (44), 3 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:24,570 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:24,570 INFO L93 Difference]: Finished difference Result 57643 states and 86947 transitions. [2022-07-14 16:02:24,570 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:02:24,570 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 57643 states and 86947 transitions. [2022-07-14 16:02:25,085 INFO L131 ngComponentsAnalysis]: Automaton has 72 accepting balls. 53732 [2022-07-14 16:02:25,232 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 57643 states to 57643 states and 86947 transitions. [2022-07-14 16:02:25,232 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 57643 [2022-07-14 16:02:25,265 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 57643 [2022-07-14 16:02:25,266 INFO L73 IsDeterministic]: Start isDeterministic. Operand 57643 states and 86947 transitions. [2022-07-14 16:02:25,292 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:25,293 INFO L369 hiAutomatonCegarLoop]: Abstraction has 57643 states and 86947 transitions. [2022-07-14 16:02:25,318 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57643 states and 86947 transitions. [2022-07-14 16:02:25,818 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57643 to 57643. [2022-07-14 16:02:25,860 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 57643 states, 57643 states have (on average 1.5083704873098207) internal successors, (86947), 57642 states have internal predecessors, (86947), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:25,956 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57643 states to 57643 states and 86947 transitions. [2022-07-14 16:02:25,957 INFO L392 hiAutomatonCegarLoop]: Abstraction has 57643 states and 86947 transitions. [2022-07-14 16:02:25,957 INFO L374 stractBuchiCegarLoop]: Abstraction has 57643 states and 86947 transitions. [2022-07-14 16:02:25,957 INFO L287 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-07-14 16:02:25,957 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 57643 states and 86947 transitions. [2022-07-14 16:02:26,119 INFO L131 ngComponentsAnalysis]: Automaton has 72 accepting balls. 53732 [2022-07-14 16:02:26,119 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:26,119 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:26,120 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:26,120 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:26,120 INFO L752 eck$LassoCheckResult]: Stem: 493890#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 493851#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 493348#L256 assume !(1 == ~main_in1_req_up~0); 493303#L256-2 assume !(1 == ~main_in2_req_up~0); 493305#L267-1 assume !(1 == ~main_sum_req_up~0); 493793#L278-1 assume !(1 == ~main_diff_req_up~0); 493448#L289-1 assume !(1 == ~main_pres_req_up~0); 493733#L300-1 assume !(1 == ~main_dbl_req_up~0); 493576#L311-1 assume !(1 == ~main_zero_req_up~0); 493577#L322-1 assume !(1 == ~main_clk_req_up~0); 500679#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 500680#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 500678#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 500676#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 500673#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 500670#L371-1 assume !(0 == ~main_in1_ev~0); 500667#L376-1 assume !(0 == ~main_in2_ev~0); 500664#L381-1 assume !(0 == ~main_sum_ev~0); 500661#L386-1 assume !(0 == ~main_diff_ev~0); 500658#L391-1 assume !(0 == ~main_pres_ev~0); 500655#L396-1 assume !(0 == ~main_dbl_ev~0); 500652#L401-1 assume !(0 == ~main_zero_ev~0); 500649#L406-1 assume !(0 == ~main_clk_ev~0); 500646#L411-1 assume !(0 == ~main_clk_pos_edge~0); 500643#L416-1 assume !(0 == ~main_clk_neg_edge~0); 500640#L421-1 assume !(1 == ~main_clk_pos_edge~0); 500637#L426-1 assume !(1 == ~main_clk_pos_edge~0); 500634#L431-1 assume !(1 == ~main_clk_pos_edge~0); 500631#L436-1 assume !(1 == ~main_clk_pos_edge~0); 500628#L441-1 assume !(1 == ~main_clk_pos_edge~0); 500625#L446-1 assume !(1 == ~main_in1_ev~0); 500622#L451-1 assume !(1 == ~main_in2_ev~0); 500619#L456-1 assume !(1 == ~main_sum_ev~0); 500616#L461-1 assume !(1 == ~main_diff_ev~0); 500613#L466-1 assume !(1 == ~main_pres_ev~0); 500610#L471-1 assume !(1 == ~main_dbl_ev~0); 500607#L476-1 assume !(1 == ~main_zero_ev~0); 500604#L481-1 assume !(1 == ~main_clk_ev~0); 500601#L486-1 assume !(1 == ~main_clk_pos_edge~0); 500589#L491-1 assume !(1 == ~main_clk_neg_edge~0); 500585#L742-1 [2022-07-14 16:02:26,120 INFO L754 eck$LassoCheckResult]: Loop: 500585#L742-1 assume !false; 500581#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 500578#L229 assume !false; 497978#L147 assume !(0 == ~N_generate_st~0); 497977#L151 assume !(0 == ~S1_addsub_st~0); 497976#L154 assume !(0 == ~S2_presdbl_st~0); 497975#L157 assume !(0 == ~S3_zero_st~0); 497973#L160 assume !(0 == ~D_print_st~0); 497972#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 497971#L509 assume !(1 == ~main_in1_req_up~0); 497970#L509-2 assume !(1 == ~main_in2_req_up~0); 494920#L520-1 assume !(1 == ~main_sum_req_up~0); 494912#L531-1 assume !(1 == ~main_diff_req_up~0); 494906#L542-1 assume !(1 == ~main_pres_req_up~0); 494899#L553-1 assume !(1 == ~main_dbl_req_up~0); 494900#L564-1 assume !(1 == ~main_zero_req_up~0); 498604#L575-1 assume !(1 == ~main_clk_req_up~0); 500674#L586-1 start_simulation_~kernel_st~0#1 := 3; 500671#L605 assume !(0 == ~main_in1_ev~0); 500668#L605-2 assume !(0 == ~main_in2_ev~0); 500665#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 500662#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 500659#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 500656#L625-1 assume !(0 == ~main_dbl_ev~0); 500653#L630-1 assume !(0 == ~main_zero_ev~0); 500650#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 500647#L640-1 assume !(0 == ~main_clk_pos_edge~0); 500644#L645-1 assume !(0 == ~main_clk_neg_edge~0); 500641#L650-1 assume !(1 == ~main_clk_pos_edge~0); 500638#L655-1 assume !(1 == ~main_clk_pos_edge~0); 500635#L660-1 assume !(1 == ~main_clk_pos_edge~0); 500632#L665-1 assume !(1 == ~main_clk_pos_edge~0); 500629#L670-1 assume !(1 == ~main_clk_pos_edge~0); 500626#L675-1 assume !(1 == ~main_in1_ev~0); 500623#L680-1 assume !(1 == ~main_in2_ev~0); 500620#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 500617#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 500614#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 500611#L700-1 assume !(1 == ~main_dbl_ev~0); 500608#L705-1 assume !(1 == ~main_zero_ev~0); 500605#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 500602#L715-1 assume !(1 == ~main_clk_pos_edge~0); 500596#L720-1 assume !(1 == ~main_clk_neg_edge~0); 500595#L725-1 assume !(0 == ~N_generate_st~0); 500593#L733 assume 0 == ~S1_addsub_st~0; 500585#L742-1 [2022-07-14 16:02:26,121 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:26,121 INFO L85 PathProgramCache]: Analyzing trace with hash 222896887, now seen corresponding path program 4 times [2022-07-14 16:02:26,121 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:26,121 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2138871882] [2022-07-14 16:02:26,121 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:26,122 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:26,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:26,127 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:02:26,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:26,136 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:02:26,136 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:26,136 INFO L85 PathProgramCache]: Analyzing trace with hash -340865996, now seen corresponding path program 1 times [2022-07-14 16:02:26,137 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:26,137 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1469661634] [2022-07-14 16:02:26,137 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:26,137 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:26,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:26,147 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:26,147 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:26,147 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1469661634] [2022-07-14 16:02:26,147 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1469661634] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:26,148 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:26,148 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-14 16:02:26,148 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [583439268] [2022-07-14 16:02:26,148 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:26,148 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:26,148 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:26,149 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:02:26,149 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:02:26,149 INFO L87 Difference]: Start difference. First operand 57643 states and 86947 transitions. cyclomatic complexity: 29376 Second operand has 3 states, 2 states have (on average 22.5) internal successors, (45), 3 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:26,363 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:26,363 INFO L93 Difference]: Finished difference Result 86850 states and 129727 transitions. [2022-07-14 16:02:26,363 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:02:26,364 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 86850 states and 129727 transitions. [2022-07-14 16:02:26,977 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 79456 [2022-07-14 16:02:27,158 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 86850 states to 86850 states and 129727 transitions. [2022-07-14 16:02:27,159 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 86850 [2022-07-14 16:02:27,214 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 86850 [2022-07-14 16:02:27,215 INFO L73 IsDeterministic]: Start isDeterministic. Operand 86850 states and 129727 transitions. [2022-07-14 16:02:27,260 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:27,260 INFO L369 hiAutomatonCegarLoop]: Abstraction has 86850 states and 129727 transitions. [2022-07-14 16:02:27,301 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 86850 states and 129727 transitions. [2022-07-14 16:02:28,030 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 86850 to 86850. [2022-07-14 16:02:28,096 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 86850 states, 86850 states have (on average 1.4936902705814623) internal successors, (129727), 86849 states have internal predecessors, (129727), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:28,230 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86850 states to 86850 states and 129727 transitions. [2022-07-14 16:02:28,230 INFO L392 hiAutomatonCegarLoop]: Abstraction has 86850 states and 129727 transitions. [2022-07-14 16:02:28,230 INFO L374 stractBuchiCegarLoop]: Abstraction has 86850 states and 129727 transitions. [2022-07-14 16:02:28,230 INFO L287 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-07-14 16:02:28,230 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 86850 states and 129727 transitions. [2022-07-14 16:02:28,460 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 79456 [2022-07-14 16:02:28,461 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:28,461 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:28,461 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:28,461 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:28,462 INFO L752 eck$LassoCheckResult]: Stem: 638405#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 638360#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 637848#L256 assume !(1 == ~main_in1_req_up~0); 637802#L256-2 assume !(1 == ~main_in2_req_up~0); 637804#L267-1 assume !(1 == ~main_sum_req_up~0); 638297#L278-1 assume !(1 == ~main_diff_req_up~0); 637947#L289-1 assume !(1 == ~main_pres_req_up~0); 638228#L300-1 assume !(1 == ~main_dbl_req_up~0); 637897#L311-1 assume !(1 == ~main_zero_req_up~0); 641657#L322-1 assume !(1 == ~main_clk_req_up~0); 641658#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 649339#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 649368#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 649365#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 649362#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 649359#L371-1 assume !(0 == ~main_in1_ev~0); 649356#L376-1 assume !(0 == ~main_in2_ev~0); 649353#L381-1 assume !(0 == ~main_sum_ev~0); 649350#L386-1 assume !(0 == ~main_diff_ev~0); 649347#L391-1 assume !(0 == ~main_pres_ev~0); 649344#L396-1 assume !(0 == ~main_dbl_ev~0); 649341#L401-1 assume !(0 == ~main_zero_ev~0); 649337#L406-1 assume !(0 == ~main_clk_ev~0); 649332#L411-1 assume !(0 == ~main_clk_pos_edge~0); 649328#L416-1 assume !(0 == ~main_clk_neg_edge~0); 649324#L421-1 assume !(1 == ~main_clk_pos_edge~0); 649320#L426-1 assume !(1 == ~main_clk_pos_edge~0); 649316#L431-1 assume !(1 == ~main_clk_pos_edge~0); 649312#L436-1 assume !(1 == ~main_clk_pos_edge~0); 649308#L441-1 assume !(1 == ~main_clk_pos_edge~0); 649304#L446-1 assume !(1 == ~main_in1_ev~0); 649300#L451-1 assume !(1 == ~main_in2_ev~0); 649296#L456-1 assume !(1 == ~main_sum_ev~0); 649292#L461-1 assume !(1 == ~main_diff_ev~0); 649288#L466-1 assume !(1 == ~main_pres_ev~0); 649284#L471-1 assume !(1 == ~main_dbl_ev~0); 649281#L476-1 assume !(1 == ~main_zero_ev~0); 649278#L481-1 assume !(1 == ~main_clk_ev~0); 649276#L486-1 assume !(1 == ~main_clk_pos_edge~0); 649274#L491-1 assume !(1 == ~main_clk_neg_edge~0); 648472#L742-1 [2022-07-14 16:02:28,462 INFO L754 eck$LassoCheckResult]: Loop: 648472#L742-1 assume !false; 648460#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 645391#L229 assume !false; 645392#L147 assume !(0 == ~N_generate_st~0); 640131#L151 assume !(0 == ~S1_addsub_st~0); 640129#L154 assume !(0 == ~S2_presdbl_st~0); 640127#L157 assume !(0 == ~S3_zero_st~0); 640124#L160 assume !(0 == ~D_print_st~0); 640121#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 640119#L509 assume !(1 == ~main_in1_req_up~0); 640116#L509-2 assume !(1 == ~main_in2_req_up~0); 640117#L520-1 assume !(1 == ~main_sum_req_up~0); 641819#L531-1 assume !(1 == ~main_diff_req_up~0); 641815#L542-1 assume !(1 == ~main_pres_req_up~0); 641809#L553-1 assume !(1 == ~main_dbl_req_up~0); 641802#L564-1 assume !(1 == ~main_zero_req_up~0); 641796#L575-1 assume !(1 == ~main_clk_req_up~0); 641797#L586-1 start_simulation_~kernel_st~0#1 := 3; 648516#L605 assume !(0 == ~main_in1_ev~0); 648515#L605-2 assume !(0 == ~main_in2_ev~0); 648514#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 648513#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 648512#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 648511#L625-1 assume !(0 == ~main_dbl_ev~0); 648510#L630-1 assume !(0 == ~main_zero_ev~0); 648509#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 648508#L640-1 assume !(0 == ~main_clk_pos_edge~0); 648507#L645-1 assume !(0 == ~main_clk_neg_edge~0); 648506#L650-1 assume !(1 == ~main_clk_pos_edge~0); 648505#L655-1 assume !(1 == ~main_clk_pos_edge~0); 648504#L660-1 assume !(1 == ~main_clk_pos_edge~0); 648503#L665-1 assume !(1 == ~main_clk_pos_edge~0); 648502#L670-1 assume !(1 == ~main_clk_pos_edge~0); 648501#L675-1 assume !(1 == ~main_in1_ev~0); 648500#L680-1 assume !(1 == ~main_in2_ev~0); 648499#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 648498#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 648497#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 648496#L700-1 assume !(1 == ~main_dbl_ev~0); 648495#L705-1 assume !(1 == ~main_zero_ev~0); 648494#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 648493#L715-1 assume !(1 == ~main_clk_pos_edge~0); 648492#L720-1 assume !(1 == ~main_clk_neg_edge~0); 648491#L725-1 assume !(0 == ~N_generate_st~0); 648490#L733 assume !(0 == ~S1_addsub_st~0); 648489#L736 assume 0 == ~S2_presdbl_st~0; 648472#L742-1 [2022-07-14 16:02:28,462 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:28,462 INFO L85 PathProgramCache]: Analyzing trace with hash 222896887, now seen corresponding path program 5 times [2022-07-14 16:02:28,462 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:28,463 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [183827616] [2022-07-14 16:02:28,463 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:28,463 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:28,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:28,468 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:02:28,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:28,478 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:02:28,479 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:28,479 INFO L85 PathProgramCache]: Analyzing trace with hash -1976910535, now seen corresponding path program 1 times [2022-07-14 16:02:28,480 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:28,480 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [990637885] [2022-07-14 16:02:28,480 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:28,480 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:28,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:28,491 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:28,491 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:28,491 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [990637885] [2022-07-14 16:02:28,491 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [990637885] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:28,491 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:28,491 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-14 16:02:28,492 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [36900367] [2022-07-14 16:02:28,492 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:28,492 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:28,492 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:28,492 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:02:28,492 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:02:28,493 INFO L87 Difference]: Start difference. First operand 86850 states and 129727 transitions. cyclomatic complexity: 42973 Second operand has 3 states, 2 states have (on average 23.0) internal successors, (46), 3 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:28,731 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:28,731 INFO L93 Difference]: Finished difference Result 91777 states and 136566 transitions. [2022-07-14 16:02:28,732 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:02:28,732 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 91777 states and 136566 transitions. [2022-07-14 16:02:29,389 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 84178 [2022-07-14 16:02:29,594 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 91777 states to 91777 states and 136566 transitions. [2022-07-14 16:02:29,594 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 91777 [2022-07-14 16:02:29,649 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 91777 [2022-07-14 16:02:29,649 INFO L73 IsDeterministic]: Start isDeterministic. Operand 91777 states and 136566 transitions. [2022-07-14 16:02:29,696 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:29,696 INFO L369 hiAutomatonCegarLoop]: Abstraction has 91777 states and 136566 transitions. [2022-07-14 16:02:29,745 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91777 states and 136566 transitions. [2022-07-14 16:02:30,672 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91777 to 91777. [2022-07-14 16:02:30,746 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 91777 states, 91777 states have (on average 1.4880198742604356) internal successors, (136566), 91776 states have internal predecessors, (136566), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:30,886 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91777 states to 91777 states and 136566 transitions. [2022-07-14 16:02:30,886 INFO L392 hiAutomatonCegarLoop]: Abstraction has 91777 states and 136566 transitions. [2022-07-14 16:02:30,886 INFO L374 stractBuchiCegarLoop]: Abstraction has 91777 states and 136566 transitions. [2022-07-14 16:02:30,886 INFO L287 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-07-14 16:02:30,887 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 91777 states and 136566 transitions. [2022-07-14 16:02:31,140 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 84178 [2022-07-14 16:02:31,141 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:31,141 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:31,141 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:31,142 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:31,142 INFO L752 eck$LassoCheckResult]: Stem: 817069#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 817009#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 816479#L256 assume !(1 == ~main_in1_req_up~0); 816435#L256-2 assume !(1 == ~main_in2_req_up~0); 816437#L267-1 assume !(1 == ~main_sum_req_up~0); 816466#L278-1 assume !(1 == ~main_diff_req_up~0); 816416#L289-1 assume !(1 == ~main_pres_req_up~0); 816417#L300-1 assume !(1 == ~main_dbl_req_up~0); 821976#L311-1 assume !(1 == ~main_zero_req_up~0); 826853#L322-1 assume !(1 == ~main_clk_req_up~0); 826847#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 826848#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 828550#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 828561#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 828560#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 828559#L371-1 assume !(0 == ~main_in1_ev~0); 828558#L376-1 assume !(0 == ~main_in2_ev~0); 828557#L381-1 assume !(0 == ~main_sum_ev~0); 828556#L386-1 assume !(0 == ~main_diff_ev~0); 828555#L391-1 assume !(0 == ~main_pres_ev~0); 828554#L396-1 assume !(0 == ~main_dbl_ev~0); 828553#L401-1 assume !(0 == ~main_zero_ev~0); 828552#L406-1 assume !(0 == ~main_clk_ev~0); 828551#L411-1 assume !(0 == ~main_clk_pos_edge~0); 828536#L416-1 assume !(0 == ~main_clk_neg_edge~0); 828533#L421-1 assume !(1 == ~main_clk_pos_edge~0); 828530#L426-1 assume !(1 == ~main_clk_pos_edge~0); 828527#L431-1 assume !(1 == ~main_clk_pos_edge~0); 828524#L436-1 assume !(1 == ~main_clk_pos_edge~0); 828521#L441-1 assume !(1 == ~main_clk_pos_edge~0); 828518#L446-1 assume !(1 == ~main_in1_ev~0); 828515#L451-1 assume !(1 == ~main_in2_ev~0); 828512#L456-1 assume !(1 == ~main_sum_ev~0); 828509#L461-1 assume !(1 == ~main_diff_ev~0); 828506#L466-1 assume !(1 == ~main_pres_ev~0); 828503#L471-1 assume !(1 == ~main_dbl_ev~0); 828500#L476-1 assume !(1 == ~main_zero_ev~0); 828497#L481-1 assume !(1 == ~main_clk_ev~0); 828494#L486-1 assume !(1 == ~main_clk_pos_edge~0); 828445#L491-1 assume !(1 == ~main_clk_neg_edge~0); 828341#L742-1 [2022-07-14 16:02:31,142 INFO L754 eck$LassoCheckResult]: Loop: 828341#L742-1 assume !false; 828342#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 828330#L229 assume !false; 828331#L147 assume !(0 == ~N_generate_st~0); 821912#L151 assume !(0 == ~S1_addsub_st~0); 821909#L154 assume !(0 == ~S2_presdbl_st~0); 821908#L157 assume !(0 == ~S3_zero_st~0); 821905#L160 assume !(0 == ~D_print_st~0); 821903#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 821900#L509 assume !(1 == ~main_in1_req_up~0); 821896#L509-2 assume !(1 == ~main_in2_req_up~0); 821897#L520-1 assume !(1 == ~main_sum_req_up~0); 828325#L531-1 assume !(1 == ~main_diff_req_up~0); 828323#L542-1 assume !(1 == ~main_pres_req_up~0); 828319#L553-1 assume !(1 == ~main_dbl_req_up~0); 828315#L564-1 assume !(1 == ~main_zero_req_up~0); 828312#L575-1 assume !(1 == ~main_clk_req_up~0); 828313#L586-1 start_simulation_~kernel_st~0#1 := 3; 828565#L605 assume !(0 == ~main_in1_ev~0); 828564#L605-2 assume !(0 == ~main_in2_ev~0); 828563#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 828562#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 828537#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 828534#L625-1 assume !(0 == ~main_dbl_ev~0); 828531#L630-1 assume !(0 == ~main_zero_ev~0); 828528#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 828525#L640-1 assume !(0 == ~main_clk_pos_edge~0); 828522#L645-1 assume !(0 == ~main_clk_neg_edge~0); 828519#L650-1 assume !(1 == ~main_clk_pos_edge~0); 828516#L655-1 assume !(1 == ~main_clk_pos_edge~0); 828513#L660-1 assume !(1 == ~main_clk_pos_edge~0); 828510#L665-1 assume !(1 == ~main_clk_pos_edge~0); 828507#L670-1 assume !(1 == ~main_clk_pos_edge~0); 828504#L675-1 assume !(1 == ~main_in1_ev~0); 828501#L680-1 assume !(1 == ~main_in2_ev~0); 828498#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 828495#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 828448#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 828444#L700-1 assume !(1 == ~main_dbl_ev~0); 828441#L705-1 assume !(1 == ~main_zero_ev~0); 828437#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 828436#L715-1 assume !(1 == ~main_clk_pos_edge~0); 828403#L720-1 assume !(1 == ~main_clk_neg_edge~0); 828400#L725-1 assume !(0 == ~N_generate_st~0); 828397#L733 assume !(0 == ~S1_addsub_st~0); 828394#L736 assume !(0 == ~S2_presdbl_st~0); 828387#L739 assume 0 == ~S3_zero_st~0; 828341#L742-1 [2022-07-14 16:02:31,142 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:31,142 INFO L85 PathProgramCache]: Analyzing trace with hash 222896887, now seen corresponding path program 6 times [2022-07-14 16:02:31,143 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:31,143 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1860863957] [2022-07-14 16:02:31,143 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:31,143 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:31,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:31,149 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:02:31,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:31,156 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:02:31,157 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:31,157 INFO L85 PathProgramCache]: Analyzing trace with hash -1154683687, now seen corresponding path program 1 times [2022-07-14 16:02:31,157 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:31,157 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1233179608] [2022-07-14 16:02:31,157 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:31,157 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:31,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:31,167 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:31,167 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:31,167 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1233179608] [2022-07-14 16:02:31,168 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1233179608] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:31,168 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:31,168 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-14 16:02:31,168 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1944822644] [2022-07-14 16:02:31,168 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:31,168 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:31,168 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:31,169 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:02:31,169 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:02:31,169 INFO L87 Difference]: Start difference. First operand 91777 states and 136566 transitions. cyclomatic complexity: 44885 Second operand has 3 states, 2 states have (on average 23.5) internal successors, (47), 3 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:31,844 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:31,845 INFO L93 Difference]: Finished difference Result 147978 states and 218783 transitions. [2022-07-14 16:02:31,845 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:02:31,845 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 147978 states and 218783 transitions. [2022-07-14 16:02:32,370 INFO L131 ngComponentsAnalysis]: Automaton has 144 accepting balls. 133258 [2022-07-14 16:02:32,698 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 147978 states to 147978 states and 218783 transitions. [2022-07-14 16:02:32,699 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 147978 [2022-07-14 16:02:32,772 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 147978 [2022-07-14 16:02:32,773 INFO L73 IsDeterministic]: Start isDeterministic. Operand 147978 states and 218783 transitions. [2022-07-14 16:02:32,839 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:32,840 INFO L369 hiAutomatonCegarLoop]: Abstraction has 147978 states and 218783 transitions. [2022-07-14 16:02:32,909 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 147978 states and 218783 transitions. [2022-07-14 16:02:34,511 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 147978 to 147978. [2022-07-14 16:02:34,619 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 147978 states, 147978 states have (on average 1.4784832880563328) internal successors, (218783), 147977 states have internal predecessors, (218783), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:34,854 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 147978 states to 147978 states and 218783 transitions. [2022-07-14 16:02:34,854 INFO L392 hiAutomatonCegarLoop]: Abstraction has 147978 states and 218783 transitions. [2022-07-14 16:02:34,854 INFO L374 stractBuchiCegarLoop]: Abstraction has 147978 states and 218783 transitions. [2022-07-14 16:02:34,854 INFO L287 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-07-14 16:02:34,854 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 147978 states and 218783 transitions. [2022-07-14 16:02:35,237 INFO L131 ngComponentsAnalysis]: Automaton has 144 accepting balls. 133258 [2022-07-14 16:02:35,237 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:35,237 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:35,238 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:35,238 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:35,238 INFO L752 eck$LassoCheckResult]: Stem: 1056893#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 1056824#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 1056239#L256 assume !(1 == ~main_in1_req_up~0); 1056195#L256-2 assume !(1 == ~main_in2_req_up~0); 1056197#L267-1 assume !(1 == ~main_sum_req_up~0); 1056226#L278-1 assume !(1 == ~main_diff_req_up~0); 1056177#L289-1 assume !(1 == ~main_pres_req_up~0); 1056178#L300-1 assume !(1 == ~main_dbl_req_up~0); 1058333#L311-1 assume !(1 == ~main_zero_req_up~0); 1058334#L322-1 assume !(1 == ~main_clk_req_up~0); 1061675#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 1061676#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 1061680#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 1061800#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 1061801#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 1061946#L371-1 assume !(0 == ~main_in1_ev~0); 1061944#L376-1 assume !(0 == ~main_in2_ev~0); 1061942#L381-1 assume !(0 == ~main_sum_ev~0); 1061940#L386-1 assume !(0 == ~main_diff_ev~0); 1061938#L391-1 assume !(0 == ~main_pres_ev~0); 1061936#L396-1 assume !(0 == ~main_dbl_ev~0); 1061934#L401-1 assume !(0 == ~main_zero_ev~0); 1061932#L406-1 assume !(0 == ~main_clk_ev~0); 1061930#L411-1 assume !(0 == ~main_clk_pos_edge~0); 1061928#L416-1 assume !(0 == ~main_clk_neg_edge~0); 1061926#L421-1 assume !(1 == ~main_clk_pos_edge~0); 1061924#L426-1 assume !(1 == ~main_clk_pos_edge~0); 1061922#L431-1 assume !(1 == ~main_clk_pos_edge~0); 1061920#L436-1 assume !(1 == ~main_clk_pos_edge~0); 1061918#L441-1 assume !(1 == ~main_clk_pos_edge~0); 1061916#L446-1 assume !(1 == ~main_in1_ev~0); 1061914#L451-1 assume !(1 == ~main_in2_ev~0); 1061912#L456-1 assume !(1 == ~main_sum_ev~0); 1061910#L461-1 assume !(1 == ~main_diff_ev~0); 1061908#L466-1 assume !(1 == ~main_pres_ev~0); 1061906#L471-1 assume !(1 == ~main_dbl_ev~0); 1061904#L476-1 assume !(1 == ~main_zero_ev~0); 1061902#L481-1 assume !(1 == ~main_clk_ev~0); 1061900#L486-1 assume !(1 == ~main_clk_pos_edge~0); 1061897#L491-1 assume !(1 == ~main_clk_neg_edge~0); 1061896#L742-1 [2022-07-14 16:02:35,238 INFO L754 eck$LassoCheckResult]: Loop: 1061896#L742-1 assume !false; 1061476#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 1061466#L229 assume !false; 1060898#L147 assume !(0 == ~N_generate_st~0); 1060726#L151 assume !(0 == ~S1_addsub_st~0); 1060719#L154 assume !(0 == ~S2_presdbl_st~0); 1056188#L157 assume !(0 == ~S3_zero_st~0); 1056189#L160 assume !(0 == ~D_print_st~0); 1056637#L245 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 1056638#L509 assume !(1 == ~main_in1_req_up~0); 1056665#L509-2 assume !(1 == ~main_in2_req_up~0); 1057380#L520-1 assume !(1 == ~main_sum_req_up~0); 1058129#L531-1 assume !(1 == ~main_diff_req_up~0); 1058122#L542-1 assume !(1 == ~main_pres_req_up~0); 1058121#L553-1 assume !(1 == ~main_dbl_req_up~0); 1058097#L564-1 assume !(1 == ~main_zero_req_up~0); 1058098#L575-1 assume !(1 == ~main_clk_req_up~0); 1061953#L586-1 start_simulation_~kernel_st~0#1 := 3; 1061952#L605 assume !(0 == ~main_in1_ev~0); 1061951#L605-2 assume !(0 == ~main_in2_ev~0); 1061950#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 1061949#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 1061948#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 1061947#L625-1 assume !(0 == ~main_dbl_ev~0); 1061945#L630-1 assume !(0 == ~main_zero_ev~0); 1061943#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 1061941#L640-1 assume !(0 == ~main_clk_pos_edge~0); 1061939#L645-1 assume !(0 == ~main_clk_neg_edge~0); 1061937#L650-1 assume !(1 == ~main_clk_pos_edge~0); 1061935#L655-1 assume !(1 == ~main_clk_pos_edge~0); 1061933#L660-1 assume !(1 == ~main_clk_pos_edge~0); 1061931#L665-1 assume !(1 == ~main_clk_pos_edge~0); 1061929#L670-1 assume !(1 == ~main_clk_pos_edge~0); 1061927#L675-1 assume !(1 == ~main_in1_ev~0); 1061925#L680-1 assume !(1 == ~main_in2_ev~0); 1061923#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 1061921#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 1061919#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 1061917#L700-1 assume !(1 == ~main_dbl_ev~0); 1061915#L705-1 assume !(1 == ~main_zero_ev~0); 1061913#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 1061911#L715-1 assume !(1 == ~main_clk_pos_edge~0); 1061909#L720-1 assume !(1 == ~main_clk_neg_edge~0); 1061907#L725-1 assume !(0 == ~N_generate_st~0); 1061905#L733 assume !(0 == ~S1_addsub_st~0); 1061903#L736 assume !(0 == ~S2_presdbl_st~0); 1061901#L739 assume !(0 == ~S3_zero_st~0); 1061898#L742 assume 0 == ~D_print_st~0; 1061896#L742-1 [2022-07-14 16:02:35,238 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:35,238 INFO L85 PathProgramCache]: Analyzing trace with hash 222896887, now seen corresponding path program 7 times [2022-07-14 16:02:35,239 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:35,239 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [971201819] [2022-07-14 16:02:35,239 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:35,239 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:35,244 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:35,244 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:02:35,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:35,251 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:02:35,251 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:35,251 INFO L85 PathProgramCache]: Analyzing trace with hash -1435455170, now seen corresponding path program 1 times [2022-07-14 16:02:35,251 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:35,251 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1667563851] [2022-07-14 16:02:35,251 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:35,251 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:35,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:35,260 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:35,260 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:35,260 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1667563851] [2022-07-14 16:02:35,261 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1667563851] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:35,261 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:35,261 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-14 16:02:35,261 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [404764678] [2022-07-14 16:02:35,261 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:35,261 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:35,261 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:35,262 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:02:35,262 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:02:35,262 INFO L87 Difference]: Start difference. First operand 147978 states and 218783 transitions. cyclomatic complexity: 70949 Second operand has 3 states, 2 states have (on average 24.0) internal successors, (48), 3 states have internal predecessors, (48), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:36,622 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:36,622 INFO L93 Difference]: Finished difference Result 253411 states and 370695 transitions. [2022-07-14 16:02:36,623 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:02:36,623 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 253411 states and 370695 transitions. [2022-07-14 16:02:38,263 INFO L131 ngComponentsAnalysis]: Automaton has 224 accepting balls. 219346 [2022-07-14 16:02:38,980 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 253411 states to 253411 states and 370695 transitions. [2022-07-14 16:02:38,980 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 253411 [2022-07-14 16:02:39,144 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 253411 [2022-07-14 16:02:39,145 INFO L73 IsDeterministic]: Start isDeterministic. Operand 253411 states and 370695 transitions. [2022-07-14 16:02:39,301 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:39,301 INFO L369 hiAutomatonCegarLoop]: Abstraction has 253411 states and 370695 transitions. [2022-07-14 16:02:39,415 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 253411 states and 370695 transitions. [2022-07-14 16:02:42,343 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 253411 to 253411. [2022-07-14 16:02:42,581 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 253411 states, 253411 states have (on average 1.4628212666379912) internal successors, (370695), 253410 states have internal predecessors, (370695), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:43,121 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 253411 states to 253411 states and 370695 transitions. [2022-07-14 16:02:43,122 INFO L392 hiAutomatonCegarLoop]: Abstraction has 253411 states and 370695 transitions. [2022-07-14 16:02:43,122 INFO L374 stractBuchiCegarLoop]: Abstraction has 253411 states and 370695 transitions. [2022-07-14 16:02:43,122 INFO L287 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-07-14 16:02:43,122 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 253411 states and 370695 transitions. [2022-07-14 16:02:44,463 INFO L131 ngComponentsAnalysis]: Automaton has 224 accepting balls. 219346 [2022-07-14 16:02:44,464 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:44,465 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:44,468 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:44,469 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:44,469 INFO L752 eck$LassoCheckResult]: Stem: 1458266#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 1458195#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 1457634#L256 assume !(1 == ~main_in1_req_up~0); 1457590#L256-2 assume !(1 == ~main_in2_req_up~0); 1457592#L267-1 assume !(1 == ~main_sum_req_up~0); 1457621#L278-1 assume !(1 == ~main_diff_req_up~0); 1457572#L289-1 assume !(1 == ~main_pres_req_up~0); 1457573#L300-1 assume !(1 == ~main_dbl_req_up~0); 1462589#L311-1 assume !(1 == ~main_zero_req_up~0); 1467522#L322-1 assume !(1 == ~main_clk_req_up~0); 1485585#L333-1 assume 1 == ~N_generate_i~0;~N_generate_st~0 := 0; 1486049#L351-1 assume 1 == ~S1_addsub_i~0;~S1_addsub_st~0 := 0; 1486050#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 1486074#L361-1 assume 1 == ~S3_zero_i~0;~S3_zero_st~0 := 0; 1486075#L366-1 assume 1 == ~D_print_i~0;~D_print_st~0 := 0; 1486094#L371-1 assume !(0 == ~main_in1_ev~0); 1486093#L376-1 assume !(0 == ~main_in2_ev~0); 1486092#L381-1 assume !(0 == ~main_sum_ev~0); 1486091#L386-1 assume !(0 == ~main_diff_ev~0); 1486090#L391-1 assume !(0 == ~main_pres_ev~0); 1486089#L396-1 assume !(0 == ~main_dbl_ev~0); 1486088#L401-1 assume !(0 == ~main_zero_ev~0); 1486087#L406-1 assume !(0 == ~main_clk_ev~0); 1486086#L411-1 assume !(0 == ~main_clk_pos_edge~0); 1486085#L416-1 assume !(0 == ~main_clk_neg_edge~0); 1486077#L421-1 assume !(1 == ~main_clk_pos_edge~0); 1486076#L426-1 assume !(1 == ~main_clk_pos_edge~0); 1486055#L431-1 assume !(1 == ~main_clk_pos_edge~0); 1486054#L436-1 assume !(1 == ~main_clk_pos_edge~0); 1486053#L441-1 assume !(1 == ~main_clk_pos_edge~0); 1486051#L446-1 assume !(1 == ~main_in1_ev~0); 1486048#L451-1 assume !(1 == ~main_in2_ev~0); 1485923#L456-1 assume !(1 == ~main_sum_ev~0); 1485920#L461-1 assume !(1 == ~main_diff_ev~0); 1485918#L466-1 assume !(1 == ~main_pres_ev~0); 1485916#L471-1 assume !(1 == ~main_dbl_ev~0); 1485914#L476-1 assume !(1 == ~main_zero_ev~0); 1485912#L481-1 assume !(1 == ~main_clk_ev~0); 1485910#L486-1 assume !(1 == ~main_clk_pos_edge~0); 1485908#L491-1 assume !(1 == ~main_clk_neg_edge~0); 1485905#L742-1 assume !false; 1485776#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 1485705#L229 [2022-07-14 16:02:44,469 INFO L754 eck$LassoCheckResult]: Loop: 1485705#L229 assume !false; 1485696#L147 assume 0 == ~N_generate_st~0; 1485682#L160-1 assume 0 == ~N_generate_st~0;eval_~tmp~0#1 := eval_#t~nondet4#1;havoc eval_#t~nondet4#1; 1485670#L173 assume !(0 != eval_~tmp~0#1); 1485671#L169 assume 0 == ~S1_addsub_st~0;eval_~tmp___0~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1485849#L188 assume !(0 != eval_~tmp___0~0#1); 1485840#L184 assume !(0 == ~S2_presdbl_st~0); 1485836#L199 assume 0 == ~S3_zero_st~0;eval_~tmp___2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1485831#L218 assume !(0 != eval_~tmp___2~0#1); 1485828#L214 assume 0 == ~D_print_st~0;eval_~tmp___3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1485774#L233 assume !(0 != eval_~tmp___3~0#1); 1485705#L229 [2022-07-14 16:02:44,473 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:44,473 INFO L85 PathProgramCache]: Analyzing trace with hash 1897430713, now seen corresponding path program 1 times [2022-07-14 16:02:44,473 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:44,474 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1917943913] [2022-07-14 16:02:44,474 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:44,474 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:44,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:44,520 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:44,521 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:44,521 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1917943913] [2022-07-14 16:02:44,521 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1917943913] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:44,521 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:44,521 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-07-14 16:02:44,521 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [270614165] [2022-07-14 16:02:44,521 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:44,522 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:44,523 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:44,523 INFO L85 PathProgramCache]: Analyzing trace with hash 263530038, now seen corresponding path program 1 times [2022-07-14 16:02:44,523 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:44,524 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1399942029] [2022-07-14 16:02:44,524 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:44,524 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:44,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:44,527 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:02:44,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:44,529 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:02:44,610 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:44,611 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:02:44,611 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:02:44,611 INFO L87 Difference]: Start difference. First operand 253411 states and 370695 transitions. cyclomatic complexity: 117508 Second operand has 4 states, 4 states have (on average 10.5) internal successors, (42), 4 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:45,086 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:45,086 INFO L93 Difference]: Finished difference Result 152871 states and 223090 transitions. [2022-07-14 16:02:45,087 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:02:45,087 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 152871 states and 223090 transitions. [2022-07-14 16:02:45,706 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 131250 [2022-07-14 16:02:46,762 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 152871 states to 152871 states and 223090 transitions. [2022-07-14 16:02:46,762 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 152871 [2022-07-14 16:02:46,845 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 152871 [2022-07-14 16:02:46,846 INFO L73 IsDeterministic]: Start isDeterministic. Operand 152871 states and 223090 transitions. [2022-07-14 16:02:46,918 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:46,919 INFO L369 hiAutomatonCegarLoop]: Abstraction has 152871 states and 223090 transitions. [2022-07-14 16:02:46,981 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 152871 states and 223090 transitions. [2022-07-14 16:02:48,240 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 152871 to 152871. [2022-07-14 16:02:48,356 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 152871 states, 152871 states have (on average 1.4593349948649514) internal successors, (223090), 152870 states have internal predecessors, (223090), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:48,617 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 152871 states to 152871 states and 223090 transitions. [2022-07-14 16:02:48,617 INFO L392 hiAutomatonCegarLoop]: Abstraction has 152871 states and 223090 transitions. [2022-07-14 16:02:48,617 INFO L374 stractBuchiCegarLoop]: Abstraction has 152871 states and 223090 transitions. [2022-07-14 16:02:48,617 INFO L287 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-07-14 16:02:48,617 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 152871 states and 223090 transitions. [2022-07-14 16:02:49,044 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 131250 [2022-07-14 16:02:49,045 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:49,045 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:49,045 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:49,045 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:49,045 INFO L752 eck$LassoCheckResult]: Stem: 1864555#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 1864493#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 1863927#L256 assume !(1 == ~main_in1_req_up~0); 1863882#L256-2 assume !(1 == ~main_in2_req_up~0); 1863884#L267-1 assume !(1 == ~main_sum_req_up~0); 1864416#L278-1 assume !(1 == ~main_diff_req_up~0); 1864026#L289-1 assume !(1 == ~main_pres_req_up~0); 1864343#L300-1 assume !(1 == ~main_dbl_req_up~0); 1863977#L311-1 assume !(1 == ~main_zero_req_up~0); 1864166#L322-1 assume !(1 == ~main_clk_req_up~0); 1904030#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 1904027#L351-1 assume 1 == ~S1_addsub_i~0;~S1_addsub_st~0 := 0; 1904025#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 1904022#L361-1 assume 1 == ~S3_zero_i~0;~S3_zero_st~0 := 0; 1904023#L366-1 assume 1 == ~D_print_i~0;~D_print_st~0 := 0; 1904039#L371-1 assume !(0 == ~main_in1_ev~0); 1904038#L376-1 assume !(0 == ~main_in2_ev~0); 1904037#L381-1 assume !(0 == ~main_sum_ev~0); 1904035#L386-1 assume !(0 == ~main_diff_ev~0); 1904034#L391-1 assume !(0 == ~main_pres_ev~0); 1904031#L396-1 assume !(0 == ~main_dbl_ev~0); 1904029#L401-1 assume !(0 == ~main_zero_ev~0); 1904026#L406-1 assume !(0 == ~main_clk_ev~0); 1904024#L411-1 assume !(0 == ~main_clk_pos_edge~0); 1904021#L416-1 assume !(0 == ~main_clk_neg_edge~0); 1904018#L421-1 assume !(1 == ~main_clk_pos_edge~0); 1904016#L426-1 assume !(1 == ~main_clk_pos_edge~0); 1904014#L431-1 assume !(1 == ~main_clk_pos_edge~0); 1904012#L436-1 assume !(1 == ~main_clk_pos_edge~0); 1904010#L441-1 assume !(1 == ~main_clk_pos_edge~0); 1904008#L446-1 assume !(1 == ~main_in1_ev~0); 1904006#L451-1 assume !(1 == ~main_in2_ev~0); 1904004#L456-1 assume !(1 == ~main_sum_ev~0); 1904002#L461-1 assume !(1 == ~main_diff_ev~0); 1904000#L466-1 assume !(1 == ~main_pres_ev~0); 1903998#L471-1 assume !(1 == ~main_dbl_ev~0); 1903996#L476-1 assume !(1 == ~main_zero_ev~0); 1903994#L481-1 assume !(1 == ~main_clk_ev~0); 1903992#L486-1 assume !(1 == ~main_clk_pos_edge~0); 1903990#L491-1 assume !(1 == ~main_clk_neg_edge~0); 1903988#L742-1 assume !false; 1903986#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 1903982#L229 [2022-07-14 16:02:49,046 INFO L754 eck$LassoCheckResult]: Loop: 1903982#L229 assume !false; 1903980#L147 assume !(0 == ~N_generate_st~0); 1903977#L151 assume 0 == ~S1_addsub_st~0; 1903975#L160-1 assume !(0 == ~N_generate_st~0); 1903972#L169 assume 0 == ~S1_addsub_st~0;eval_~tmp___0~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1903969#L188 assume !(0 != eval_~tmp___0~0#1); 1903967#L184 assume !(0 == ~S2_presdbl_st~0); 1903965#L199 assume 0 == ~S3_zero_st~0;eval_~tmp___2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1903963#L218 assume !(0 != eval_~tmp___2~0#1); 1903964#L214 assume 0 == ~D_print_st~0;eval_~tmp___3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1903984#L233 assume !(0 != eval_~tmp___3~0#1); 1903982#L229 [2022-07-14 16:02:49,046 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:49,046 INFO L85 PathProgramCache]: Analyzing trace with hash -2122776969, now seen corresponding path program 1 times [2022-07-14 16:02:49,046 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:49,047 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1837821921] [2022-07-14 16:02:49,047 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:49,047 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:49,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:49,064 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:49,064 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:49,064 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1837821921] [2022-07-14 16:02:49,065 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1837821921] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:49,066 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:49,066 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-07-14 16:02:49,066 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [846277468] [2022-07-14 16:02:49,067 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:49,067 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:49,067 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:49,067 INFO L85 PathProgramCache]: Analyzing trace with hash 105804796, now seen corresponding path program 1 times [2022-07-14 16:02:49,067 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:49,067 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [891206496] [2022-07-14 16:02:49,068 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:49,068 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:49,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:49,073 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:02:49,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:49,076 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:02:49,134 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:49,134 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:02:49,134 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:02:49,135 INFO L87 Difference]: Start difference. First operand 152871 states and 223090 transitions. cyclomatic complexity: 70315 Second operand has 4 states, 4 states have (on average 10.5) internal successors, (42), 4 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:49,441 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:49,441 INFO L93 Difference]: Finished difference Result 109199 states and 158994 transitions. [2022-07-14 16:02:49,442 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:02:49,442 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 109199 states and 158994 transitions. [2022-07-14 16:02:50,424 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 94626 [2022-07-14 16:02:50,673 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 109199 states to 109199 states and 158994 transitions. [2022-07-14 16:02:50,674 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 109199 [2022-07-14 16:02:50,742 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 109199 [2022-07-14 16:02:50,742 INFO L73 IsDeterministic]: Start isDeterministic. Operand 109199 states and 158994 transitions. [2022-07-14 16:02:50,793 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:50,794 INFO L369 hiAutomatonCegarLoop]: Abstraction has 109199 states and 158994 transitions. [2022-07-14 16:02:50,845 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 109199 states and 158994 transitions. [2022-07-14 16:02:51,956 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 109199 to 109199. [2022-07-14 16:02:52,036 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 109199 states, 109199 states have (on average 1.4560023443438126) internal successors, (158994), 109198 states have internal predecessors, (158994), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:52,229 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 109199 states to 109199 states and 158994 transitions. [2022-07-14 16:02:52,229 INFO L392 hiAutomatonCegarLoop]: Abstraction has 109199 states and 158994 transitions. [2022-07-14 16:02:52,229 INFO L374 stractBuchiCegarLoop]: Abstraction has 109199 states and 158994 transitions. [2022-07-14 16:02:52,229 INFO L287 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-07-14 16:02:52,229 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 109199 states and 158994 transitions. [2022-07-14 16:02:52,543 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 94626 [2022-07-14 16:02:52,544 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:52,544 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:52,544 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:52,544 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:52,545 INFO L752 eck$LassoCheckResult]: Stem: 2126666#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 2126597#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2126007#L256 assume !(1 == ~main_in1_req_up~0); 2125962#L256-2 assume !(1 == ~main_in2_req_up~0); 2125964#L267-1 assume !(1 == ~main_sum_req_up~0); 2125993#L278-1 assume !(1 == ~main_diff_req_up~0); 2125944#L289-1 assume !(1 == ~main_pres_req_up~0); 2125945#L300-1 assume !(1 == ~main_dbl_req_up~0); 2128392#L311-1 assume !(1 == ~main_zero_req_up~0); 2128383#L322-1 assume !(1 == ~main_clk_req_up~0); 2128384#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2129999#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2129998#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2129996#L361-1 assume 1 == ~S3_zero_i~0;~S3_zero_st~0 := 0; 2129994#L366-1 assume 1 == ~D_print_i~0;~D_print_st~0 := 0; 2129995#L371-1 assume !(0 == ~main_in1_ev~0); 2130045#L376-1 assume !(0 == ~main_in2_ev~0); 2130044#L381-1 assume !(0 == ~main_sum_ev~0); 2130043#L386-1 assume !(0 == ~main_diff_ev~0); 2130042#L391-1 assume !(0 == ~main_pres_ev~0); 2130041#L396-1 assume !(0 == ~main_dbl_ev~0); 2130040#L401-1 assume !(0 == ~main_zero_ev~0); 2130039#L406-1 assume !(0 == ~main_clk_ev~0); 2130038#L411-1 assume !(0 == ~main_clk_pos_edge~0); 2130036#L416-1 assume !(0 == ~main_clk_neg_edge~0); 2130032#L421-1 assume !(1 == ~main_clk_pos_edge~0); 2130028#L426-1 assume !(1 == ~main_clk_pos_edge~0); 2130024#L431-1 assume !(1 == ~main_clk_pos_edge~0); 2130020#L436-1 assume !(1 == ~main_clk_pos_edge~0); 2130016#L441-1 assume !(1 == ~main_clk_pos_edge~0); 2130012#L446-1 assume !(1 == ~main_in1_ev~0); 2130008#L451-1 assume !(1 == ~main_in2_ev~0); 2130004#L456-1 assume !(1 == ~main_sum_ev~0); 2130000#L461-1 assume !(1 == ~main_diff_ev~0); 2129980#L466-1 assume !(1 == ~main_pres_ev~0); 2129976#L471-1 assume !(1 == ~main_dbl_ev~0); 2129972#L476-1 assume !(1 == ~main_zero_ev~0); 2129968#L481-1 assume !(1 == ~main_clk_ev~0); 2129915#L486-1 assume !(1 == ~main_clk_pos_edge~0); 2129885#L491-1 assume !(1 == ~main_clk_neg_edge~0); 2129876#L742-1 assume !false; 2129872#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2129615#L229 [2022-07-14 16:02:52,546 INFO L754 eck$LassoCheckResult]: Loop: 2129615#L229 assume !false; 2129865#L147 assume !(0 == ~N_generate_st~0); 2129863#L151 assume !(0 == ~S1_addsub_st~0); 2129861#L154 assume !(0 == ~S2_presdbl_st~0); 2129859#L157 assume 0 == ~S3_zero_st~0; 2129856#L160-1 assume !(0 == ~N_generate_st~0); 2129853#L169 assume !(0 == ~S1_addsub_st~0); 2129810#L184 assume !(0 == ~S2_presdbl_st~0); 2129811#L199 assume 0 == ~S3_zero_st~0;eval_~tmp___2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 2129812#L218 assume !(0 != eval_~tmp___2~0#1); 2129804#L214 assume 0 == ~D_print_st~0;eval_~tmp___3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 2129613#L233 assume !(0 != eval_~tmp___3~0#1); 2129615#L229 [2022-07-14 16:02:52,546 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:52,546 INFO L85 PathProgramCache]: Analyzing trace with hash -1421177095, now seen corresponding path program 1 times [2022-07-14 16:02:52,547 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:52,547 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1260969720] [2022-07-14 16:02:52,547 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:52,547 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:52,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:52,568 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:52,568 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:52,569 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1260969720] [2022-07-14 16:02:52,569 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1260969720] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:52,569 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:52,569 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-07-14 16:02:52,569 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1404994574] [2022-07-14 16:02:52,569 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:52,569 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:52,570 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:52,570 INFO L85 PathProgramCache]: Analyzing trace with hash 1118247229, now seen corresponding path program 1 times [2022-07-14 16:02:52,570 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:52,570 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1871223423] [2022-07-14 16:02:52,570 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:52,570 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:52,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:52,572 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:02:52,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:52,574 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:02:52,610 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:52,610 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:02:52,610 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:02:52,610 INFO L87 Difference]: Start difference. First operand 109199 states and 158994 transitions. cyclomatic complexity: 49859 Second operand has 4 states, 4 states have (on average 10.5) internal successors, (42), 4 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)