./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/array-examples/sanfoundry_24-1.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version f4b24e32 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/array-examples/sanfoundry_24-1.i -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash e0a16588b251f5de7b3febde43795c7086835cc989637b8bd82aa8d6af355c6b --- Real Ultimate output --- This is Ultimate 0.2.2-?-f4b24e3 [2022-07-14 15:06:57,909 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-07-14 15:06:57,913 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-07-14 15:06:57,943 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-07-14 15:06:57,944 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-07-14 15:06:57,945 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-07-14 15:06:57,946 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-07-14 15:06:57,947 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-07-14 15:06:57,952 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-07-14 15:06:57,956 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-07-14 15:06:57,957 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-07-14 15:06:57,959 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-07-14 15:06:57,959 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-07-14 15:06:57,961 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-07-14 15:06:57,963 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-07-14 15:06:57,964 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-07-14 15:06:57,965 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-07-14 15:06:57,966 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-07-14 15:06:57,967 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-07-14 15:06:57,972 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-07-14 15:06:57,974 INFO L181 SettingsManager]: Resetting HornVerifier preferences to default values [2022-07-14 15:06:57,975 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-07-14 15:06:57,975 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-07-14 15:06:57,976 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-07-14 15:06:57,978 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-07-14 15:06:57,984 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-07-14 15:06:57,984 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-07-14 15:06:57,984 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-07-14 15:06:57,985 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-07-14 15:06:57,986 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-07-14 15:06:57,987 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-07-14 15:06:57,987 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-07-14 15:06:57,988 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-07-14 15:06:57,989 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-07-14 15:06:57,989 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-07-14 15:06:57,990 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-07-14 15:06:57,990 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-07-14 15:06:57,991 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-07-14 15:06:57,992 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-07-14 15:06:57,992 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-07-14 15:06:57,992 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-07-14 15:06:57,994 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-07-14 15:06:57,995 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-07-14 15:06:58,023 INFO L113 SettingsManager]: Loading preferences was successful [2022-07-14 15:06:58,023 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-07-14 15:06:58,024 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-07-14 15:06:58,024 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-07-14 15:06:58,025 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-07-14 15:06:58,025 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-07-14 15:06:58,025 INFO L138 SettingsManager]: * Use SBE=true [2022-07-14 15:06:58,025 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-07-14 15:06:58,025 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-07-14 15:06:58,026 INFO L138 SettingsManager]: * Use old map elimination=false [2022-07-14 15:06:58,026 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-07-14 15:06:58,026 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-07-14 15:06:58,027 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-07-14 15:06:58,027 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-07-14 15:06:58,027 INFO L138 SettingsManager]: * sizeof long=4 [2022-07-14 15:06:58,027 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-07-14 15:06:58,027 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-07-14 15:06:58,027 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-07-14 15:06:58,027 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-07-14 15:06:58,028 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-07-14 15:06:58,028 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-07-14 15:06:58,028 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-07-14 15:06:58,028 INFO L138 SettingsManager]: * sizeof long double=12 [2022-07-14 15:06:58,028 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-07-14 15:06:58,028 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-07-14 15:06:58,028 INFO L138 SettingsManager]: * Use constant arrays=true [2022-07-14 15:06:58,029 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-07-14 15:06:58,029 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-07-14 15:06:58,029 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-07-14 15:06:58,029 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-07-14 15:06:58,029 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-07-14 15:06:58,030 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-07-14 15:06:58,030 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> e0a16588b251f5de7b3febde43795c7086835cc989637b8bd82aa8d6af355c6b [2022-07-14 15:06:58,209 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-07-14 15:06:58,226 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-07-14 15:06:58,229 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-07-14 15:06:58,230 INFO L271 PluginConnector]: Initializing CDTParser... [2022-07-14 15:06:58,235 INFO L275 PluginConnector]: CDTParser initialized [2022-07-14 15:06:58,236 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/array-examples/sanfoundry_24-1.i [2022-07-14 15:06:58,306 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/8f8b66231/320b9c816d6f44439aca3ccc6754f204/FLAG160fca480 [2022-07-14 15:06:58,725 INFO L306 CDTParser]: Found 1 translation units. [2022-07-14 15:06:58,726 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/array-examples/sanfoundry_24-1.i [2022-07-14 15:06:58,730 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/8f8b66231/320b9c816d6f44439aca3ccc6754f204/FLAG160fca480 [2022-07-14 15:06:58,741 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/8f8b66231/320b9c816d6f44439aca3ccc6754f204 [2022-07-14 15:06:58,743 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-07-14 15:06:58,744 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-07-14 15:06:58,745 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-07-14 15:06:58,745 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-07-14 15:06:58,747 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-07-14 15:06:58,747 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.07 03:06:58" (1/1) ... [2022-07-14 15:06:58,748 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5b4dfa9c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 03:06:58, skipping insertion in model container [2022-07-14 15:06:58,748 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.07 03:06:58" (1/1) ... [2022-07-14 15:06:58,752 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-07-14 15:06:58,767 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-07-14 15:06:58,923 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/array-examples/sanfoundry_24-1.i[848,861] [2022-07-14 15:06:58,932 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-14 15:06:58,937 INFO L203 MainTranslator]: Completed pre-run [2022-07-14 15:06:58,945 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/array-examples/sanfoundry_24-1.i[848,861] [2022-07-14 15:06:58,949 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-14 15:06:58,961 INFO L208 MainTranslator]: Completed translation [2022-07-14 15:06:58,961 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 03:06:58 WrapperNode [2022-07-14 15:06:58,961 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-07-14 15:06:58,962 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-07-14 15:06:58,962 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-07-14 15:06:58,962 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-07-14 15:06:58,967 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 03:06:58" (1/1) ... [2022-07-14 15:06:58,972 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 03:06:58" (1/1) ... [2022-07-14 15:06:58,985 INFO L137 Inliner]: procedures = 18, calls = 18, calls flagged for inlining = 6, calls inlined = 6, statements flattened = 73 [2022-07-14 15:06:58,985 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-07-14 15:06:58,986 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-07-14 15:06:58,986 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-07-14 15:06:58,986 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-07-14 15:06:58,992 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 03:06:58" (1/1) ... [2022-07-14 15:06:58,995 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 03:06:58" (1/1) ... [2022-07-14 15:06:58,997 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 03:06:58" (1/1) ... [2022-07-14 15:06:58,997 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 03:06:58" (1/1) ... [2022-07-14 15:06:59,001 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 03:06:58" (1/1) ... [2022-07-14 15:06:59,004 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 03:06:58" (1/1) ... [2022-07-14 15:06:59,005 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 03:06:58" (1/1) ... [2022-07-14 15:06:59,007 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-07-14 15:06:59,008 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-07-14 15:06:59,008 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-07-14 15:06:59,008 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-07-14 15:06:59,009 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 03:06:58" (1/1) ... [2022-07-14 15:06:59,013 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 15:06:59,022 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:06:59,031 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-14 15:06:59,040 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-07-14 15:06:59,058 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-07-14 15:06:59,059 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-07-14 15:06:59,059 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-07-14 15:06:59,059 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-07-14 15:06:59,059 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-07-14 15:06:59,059 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-07-14 15:06:59,059 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-07-14 15:06:59,059 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-07-14 15:06:59,107 INFO L234 CfgBuilder]: Building ICFG [2022-07-14 15:06:59,108 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-07-14 15:06:59,250 INFO L275 CfgBuilder]: Performing block encoding [2022-07-14 15:06:59,254 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-07-14 15:06:59,254 INFO L299 CfgBuilder]: Removed 3 assume(true) statements. [2022-07-14 15:06:59,255 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.07 03:06:59 BoogieIcfgContainer [2022-07-14 15:06:59,256 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-07-14 15:06:59,256 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-07-14 15:06:59,256 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-07-14 15:06:59,258 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-07-14 15:06:59,259 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-14 15:06:59,259 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 14.07 03:06:58" (1/3) ... [2022-07-14 15:06:59,260 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5eaff483 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 14.07 03:06:59, skipping insertion in model container [2022-07-14 15:06:59,260 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-14 15:06:59,260 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 03:06:58" (2/3) ... [2022-07-14 15:06:59,260 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5eaff483 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 14.07 03:06:59, skipping insertion in model container [2022-07-14 15:06:59,260 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-14 15:06:59,261 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.07 03:06:59" (3/3) ... [2022-07-14 15:06:59,262 INFO L354 chiAutomizerObserver]: Analyzing ICFG sanfoundry_24-1.i [2022-07-14 15:06:59,296 INFO L255 stractBuchiCegarLoop]: Interprodecural is true [2022-07-14 15:06:59,297 INFO L256 stractBuchiCegarLoop]: Hoare is false [2022-07-14 15:06:59,297 INFO L257 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-07-14 15:06:59,297 INFO L258 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-07-14 15:06:59,297 INFO L259 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-07-14 15:06:59,297 INFO L260 stractBuchiCegarLoop]: Difference is false [2022-07-14 15:06:59,298 INFO L261 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-07-14 15:06:59,298 INFO L265 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-07-14 15:06:59,301 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 24 states, 23 states have (on average 1.434782608695652) internal successors, (33), 23 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:06:59,314 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 16 [2022-07-14 15:06:59,314 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:06:59,314 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:06:59,317 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-07-14 15:06:59,317 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-07-14 15:06:59,317 INFO L287 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-07-14 15:06:59,318 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 24 states, 23 states have (on average 1.434782608695652) internal successors, (33), 23 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:06:59,319 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 16 [2022-07-14 15:06:59,319 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:06:59,319 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:06:59,319 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-07-14 15:06:59,320 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-07-14 15:06:59,324 INFO L752 eck$LassoCheckResult]: Stem: 4#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 7#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 19#L27-3true [2022-07-14 15:06:59,324 INFO L754 eck$LassoCheckResult]: Loop: 19#L27-3true assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 10#L27-2true main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19#L27-3true [2022-07-14 15:06:59,328 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:06:59,329 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times [2022-07-14 15:06:59,335 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:06:59,335 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1019096648] [2022-07-14 15:06:59,335 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:06:59,336 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:06:59,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:06:59,417 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:06:59,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:06:59,448 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:06:59,458 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:06:59,459 INFO L85 PathProgramCache]: Analyzing trace with hash 1283, now seen corresponding path program 1 times [2022-07-14 15:06:59,459 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:06:59,460 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [434703640] [2022-07-14 15:06:59,460 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:06:59,460 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:06:59,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:06:59,476 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:06:59,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:06:59,489 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:06:59,491 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:06:59,492 INFO L85 PathProgramCache]: Analyzing trace with hash 925765, now seen corresponding path program 1 times [2022-07-14 15:06:59,492 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:06:59,492 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2088896751] [2022-07-14 15:06:59,493 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:06:59,493 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:06:59,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:06:59,525 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:06:59,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:06:59,546 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:06:59,817 INFO L210 LassoAnalysis]: Preferences: [2022-07-14 15:06:59,818 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-07-14 15:06:59,818 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-07-14 15:06:59,818 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-07-14 15:06:59,818 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2022-07-14 15:06:59,818 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 15:06:59,819 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-07-14 15:06:59,819 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-07-14 15:06:59,819 INFO L133 ssoRankerPreferences]: Filename of dumped script: sanfoundry_24-1.i_Iteration1_Lasso [2022-07-14 15:06:59,819 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-07-14 15:06:59,819 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-07-14 15:06:59,832 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 15:06:59,977 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 15:06:59,979 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 15:06:59,981 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 15:06:59,983 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 15:06:59,984 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 15:06:59,987 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 15:06:59,989 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 15:06:59,991 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 15:06:59,993 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 15:06:59,995 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 15:06:59,997 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 15:07:00,160 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-07-14 15:07:00,163 INFO L490 LassoAnalysis]: Using template 'affine'. [2022-07-14 15:07:00,164 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 15:07:00,164 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:07:00,166 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-14 15:07:00,171 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-07-14 15:07:00,178 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-07-14 15:07:00,178 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-07-14 15:07:00,178 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-07-14 15:07:00,178 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-07-14 15:07:00,181 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-07-14 15:07:00,181 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-07-14 15:07:00,185 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2022-07-14 15:07:00,186 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-07-14 15:07:00,207 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2022-07-14 15:07:00,208 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 15:07:00,208 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:07:00,209 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-14 15:07:00,211 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2022-07-14 15:07:00,212 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-07-14 15:07:00,219 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-07-14 15:07:00,219 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-07-14 15:07:00,219 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-07-14 15:07:00,219 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-07-14 15:07:00,234 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-07-14 15:07:00,234 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-07-14 15:07:00,251 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-07-14 15:07:00,269 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2022-07-14 15:07:00,270 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 15:07:00,270 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:07:00,271 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-14 15:07:00,272 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2022-07-14 15:07:00,274 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-07-14 15:07:00,280 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-07-14 15:07:00,280 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-07-14 15:07:00,280 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-07-14 15:07:00,280 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-07-14 15:07:00,280 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-07-14 15:07:00,281 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-07-14 15:07:00,281 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-07-14 15:07:00,296 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-07-14 15:07:00,315 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2022-07-14 15:07:00,315 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 15:07:00,316 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:07:00,317 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-14 15:07:00,318 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2022-07-14 15:07:00,319 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-07-14 15:07:00,325 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-07-14 15:07:00,325 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-07-14 15:07:00,325 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-07-14 15:07:00,325 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-07-14 15:07:00,334 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-07-14 15:07:00,335 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-07-14 15:07:00,351 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-07-14 15:07:00,369 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2022-07-14 15:07:00,369 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 15:07:00,369 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:07:00,372 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-14 15:07:00,372 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2022-07-14 15:07:00,375 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-07-14 15:07:00,380 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-07-14 15:07:00,381 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-07-14 15:07:00,381 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-07-14 15:07:00,381 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-07-14 15:07:00,385 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-07-14 15:07:00,385 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-07-14 15:07:00,400 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-07-14 15:07:00,415 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2022-07-14 15:07:00,416 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 15:07:00,416 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:07:00,417 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-14 15:07:00,419 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2022-07-14 15:07:00,420 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-07-14 15:07:00,427 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-07-14 15:07:00,427 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-07-14 15:07:00,427 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-07-14 15:07:00,427 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-07-14 15:07:00,435 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-07-14 15:07:00,435 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-07-14 15:07:00,445 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-07-14 15:07:00,461 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2022-07-14 15:07:00,462 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 15:07:00,462 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:07:00,463 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-14 15:07:00,463 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2022-07-14 15:07:00,465 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-07-14 15:07:00,471 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-07-14 15:07:00,471 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-07-14 15:07:00,471 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-07-14 15:07:00,471 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-07-14 15:07:00,473 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-07-14 15:07:00,473 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-07-14 15:07:00,499 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-07-14 15:07:00,517 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2022-07-14 15:07:00,518 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 15:07:00,518 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:07:00,519 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-14 15:07:00,528 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-07-14 15:07:00,533 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-07-14 15:07:00,533 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-07-14 15:07:00,534 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-07-14 15:07:00,534 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-07-14 15:07:00,534 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2022-07-14 15:07:00,535 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-07-14 15:07:00,535 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-07-14 15:07:00,547 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-07-14 15:07:00,564 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2022-07-14 15:07:00,564 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 15:07:00,565 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:07:00,572 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-14 15:07:00,573 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2022-07-14 15:07:00,574 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-07-14 15:07:00,580 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-07-14 15:07:00,580 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-07-14 15:07:00,580 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-07-14 15:07:00,580 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-07-14 15:07:00,582 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-07-14 15:07:00,582 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-07-14 15:07:00,595 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-07-14 15:07:00,614 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Forceful destruction successful, exit code 0 [2022-07-14 15:07:00,614 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 15:07:00,614 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:07:00,615 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-14 15:07:00,621 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-07-14 15:07:00,626 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-07-14 15:07:00,626 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-07-14 15:07:00,626 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-07-14 15:07:00,627 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-07-14 15:07:00,630 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-07-14 15:07:00,630 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-07-14 15:07:00,635 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2022-07-14 15:07:00,642 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2022-07-14 15:07:00,664 INFO L443 ModelExtractionUtils]: Simplification made 10 calls to the SMT solver. [2022-07-14 15:07:00,664 INFO L444 ModelExtractionUtils]: 3 out of 16 variables were initially zero. Simplification set additionally 9 variables to zero. [2022-07-14 15:07:00,665 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 15:07:00,665 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:07:00,668 INFO L229 MonitoredProcess]: Starting monitored process 12 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-14 15:07:00,668 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2022-07-14 15:07:00,720 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2022-07-14 15:07:00,792 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2022-07-14 15:07:00,792 INFO L513 LassoAnalysis]: Proved termination. [2022-07-14 15:07:00,792 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(v_rep(select #length ULTIMATE.start_main_~#array~0#1.base)_1, ULTIMATE.start_main_~i~0#1, ULTIMATE.start_main_~#array~0#1.offset) = 1*v_rep(select #length ULTIMATE.start_main_~#array~0#1.base)_1 - 4*ULTIMATE.start_main_~i~0#1 - 1*ULTIMATE.start_main_~#array~0#1.offset Supporting invariants [] [2022-07-14 15:07:00,810 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2022-07-14 15:07:00,823 INFO L293 tatePredicateManager]: 5 out of 5 supporting invariants were superfluous and have been removed [2022-07-14 15:07:00,845 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:00,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:07:00,855 INFO L263 TraceCheckSpWp]: Trace formula consists of 35 conjuncts, 2 conjunts are in the unsatisfiable core [2022-07-14 15:07:00,856 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:07:00,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:07:00,867 INFO L263 TraceCheckSpWp]: Trace formula consists of 13 conjuncts, 4 conjunts are in the unsatisfiable core [2022-07-14 15:07:00,868 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:07:00,881 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:00,912 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2022-07-14 15:07:00,913 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 24 states, 23 states have (on average 1.434782608695652) internal successors, (33), 23 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:00,945 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 24 states, 23 states have (on average 1.434782608695652) internal successors, (33), 23 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 47 states and 67 transitions. Complement of second has 8 states. [2022-07-14 15:07:00,946 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 5 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2022-07-14 15:07:00,951 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:00,951 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 33 transitions. [2022-07-14 15:07:00,952 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 2 letters. Loop has 2 letters. [2022-07-14 15:07:00,952 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-07-14 15:07:00,952 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 4 letters. Loop has 2 letters. [2022-07-14 15:07:00,952 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-07-14 15:07:00,952 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 2 letters. Loop has 4 letters. [2022-07-14 15:07:00,952 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-07-14 15:07:00,953 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 47 states and 67 transitions. [2022-07-14 15:07:00,955 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14 [2022-07-14 15:07:00,957 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 47 states to 21 states and 29 transitions. [2022-07-14 15:07:00,963 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2022-07-14 15:07:00,963 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2022-07-14 15:07:00,964 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21 states and 29 transitions. [2022-07-14 15:07:00,964 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 15:07:00,964 INFO L369 hiAutomatonCegarLoop]: Abstraction has 21 states and 29 transitions. [2022-07-14 15:07:00,978 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states and 29 transitions. [2022-07-14 15:07:00,983 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2022-07-14 15:07:00,983 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21 states, 21 states have (on average 1.380952380952381) internal successors, (29), 20 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:00,983 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 29 transitions. [2022-07-14 15:07:00,984 INFO L392 hiAutomatonCegarLoop]: Abstraction has 21 states and 29 transitions. [2022-07-14 15:07:00,984 INFO L374 stractBuchiCegarLoop]: Abstraction has 21 states and 29 transitions. [2022-07-14 15:07:00,984 INFO L287 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-07-14 15:07:00,984 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21 states and 29 transitions. [2022-07-14 15:07:00,985 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14 [2022-07-14 15:07:00,985 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:07:00,985 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:07:00,985 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1] [2022-07-14 15:07:00,985 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-07-14 15:07:00,985 INFO L752 eck$LassoCheckResult]: Stem: 133#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 134#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 140#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 144#L27-4 main_~i~0#1 := 0; 145#L32-3 [2022-07-14 15:07:00,985 INFO L754 eck$LassoCheckResult]: Loop: 145#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 150#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 139#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 145#L32-3 [2022-07-14 15:07:00,986 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:00,986 INFO L85 PathProgramCache]: Analyzing trace with hash 925707, now seen corresponding path program 1 times [2022-07-14 15:07:00,986 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:00,986 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1651236268] [2022-07-14 15:07:00,986 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:00,986 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:00,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:00,992 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:00,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:01,005 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:01,005 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:01,005 INFO L85 PathProgramCache]: Analyzing trace with hash 54137, now seen corresponding path program 1 times [2022-07-14 15:07:01,006 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:01,006 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1034178262] [2022-07-14 15:07:01,006 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:01,006 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:01,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:01,012 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:01,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:01,017 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:01,017 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:01,017 INFO L85 PathProgramCache]: Analyzing trace with hash 1807957807, now seen corresponding path program 1 times [2022-07-14 15:07:01,017 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:01,018 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1387972101] [2022-07-14 15:07:01,018 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:01,018 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:01,030 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:07:01,072 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:01,073 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:07:01,073 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1387972101] [2022-07-14 15:07:01,073 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1387972101] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 15:07:01,073 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 15:07:01,073 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 15:07:01,073 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [635880029] [2022-07-14 15:07:01,074 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 15:07:01,115 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:07:01,117 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-07-14 15:07:01,118 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-07-14 15:07:01,119 INFO L87 Difference]: Start difference. First operand 21 states and 29 transitions. cyclomatic complexity: 11 Second operand has 5 states, 5 states have (on average 1.4) internal successors, (7), 5 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:01,166 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:07:01,166 INFO L93 Difference]: Finished difference Result 40 states and 47 transitions. [2022-07-14 15:07:01,166 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 15:07:01,167 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 40 states and 47 transitions. [2022-07-14 15:07:01,168 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:01,169 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 40 states to 32 states and 38 transitions. [2022-07-14 15:07:01,169 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29 [2022-07-14 15:07:01,169 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29 [2022-07-14 15:07:01,169 INFO L73 IsDeterministic]: Start isDeterministic. Operand 32 states and 38 transitions. [2022-07-14 15:07:01,169 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 15:07:01,169 INFO L369 hiAutomatonCegarLoop]: Abstraction has 32 states and 38 transitions. [2022-07-14 15:07:01,169 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states and 38 transitions. [2022-07-14 15:07:01,170 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 20. [2022-07-14 15:07:01,171 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20 states, 20 states have (on average 1.2) internal successors, (24), 19 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:01,171 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 24 transitions. [2022-07-14 15:07:01,171 INFO L392 hiAutomatonCegarLoop]: Abstraction has 20 states and 24 transitions. [2022-07-14 15:07:01,171 INFO L374 stractBuchiCegarLoop]: Abstraction has 20 states and 24 transitions. [2022-07-14 15:07:01,171 INFO L287 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-07-14 15:07:01,171 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20 states and 24 transitions. [2022-07-14 15:07:01,172 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:01,172 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:07:01,172 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:07:01,172 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1] [2022-07-14 15:07:01,172 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-07-14 15:07:01,173 INFO L752 eck$LassoCheckResult]: Stem: 204#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 205#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 210#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 213#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 214#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 215#L27-4 main_~i~0#1 := 0; 216#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 220#L34 [2022-07-14 15:07:01,173 INFO L754 eck$LassoCheckResult]: Loop: 220#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 209#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 217#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 220#L34 [2022-07-14 15:07:01,173 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:01,173 INFO L85 PathProgramCache]: Analyzing trace with hash 1809669547, now seen corresponding path program 1 times [2022-07-14 15:07:01,173 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:01,173 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1227308725] [2022-07-14 15:07:01,174 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:01,174 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:01,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:01,184 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:01,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:01,193 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:01,193 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:01,193 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 2 times [2022-07-14 15:07:01,193 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:01,193 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [269751262] [2022-07-14 15:07:01,194 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:01,194 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:01,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:01,198 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:01,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:01,208 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:01,209 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:01,209 INFO L85 PathProgramCache]: Analyzing trace with hash 1436015051, now seen corresponding path program 1 times [2022-07-14 15:07:01,209 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:01,209 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [251101059] [2022-07-14 15:07:01,211 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:01,211 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:01,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:07:01,277 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:01,278 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:07:01,278 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [251101059] [2022-07-14 15:07:01,278 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [251101059] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:07:01,278 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [40719694] [2022-07-14 15:07:01,278 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:01,279 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:07:01,279 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:07:01,280 INFO L229 MonitoredProcess]: Starting monitored process 13 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:07:01,281 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2022-07-14 15:07:01,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:07:01,314 INFO L263 TraceCheckSpWp]: Trace formula consists of 66 conjuncts, 6 conjunts are in the unsatisfiable core [2022-07-14 15:07:01,315 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:07:01,342 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2022-07-14 15:07:01,363 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:01,363 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:07:01,394 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:01,395 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [40719694] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:07:01,395 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:07:01,395 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 10 [2022-07-14 15:07:01,395 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1675143186] [2022-07-14 15:07:01,395 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:07:01,426 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:07:01,427 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2022-07-14 15:07:01,427 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=75, Unknown=0, NotChecked=0, Total=110 [2022-07-14 15:07:01,427 INFO L87 Difference]: Start difference. First operand 20 states and 24 transitions. cyclomatic complexity: 7 Second operand has 11 states, 10 states have (on average 2.2) internal successors, (22), 11 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:01,535 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:07:01,535 INFO L93 Difference]: Finished difference Result 63 states and 74 transitions. [2022-07-14 15:07:01,537 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-07-14 15:07:01,537 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63 states and 74 transitions. [2022-07-14 15:07:01,539 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:01,539 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63 states to 46 states and 54 transitions. [2022-07-14 15:07:01,539 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41 [2022-07-14 15:07:01,539 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41 [2022-07-14 15:07:01,539 INFO L73 IsDeterministic]: Start isDeterministic. Operand 46 states and 54 transitions. [2022-07-14 15:07:01,540 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 15:07:01,540 INFO L369 hiAutomatonCegarLoop]: Abstraction has 46 states and 54 transitions. [2022-07-14 15:07:01,540 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46 states and 54 transitions. [2022-07-14 15:07:01,541 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46 to 28. [2022-07-14 15:07:01,541 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28 states, 28 states have (on average 1.1785714285714286) internal successors, (33), 27 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:01,541 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 33 transitions. [2022-07-14 15:07:01,541 INFO L392 hiAutomatonCegarLoop]: Abstraction has 28 states and 33 transitions. [2022-07-14 15:07:01,541 INFO L374 stractBuchiCegarLoop]: Abstraction has 28 states and 33 transitions. [2022-07-14 15:07:01,542 INFO L287 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-07-14 15:07:01,542 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28 states and 33 transitions. [2022-07-14 15:07:01,542 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:01,542 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:07:01,542 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:07:01,542 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 2, 1, 1, 1, 1, 1, 1] [2022-07-14 15:07:01,542 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-07-14 15:07:01,543 INFO L752 eck$LassoCheckResult]: Stem: 361#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 362#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 367#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 381#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 382#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 370#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 371#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 372#L27-4 main_~i~0#1 := 0; 373#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 378#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 366#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 375#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 380#L34 [2022-07-14 15:07:01,543 INFO L754 eck$LassoCheckResult]: Loop: 380#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 385#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 384#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 380#L34 [2022-07-14 15:07:01,543 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:01,544 INFO L85 PathProgramCache]: Analyzing trace with hash 780817485, now seen corresponding path program 2 times [2022-07-14 15:07:01,544 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:01,544 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1362505153] [2022-07-14 15:07:01,544 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:01,544 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:01,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:01,579 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:01,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:01,608 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:01,609 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:01,609 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 3 times [2022-07-14 15:07:01,609 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:01,609 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [645074608] [2022-07-14 15:07:01,609 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:01,609 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:01,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:01,615 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:01,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:01,619 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:01,619 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:01,619 INFO L85 PathProgramCache]: Analyzing trace with hash -209139735, now seen corresponding path program 3 times [2022-07-14 15:07:01,619 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:01,619 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1144953236] [2022-07-14 15:07:01,619 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:01,619 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:01,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:07:01,666 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 1 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:01,666 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:07:01,666 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1144953236] [2022-07-14 15:07:01,666 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1144953236] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:07:01,666 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [145576292] [2022-07-14 15:07:01,666 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-07-14 15:07:01,667 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:07:01,667 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:07:01,668 INFO L229 MonitoredProcess]: Starting monitored process 14 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:07:01,669 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2022-07-14 15:07:01,703 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2022-07-14 15:07:01,703 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-07-14 15:07:01,704 INFO L263 TraceCheckSpWp]: Trace formula consists of 87 conjuncts, 8 conjunts are in the unsatisfiable core [2022-07-14 15:07:01,705 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:07:01,765 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 5 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:01,765 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:07:01,798 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 5 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:01,799 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [145576292] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:07:01,799 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:07:01,799 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8] total 13 [2022-07-14 15:07:01,802 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [546061405] [2022-07-14 15:07:01,802 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:07:01,833 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:07:01,835 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-07-14 15:07:01,835 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=129, Unknown=0, NotChecked=0, Total=182 [2022-07-14 15:07:01,836 INFO L87 Difference]: Start difference. First operand 28 states and 33 transitions. cyclomatic complexity: 8 Second operand has 14 states, 13 states have (on average 2.3076923076923075) internal successors, (30), 14 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:01,981 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:07:01,981 INFO L93 Difference]: Finished difference Result 89 states and 104 transitions. [2022-07-14 15:07:01,982 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-07-14 15:07:01,982 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 89 states and 104 transitions. [2022-07-14 15:07:01,984 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:01,984 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 89 states to 60 states and 70 transitions. [2022-07-14 15:07:01,984 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 53 [2022-07-14 15:07:01,984 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 53 [2022-07-14 15:07:01,984 INFO L73 IsDeterministic]: Start isDeterministic. Operand 60 states and 70 transitions. [2022-07-14 15:07:01,993 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 15:07:01,994 INFO L369 hiAutomatonCegarLoop]: Abstraction has 60 states and 70 transitions. [2022-07-14 15:07:01,994 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states and 70 transitions. [2022-07-14 15:07:01,998 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 36. [2022-07-14 15:07:02,001 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36 states, 36 states have (on average 1.1666666666666667) internal successors, (42), 35 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:02,002 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 42 transitions. [2022-07-14 15:07:02,002 INFO L392 hiAutomatonCegarLoop]: Abstraction has 36 states and 42 transitions. [2022-07-14 15:07:02,002 INFO L374 stractBuchiCegarLoop]: Abstraction has 36 states and 42 transitions. [2022-07-14 15:07:02,003 INFO L287 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-07-14 15:07:02,003 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 36 states and 42 transitions. [2022-07-14 15:07:02,006 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:02,007 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:07:02,007 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:07:02,008 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 3, 2, 2, 1, 1, 1, 1] [2022-07-14 15:07:02,010 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-07-14 15:07:02,010 INFO L752 eck$LassoCheckResult]: Stem: 587#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 588#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 593#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 604#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 605#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 596#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 597#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 608#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 607#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 598#L27-4 main_~i~0#1 := 0; 599#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 603#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 592#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 600#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 618#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 616#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 615#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 610#L34 [2022-07-14 15:07:02,010 INFO L754 eck$LassoCheckResult]: Loop: 610#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 611#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 609#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 610#L34 [2022-07-14 15:07:02,010 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:02,011 INFO L85 PathProgramCache]: Analyzing trace with hash -286749017, now seen corresponding path program 4 times [2022-07-14 15:07:02,011 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:02,011 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [353256086] [2022-07-14 15:07:02,011 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:02,011 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:02,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:02,044 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:02,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:02,071 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:02,073 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:02,073 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 4 times [2022-07-14 15:07:02,073 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:02,074 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1252841240] [2022-07-14 15:07:02,074 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:02,074 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:02,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:02,080 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:02,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:02,089 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:02,090 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:02,090 INFO L85 PathProgramCache]: Analyzing trace with hash 150026063, now seen corresponding path program 5 times [2022-07-14 15:07:02,090 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:02,090 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [709026008] [2022-07-14 15:07:02,091 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:02,091 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:02,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:07:02,159 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 5 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:02,159 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:07:02,159 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [709026008] [2022-07-14 15:07:02,159 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [709026008] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:07:02,159 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [422505805] [2022-07-14 15:07:02,159 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-07-14 15:07:02,159 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:07:02,159 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:07:02,164 INFO L229 MonitoredProcess]: Starting monitored process 15 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:07:02,166 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2022-07-14 15:07:02,211 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2022-07-14 15:07:02,211 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-07-14 15:07:02,212 INFO L263 TraceCheckSpWp]: Trace formula consists of 108 conjuncts, 10 conjunts are in the unsatisfiable core [2022-07-14 15:07:02,213 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:07:02,309 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 12 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:02,309 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:07:02,342 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 12 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:02,342 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [422505805] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:07:02,342 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:07:02,342 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10] total 16 [2022-07-14 15:07:02,342 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [872399554] [2022-07-14 15:07:02,342 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:07:02,383 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:07:02,384 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2022-07-14 15:07:02,384 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=75, Invalid=197, Unknown=0, NotChecked=0, Total=272 [2022-07-14 15:07:02,384 INFO L87 Difference]: Start difference. First operand 36 states and 42 transitions. cyclomatic complexity: 9 Second operand has 17 states, 16 states have (on average 2.375) internal successors, (38), 17 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:02,527 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:07:02,527 INFO L93 Difference]: Finished difference Result 115 states and 134 transitions. [2022-07-14 15:07:02,528 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-07-14 15:07:02,528 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 115 states and 134 transitions. [2022-07-14 15:07:02,529 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:02,530 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 115 states to 74 states and 86 transitions. [2022-07-14 15:07:02,530 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 65 [2022-07-14 15:07:02,530 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 65 [2022-07-14 15:07:02,530 INFO L73 IsDeterministic]: Start isDeterministic. Operand 74 states and 86 transitions. [2022-07-14 15:07:02,530 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 15:07:02,530 INFO L369 hiAutomatonCegarLoop]: Abstraction has 74 states and 86 transitions. [2022-07-14 15:07:02,530 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74 states and 86 transitions. [2022-07-14 15:07:02,532 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74 to 44. [2022-07-14 15:07:02,532 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44 states, 44 states have (on average 1.1590909090909092) internal successors, (51), 43 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:02,532 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 51 transitions. [2022-07-14 15:07:02,532 INFO L392 hiAutomatonCegarLoop]: Abstraction has 44 states and 51 transitions. [2022-07-14 15:07:02,532 INFO L374 stractBuchiCegarLoop]: Abstraction has 44 states and 51 transitions. [2022-07-14 15:07:02,532 INFO L287 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-07-14 15:07:02,532 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44 states and 51 transitions. [2022-07-14 15:07:02,533 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:02,533 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:07:02,533 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:07:02,533 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 4, 3, 3, 1, 1, 1, 1] [2022-07-14 15:07:02,533 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-07-14 15:07:02,533 INFO L752 eck$LassoCheckResult]: Stem: 882#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 883#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 888#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 902#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 903#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 891#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 892#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 911#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 910#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 906#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 905#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 893#L27-4 main_~i~0#1 := 0; 894#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 922#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 920#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 919#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 899#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 887#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 896#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 901#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 916#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 915#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 908#L34 [2022-07-14 15:07:02,533 INFO L754 eck$LassoCheckResult]: Loop: 908#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 909#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 907#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 908#L34 [2022-07-14 15:07:02,533 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:02,534 INFO L85 PathProgramCache]: Analyzing trace with hash 1958082385, now seen corresponding path program 6 times [2022-07-14 15:07:02,534 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:02,534 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [530629043] [2022-07-14 15:07:02,534 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:02,534 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:02,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:02,565 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:02,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:02,579 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:02,586 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:02,586 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 5 times [2022-07-14 15:07:02,587 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:02,587 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [292060658] [2022-07-14 15:07:02,588 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:02,588 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:02,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:02,591 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:02,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:02,594 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:02,595 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:02,595 INFO L85 PathProgramCache]: Analyzing trace with hash -1013442971, now seen corresponding path program 7 times [2022-07-14 15:07:02,595 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:02,595 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [100462758] [2022-07-14 15:07:02,595 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:02,596 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:02,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:07:02,685 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 12 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:02,686 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:07:02,687 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [100462758] [2022-07-14 15:07:02,687 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [100462758] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:07:02,687 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1963914744] [2022-07-14 15:07:02,687 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-07-14 15:07:02,688 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:07:02,688 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:07:02,695 INFO L229 MonitoredProcess]: Starting monitored process 16 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:07:02,696 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2022-07-14 15:07:02,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:07:02,736 INFO L263 TraceCheckSpWp]: Trace formula consists of 129 conjuncts, 12 conjunts are in the unsatisfiable core [2022-07-14 15:07:02,737 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:07:02,829 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 22 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:02,829 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:07:02,879 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 22 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:02,879 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1963914744] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:07:02,879 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:07:02,879 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12] total 19 [2022-07-14 15:07:02,879 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1602385422] [2022-07-14 15:07:02,879 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:07:02,910 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:07:02,910 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2022-07-14 15:07:02,911 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=101, Invalid=279, Unknown=0, NotChecked=0, Total=380 [2022-07-14 15:07:02,911 INFO L87 Difference]: Start difference. First operand 44 states and 51 transitions. cyclomatic complexity: 10 Second operand has 20 states, 19 states have (on average 2.4210526315789473) internal successors, (46), 20 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:03,073 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:07:03,074 INFO L93 Difference]: Finished difference Result 141 states and 164 transitions. [2022-07-14 15:07:03,074 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2022-07-14 15:07:03,074 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 141 states and 164 transitions. [2022-07-14 15:07:03,075 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:03,076 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 141 states to 88 states and 102 transitions. [2022-07-14 15:07:03,076 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 77 [2022-07-14 15:07:03,076 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 77 [2022-07-14 15:07:03,076 INFO L73 IsDeterministic]: Start isDeterministic. Operand 88 states and 102 transitions. [2022-07-14 15:07:03,076 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 15:07:03,076 INFO L369 hiAutomatonCegarLoop]: Abstraction has 88 states and 102 transitions. [2022-07-14 15:07:03,077 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88 states and 102 transitions. [2022-07-14 15:07:03,078 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88 to 52. [2022-07-14 15:07:03,078 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 52 states, 52 states have (on average 1.1538461538461537) internal successors, (60), 51 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:03,079 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 60 transitions. [2022-07-14 15:07:03,079 INFO L392 hiAutomatonCegarLoop]: Abstraction has 52 states and 60 transitions. [2022-07-14 15:07:03,079 INFO L374 stractBuchiCegarLoop]: Abstraction has 52 states and 60 transitions. [2022-07-14 15:07:03,079 INFO L287 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-07-14 15:07:03,079 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 52 states and 60 transitions. [2022-07-14 15:07:03,079 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:03,079 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:07:03,079 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:07:03,080 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 5, 4, 4, 1, 1, 1, 1] [2022-07-14 15:07:03,080 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-07-14 15:07:03,080 INFO L752 eck$LassoCheckResult]: Stem: 1246#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 1247#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 1252#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1266#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1267#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1255#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1256#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1277#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1276#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1275#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1274#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1270#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1269#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 1257#L27-4 main_~i~0#1 := 0; 1258#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1290#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1287#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1285#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1286#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1294#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1293#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1263#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1251#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1260#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1265#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1282#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1281#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1272#L34 [2022-07-14 15:07:03,080 INFO L754 eck$LassoCheckResult]: Loop: 1272#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1273#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1271#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1272#L34 [2022-07-14 15:07:03,080 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:03,080 INFO L85 PathProgramCache]: Analyzing trace with hash -1204484189, now seen corresponding path program 8 times [2022-07-14 15:07:03,080 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:03,080 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1532573918] [2022-07-14 15:07:03,080 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:03,080 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:03,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:03,099 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:03,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:03,123 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:03,124 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:03,124 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 6 times [2022-07-14 15:07:03,124 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:03,124 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1216572505] [2022-07-14 15:07:03,124 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:03,124 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:03,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:03,126 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:03,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:03,129 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:03,129 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:03,129 INFO L85 PathProgramCache]: Analyzing trace with hash 1663323347, now seen corresponding path program 9 times [2022-07-14 15:07:03,129 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:03,129 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [773675894] [2022-07-14 15:07:03,129 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:03,129 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:03,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:07:03,234 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 22 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:03,234 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:07:03,234 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [773675894] [2022-07-14 15:07:03,234 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [773675894] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:07:03,234 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1162033175] [2022-07-14 15:07:03,234 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-07-14 15:07:03,235 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:07:03,235 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:07:03,246 INFO L229 MonitoredProcess]: Starting monitored process 17 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:07:03,247 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2022-07-14 15:07:03,299 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2022-07-14 15:07:03,299 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-07-14 15:07:03,300 INFO L263 TraceCheckSpWp]: Trace formula consists of 150 conjuncts, 14 conjunts are in the unsatisfiable core [2022-07-14 15:07:03,301 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:07:03,424 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 35 proven. 25 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:03,424 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:07:03,483 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 35 proven. 25 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:03,483 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1162033175] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:07:03,484 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:07:03,484 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14] total 22 [2022-07-14 15:07:03,484 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1383773216] [2022-07-14 15:07:03,484 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:07:03,512 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:07:03,513 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2022-07-14 15:07:03,513 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=131, Invalid=375, Unknown=0, NotChecked=0, Total=506 [2022-07-14 15:07:03,515 INFO L87 Difference]: Start difference. First operand 52 states and 60 transitions. cyclomatic complexity: 11 Second operand has 23 states, 22 states have (on average 2.4545454545454546) internal successors, (54), 23 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:03,727 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:07:03,727 INFO L93 Difference]: Finished difference Result 167 states and 194 transitions. [2022-07-14 15:07:03,728 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2022-07-14 15:07:03,728 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 167 states and 194 transitions. [2022-07-14 15:07:03,729 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:03,730 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 167 states to 102 states and 118 transitions. [2022-07-14 15:07:03,730 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 89 [2022-07-14 15:07:03,730 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 89 [2022-07-14 15:07:03,730 INFO L73 IsDeterministic]: Start isDeterministic. Operand 102 states and 118 transitions. [2022-07-14 15:07:03,730 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 15:07:03,730 INFO L369 hiAutomatonCegarLoop]: Abstraction has 102 states and 118 transitions. [2022-07-14 15:07:03,730 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102 states and 118 transitions. [2022-07-14 15:07:03,732 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102 to 60. [2022-07-14 15:07:03,734 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 60 states, 60 states have (on average 1.15) internal successors, (69), 59 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:03,735 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 69 transitions. [2022-07-14 15:07:03,735 INFO L392 hiAutomatonCegarLoop]: Abstraction has 60 states and 69 transitions. [2022-07-14 15:07:03,735 INFO L374 stractBuchiCegarLoop]: Abstraction has 60 states and 69 transitions. [2022-07-14 15:07:03,735 INFO L287 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-07-14 15:07:03,735 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 60 states and 69 transitions. [2022-07-14 15:07:03,736 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:03,736 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:07:03,736 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:07:03,737 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 6, 5, 5, 1, 1, 1, 1] [2022-07-14 15:07:03,737 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-07-14 15:07:03,737 INFO L752 eck$LassoCheckResult]: Stem: 1679#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 1680#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 1685#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1699#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1700#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1688#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1689#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1712#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1711#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1710#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1709#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1708#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1707#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1703#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1702#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 1690#L27-4 main_~i~0#1 := 0; 1691#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1733#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1722#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1720#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1721#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1725#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1731#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1730#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1729#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1728#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1696#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1684#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1693#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1698#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1717#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1716#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1705#L34 [2022-07-14 15:07:03,737 INFO L754 eck$LassoCheckResult]: Loop: 1705#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1706#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1704#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1705#L34 [2022-07-14 15:07:03,738 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:03,738 INFO L85 PathProgramCache]: Analyzing trace with hash -1715309995, now seen corresponding path program 10 times [2022-07-14 15:07:03,738 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:03,738 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1507029935] [2022-07-14 15:07:03,738 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:03,738 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:03,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:03,784 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:03,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:03,813 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:03,814 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:03,814 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 7 times [2022-07-14 15:07:03,814 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:03,814 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [494929343] [2022-07-14 15:07:03,814 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:03,814 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:03,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:03,823 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:03,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:03,826 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:03,827 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:03,827 INFO L85 PathProgramCache]: Analyzing trace with hash 720866529, now seen corresponding path program 11 times [2022-07-14 15:07:03,827 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:03,827 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [137288960] [2022-07-14 15:07:03,827 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:03,827 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:03,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:07:03,943 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 35 proven. 52 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:03,943 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:07:03,944 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [137288960] [2022-07-14 15:07:03,944 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [137288960] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:07:03,944 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1466751776] [2022-07-14 15:07:03,944 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-07-14 15:07:03,944 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:07:03,944 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:07:03,945 INFO L229 MonitoredProcess]: Starting monitored process 18 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:07:03,946 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2022-07-14 15:07:04,018 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2022-07-14 15:07:04,018 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-07-14 15:07:04,019 INFO L263 TraceCheckSpWp]: Trace formula consists of 171 conjuncts, 16 conjunts are in the unsatisfiable core [2022-07-14 15:07:04,020 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:07:04,181 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 51 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:04,182 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:07:04,237 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 51 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:04,237 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1466751776] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:07:04,238 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:07:04,238 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16] total 25 [2022-07-14 15:07:04,238 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2031098480] [2022-07-14 15:07:04,238 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:07:04,268 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:07:04,268 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2022-07-14 15:07:04,269 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=165, Invalid=485, Unknown=0, NotChecked=0, Total=650 [2022-07-14 15:07:04,269 INFO L87 Difference]: Start difference. First operand 60 states and 69 transitions. cyclomatic complexity: 12 Second operand has 26 states, 25 states have (on average 2.48) internal successors, (62), 26 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:04,489 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:07:04,489 INFO L93 Difference]: Finished difference Result 193 states and 224 transitions. [2022-07-14 15:07:04,490 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2022-07-14 15:07:04,490 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 193 states and 224 transitions. [2022-07-14 15:07:04,491 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:04,492 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 193 states to 116 states and 134 transitions. [2022-07-14 15:07:04,492 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 101 [2022-07-14 15:07:04,492 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 101 [2022-07-14 15:07:04,492 INFO L73 IsDeterministic]: Start isDeterministic. Operand 116 states and 134 transitions. [2022-07-14 15:07:04,493 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 15:07:04,493 INFO L369 hiAutomatonCegarLoop]: Abstraction has 116 states and 134 transitions. [2022-07-14 15:07:04,493 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 116 states and 134 transitions. [2022-07-14 15:07:04,495 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 116 to 68. [2022-07-14 15:07:04,495 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 68 states, 68 states have (on average 1.1470588235294117) internal successors, (78), 67 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:04,495 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68 states to 68 states and 78 transitions. [2022-07-14 15:07:04,495 INFO L392 hiAutomatonCegarLoop]: Abstraction has 68 states and 78 transitions. [2022-07-14 15:07:04,495 INFO L374 stractBuchiCegarLoop]: Abstraction has 68 states and 78 transitions. [2022-07-14 15:07:04,495 INFO L287 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-07-14 15:07:04,495 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 68 states and 78 transitions. [2022-07-14 15:07:04,496 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:04,496 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:07:04,496 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:07:04,496 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 7, 7, 6, 6, 1, 1, 1, 1] [2022-07-14 15:07:04,496 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-07-14 15:07:04,496 INFO L752 eck$LassoCheckResult]: Stem: 2181#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 2182#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 2187#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2202#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2203#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2190#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2191#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2217#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2216#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2215#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2214#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2213#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2212#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2211#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2210#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2206#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2205#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 2192#L27-4 main_~i~0#1 := 0; 2193#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2225#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2226#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2227#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2231#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2230#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2243#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2240#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2238#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2237#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2235#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2234#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2233#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2199#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2186#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2196#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2201#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2222#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2221#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2208#L34 [2022-07-14 15:07:04,496 INFO L754 eck$LassoCheckResult]: Loop: 2208#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2209#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2207#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2208#L34 [2022-07-14 15:07:04,497 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:04,497 INFO L85 PathProgramCache]: Analyzing trace with hash 1748928671, now seen corresponding path program 12 times [2022-07-14 15:07:04,497 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:04,497 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1203610693] [2022-07-14 15:07:04,497 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:04,497 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:04,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:04,516 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:04,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:04,545 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:04,545 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:04,545 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 8 times [2022-07-14 15:07:04,545 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:04,545 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [774715907] [2022-07-14 15:07:04,545 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:04,546 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:04,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:04,551 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:04,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:04,554 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:04,554 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:04,554 INFO L85 PathProgramCache]: Analyzing trace with hash 85809751, now seen corresponding path program 13 times [2022-07-14 15:07:04,554 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:04,556 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1047987098] [2022-07-14 15:07:04,556 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:04,556 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:04,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:07:04,693 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 51 proven. 68 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:04,693 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:07:04,693 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1047987098] [2022-07-14 15:07:04,693 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1047987098] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:07:04,693 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [766490679] [2022-07-14 15:07:04,693 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-07-14 15:07:04,694 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:07:04,694 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:07:04,695 INFO L229 MonitoredProcess]: Starting monitored process 19 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:07:04,696 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2022-07-14 15:07:04,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:07:04,752 INFO L263 TraceCheckSpWp]: Trace formula consists of 192 conjuncts, 18 conjunts are in the unsatisfiable core [2022-07-14 15:07:04,754 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:07:04,939 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 70 proven. 49 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:04,940 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:07:05,005 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 70 proven. 49 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:05,006 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [766490679] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:07:05,006 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:07:05,006 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18] total 28 [2022-07-14 15:07:05,006 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [170225146] [2022-07-14 15:07:05,006 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:07:05,038 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:07:05,039 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2022-07-14 15:07:05,039 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=203, Invalid=609, Unknown=0, NotChecked=0, Total=812 [2022-07-14 15:07:05,039 INFO L87 Difference]: Start difference. First operand 68 states and 78 transitions. cyclomatic complexity: 13 Second operand has 29 states, 28 states have (on average 2.5) internal successors, (70), 29 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:05,349 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:07:05,349 INFO L93 Difference]: Finished difference Result 219 states and 254 transitions. [2022-07-14 15:07:05,349 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2022-07-14 15:07:05,350 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 219 states and 254 transitions. [2022-07-14 15:07:05,352 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:05,353 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 219 states to 130 states and 150 transitions. [2022-07-14 15:07:05,353 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 113 [2022-07-14 15:07:05,353 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 113 [2022-07-14 15:07:05,353 INFO L73 IsDeterministic]: Start isDeterministic. Operand 130 states and 150 transitions. [2022-07-14 15:07:05,353 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 15:07:05,353 INFO L369 hiAutomatonCegarLoop]: Abstraction has 130 states and 150 transitions. [2022-07-14 15:07:05,354 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 130 states and 150 transitions. [2022-07-14 15:07:05,356 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 130 to 76. [2022-07-14 15:07:05,356 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 76 states, 76 states have (on average 1.144736842105263) internal successors, (87), 75 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:05,357 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76 states to 76 states and 87 transitions. [2022-07-14 15:07:05,357 INFO L392 hiAutomatonCegarLoop]: Abstraction has 76 states and 87 transitions. [2022-07-14 15:07:05,357 INFO L374 stractBuchiCegarLoop]: Abstraction has 76 states and 87 transitions. [2022-07-14 15:07:05,357 INFO L287 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-07-14 15:07:05,357 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 76 states and 87 transitions. [2022-07-14 15:07:05,357 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:05,358 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:07:05,358 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:07:05,359 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 8, 7, 7, 1, 1, 1, 1] [2022-07-14 15:07:05,359 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-07-14 15:07:05,359 INFO L752 eck$LassoCheckResult]: Stem: 2752#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 2753#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 2758#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2772#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2773#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2761#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2762#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2789#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2788#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2787#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2786#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2785#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2784#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2783#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2782#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2781#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2780#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2776#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2775#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 2763#L27-4 main_~i~0#1 := 0; 2764#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2823#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2799#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2797#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2798#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2802#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2822#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2819#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2817#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2816#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2813#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2811#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2810#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2808#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2806#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2805#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2769#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2757#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2766#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2771#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2794#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2793#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2778#L34 [2022-07-14 15:07:05,359 INFO L754 eck$LassoCheckResult]: Loop: 2778#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2779#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2777#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2778#L34 [2022-07-14 15:07:05,360 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:05,360 INFO L85 PathProgramCache]: Analyzing trace with hash -1204550311, now seen corresponding path program 14 times [2022-07-14 15:07:05,360 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:05,360 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [993408158] [2022-07-14 15:07:05,360 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:05,360 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:05,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:05,389 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:05,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:05,432 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:05,432 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:05,433 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 9 times [2022-07-14 15:07:05,433 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:05,433 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [786287150] [2022-07-14 15:07:05,433 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:05,433 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:05,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:05,435 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:05,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:05,437 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:05,437 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:05,437 INFO L85 PathProgramCache]: Analyzing trace with hash -306517155, now seen corresponding path program 15 times [2022-07-14 15:07:05,438 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:05,438 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1621505899] [2022-07-14 15:07:05,438 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:05,438 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:05,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:07:05,586 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 70 proven. 86 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:05,586 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:07:05,586 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1621505899] [2022-07-14 15:07:05,586 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1621505899] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:07:05,587 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1495708274] [2022-07-14 15:07:05,587 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-07-14 15:07:05,587 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:07:05,587 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:07:05,589 INFO L229 MonitoredProcess]: Starting monitored process 20 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:07:05,592 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2022-07-14 15:07:05,695 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2022-07-14 15:07:05,695 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-07-14 15:07:05,696 INFO L263 TraceCheckSpWp]: Trace formula consists of 213 conjuncts, 20 conjunts are in the unsatisfiable core [2022-07-14 15:07:05,697 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:07:05,906 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 92 proven. 64 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:05,906 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:07:05,976 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 92 proven. 64 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:05,976 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1495708274] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:07:05,976 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:07:05,976 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20] total 31 [2022-07-14 15:07:05,976 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1177130382] [2022-07-14 15:07:05,976 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:07:06,005 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:07:06,006 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2022-07-14 15:07:06,006 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=245, Invalid=747, Unknown=0, NotChecked=0, Total=992 [2022-07-14 15:07:06,006 INFO L87 Difference]: Start difference. First operand 76 states and 87 transitions. cyclomatic complexity: 14 Second operand has 32 states, 31 states have (on average 2.5161290322580645) internal successors, (78), 32 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:06,328 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:07:06,328 INFO L93 Difference]: Finished difference Result 245 states and 284 transitions. [2022-07-14 15:07:06,329 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2022-07-14 15:07:06,329 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 245 states and 284 transitions. [2022-07-14 15:07:06,330 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:06,331 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 245 states to 144 states and 166 transitions. [2022-07-14 15:07:06,331 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 125 [2022-07-14 15:07:06,331 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 125 [2022-07-14 15:07:06,331 INFO L73 IsDeterministic]: Start isDeterministic. Operand 144 states and 166 transitions. [2022-07-14 15:07:06,331 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 15:07:06,332 INFO L369 hiAutomatonCegarLoop]: Abstraction has 144 states and 166 transitions. [2022-07-14 15:07:06,332 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144 states and 166 transitions. [2022-07-14 15:07:06,333 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144 to 84. [2022-07-14 15:07:06,334 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 84 states, 84 states have (on average 1.1428571428571428) internal successors, (96), 83 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:06,334 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 96 transitions. [2022-07-14 15:07:06,334 INFO L392 hiAutomatonCegarLoop]: Abstraction has 84 states and 96 transitions. [2022-07-14 15:07:06,334 INFO L374 stractBuchiCegarLoop]: Abstraction has 84 states and 96 transitions. [2022-07-14 15:07:06,334 INFO L287 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-07-14 15:07:06,334 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 84 states and 96 transitions. [2022-07-14 15:07:06,335 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:06,335 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:07:06,335 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:07:06,335 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 9, 9, 8, 8, 1, 1, 1, 1] [2022-07-14 15:07:06,335 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-07-14 15:07:06,335 INFO L752 eck$LassoCheckResult]: Stem: 3392#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 3393#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 3398#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3413#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3414#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3401#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3402#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3432#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3431#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3430#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3429#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3428#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3427#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3426#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3425#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3424#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3423#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3422#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3421#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3417#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3416#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 3403#L27-4 main_~i~0#1 := 0; 3404#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3440#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3441#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3442#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3446#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3445#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3470#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3467#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3465#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3464#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3461#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3459#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3458#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3455#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3453#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3452#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3450#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3449#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3448#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3410#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3397#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3407#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3412#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3437#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3436#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3419#L34 [2022-07-14 15:07:06,335 INFO L754 eck$LassoCheckResult]: Loop: 3419#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3420#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3418#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3419#L34 [2022-07-14 15:07:06,336 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:06,336 INFO L85 PathProgramCache]: Analyzing trace with hash -2004823653, now seen corresponding path program 16 times [2022-07-14 15:07:06,336 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:06,336 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [835478141] [2022-07-14 15:07:06,336 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:06,336 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:06,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:06,362 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:06,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:06,395 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:06,395 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:06,396 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 10 times [2022-07-14 15:07:06,396 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:06,396 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1694185978] [2022-07-14 15:07:06,396 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:06,396 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:06,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:06,398 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:06,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:06,401 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:06,401 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:06,401 INFO L85 PathProgramCache]: Analyzing trace with hash 113811419, now seen corresponding path program 17 times [2022-07-14 15:07:06,401 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:06,401 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1945396343] [2022-07-14 15:07:06,402 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:06,402 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:06,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:07:06,558 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 92 proven. 106 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:06,558 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:07:06,558 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1945396343] [2022-07-14 15:07:06,558 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1945396343] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:07:06,558 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1558845011] [2022-07-14 15:07:06,558 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-07-14 15:07:06,558 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:07:06,558 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:07:06,560 INFO L229 MonitoredProcess]: Starting monitored process 21 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:07:06,561 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2022-07-14 15:07:06,692 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2022-07-14 15:07:06,692 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-07-14 15:07:06,694 INFO L263 TraceCheckSpWp]: Trace formula consists of 234 conjuncts, 22 conjunts are in the unsatisfiable core [2022-07-14 15:07:06,695 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:07:06,948 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 117 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:06,948 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:07:07,040 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 117 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:07,040 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1558845011] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:07:07,040 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:07:07,040 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22, 22] total 34 [2022-07-14 15:07:07,041 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [936762161] [2022-07-14 15:07:07,041 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:07:07,072 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:07:07,072 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2022-07-14 15:07:07,072 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=291, Invalid=899, Unknown=0, NotChecked=0, Total=1190 [2022-07-14 15:07:07,073 INFO L87 Difference]: Start difference. First operand 84 states and 96 transitions. cyclomatic complexity: 15 Second operand has 35 states, 34 states have (on average 2.5294117647058822) internal successors, (86), 35 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:07,414 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:07:07,414 INFO L93 Difference]: Finished difference Result 271 states and 314 transitions. [2022-07-14 15:07:07,414 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2022-07-14 15:07:07,415 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 271 states and 314 transitions. [2022-07-14 15:07:07,416 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:07,417 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 271 states to 158 states and 182 transitions. [2022-07-14 15:07:07,417 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 137 [2022-07-14 15:07:07,417 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 137 [2022-07-14 15:07:07,417 INFO L73 IsDeterministic]: Start isDeterministic. Operand 158 states and 182 transitions. [2022-07-14 15:07:07,417 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 15:07:07,417 INFO L369 hiAutomatonCegarLoop]: Abstraction has 158 states and 182 transitions. [2022-07-14 15:07:07,417 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 158 states and 182 transitions. [2022-07-14 15:07:07,424 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 158 to 92. [2022-07-14 15:07:07,426 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 92 states, 92 states have (on average 1.141304347826087) internal successors, (105), 91 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:07,427 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92 states to 92 states and 105 transitions. [2022-07-14 15:07:07,430 INFO L392 hiAutomatonCegarLoop]: Abstraction has 92 states and 105 transitions. [2022-07-14 15:07:07,430 INFO L374 stractBuchiCegarLoop]: Abstraction has 92 states and 105 transitions. [2022-07-14 15:07:07,430 INFO L287 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-07-14 15:07:07,431 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 92 states and 105 transitions. [2022-07-14 15:07:07,431 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:07,432 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:07:07,432 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:07:07,432 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 10, 9, 9, 1, 1, 1, 1] [2022-07-14 15:07:07,435 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-07-14 15:07:07,435 INFO L752 eck$LassoCheckResult]: Stem: 4101#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 4102#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 4107#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4121#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4122#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4110#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4111#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4142#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4141#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4140#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4139#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4138#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4137#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4136#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4135#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4134#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4133#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4132#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4131#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4130#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4129#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4125#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4124#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 4112#L27-4 main_~i~0#1 := 0; 4113#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4187#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4152#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4150#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4151#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4155#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4185#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4182#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4180#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4179#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4176#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4174#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4173#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4170#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4168#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4167#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4164#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4162#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4161#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4160#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4159#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4158#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4118#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4106#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4115#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4120#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4147#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4146#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4127#L34 [2022-07-14 15:07:07,435 INFO L754 eck$LassoCheckResult]: Loop: 4127#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4128#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4126#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4127#L34 [2022-07-14 15:07:07,436 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:07,436 INFO L85 PathProgramCache]: Analyzing trace with hash 1133441117, now seen corresponding path program 18 times [2022-07-14 15:07:07,436 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:07,436 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [510028319] [2022-07-14 15:07:07,436 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:07,436 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:07,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:07,468 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:07,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:07,497 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:07,498 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:07,498 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 11 times [2022-07-14 15:07:07,498 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:07,498 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [926595221] [2022-07-14 15:07:07,498 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:07,498 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:07,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:07,503 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:07,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:07,506 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:07,506 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:07,506 INFO L85 PathProgramCache]: Analyzing trace with hash -688524839, now seen corresponding path program 19 times [2022-07-14 15:07:07,506 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:07,506 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [177556164] [2022-07-14 15:07:07,507 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:07,507 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:07,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:07:07,717 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 117 proven. 128 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:07,717 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:07:07,717 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [177556164] [2022-07-14 15:07:07,717 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [177556164] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:07:07,717 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1820467011] [2022-07-14 15:07:07,717 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-07-14 15:07:07,717 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:07:07,718 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:07:07,719 INFO L229 MonitoredProcess]: Starting monitored process 22 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:07:07,732 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2022-07-14 15:07:07,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:07:07,795 INFO L263 TraceCheckSpWp]: Trace formula consists of 255 conjuncts, 24 conjunts are in the unsatisfiable core [2022-07-14 15:07:07,796 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:07:08,092 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 145 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:08,092 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:07:08,179 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 145 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:08,179 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1820467011] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:07:08,179 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:07:08,179 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24] total 37 [2022-07-14 15:07:08,180 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1930788966] [2022-07-14 15:07:08,180 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:07:08,212 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:07:08,213 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2022-07-14 15:07:08,213 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=341, Invalid=1065, Unknown=0, NotChecked=0, Total=1406 [2022-07-14 15:07:08,213 INFO L87 Difference]: Start difference. First operand 92 states and 105 transitions. cyclomatic complexity: 16 Second operand has 38 states, 37 states have (on average 2.5405405405405403) internal successors, (94), 38 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:08,603 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:07:08,603 INFO L93 Difference]: Finished difference Result 297 states and 344 transitions. [2022-07-14 15:07:08,603 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2022-07-14 15:07:08,604 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 297 states and 344 transitions. [2022-07-14 15:07:08,606 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:08,607 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 297 states to 172 states and 198 transitions. [2022-07-14 15:07:08,607 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 149 [2022-07-14 15:07:08,607 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 149 [2022-07-14 15:07:08,607 INFO L73 IsDeterministic]: Start isDeterministic. Operand 172 states and 198 transitions. [2022-07-14 15:07:08,607 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 15:07:08,607 INFO L369 hiAutomatonCegarLoop]: Abstraction has 172 states and 198 transitions. [2022-07-14 15:07:08,608 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 172 states and 198 transitions. [2022-07-14 15:07:08,610 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 172 to 100. [2022-07-14 15:07:08,610 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 100 states, 100 states have (on average 1.14) internal successors, (114), 99 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:08,610 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100 states to 100 states and 114 transitions. [2022-07-14 15:07:08,610 INFO L392 hiAutomatonCegarLoop]: Abstraction has 100 states and 114 transitions. [2022-07-14 15:07:08,610 INFO L374 stractBuchiCegarLoop]: Abstraction has 100 states and 114 transitions. [2022-07-14 15:07:08,610 INFO L287 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-07-14 15:07:08,610 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 100 states and 114 transitions. [2022-07-14 15:07:08,611 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:08,611 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:07:08,611 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:07:08,611 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 11, 11, 10, 10, 1, 1, 1, 1] [2022-07-14 15:07:08,611 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-07-14 15:07:08,611 INFO L752 eck$LassoCheckResult]: Stem: 4879#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 4880#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 4885#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4900#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4901#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4888#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4889#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4923#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4922#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4921#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4920#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4919#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4918#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4917#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4916#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4915#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4914#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4913#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4912#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4911#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4910#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4909#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4908#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4904#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4903#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 4890#L27-4 main_~i~0#1 := 0; 4891#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4931#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4932#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4933#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4937#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4936#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4973#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4970#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4968#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4967#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4964#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4962#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4961#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4958#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4956#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4955#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4952#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4950#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4949#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4946#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4944#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4943#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4941#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4940#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4939#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4897#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4884#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4894#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4899#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4928#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4927#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4906#L34 [2022-07-14 15:07:08,611 INFO L754 eck$LassoCheckResult]: Loop: 4906#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4907#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4905#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4906#L34 [2022-07-14 15:07:08,612 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:08,612 INFO L85 PathProgramCache]: Analyzing trace with hash 125280919, now seen corresponding path program 20 times [2022-07-14 15:07:08,612 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:08,612 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1703101595] [2022-07-14 15:07:08,612 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:08,612 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:08,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:08,665 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:08,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:08,725 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:08,725 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:08,725 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 12 times [2022-07-14 15:07:08,725 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:08,725 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [395807465] [2022-07-14 15:07:08,725 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:08,726 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:08,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:08,728 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:08,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:08,734 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:08,734 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:08,734 INFO L85 PathProgramCache]: Analyzing trace with hash -82682529, now seen corresponding path program 21 times [2022-07-14 15:07:08,734 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:08,734 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1650544167] [2022-07-14 15:07:08,738 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:08,738 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:08,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:07:09,002 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 145 proven. 152 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:09,002 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:07:09,003 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1650544167] [2022-07-14 15:07:09,003 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1650544167] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:07:09,003 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [922268502] [2022-07-14 15:07:09,003 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-07-14 15:07:09,003 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:07:09,003 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:07:09,005 INFO L229 MonitoredProcess]: Starting monitored process 23 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:07:09,006 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2022-07-14 15:07:09,240 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2022-07-14 15:07:09,240 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-07-14 15:07:09,242 INFO L263 TraceCheckSpWp]: Trace formula consists of 276 conjuncts, 26 conjunts are in the unsatisfiable core [2022-07-14 15:07:09,243 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:07:09,571 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 176 proven. 121 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:09,571 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:07:09,673 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 176 proven. 121 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:09,674 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [922268502] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:07:09,674 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:07:09,674 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26, 26] total 40 [2022-07-14 15:07:09,674 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1510703947] [2022-07-14 15:07:09,674 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:07:09,710 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:07:09,711 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2022-07-14 15:07:09,711 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=395, Invalid=1245, Unknown=0, NotChecked=0, Total=1640 [2022-07-14 15:07:09,712 INFO L87 Difference]: Start difference. First operand 100 states and 114 transitions. cyclomatic complexity: 17 Second operand has 41 states, 40 states have (on average 2.55) internal successors, (102), 41 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:10,149 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:07:10,149 INFO L93 Difference]: Finished difference Result 323 states and 374 transitions. [2022-07-14 15:07:10,150 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2022-07-14 15:07:10,151 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 323 states and 374 transitions. [2022-07-14 15:07:10,152 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:10,153 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 323 states to 186 states and 214 transitions. [2022-07-14 15:07:10,153 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 161 [2022-07-14 15:07:10,153 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 161 [2022-07-14 15:07:10,153 INFO L73 IsDeterministic]: Start isDeterministic. Operand 186 states and 214 transitions. [2022-07-14 15:07:10,153 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 15:07:10,153 INFO L369 hiAutomatonCegarLoop]: Abstraction has 186 states and 214 transitions. [2022-07-14 15:07:10,153 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states and 214 transitions. [2022-07-14 15:07:10,155 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 108. [2022-07-14 15:07:10,155 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 108 states, 108 states have (on average 1.1388888888888888) internal successors, (123), 107 states have internal predecessors, (123), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:10,156 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 123 transitions. [2022-07-14 15:07:10,156 INFO L392 hiAutomatonCegarLoop]: Abstraction has 108 states and 123 transitions. [2022-07-14 15:07:10,156 INFO L374 stractBuchiCegarLoop]: Abstraction has 108 states and 123 transitions. [2022-07-14 15:07:10,156 INFO L287 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-07-14 15:07:10,156 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 108 states and 123 transitions. [2022-07-14 15:07:10,157 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:10,157 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:07:10,157 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:07:10,157 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 12, 12, 11, 11, 1, 1, 1, 1] [2022-07-14 15:07:10,157 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-07-14 15:07:10,157 INFO L752 eck$LassoCheckResult]: Stem: 5726#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 5727#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 5732#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5746#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5747#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5735#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5736#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5771#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5770#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5769#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5768#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5767#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5766#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5765#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5764#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5763#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5762#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5761#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5760#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5759#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5758#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5757#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5756#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5755#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5754#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5750#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5749#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 5737#L27-4 main_~i~0#1 := 0; 5738#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5829#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5781#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5779#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5780#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5784#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5828#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5825#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5823#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5822#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5819#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5817#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5816#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5813#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5811#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5810#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5807#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5805#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5804#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5801#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5799#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5798#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5795#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5793#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5792#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5790#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5788#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5787#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5743#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5731#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5740#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5745#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5776#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5775#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5752#L34 [2022-07-14 15:07:10,159 INFO L754 eck$LassoCheckResult]: Loop: 5752#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5753#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5751#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5752#L34 [2022-07-14 15:07:10,159 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:10,160 INFO L85 PathProgramCache]: Analyzing trace with hash -1940425887, now seen corresponding path program 22 times [2022-07-14 15:07:10,160 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:10,160 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [573660358] [2022-07-14 15:07:10,160 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:10,160 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:10,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:10,191 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:10,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:10,223 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:10,223 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:10,224 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 13 times [2022-07-14 15:07:10,224 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:10,224 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1153819235] [2022-07-14 15:07:10,224 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:10,224 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:10,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:10,226 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:10,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:10,232 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:10,233 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:10,233 INFO L85 PathProgramCache]: Analyzing trace with hash -1262722987, now seen corresponding path program 23 times [2022-07-14 15:07:10,234 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:10,234 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1806461242] [2022-07-14 15:07:10,234 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:10,234 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:10,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:07:10,507 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 176 proven. 178 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:10,507 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:07:10,507 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1806461242] [2022-07-14 15:07:10,507 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1806461242] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:07:10,507 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [298695002] [2022-07-14 15:07:10,507 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-07-14 15:07:10,507 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:07:10,508 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:07:10,509 INFO L229 MonitoredProcess]: Starting monitored process 24 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:07:10,510 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2022-07-14 15:07:10,776 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) [2022-07-14 15:07:10,776 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-07-14 15:07:10,778 INFO L263 TraceCheckSpWp]: Trace formula consists of 297 conjuncts, 28 conjunts are in the unsatisfiable core [2022-07-14 15:07:10,780 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:07:11,149 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 210 proven. 144 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:11,150 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:07:11,267 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 210 proven. 144 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:11,267 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [298695002] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:07:11,267 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:07:11,267 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28, 28] total 43 [2022-07-14 15:07:11,267 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1749678145] [2022-07-14 15:07:11,268 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:07:11,295 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:07:11,296 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2022-07-14 15:07:11,296 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=453, Invalid=1439, Unknown=0, NotChecked=0, Total=1892 [2022-07-14 15:07:11,296 INFO L87 Difference]: Start difference. First operand 108 states and 123 transitions. cyclomatic complexity: 18 Second operand has 44 states, 43 states have (on average 2.558139534883721) internal successors, (110), 44 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:11,712 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:07:11,713 INFO L93 Difference]: Finished difference Result 349 states and 404 transitions. [2022-07-14 15:07:11,713 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2022-07-14 15:07:11,713 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 349 states and 404 transitions. [2022-07-14 15:07:11,715 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:11,716 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 349 states to 200 states and 230 transitions. [2022-07-14 15:07:11,716 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 173 [2022-07-14 15:07:11,716 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 173 [2022-07-14 15:07:11,716 INFO L73 IsDeterministic]: Start isDeterministic. Operand 200 states and 230 transitions. [2022-07-14 15:07:11,716 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 15:07:11,716 INFO L369 hiAutomatonCegarLoop]: Abstraction has 200 states and 230 transitions. [2022-07-14 15:07:11,716 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 200 states and 230 transitions. [2022-07-14 15:07:11,718 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 200 to 116. [2022-07-14 15:07:11,718 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 116 states, 116 states have (on average 1.1379310344827587) internal successors, (132), 115 states have internal predecessors, (132), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:11,718 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 116 states to 116 states and 132 transitions. [2022-07-14 15:07:11,718 INFO L392 hiAutomatonCegarLoop]: Abstraction has 116 states and 132 transitions. [2022-07-14 15:07:11,718 INFO L374 stractBuchiCegarLoop]: Abstraction has 116 states and 132 transitions. [2022-07-14 15:07:11,718 INFO L287 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-07-14 15:07:11,718 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 116 states and 132 transitions. [2022-07-14 15:07:11,719 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:11,719 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:07:11,719 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:07:11,720 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [13, 13, 13, 12, 12, 1, 1, 1, 1] [2022-07-14 15:07:11,720 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-07-14 15:07:11,720 INFO L752 eck$LassoCheckResult]: Stem: 6642#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 6643#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 6648#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6663#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6664#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6651#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6652#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6690#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6689#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6688#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6687#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6686#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6685#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6684#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6683#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6682#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6681#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6680#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6679#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6678#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6677#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6676#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6675#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6674#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6673#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6672#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6671#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6667#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6666#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 6653#L27-4 main_~i~0#1 := 0; 6654#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6698#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6699#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6700#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6704#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6703#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6752#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6749#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6747#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6746#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6743#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6741#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6740#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6737#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6735#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6734#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6731#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6729#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6728#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6725#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6723#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6722#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6719#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6717#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6716#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6713#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6711#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6710#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6708#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6707#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6706#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6660#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6647#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6657#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6662#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6695#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6694#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6669#L34 [2022-07-14 15:07:11,720 INFO L754 eck$LassoCheckResult]: Loop: 6669#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6670#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6668#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6669#L34 [2022-07-14 15:07:11,720 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:11,720 INFO L85 PathProgramCache]: Analyzing trace with hash -1264665709, now seen corresponding path program 24 times [2022-07-14 15:07:11,720 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:11,721 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1861382857] [2022-07-14 15:07:11,721 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:11,721 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:11,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:11,751 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:11,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:11,780 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:11,780 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:11,781 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 14 times [2022-07-14 15:07:11,781 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:11,781 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1711920500] [2022-07-14 15:07:11,781 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:11,781 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:11,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:11,783 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:11,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:11,785 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:11,785 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:11,785 INFO L85 PathProgramCache]: Analyzing trace with hash -202976541, now seen corresponding path program 25 times [2022-07-14 15:07:11,785 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:11,785 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1651783489] [2022-07-14 15:07:11,785 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:11,785 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:11,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:07:12,064 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 210 proven. 206 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:12,064 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:07:12,064 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1651783489] [2022-07-14 15:07:12,064 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1651783489] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:07:12,064 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1354048045] [2022-07-14 15:07:12,064 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-07-14 15:07:12,064 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:07:12,065 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:07:12,066 INFO L229 MonitoredProcess]: Starting monitored process 25 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:07:12,066 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Waiting until timeout for monitored process [2022-07-14 15:07:12,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:07:12,152 INFO L263 TraceCheckSpWp]: Trace formula consists of 318 conjuncts, 30 conjunts are in the unsatisfiable core [2022-07-14 15:07:12,153 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:07:12,518 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 247 proven. 169 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:12,519 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:07:12,630 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 247 proven. 169 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:12,630 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1354048045] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:07:12,630 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:07:12,630 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30, 30] total 46 [2022-07-14 15:07:12,630 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [368165635] [2022-07-14 15:07:12,630 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:07:12,660 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:07:12,661 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2022-07-14 15:07:12,661 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=515, Invalid=1647, Unknown=0, NotChecked=0, Total=2162 [2022-07-14 15:07:12,661 INFO L87 Difference]: Start difference. First operand 116 states and 132 transitions. cyclomatic complexity: 19 Second operand has 47 states, 46 states have (on average 2.5652173913043477) internal successors, (118), 47 states have internal predecessors, (118), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:13,115 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:07:13,116 INFO L93 Difference]: Finished difference Result 375 states and 434 transitions. [2022-07-14 15:07:13,116 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2022-07-14 15:07:13,116 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 375 states and 434 transitions. [2022-07-14 15:07:13,118 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:13,118 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 375 states to 214 states and 246 transitions. [2022-07-14 15:07:13,119 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 185 [2022-07-14 15:07:13,119 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 185 [2022-07-14 15:07:13,119 INFO L73 IsDeterministic]: Start isDeterministic. Operand 214 states and 246 transitions. [2022-07-14 15:07:13,119 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 15:07:13,119 INFO L369 hiAutomatonCegarLoop]: Abstraction has 214 states and 246 transitions. [2022-07-14 15:07:13,119 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 214 states and 246 transitions. [2022-07-14 15:07:13,120 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 214 to 124. [2022-07-14 15:07:13,121 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 124 states, 124 states have (on average 1.1370967741935485) internal successors, (141), 123 states have internal predecessors, (141), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:13,121 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124 states to 124 states and 141 transitions. [2022-07-14 15:07:13,121 INFO L392 hiAutomatonCegarLoop]: Abstraction has 124 states and 141 transitions. [2022-07-14 15:07:13,121 INFO L374 stractBuchiCegarLoop]: Abstraction has 124 states and 141 transitions. [2022-07-14 15:07:13,121 INFO L287 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-07-14 15:07:13,121 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 124 states and 141 transitions. [2022-07-14 15:07:13,122 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:13,122 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:07:13,122 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:07:13,122 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [14, 14, 14, 13, 13, 1, 1, 1, 1] [2022-07-14 15:07:13,123 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-07-14 15:07:13,123 INFO L752 eck$LassoCheckResult]: Stem: 7627#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 7628#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 7633#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7647#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7648#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7636#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7637#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7676#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7675#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7674#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7673#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7672#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7671#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7670#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7669#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7668#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7667#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7666#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7665#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7664#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7663#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7662#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7661#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7660#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7659#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7658#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7657#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7656#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7655#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7651#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7650#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 7638#L27-4 main_~i~0#1 := 0; 7639#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7745#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7686#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7684#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7685#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7689#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7743#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7740#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7738#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7737#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7734#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7732#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7731#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7728#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7726#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7725#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7722#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7720#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7719#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7716#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7714#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7713#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7710#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7708#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7707#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7704#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7702#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7701#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7698#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7696#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7695#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7694#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7693#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7692#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7644#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7632#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7641#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7646#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7681#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7680#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7653#L34 [2022-07-14 15:07:13,123 INFO L754 eck$LassoCheckResult]: Loop: 7653#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7654#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7652#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7653#L34 [2022-07-14 15:07:13,124 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:13,124 INFO L85 PathProgramCache]: Analyzing trace with hash 1142017637, now seen corresponding path program 26 times [2022-07-14 15:07:13,124 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:13,124 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1967946301] [2022-07-14 15:07:13,124 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:13,124 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:13,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:13,159 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:13,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:13,195 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:13,195 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:13,195 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 15 times [2022-07-14 15:07:13,195 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:13,196 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1994193309] [2022-07-14 15:07:13,196 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:13,196 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:13,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:13,198 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:13,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:13,200 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:13,200 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:13,200 INFO L85 PathProgramCache]: Analyzing trace with hash 1411512017, now seen corresponding path program 27 times [2022-07-14 15:07:13,201 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:13,201 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [235236754] [2022-07-14 15:07:13,201 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:13,201 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:13,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:07:13,506 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 247 proven. 236 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:13,506 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:07:13,506 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [235236754] [2022-07-14 15:07:13,506 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [235236754] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:07:13,506 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1156339220] [2022-07-14 15:07:13,506 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-07-14 15:07:13,507 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:07:13,507 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:07:13,516 INFO L229 MonitoredProcess]: Starting monitored process 26 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:07:13,517 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Waiting until timeout for monitored process [2022-07-14 15:07:13,808 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2022-07-14 15:07:13,808 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-07-14 15:07:13,811 INFO L263 TraceCheckSpWp]: Trace formula consists of 339 conjuncts, 32 conjunts are in the unsatisfiable core [2022-07-14 15:07:13,812 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:07:14,262 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 287 proven. 196 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:14,262 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:07:14,364 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 287 proven. 196 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:14,364 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1156339220] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:07:14,364 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:07:14,364 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 32, 32] total 49 [2022-07-14 15:07:14,365 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [661691560] [2022-07-14 15:07:14,365 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:07:14,404 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:07:14,404 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2022-07-14 15:07:14,405 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=581, Invalid=1869, Unknown=0, NotChecked=0, Total=2450 [2022-07-14 15:07:14,405 INFO L87 Difference]: Start difference. First operand 124 states and 141 transitions. cyclomatic complexity: 20 Second operand has 50 states, 49 states have (on average 2.5714285714285716) internal successors, (126), 50 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:14,892 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:07:14,892 INFO L93 Difference]: Finished difference Result 401 states and 464 transitions. [2022-07-14 15:07:14,893 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2022-07-14 15:07:14,893 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 401 states and 464 transitions. [2022-07-14 15:07:14,895 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:14,896 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 401 states to 228 states and 262 transitions. [2022-07-14 15:07:14,896 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 197 [2022-07-14 15:07:14,896 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 197 [2022-07-14 15:07:14,896 INFO L73 IsDeterministic]: Start isDeterministic. Operand 228 states and 262 transitions. [2022-07-14 15:07:14,896 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 15:07:14,896 INFO L369 hiAutomatonCegarLoop]: Abstraction has 228 states and 262 transitions. [2022-07-14 15:07:14,897 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 228 states and 262 transitions. [2022-07-14 15:07:14,898 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 228 to 132. [2022-07-14 15:07:14,898 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 132 states, 132 states have (on average 1.1363636363636365) internal successors, (150), 131 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:14,898 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 132 states to 132 states and 150 transitions. [2022-07-14 15:07:14,898 INFO L392 hiAutomatonCegarLoop]: Abstraction has 132 states and 150 transitions. [2022-07-14 15:07:14,899 INFO L374 stractBuchiCegarLoop]: Abstraction has 132 states and 150 transitions. [2022-07-14 15:07:14,899 INFO L287 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-07-14 15:07:14,899 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 132 states and 150 transitions. [2022-07-14 15:07:14,899 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:14,899 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:07:14,899 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:07:14,900 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [15, 15, 15, 14, 14, 1, 1, 1, 1] [2022-07-14 15:07:14,900 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-07-14 15:07:14,900 INFO L752 eck$LassoCheckResult]: Stem: 8681#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 8682#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 8687#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8702#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8703#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8690#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8691#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8733#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8732#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8731#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8730#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8729#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8728#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8727#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8726#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8725#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8724#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8723#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8722#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8721#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8720#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8719#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8718#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8717#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8716#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8715#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8714#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8713#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8712#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8711#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8710#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8706#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8705#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 8692#L27-4 main_~i~0#1 := 0; 8693#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8741#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8742#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8743#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8747#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8746#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8807#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8804#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8802#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8801#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8798#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8796#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8795#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8792#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8790#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8789#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8786#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8784#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8783#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8780#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8778#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8777#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8774#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8772#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8771#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8768#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8766#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8765#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8762#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8760#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8759#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8756#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8754#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8753#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8751#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8750#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8749#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8699#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8686#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8696#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8701#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8738#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8737#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8708#L34 [2022-07-14 15:07:14,900 INFO L754 eck$LassoCheckResult]: Loop: 8708#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8709#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8707#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8708#L34 [2022-07-14 15:07:14,900 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:14,901 INFO L85 PathProgramCache]: Analyzing trace with hash -1133388657, now seen corresponding path program 28 times [2022-07-14 15:07:14,901 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:14,901 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [611143991] [2022-07-14 15:07:14,901 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:14,901 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:14,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:14,954 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:14,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:14,991 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:14,991 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:14,992 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 16 times [2022-07-14 15:07:14,992 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:14,992 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1619047012] [2022-07-14 15:07:14,992 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:14,992 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:14,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:14,994 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:14,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:14,996 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:14,997 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:14,997 INFO L85 PathProgramCache]: Analyzing trace with hash -2043527065, now seen corresponding path program 29 times [2022-07-14 15:07:14,997 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:14,997 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [641548588] [2022-07-14 15:07:14,997 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:14,997 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:15,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:07:15,366 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 287 proven. 268 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:15,367 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:07:15,367 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [641548588] [2022-07-14 15:07:15,367 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [641548588] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:07:15,367 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1628759225] [2022-07-14 15:07:15,367 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-07-14 15:07:15,367 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:07:15,367 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:07:15,384 INFO L229 MonitoredProcess]: Starting monitored process 27 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:07:15,411 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Waiting until timeout for monitored process [2022-07-14 15:07:15,790 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 16 check-sat command(s) [2022-07-14 15:07:15,790 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-07-14 15:07:15,794 INFO L263 TraceCheckSpWp]: Trace formula consists of 360 conjuncts, 34 conjunts are in the unsatisfiable core [2022-07-14 15:07:15,795 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:07:16,279 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 330 proven. 225 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:16,280 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:07:16,391 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 330 proven. 225 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:16,392 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1628759225] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:07:16,392 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:07:16,392 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 34, 34] total 52 [2022-07-14 15:07:16,392 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [159577609] [2022-07-14 15:07:16,392 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:07:16,438 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:07:16,439 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2022-07-14 15:07:16,440 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=651, Invalid=2105, Unknown=0, NotChecked=0, Total=2756 [2022-07-14 15:07:16,440 INFO L87 Difference]: Start difference. First operand 132 states and 150 transitions. cyclomatic complexity: 21 Second operand has 53 states, 52 states have (on average 2.576923076923077) internal successors, (134), 53 states have internal predecessors, (134), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:17,021 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:07:17,022 INFO L93 Difference]: Finished difference Result 427 states and 494 transitions. [2022-07-14 15:07:17,022 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2022-07-14 15:07:17,022 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 427 states and 494 transitions. [2022-07-14 15:07:17,024 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:17,025 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 427 states to 242 states and 278 transitions. [2022-07-14 15:07:17,025 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 209 [2022-07-14 15:07:17,025 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 209 [2022-07-14 15:07:17,025 INFO L73 IsDeterministic]: Start isDeterministic. Operand 242 states and 278 transitions. [2022-07-14 15:07:17,025 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 15:07:17,025 INFO L369 hiAutomatonCegarLoop]: Abstraction has 242 states and 278 transitions. [2022-07-14 15:07:17,026 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 242 states and 278 transitions. [2022-07-14 15:07:17,027 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 242 to 140. [2022-07-14 15:07:17,027 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 140 states, 140 states have (on average 1.1357142857142857) internal successors, (159), 139 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:17,027 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 140 states to 140 states and 159 transitions. [2022-07-14 15:07:17,027 INFO L392 hiAutomatonCegarLoop]: Abstraction has 140 states and 159 transitions. [2022-07-14 15:07:17,027 INFO L374 stractBuchiCegarLoop]: Abstraction has 140 states and 159 transitions. [2022-07-14 15:07:17,028 INFO L287 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-07-14 15:07:17,028 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 140 states and 159 transitions. [2022-07-14 15:07:17,028 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:17,028 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:07:17,028 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:07:17,029 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [16, 16, 16, 15, 15, 1, 1, 1, 1] [2022-07-14 15:07:17,029 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-07-14 15:07:17,029 INFO L752 eck$LassoCheckResult]: Stem: 9804#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 9805#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 9810#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9824#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9825#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9813#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9814#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9857#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9856#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9855#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9854#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9853#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9852#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9851#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9850#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9849#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9848#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9847#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9846#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9845#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9844#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9843#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9842#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9841#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9840#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9839#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9838#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9837#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9836#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9835#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9834#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9833#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9832#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9828#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9827#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 9815#L27-4 main_~i~0#1 := 0; 9816#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9939#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9867#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9865#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9866#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9870#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9938#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9935#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9933#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9932#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9929#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9927#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9926#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9923#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9921#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9920#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9917#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9915#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9914#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9911#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9909#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9908#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9905#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9903#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9902#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9899#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9897#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9896#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9893#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9891#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9890#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9887#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9885#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9884#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9881#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9879#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9878#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9876#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9874#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9873#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9821#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9809#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9818#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9823#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9862#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9861#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9830#L34 [2022-07-14 15:07:17,029 INFO L754 eck$LassoCheckResult]: Loop: 9830#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9831#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9829#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9830#L34 [2022-07-14 15:07:17,029 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:17,030 INFO L85 PathProgramCache]: Analyzing trace with hash 21119337, now seen corresponding path program 30 times [2022-07-14 15:07:17,030 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:17,030 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1688552332] [2022-07-14 15:07:17,030 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:17,030 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:17,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:17,096 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:17,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:17,185 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:17,186 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:17,186 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 17 times [2022-07-14 15:07:17,186 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:17,186 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2079337775] [2022-07-14 15:07:17,186 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:17,187 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:17,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:17,191 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:17,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:17,194 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:17,194 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:17,194 INFO L85 PathProgramCache]: Analyzing trace with hash 2100983117, now seen corresponding path program 31 times [2022-07-14 15:07:17,194 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:17,194 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [280472958] [2022-07-14 15:07:17,194 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:17,195 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:17,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:07:17,563 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 330 proven. 302 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:17,564 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:07:17,564 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [280472958] [2022-07-14 15:07:17,564 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [280472958] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:07:17,564 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [629656324] [2022-07-14 15:07:17,564 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-07-14 15:07:17,564 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:07:17,565 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:07:17,566 INFO L229 MonitoredProcess]: Starting monitored process 28 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:07:17,567 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Waiting until timeout for monitored process [2022-07-14 15:07:17,662 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:07:17,664 INFO L263 TraceCheckSpWp]: Trace formula consists of 381 conjuncts, 36 conjunts are in the unsatisfiable core [2022-07-14 15:07:17,665 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:07:18,190 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 376 proven. 256 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:18,190 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:07:18,312 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 376 proven. 256 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:18,312 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [629656324] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:07:18,313 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:07:18,313 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 36, 36] total 55 [2022-07-14 15:07:18,313 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1046804625] [2022-07-14 15:07:18,313 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:07:18,343 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:07:18,343 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 56 interpolants. [2022-07-14 15:07:18,344 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=725, Invalid=2355, Unknown=0, NotChecked=0, Total=3080 [2022-07-14 15:07:18,344 INFO L87 Difference]: Start difference. First operand 140 states and 159 transitions. cyclomatic complexity: 22 Second operand has 56 states, 55 states have (on average 2.581818181818182) internal successors, (142), 56 states have internal predecessors, (142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:18,906 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:07:18,906 INFO L93 Difference]: Finished difference Result 453 states and 524 transitions. [2022-07-14 15:07:18,907 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2022-07-14 15:07:18,907 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 453 states and 524 transitions. [2022-07-14 15:07:18,909 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:18,910 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 453 states to 256 states and 294 transitions. [2022-07-14 15:07:18,910 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 221 [2022-07-14 15:07:18,910 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 221 [2022-07-14 15:07:18,910 INFO L73 IsDeterministic]: Start isDeterministic. Operand 256 states and 294 transitions. [2022-07-14 15:07:18,910 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 15:07:18,910 INFO L369 hiAutomatonCegarLoop]: Abstraction has 256 states and 294 transitions. [2022-07-14 15:07:18,911 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 256 states and 294 transitions. [2022-07-14 15:07:18,912 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 256 to 148. [2022-07-14 15:07:18,912 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 148 states, 148 states have (on average 1.135135135135135) internal successors, (168), 147 states have internal predecessors, (168), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:18,912 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 148 states to 148 states and 168 transitions. [2022-07-14 15:07:18,912 INFO L392 hiAutomatonCegarLoop]: Abstraction has 148 states and 168 transitions. [2022-07-14 15:07:18,913 INFO L374 stractBuchiCegarLoop]: Abstraction has 148 states and 168 transitions. [2022-07-14 15:07:18,913 INFO L287 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-07-14 15:07:18,913 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 148 states and 168 transitions. [2022-07-14 15:07:18,913 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:18,913 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:07:18,913 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:07:18,914 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [17, 17, 17, 16, 16, 1, 1, 1, 1] [2022-07-14 15:07:18,914 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-07-14 15:07:18,914 INFO L752 eck$LassoCheckResult]: Stem: 10996#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 10997#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 11002#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11017#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11018#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11005#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11006#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11052#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11051#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11050#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11049#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11048#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11047#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11046#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11045#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11044#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11043#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11042#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11041#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11040#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11039#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11038#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11037#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11036#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11035#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11034#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11033#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11032#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11031#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11030#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11029#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11028#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11027#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11026#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11025#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11021#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11020#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 11007#L27-4 main_~i~0#1 := 0; 11008#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11060#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11061#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11062#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11066#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11065#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11138#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11135#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11133#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11132#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11129#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11127#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11126#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11123#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11121#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11120#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11117#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11115#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11114#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11111#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11109#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11108#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11105#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11103#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11102#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11099#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11097#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11096#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11093#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11091#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11090#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11087#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11085#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11084#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11081#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11079#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11078#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11075#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11073#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11072#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11070#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11069#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11068#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11014#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11001#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11011#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11016#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11057#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11056#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11023#L34 [2022-07-14 15:07:18,914 INFO L754 eck$LassoCheckResult]: Loop: 11023#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11024#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11022#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11023#L34 [2022-07-14 15:07:18,914 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:18,915 INFO L85 PathProgramCache]: Analyzing trace with hash 611108235, now seen corresponding path program 32 times [2022-07-14 15:07:18,915 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:18,915 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1718655155] [2022-07-14 15:07:18,915 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:18,915 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:19,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:19,001 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:19,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:19,063 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:19,064 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:19,064 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 18 times [2022-07-14 15:07:19,064 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:19,064 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [282457540] [2022-07-14 15:07:19,064 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:19,065 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:19,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:19,068 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:19,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:19,070 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:19,071 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:19,071 INFO L85 PathProgramCache]: Analyzing trace with hash -840899093, now seen corresponding path program 33 times [2022-07-14 15:07:19,072 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:19,072 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1047258773] [2022-07-14 15:07:19,072 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:19,072 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:19,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:07:19,467 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 376 proven. 338 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:19,467 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:07:19,467 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1047258773] [2022-07-14 15:07:19,467 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1047258773] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:07:19,467 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1052952010] [2022-07-14 15:07:19,468 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-07-14 15:07:19,468 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:07:19,468 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:07:19,469 INFO L229 MonitoredProcess]: Starting monitored process 29 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:07:19,470 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Waiting until timeout for monitored process [2022-07-14 15:07:20,098 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) [2022-07-14 15:07:20,099 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-07-14 15:07:20,103 INFO L263 TraceCheckSpWp]: Trace formula consists of 402 conjuncts, 38 conjunts are in the unsatisfiable core [2022-07-14 15:07:20,105 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:07:20,672 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 425 proven. 289 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:20,672 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:07:20,798 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 425 proven. 289 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:20,798 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1052952010] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:07:20,798 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:07:20,798 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 38, 38] total 58 [2022-07-14 15:07:20,799 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1415462465] [2022-07-14 15:07:20,799 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:07:20,839 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:07:20,839 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2022-07-14 15:07:20,840 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=803, Invalid=2619, Unknown=0, NotChecked=0, Total=3422 [2022-07-14 15:07:20,840 INFO L87 Difference]: Start difference. First operand 148 states and 168 transitions. cyclomatic complexity: 23 Second operand has 59 states, 58 states have (on average 2.586206896551724) internal successors, (150), 59 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:21,478 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:07:21,478 INFO L93 Difference]: Finished difference Result 479 states and 554 transitions. [2022-07-14 15:07:21,478 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2022-07-14 15:07:21,479 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 479 states and 554 transitions. [2022-07-14 15:07:21,482 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:21,483 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 479 states to 270 states and 310 transitions. [2022-07-14 15:07:21,483 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 233 [2022-07-14 15:07:21,484 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 233 [2022-07-14 15:07:21,484 INFO L73 IsDeterministic]: Start isDeterministic. Operand 270 states and 310 transitions. [2022-07-14 15:07:21,484 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 15:07:21,484 INFO L369 hiAutomatonCegarLoop]: Abstraction has 270 states and 310 transitions. [2022-07-14 15:07:21,484 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 270 states and 310 transitions. [2022-07-14 15:07:21,486 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 270 to 156. [2022-07-14 15:07:21,486 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 156 states, 156 states have (on average 1.1346153846153846) internal successors, (177), 155 states have internal predecessors, (177), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:21,486 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 156 states to 156 states and 177 transitions. [2022-07-14 15:07:21,486 INFO L392 hiAutomatonCegarLoop]: Abstraction has 156 states and 177 transitions. [2022-07-14 15:07:21,486 INFO L374 stractBuchiCegarLoop]: Abstraction has 156 states and 177 transitions. [2022-07-14 15:07:21,486 INFO L287 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-07-14 15:07:21,487 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 156 states and 177 transitions. [2022-07-14 15:07:21,487 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:21,487 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:07:21,487 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:07:21,488 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [18, 18, 18, 17, 17, 1, 1, 1, 1] [2022-07-14 15:07:21,488 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-07-14 15:07:21,488 INFO L752 eck$LassoCheckResult]: Stem: 12257#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 12258#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 12263#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12277#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12278#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12266#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12267#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12314#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12313#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12312#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12311#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12310#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12309#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12308#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12307#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12306#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12305#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12304#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12303#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12302#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12301#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12300#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12299#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12298#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12297#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12296#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12295#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12294#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12293#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12292#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12291#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12290#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12289#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12288#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12287#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12286#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12285#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12281#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12280#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 12268#L27-4 main_~i~0#1 := 0; 12269#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12407#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12324#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12322#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12323#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12327#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12405#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12402#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12400#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12399#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12396#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12394#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12393#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12390#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12388#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12387#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12384#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12382#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12381#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12378#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12376#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12375#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12372#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12370#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12369#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12366#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12364#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12363#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12360#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12358#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12357#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12354#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12352#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12351#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12348#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12346#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12345#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12342#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12340#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12339#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12336#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12334#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12333#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12332#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12331#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12330#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12274#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12262#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12271#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12276#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12319#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12318#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12283#L34 [2022-07-14 15:07:21,488 INFO L754 eck$LassoCheckResult]: Loop: 12283#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12284#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12282#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12283#L34 [2022-07-14 15:07:21,489 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:21,489 INFO L85 PathProgramCache]: Analyzing trace with hash -1016263571, now seen corresponding path program 34 times [2022-07-14 15:07:21,489 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:21,489 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1903932972] [2022-07-14 15:07:21,489 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:21,489 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:21,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:21,550 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:21,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:21,631 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:21,632 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:21,632 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 19 times [2022-07-14 15:07:21,632 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:21,632 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2044676384] [2022-07-14 15:07:21,632 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:21,632 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:21,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:21,635 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:21,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:21,645 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:21,645 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:21,645 INFO L85 PathProgramCache]: Analyzing trace with hash -283534391, now seen corresponding path program 35 times [2022-07-14 15:07:21,646 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:21,646 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1926221889] [2022-07-14 15:07:21,646 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:21,646 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:21,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:07:22,124 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 425 proven. 376 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:22,124 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:07:22,124 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1926221889] [2022-07-14 15:07:22,124 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1926221889] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:07:22,124 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1538159011] [2022-07-14 15:07:22,124 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-07-14 15:07:22,124 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:07:22,125 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:07:22,126 INFO L229 MonitoredProcess]: Starting monitored process 30 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:07:22,126 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Waiting until timeout for monitored process [2022-07-14 15:07:22,584 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 19 check-sat command(s) [2022-07-14 15:07:22,584 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-07-14 15:07:22,589 INFO L263 TraceCheckSpWp]: Trace formula consists of 423 conjuncts, 40 conjunts are in the unsatisfiable core [2022-07-14 15:07:22,590 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:07:23,212 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 477 proven. 324 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:23,212 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:07:23,327 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 477 proven. 324 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:23,327 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1538159011] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:07:23,327 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:07:23,327 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 40, 40] total 61 [2022-07-14 15:07:23,327 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [340211022] [2022-07-14 15:07:23,327 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:07:23,355 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:07:23,355 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2022-07-14 15:07:23,356 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=885, Invalid=2897, Unknown=0, NotChecked=0, Total=3782 [2022-07-14 15:07:23,356 INFO L87 Difference]: Start difference. First operand 156 states and 177 transitions. cyclomatic complexity: 24 Second operand has 62 states, 61 states have (on average 2.5901639344262297) internal successors, (158), 62 states have internal predecessors, (158), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:24,136 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:07:24,136 INFO L93 Difference]: Finished difference Result 505 states and 584 transitions. [2022-07-14 15:07:24,137 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2022-07-14 15:07:24,137 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 505 states and 584 transitions. [2022-07-14 15:07:24,139 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:24,139 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 505 states to 284 states and 326 transitions. [2022-07-14 15:07:24,140 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 245 [2022-07-14 15:07:24,140 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 245 [2022-07-14 15:07:24,140 INFO L73 IsDeterministic]: Start isDeterministic. Operand 284 states and 326 transitions. [2022-07-14 15:07:24,140 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 15:07:24,140 INFO L369 hiAutomatonCegarLoop]: Abstraction has 284 states and 326 transitions. [2022-07-14 15:07:24,140 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 284 states and 326 transitions. [2022-07-14 15:07:24,142 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 284 to 164. [2022-07-14 15:07:24,142 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 164 states, 164 states have (on average 1.1341463414634145) internal successors, (186), 163 states have internal predecessors, (186), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:24,142 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 164 states to 164 states and 186 transitions. [2022-07-14 15:07:24,142 INFO L392 hiAutomatonCegarLoop]: Abstraction has 164 states and 186 transitions. [2022-07-14 15:07:24,142 INFO L374 stractBuchiCegarLoop]: Abstraction has 164 states and 186 transitions. [2022-07-14 15:07:24,143 INFO L287 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-07-14 15:07:24,143 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 164 states and 186 transitions. [2022-07-14 15:07:24,143 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:24,143 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:07:24,143 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:07:24,144 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [19, 19, 19, 18, 18, 1, 1, 1, 1] [2022-07-14 15:07:24,144 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-07-14 15:07:24,144 INFO L752 eck$LassoCheckResult]: Stem: 13587#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 13588#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 13593#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13608#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13609#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13596#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13597#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13647#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13646#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13645#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13644#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13643#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13642#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13641#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13640#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13639#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13638#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13637#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13636#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13635#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13634#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13633#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13632#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13631#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13630#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13629#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13628#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13627#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13626#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13625#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13624#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13623#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13622#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13621#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13620#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13619#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13618#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13617#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13616#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13612#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13611#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 13598#L27-4 main_~i~0#1 := 0; 13599#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13655#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13656#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13657#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13661#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13660#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13745#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13742#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13740#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13739#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13736#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13734#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13733#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13730#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13728#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13727#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13724#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13722#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13721#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13718#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13716#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13715#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13712#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13710#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13709#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13706#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13704#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13703#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13700#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13698#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13697#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13694#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13692#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13691#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13688#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13686#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13685#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13682#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13680#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13679#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13676#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13674#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13673#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13670#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13668#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13667#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13665#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13664#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13663#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13605#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13592#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13602#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13607#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13652#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13651#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13614#L34 [2022-07-14 15:07:24,144 INFO L754 eck$LassoCheckResult]: Loop: 13614#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13615#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13613#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13614#L34 [2022-07-14 15:07:24,144 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:24,145 INFO L85 PathProgramCache]: Analyzing trace with hash 1191917191, now seen corresponding path program 36 times [2022-07-14 15:07:24,145 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:24,145 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1932451126] [2022-07-14 15:07:24,145 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:24,145 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:24,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:24,214 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:24,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:24,289 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:24,290 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:24,290 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 20 times [2022-07-14 15:07:24,290 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:24,290 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1126897728] [2022-07-14 15:07:24,290 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:24,290 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:24,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:24,293 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:24,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:24,295 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:24,295 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:24,295 INFO L85 PathProgramCache]: Analyzing trace with hash 1910440815, now seen corresponding path program 37 times [2022-07-14 15:07:24,295 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:24,296 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2028039868] [2022-07-14 15:07:24,296 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:24,296 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:24,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:07:24,789 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 477 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:24,789 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:07:24,789 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2028039868] [2022-07-14 15:07:24,789 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2028039868] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:07:24,789 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [303629107] [2022-07-14 15:07:24,789 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-07-14 15:07:24,790 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:07:24,790 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:07:24,791 INFO L229 MonitoredProcess]: Starting monitored process 31 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:07:24,792 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (31)] Waiting until timeout for monitored process [2022-07-14 15:07:24,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:07:24,916 INFO L263 TraceCheckSpWp]: Trace formula consists of 444 conjuncts, 42 conjunts are in the unsatisfiable core [2022-07-14 15:07:24,918 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:07:25,561 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 532 proven. 361 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:25,562 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:07:25,822 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 532 proven. 361 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:25,822 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [303629107] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:07:25,822 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:07:25,822 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 42, 42] total 64 [2022-07-14 15:07:25,822 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [618914104] [2022-07-14 15:07:25,822 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:07:25,851 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:07:25,852 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 65 interpolants. [2022-07-14 15:07:25,853 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=971, Invalid=3189, Unknown=0, NotChecked=0, Total=4160 [2022-07-14 15:07:25,853 INFO L87 Difference]: Start difference. First operand 164 states and 186 transitions. cyclomatic complexity: 25 Second operand has 65 states, 64 states have (on average 2.59375) internal successors, (166), 65 states have internal predecessors, (166), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:26,616 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:07:26,617 INFO L93 Difference]: Finished difference Result 531 states and 614 transitions. [2022-07-14 15:07:26,617 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2022-07-14 15:07:26,617 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 531 states and 614 transitions. [2022-07-14 15:07:26,628 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:26,630 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 531 states to 298 states and 342 transitions. [2022-07-14 15:07:26,630 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 257 [2022-07-14 15:07:26,630 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 257 [2022-07-14 15:07:26,631 INFO L73 IsDeterministic]: Start isDeterministic. Operand 298 states and 342 transitions. [2022-07-14 15:07:26,631 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 15:07:26,631 INFO L369 hiAutomatonCegarLoop]: Abstraction has 298 states and 342 transitions. [2022-07-14 15:07:26,631 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 298 states and 342 transitions. [2022-07-14 15:07:26,633 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 298 to 172. [2022-07-14 15:07:26,633 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 172 states, 172 states have (on average 1.1337209302325582) internal successors, (195), 171 states have internal predecessors, (195), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:26,633 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 172 states to 172 states and 195 transitions. [2022-07-14 15:07:26,633 INFO L392 hiAutomatonCegarLoop]: Abstraction has 172 states and 195 transitions. [2022-07-14 15:07:26,633 INFO L374 stractBuchiCegarLoop]: Abstraction has 172 states and 195 transitions. [2022-07-14 15:07:26,633 INFO L287 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-07-14 15:07:26,634 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 172 states and 195 transitions. [2022-07-14 15:07:26,634 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:26,634 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:07:26,634 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:07:26,635 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [20, 20, 20, 19, 19, 1, 1, 1, 1] [2022-07-14 15:07:26,635 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-07-14 15:07:26,635 INFO L752 eck$LassoCheckResult]: Stem: 14986#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 14987#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 14992#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15006#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15007#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 14995#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14996#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15047#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15046#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15045#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15044#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15043#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15042#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15041#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15040#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15039#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15038#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15037#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15036#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15035#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15034#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15033#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15032#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15031#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15030#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15029#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15028#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15027#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15026#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15025#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15024#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15023#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15022#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15021#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15020#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15019#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15018#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15017#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15016#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15015#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15014#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15010#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15009#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 14997#L27-4 main_~i~0#1 := 0; 14998#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15153#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15057#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15055#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15056#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15060#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15152#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15149#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15147#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15146#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15143#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15141#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15140#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15137#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15135#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15134#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15131#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15129#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15128#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15125#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15123#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15122#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15119#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15117#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15116#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15113#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15111#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15110#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15107#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15105#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15104#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15101#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15099#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15098#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15095#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15093#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15092#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15089#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15087#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15086#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15083#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15081#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15080#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15077#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15075#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15074#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15071#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15069#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15068#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15066#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15064#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15063#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15003#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 14991#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15000#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15005#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15052#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15051#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15012#L34 [2022-07-14 15:07:26,635 INFO L754 eck$LassoCheckResult]: Loop: 15012#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15013#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15011#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15012#L34 [2022-07-14 15:07:26,635 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:26,636 INFO L85 PathProgramCache]: Analyzing trace with hash 1997959025, now seen corresponding path program 38 times [2022-07-14 15:07:26,636 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:26,636 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1824300849] [2022-07-14 15:07:26,636 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:26,636 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:26,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:26,695 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:26,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:26,760 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:26,760 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:26,760 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 21 times [2022-07-14 15:07:26,760 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:26,761 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [421807848] [2022-07-14 15:07:26,761 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:26,761 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:26,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:26,763 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:26,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:26,765 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:26,766 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:26,766 INFO L85 PathProgramCache]: Analyzing trace with hash 1540565573, now seen corresponding path program 39 times [2022-07-14 15:07:26,766 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:26,766 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [475006262] [2022-07-14 15:07:26,766 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:26,766 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:26,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:07:27,338 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 532 proven. 458 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:27,338 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:07:27,338 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [475006262] [2022-07-14 15:07:27,338 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [475006262] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:07:27,338 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [155411417] [2022-07-14 15:07:27,339 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-07-14 15:07:27,339 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:07:27,339 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:07:27,343 INFO L229 MonitoredProcess]: Starting monitored process 32 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:07:27,344 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Waiting until timeout for monitored process [2022-07-14 15:07:28,173 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) [2022-07-14 15:07:28,173 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-07-14 15:07:28,178 INFO L263 TraceCheckSpWp]: Trace formula consists of 465 conjuncts, 44 conjunts are in the unsatisfiable core [2022-07-14 15:07:28,180 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:07:28,900 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 590 proven. 400 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:28,900 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:07:29,044 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 590 proven. 400 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:29,044 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [155411417] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:07:29,044 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:07:29,044 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 44, 44] total 67 [2022-07-14 15:07:29,044 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1990494041] [2022-07-14 15:07:29,044 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:07:29,072 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:07:29,073 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 68 interpolants. [2022-07-14 15:07:29,074 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1061, Invalid=3495, Unknown=0, NotChecked=0, Total=4556 [2022-07-14 15:07:29,074 INFO L87 Difference]: Start difference. First operand 172 states and 195 transitions. cyclomatic complexity: 26 Second operand has 68 states, 67 states have (on average 2.5970149253731343) internal successors, (174), 68 states have internal predecessors, (174), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:29,902 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:07:29,902 INFO L93 Difference]: Finished difference Result 557 states and 644 transitions. [2022-07-14 15:07:29,902 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2022-07-14 15:07:29,902 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 557 states and 644 transitions. [2022-07-14 15:07:29,904 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:29,905 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 557 states to 312 states and 358 transitions. [2022-07-14 15:07:29,905 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 269 [2022-07-14 15:07:29,906 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 269 [2022-07-14 15:07:29,906 INFO L73 IsDeterministic]: Start isDeterministic. Operand 312 states and 358 transitions. [2022-07-14 15:07:29,906 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 15:07:29,906 INFO L369 hiAutomatonCegarLoop]: Abstraction has 312 states and 358 transitions. [2022-07-14 15:07:29,906 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 312 states and 358 transitions. [2022-07-14 15:07:29,908 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 312 to 180. [2022-07-14 15:07:29,908 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 180 states, 180 states have (on average 1.1333333333333333) internal successors, (204), 179 states have internal predecessors, (204), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:29,908 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 180 states to 180 states and 204 transitions. [2022-07-14 15:07:29,908 INFO L392 hiAutomatonCegarLoop]: Abstraction has 180 states and 204 transitions. [2022-07-14 15:07:29,908 INFO L374 stractBuchiCegarLoop]: Abstraction has 180 states and 204 transitions. [2022-07-14 15:07:29,908 INFO L287 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-07-14 15:07:29,909 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 180 states and 204 transitions. [2022-07-14 15:07:29,909 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:29,909 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:07:29,909 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:07:29,910 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [21, 21, 21, 20, 20, 1, 1, 1, 1] [2022-07-14 15:07:29,910 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-07-14 15:07:29,910 INFO L752 eck$LassoCheckResult]: Stem: 16454#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 16455#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 16460#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16475#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16476#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16463#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16464#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16518#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16517#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16516#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16515#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16514#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16513#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16512#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16511#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16510#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16509#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16508#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16507#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16506#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16505#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16504#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16503#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16502#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16501#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16500#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16499#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16498#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16497#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16496#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16495#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16494#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16493#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16492#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16491#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16490#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16489#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16488#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16487#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16486#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16485#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16484#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16483#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16479#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16478#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 16465#L27-4 main_~i~0#1 := 0; 16466#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16526#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16527#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16528#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16532#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16531#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16628#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16625#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16623#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16622#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16619#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16617#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16616#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16613#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16611#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16610#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16607#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16605#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16604#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16601#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16599#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16598#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16595#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16593#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16592#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16589#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16587#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16586#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16583#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16581#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16580#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16577#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16575#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16574#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16571#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16569#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16568#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16565#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16563#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16562#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16559#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16557#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16556#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16553#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16551#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16550#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16547#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16545#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16544#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16541#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16539#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16538#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16536#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16535#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16534#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16472#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16459#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16469#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16474#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16523#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16522#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16481#L34 [2022-07-14 15:07:29,910 INFO L754 eck$LassoCheckResult]: Loop: 16481#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16482#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16480#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16481#L34 [2022-07-14 15:07:29,910 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:29,911 INFO L85 PathProgramCache]: Analyzing trace with hash 1338568579, now seen corresponding path program 40 times [2022-07-14 15:07:29,911 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:29,911 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1852132141] [2022-07-14 15:07:29,911 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:29,911 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:29,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:29,984 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:30,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:30,059 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:30,060 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:30,060 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 22 times [2022-07-14 15:07:30,061 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:30,061 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1112915818] [2022-07-14 15:07:30,061 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:30,061 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:30,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:30,063 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:30,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:30,066 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:30,066 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:30,066 INFO L85 PathProgramCache]: Analyzing trace with hash -1474766605, now seen corresponding path program 41 times [2022-07-14 15:07:30,066 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:30,066 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1034390466] [2022-07-14 15:07:30,066 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:30,067 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:30,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:07:30,626 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 590 proven. 502 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:30,626 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:07:30,626 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1034390466] [2022-07-14 15:07:30,627 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1034390466] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:07:30,627 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [704172347] [2022-07-14 15:07:30,627 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-07-14 15:07:30,627 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:07:30,627 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:07:30,628 INFO L229 MonitoredProcess]: Starting monitored process 33 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:07:30,629 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (33)] Waiting until timeout for monitored process [2022-07-14 15:07:31,603 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 22 check-sat command(s) [2022-07-14 15:07:31,603 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-07-14 15:07:31,610 INFO L263 TraceCheckSpWp]: Trace formula consists of 486 conjuncts, 46 conjunts are in the unsatisfiable core [2022-07-14 15:07:31,612 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:07:32,380 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 651 proven. 441 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:32,380 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:07:32,510 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 651 proven. 441 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:32,510 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [704172347] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:07:32,510 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:07:32,510 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 46, 46] total 70 [2022-07-14 15:07:32,511 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1433119017] [2022-07-14 15:07:32,511 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:07:32,547 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:07:32,547 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 71 interpolants. [2022-07-14 15:07:32,548 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1155, Invalid=3815, Unknown=0, NotChecked=0, Total=4970 [2022-07-14 15:07:32,549 INFO L87 Difference]: Start difference. First operand 180 states and 204 transitions. cyclomatic complexity: 27 Second operand has 71 states, 70 states have (on average 2.6) internal successors, (182), 71 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:33,435 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:07:33,435 INFO L93 Difference]: Finished difference Result 583 states and 674 transitions. [2022-07-14 15:07:33,435 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2022-07-14 15:07:33,435 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 583 states and 674 transitions. [2022-07-14 15:07:33,438 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:33,438 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 583 states to 326 states and 374 transitions. [2022-07-14 15:07:33,439 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 281 [2022-07-14 15:07:33,439 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 281 [2022-07-14 15:07:33,439 INFO L73 IsDeterministic]: Start isDeterministic. Operand 326 states and 374 transitions. [2022-07-14 15:07:33,439 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 15:07:33,439 INFO L369 hiAutomatonCegarLoop]: Abstraction has 326 states and 374 transitions. [2022-07-14 15:07:33,439 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 326 states and 374 transitions. [2022-07-14 15:07:33,441 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 326 to 188. [2022-07-14 15:07:33,441 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 188 states, 188 states have (on average 1.1329787234042554) internal successors, (213), 187 states have internal predecessors, (213), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:33,442 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 188 states to 188 states and 213 transitions. [2022-07-14 15:07:33,442 INFO L392 hiAutomatonCegarLoop]: Abstraction has 188 states and 213 transitions. [2022-07-14 15:07:33,442 INFO L374 stractBuchiCegarLoop]: Abstraction has 188 states and 213 transitions. [2022-07-14 15:07:33,442 INFO L287 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2022-07-14 15:07:33,442 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 188 states and 213 transitions. [2022-07-14 15:07:33,443 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:33,443 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:07:33,443 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:07:33,443 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [22, 22, 22, 21, 21, 1, 1, 1, 1] [2022-07-14 15:07:33,443 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-07-14 15:07:33,444 INFO L752 eck$LassoCheckResult]: Stem: 17991#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 17992#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 17997#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18011#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18012#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18000#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18001#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18056#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18055#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18054#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18053#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18052#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18051#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18050#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18049#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18048#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18047#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18046#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18045#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18044#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18043#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18042#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18041#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18040#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18039#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18038#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18037#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18036#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18035#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18034#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18033#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18032#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18031#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18030#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18029#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18028#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18027#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18026#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18025#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18024#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18023#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18022#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18021#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18020#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18019#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18015#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18014#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 18002#L27-4 main_~i~0#1 := 0; 18003#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18173#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18066#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18064#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18065#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18069#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18171#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18168#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18166#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18165#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18162#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18160#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18159#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18156#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18154#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18153#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18150#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18148#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18147#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18144#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18142#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18141#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18138#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18136#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18135#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18132#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18130#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18129#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18126#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18124#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18123#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18120#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18118#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18117#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18114#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18112#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18111#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18108#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18106#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18105#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18102#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18100#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18099#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18096#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18094#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18093#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18090#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18088#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18087#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18084#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18082#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18081#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18078#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18076#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18075#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18074#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18073#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18072#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18008#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 17996#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18005#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18010#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18061#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18060#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18017#L34 [2022-07-14 15:07:33,444 INFO L754 eck$LassoCheckResult]: Loop: 18017#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18018#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18016#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18017#L34 [2022-07-14 15:07:33,444 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:33,444 INFO L85 PathProgramCache]: Analyzing trace with hash 2042800757, now seen corresponding path program 42 times [2022-07-14 15:07:33,444 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:33,444 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [973481033] [2022-07-14 15:07:33,445 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:33,445 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:33,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:33,565 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:33,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:33,632 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:33,633 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:33,633 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 23 times [2022-07-14 15:07:33,633 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:33,633 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1840629756] [2022-07-14 15:07:33,633 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:33,633 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:33,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:33,637 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:33,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:33,640 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:33,640 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:33,640 INFO L85 PathProgramCache]: Analyzing trace with hash 1685774529, now seen corresponding path program 43 times [2022-07-14 15:07:33,640 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:33,640 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [596727252] [2022-07-14 15:07:33,641 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:33,641 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:33,662 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:07:34,302 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 651 proven. 548 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:34,302 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:07:34,302 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [596727252] [2022-07-14 15:07:34,302 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [596727252] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:07:34,302 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1154491382] [2022-07-14 15:07:34,302 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-07-14 15:07:34,302 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:07:34,303 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:07:34,304 INFO L229 MonitoredProcess]: Starting monitored process 34 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:07:34,305 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (34)] Waiting until timeout for monitored process [2022-07-14 15:07:34,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:07:34,452 INFO L263 TraceCheckSpWp]: Trace formula consists of 507 conjuncts, 48 conjunts are in the unsatisfiable core [2022-07-14 15:07:34,454 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:07:35,316 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 715 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:35,316 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:07:35,456 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 715 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:35,456 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1154491382] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:07:35,456 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:07:35,456 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48, 48] total 73 [2022-07-14 15:07:35,456 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1308275058] [2022-07-14 15:07:35,456 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:07:35,484 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:07:35,484 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 74 interpolants. [2022-07-14 15:07:35,485 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1253, Invalid=4149, Unknown=0, NotChecked=0, Total=5402 [2022-07-14 15:07:35,486 INFO L87 Difference]: Start difference. First operand 188 states and 213 transitions. cyclomatic complexity: 28 Second operand has 74 states, 73 states have (on average 2.6027397260273974) internal successors, (190), 74 states have internal predecessors, (190), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:36,450 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:07:36,451 INFO L93 Difference]: Finished difference Result 609 states and 704 transitions. [2022-07-14 15:07:36,452 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2022-07-14 15:07:36,452 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 609 states and 704 transitions. [2022-07-14 15:07:36,455 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:36,456 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 609 states to 340 states and 390 transitions. [2022-07-14 15:07:36,456 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 293 [2022-07-14 15:07:36,457 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 293 [2022-07-14 15:07:36,457 INFO L73 IsDeterministic]: Start isDeterministic. Operand 340 states and 390 transitions. [2022-07-14 15:07:36,457 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 15:07:36,457 INFO L369 hiAutomatonCegarLoop]: Abstraction has 340 states and 390 transitions. [2022-07-14 15:07:36,457 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 340 states and 390 transitions. [2022-07-14 15:07:36,460 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 340 to 196. [2022-07-14 15:07:36,460 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 196 states, 196 states have (on average 1.1326530612244898) internal successors, (222), 195 states have internal predecessors, (222), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:36,461 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 196 states to 196 states and 222 transitions. [2022-07-14 15:07:36,461 INFO L392 hiAutomatonCegarLoop]: Abstraction has 196 states and 222 transitions. [2022-07-14 15:07:36,461 INFO L374 stractBuchiCegarLoop]: Abstraction has 196 states and 222 transitions. [2022-07-14 15:07:36,461 INFO L287 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2022-07-14 15:07:36,461 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 196 states and 222 transitions. [2022-07-14 15:07:36,462 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:36,462 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:07:36,462 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:07:36,463 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [23, 23, 23, 22, 22, 1, 1, 1, 1] [2022-07-14 15:07:36,463 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-07-14 15:07:36,463 INFO L752 eck$LassoCheckResult]: Stem: 19597#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 19598#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 19603#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19618#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19619#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19606#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19607#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19665#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19664#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19663#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19662#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19661#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19660#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19659#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19658#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19657#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19656#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19655#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19654#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19653#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19652#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19651#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19650#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19649#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19648#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19647#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19646#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19645#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19644#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19643#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19642#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19641#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19640#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19639#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19638#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19637#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19636#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19635#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19634#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19633#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19632#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19631#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19630#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19629#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19628#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19627#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19626#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19622#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19621#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 19608#L27-4 main_~i~0#1 := 0; 19609#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19673#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19674#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19675#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19679#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19678#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19787#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19784#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19782#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19781#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19778#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19776#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19775#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19772#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19770#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19769#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19766#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19764#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19763#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19760#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19758#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19757#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19754#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19752#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19751#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19748#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19746#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19745#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19742#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19740#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19739#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19736#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19734#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19733#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19730#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19728#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19727#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19724#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19722#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19721#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19718#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19716#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19715#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19712#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19710#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19709#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19706#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19704#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19703#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19700#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19698#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19697#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19694#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19692#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19691#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19688#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19686#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19685#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19683#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19682#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19681#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19615#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19602#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19612#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19617#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19670#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19669#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19624#L34 [2022-07-14 15:07:36,463 INFO L754 eck$LassoCheckResult]: Loop: 19624#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19625#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19623#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19624#L34 [2022-07-14 15:07:36,464 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:36,464 INFO L85 PathProgramCache]: Analyzing trace with hash -1222528897, now seen corresponding path program 44 times [2022-07-14 15:07:36,464 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:36,464 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [153614392] [2022-07-14 15:07:36,464 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:36,464 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:36,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:36,591 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:36,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:36,725 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:36,726 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:36,726 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 24 times [2022-07-14 15:07:36,726 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:36,726 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1487622044] [2022-07-14 15:07:36,727 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:36,727 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:36,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:36,730 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:36,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:36,734 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:36,734 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:36,734 INFO L85 PathProgramCache]: Analyzing trace with hash 964339319, now seen corresponding path program 45 times [2022-07-14 15:07:36,734 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:36,735 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [133553730] [2022-07-14 15:07:36,735 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:36,735 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:36,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:07:37,531 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 715 proven. 596 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:37,531 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:07:37,531 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [133553730] [2022-07-14 15:07:37,532 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [133553730] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:07:37,532 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [639343962] [2022-07-14 15:07:37,532 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-07-14 15:07:37,532 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:07:37,532 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:07:37,545 INFO L229 MonitoredProcess]: Starting monitored process 35 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:07:37,546 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Waiting until timeout for monitored process [2022-07-14 15:07:39,611 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 24 check-sat command(s) [2022-07-14 15:07:39,611 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-07-14 15:07:39,621 INFO L263 TraceCheckSpWp]: Trace formula consists of 528 conjuncts, 50 conjunts are in the unsatisfiable core [2022-07-14 15:07:39,623 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:07:40,647 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 782 proven. 529 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:40,647 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:07:40,858 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 782 proven. 529 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:40,859 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [639343962] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:07:40,859 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:07:40,859 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 50, 50] total 76 [2022-07-14 15:07:40,860 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1636402381] [2022-07-14 15:07:40,860 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:07:40,892 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:07:40,893 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 77 interpolants. [2022-07-14 15:07:40,895 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1355, Invalid=4497, Unknown=0, NotChecked=0, Total=5852 [2022-07-14 15:07:40,895 INFO L87 Difference]: Start difference. First operand 196 states and 222 transitions. cyclomatic complexity: 29 Second operand has 77 states, 76 states have (on average 2.6052631578947367) internal successors, (198), 77 states have internal predecessors, (198), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:42,017 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:07:42,017 INFO L93 Difference]: Finished difference Result 635 states and 734 transitions. [2022-07-14 15:07:42,017 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2022-07-14 15:07:42,017 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 635 states and 734 transitions. [2022-07-14 15:07:42,020 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:42,021 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 635 states to 354 states and 406 transitions. [2022-07-14 15:07:42,022 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 305 [2022-07-14 15:07:42,022 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 305 [2022-07-14 15:07:42,022 INFO L73 IsDeterministic]: Start isDeterministic. Operand 354 states and 406 transitions. [2022-07-14 15:07:42,022 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 15:07:42,022 INFO L369 hiAutomatonCegarLoop]: Abstraction has 354 states and 406 transitions. [2022-07-14 15:07:42,022 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 354 states and 406 transitions. [2022-07-14 15:07:42,024 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 354 to 204. [2022-07-14 15:07:42,025 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 204 states, 204 states have (on average 1.1323529411764706) internal successors, (231), 203 states have internal predecessors, (231), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:42,025 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 204 states to 204 states and 231 transitions. [2022-07-14 15:07:42,025 INFO L392 hiAutomatonCegarLoop]: Abstraction has 204 states and 231 transitions. [2022-07-14 15:07:42,025 INFO L374 stractBuchiCegarLoop]: Abstraction has 204 states and 231 transitions. [2022-07-14 15:07:42,025 INFO L287 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2022-07-14 15:07:42,025 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 204 states and 231 transitions. [2022-07-14 15:07:42,026 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:42,026 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:07:42,026 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:07:42,027 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [24, 24, 24, 23, 23, 1, 1, 1, 1] [2022-07-14 15:07:42,027 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-07-14 15:07:42,027 INFO L752 eck$LassoCheckResult]: Stem: 21272#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 21273#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 21278#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21292#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21293#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21281#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21282#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21341#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21340#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21339#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21338#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21337#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21336#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21335#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21334#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21333#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21332#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21331#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21330#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21329#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21328#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21327#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21326#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21325#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21324#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21323#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21322#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21321#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21320#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21319#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21318#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21317#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21316#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21315#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21314#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21313#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21312#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21311#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21310#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21309#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21308#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21307#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21306#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21305#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21304#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21303#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21302#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21301#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21300#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21296#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21295#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 21283#L27-4 main_~i~0#1 := 0; 21284#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21471#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21351#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21349#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21350#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21354#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21470#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21467#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21465#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21464#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21461#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21459#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21458#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21455#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21453#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21452#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21449#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21447#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21446#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21443#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21441#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21440#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21437#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21435#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21434#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21431#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21429#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21428#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21425#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21423#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21422#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21419#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21417#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21416#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21413#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21411#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21410#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21407#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21405#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21404#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21401#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21399#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21398#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21395#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21393#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21392#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21389#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21387#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21386#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21383#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21381#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21380#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21377#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21375#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21374#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21371#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21369#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21368#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21365#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21363#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21362#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21360#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21358#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21357#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21289#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21277#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21286#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21291#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21346#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21345#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21298#L34 [2022-07-14 15:07:42,027 INFO L754 eck$LassoCheckResult]: Loop: 21298#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21299#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21297#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21298#L34 [2022-07-14 15:07:42,027 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:42,028 INFO L85 PathProgramCache]: Analyzing trace with hash 502660473, now seen corresponding path program 46 times [2022-07-14 15:07:42,028 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:42,028 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [957251768] [2022-07-14 15:07:42,028 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:42,028 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:42,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:42,156 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:42,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:42,298 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:42,298 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:42,298 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 25 times [2022-07-14 15:07:42,299 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:42,299 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1183825023] [2022-07-14 15:07:42,299 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:42,299 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:42,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:42,302 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:42,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:42,305 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:42,307 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:42,308 INFO L85 PathProgramCache]: Analyzing trace with hash -1792770243, now seen corresponding path program 47 times [2022-07-14 15:07:42,308 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:42,308 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [704099716] [2022-07-14 15:07:42,308 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:42,308 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:42,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:07:43,181 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 782 proven. 646 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:43,181 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:07:43,181 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [704099716] [2022-07-14 15:07:43,182 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [704099716] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:07:43,182 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [827598374] [2022-07-14 15:07:43,182 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-07-14 15:07:43,182 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:07:43,182 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:07:43,185 INFO L229 MonitoredProcess]: Starting monitored process 36 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:07:43,205 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (36)] Waiting until timeout for monitored process [2022-07-14 15:07:44,442 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 25 check-sat command(s) [2022-07-14 15:07:44,442 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-07-14 15:07:44,453 INFO L263 TraceCheckSpWp]: Trace formula consists of 549 conjuncts, 52 conjunts are in the unsatisfiable core [2022-07-14 15:07:44,455 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:07:45,437 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 852 proven. 576 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:45,437 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:07:45,589 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 852 proven. 576 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:45,589 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [827598374] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:07:45,589 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:07:45,589 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [52, 52, 52] total 79 [2022-07-14 15:07:45,589 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1862434059] [2022-07-14 15:07:45,589 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:07:45,617 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:07:45,617 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 80 interpolants. [2022-07-14 15:07:45,619 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1461, Invalid=4859, Unknown=0, NotChecked=0, Total=6320 [2022-07-14 15:07:45,619 INFO L87 Difference]: Start difference. First operand 204 states and 231 transitions. cyclomatic complexity: 30 Second operand has 80 states, 79 states have (on average 2.607594936708861) internal successors, (206), 80 states have internal predecessors, (206), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:46,686 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:07:46,686 INFO L93 Difference]: Finished difference Result 661 states and 764 transitions. [2022-07-14 15:07:46,686 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2022-07-14 15:07:46,687 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 661 states and 764 transitions. [2022-07-14 15:07:46,692 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:46,693 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 661 states to 368 states and 422 transitions. [2022-07-14 15:07:46,693 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 317 [2022-07-14 15:07:46,694 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 317 [2022-07-14 15:07:46,694 INFO L73 IsDeterministic]: Start isDeterministic. Operand 368 states and 422 transitions. [2022-07-14 15:07:46,694 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 15:07:46,695 INFO L369 hiAutomatonCegarLoop]: Abstraction has 368 states and 422 transitions. [2022-07-14 15:07:46,695 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 368 states and 422 transitions. [2022-07-14 15:07:46,696 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 368 to 212. [2022-07-14 15:07:46,697 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 212 states, 212 states have (on average 1.1320754716981132) internal successors, (240), 211 states have internal predecessors, (240), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:46,697 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 212 states to 212 states and 240 transitions. [2022-07-14 15:07:46,697 INFO L392 hiAutomatonCegarLoop]: Abstraction has 212 states and 240 transitions. [2022-07-14 15:07:46,697 INFO L374 stractBuchiCegarLoop]: Abstraction has 212 states and 240 transitions. [2022-07-14 15:07:46,697 INFO L287 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2022-07-14 15:07:46,697 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 212 states and 240 transitions. [2022-07-14 15:07:46,698 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:46,698 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:07:46,698 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:07:46,699 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [25, 25, 25, 24, 24, 1, 1, 1, 1] [2022-07-14 15:07:46,699 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-07-14 15:07:46,699 INFO L752 eck$LassoCheckResult]: Stem: 23016#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 23017#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 23022#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23037#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23038#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23025#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23026#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23088#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23087#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23086#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23085#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23084#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23083#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23082#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23081#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23080#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23079#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23078#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23077#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23076#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23075#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23074#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23073#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23072#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23071#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23070#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23069#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23068#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23067#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23066#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23065#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23064#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23063#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23062#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23061#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23060#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23059#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23058#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23057#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23056#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23055#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23054#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23053#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23052#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23051#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23050#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23049#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23048#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23047#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23046#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23045#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23041#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23040#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 23027#L27-4 main_~i~0#1 := 0; 23028#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23096#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23097#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23098#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23102#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23101#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23222#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23219#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23217#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23216#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23213#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23211#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23210#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23207#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23205#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23204#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23201#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23199#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23198#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23195#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23193#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23192#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23189#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23187#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23186#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23183#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23181#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23180#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23177#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23175#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23174#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23171#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23169#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23168#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23165#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23163#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23162#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23159#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23157#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23156#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23153#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23151#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23150#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23147#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23145#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23144#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23141#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23139#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23138#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23135#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23133#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23132#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23129#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23127#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23126#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23123#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23121#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23120#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23117#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23115#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23114#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23111#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23109#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23108#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23106#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23105#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23104#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23034#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23021#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23031#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23036#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23093#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23092#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23043#L34 [2022-07-14 15:07:46,700 INFO L754 eck$LassoCheckResult]: Loop: 23043#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23044#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23042#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23043#L34 [2022-07-14 15:07:46,700 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:46,700 INFO L85 PathProgramCache]: Analyzing trace with hash -1097778821, now seen corresponding path program 48 times [2022-07-14 15:07:46,700 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:46,700 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [432213101] [2022-07-14 15:07:46,700 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:46,700 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:46,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:46,824 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:46,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:46,957 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:46,958 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:46,958 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 26 times [2022-07-14 15:07:46,958 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:46,958 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [782637718] [2022-07-14 15:07:46,958 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:46,959 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:46,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:46,962 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:46,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:46,964 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:46,965 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:46,966 INFO L85 PathProgramCache]: Analyzing trace with hash -2047824901, now seen corresponding path program 49 times [2022-07-14 15:07:46,966 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:46,966 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [156082317] [2022-07-14 15:07:46,966 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:46,966 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:46,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:07:47,787 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 852 proven. 698 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:47,787 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:07:47,788 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [156082317] [2022-07-14 15:07:47,788 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [156082317] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:07:47,788 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1166798308] [2022-07-14 15:07:47,788 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-07-14 15:07:47,788 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:07:47,788 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:07:47,789 INFO L229 MonitoredProcess]: Starting monitored process 37 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:07:47,790 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (37)] Waiting until timeout for monitored process [2022-07-14 15:07:47,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:07:47,952 INFO L263 TraceCheckSpWp]: Trace formula consists of 570 conjuncts, 54 conjunts are in the unsatisfiable core [2022-07-14 15:07:47,954 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:07:48,949 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 925 proven. 625 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:48,949 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:07:49,106 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 925 proven. 625 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:49,106 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1166798308] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:07:49,106 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:07:49,106 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 54, 54] total 82 [2022-07-14 15:07:49,106 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [941375373] [2022-07-14 15:07:49,106 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:07:49,134 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:07:49,135 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 83 interpolants. [2022-07-14 15:07:49,136 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1571, Invalid=5235, Unknown=0, NotChecked=0, Total=6806 [2022-07-14 15:07:49,137 INFO L87 Difference]: Start difference. First operand 212 states and 240 transitions. cyclomatic complexity: 31 Second operand has 83 states, 82 states have (on average 2.6097560975609757) internal successors, (214), 83 states have internal predecessors, (214), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:50,201 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:07:50,202 INFO L93 Difference]: Finished difference Result 687 states and 794 transitions. [2022-07-14 15:07:50,202 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2022-07-14 15:07:50,202 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 687 states and 794 transitions. [2022-07-14 15:07:50,204 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:50,205 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 687 states to 382 states and 438 transitions. [2022-07-14 15:07:50,205 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 329 [2022-07-14 15:07:50,205 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 329 [2022-07-14 15:07:50,205 INFO L73 IsDeterministic]: Start isDeterministic. Operand 382 states and 438 transitions. [2022-07-14 15:07:50,206 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 15:07:50,206 INFO L369 hiAutomatonCegarLoop]: Abstraction has 382 states and 438 transitions. [2022-07-14 15:07:50,206 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 382 states and 438 transitions. [2022-07-14 15:07:50,208 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 382 to 220. [2022-07-14 15:07:50,208 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 220 states, 220 states have (on average 1.1318181818181818) internal successors, (249), 219 states have internal predecessors, (249), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:50,208 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220 states to 220 states and 249 transitions. [2022-07-14 15:07:50,208 INFO L392 hiAutomatonCegarLoop]: Abstraction has 220 states and 249 transitions. [2022-07-14 15:07:50,208 INFO L374 stractBuchiCegarLoop]: Abstraction has 220 states and 249 transitions. [2022-07-14 15:07:50,208 INFO L287 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2022-07-14 15:07:50,208 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 220 states and 249 transitions. [2022-07-14 15:07:50,209 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:50,209 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:07:50,209 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:07:50,209 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [26, 26, 26, 25, 25, 1, 1, 1, 1] [2022-07-14 15:07:50,209 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-07-14 15:07:50,209 INFO L752 eck$LassoCheckResult]: Stem: 24829#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 24830#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 24835#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24849#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24850#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24838#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24839#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24902#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24901#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24900#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24899#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24898#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24897#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24896#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24895#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24894#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24893#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24892#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24891#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24890#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24889#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24888#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24887#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24886#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24885#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24884#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24883#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24882#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24881#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24880#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24879#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24878#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24877#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24876#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24875#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24874#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24873#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24872#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24871#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24870#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24869#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24868#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24867#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24866#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24865#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24864#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24863#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24862#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24861#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24860#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24859#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24858#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24857#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24853#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24852#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 24840#L27-4 main_~i~0#1 := 0; 24841#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 25043#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24912#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24910#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24911#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24915#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 25041#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 25038#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 25036#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 25035#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 25032#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 25030#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 25029#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 25026#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 25024#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 25023#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 25020#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 25018#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 25017#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 25014#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 25012#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 25011#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 25008#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 25006#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 25005#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 25002#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 25000#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24999#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24996#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24994#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24993#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24990#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24988#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24987#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24984#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24982#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24981#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24978#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24976#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24975#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24972#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24970#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24969#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24966#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24964#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24963#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24960#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24958#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24957#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24954#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24952#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24951#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24948#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24946#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24945#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24942#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24940#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24939#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24936#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24934#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24933#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24930#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24928#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24927#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24924#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24922#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24921#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24920#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24919#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24918#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24846#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24834#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24843#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24848#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24907#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24906#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24855#L34 [2022-07-14 15:07:50,210 INFO L754 eck$LassoCheckResult]: Loop: 24855#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24856#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24854#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24855#L34 [2022-07-14 15:07:50,210 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:50,210 INFO L85 PathProgramCache]: Analyzing trace with hash 791980157, now seen corresponding path program 50 times [2022-07-14 15:07:50,210 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:50,210 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [572497460] [2022-07-14 15:07:50,210 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:50,210 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:50,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:50,335 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:50,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:50,437 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:50,437 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:50,437 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 27 times [2022-07-14 15:07:50,438 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:50,438 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1852155694] [2022-07-14 15:07:50,438 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:50,438 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:50,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:50,441 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:50,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:50,444 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:50,444 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:50,444 INFO L85 PathProgramCache]: Analyzing trace with hash 1625540025, now seen corresponding path program 51 times [2022-07-14 15:07:50,444 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:50,444 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1109060500] [2022-07-14 15:07:50,445 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:50,445 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:50,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:07:51,266 INFO L134 CoverageAnalysis]: Checked inductivity of 1677 backedges. 925 proven. 752 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:51,266 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:07:51,266 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1109060500] [2022-07-14 15:07:51,266 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1109060500] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:07:51,266 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [944348480] [2022-07-14 15:07:51,266 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-07-14 15:07:51,266 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:07:51,266 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:07:51,268 INFO L229 MonitoredProcess]: Starting monitored process 38 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:07:51,269 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (38)] Waiting until timeout for monitored process [2022-07-14 15:07:55,827 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 27 check-sat command(s) [2022-07-14 15:07:55,828 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-07-14 15:07:55,843 INFO L263 TraceCheckSpWp]: Trace formula consists of 591 conjuncts, 56 conjunts are in the unsatisfiable core [2022-07-14 15:07:55,845 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:07:56,932 INFO L134 CoverageAnalysis]: Checked inductivity of 1677 backedges. 1001 proven. 676 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:56,932 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:07:57,105 INFO L134 CoverageAnalysis]: Checked inductivity of 1677 backedges. 1001 proven. 676 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:57,105 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [944348480] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:07:57,106 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:07:57,106 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [56, 56, 56] total 85 [2022-07-14 15:07:57,106 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1425231000] [2022-07-14 15:07:57,106 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:07:57,147 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:07:57,148 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 86 interpolants. [2022-07-14 15:07:57,149 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1685, Invalid=5625, Unknown=0, NotChecked=0, Total=7310 [2022-07-14 15:07:57,149 INFO L87 Difference]: Start difference. First operand 220 states and 249 transitions. cyclomatic complexity: 32 Second operand has 86 states, 85 states have (on average 2.611764705882353) internal successors, (222), 86 states have internal predecessors, (222), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:58,262 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:07:58,262 INFO L93 Difference]: Finished difference Result 713 states and 824 transitions. [2022-07-14 15:07:58,263 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2022-07-14 15:07:58,263 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 713 states and 824 transitions. [2022-07-14 15:07:58,266 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:58,267 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 713 states to 396 states and 454 transitions. [2022-07-14 15:07:58,268 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 341 [2022-07-14 15:07:58,268 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 341 [2022-07-14 15:07:58,268 INFO L73 IsDeterministic]: Start isDeterministic. Operand 396 states and 454 transitions. [2022-07-14 15:07:58,268 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 15:07:58,268 INFO L369 hiAutomatonCegarLoop]: Abstraction has 396 states and 454 transitions. [2022-07-14 15:07:58,268 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 396 states and 454 transitions. [2022-07-14 15:07:58,271 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 396 to 228. [2022-07-14 15:07:58,271 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 228 states, 228 states have (on average 1.131578947368421) internal successors, (258), 227 states have internal predecessors, (258), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:07:58,272 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 228 states to 228 states and 258 transitions. [2022-07-14 15:07:58,272 INFO L392 hiAutomatonCegarLoop]: Abstraction has 228 states and 258 transitions. [2022-07-14 15:07:58,272 INFO L374 stractBuchiCegarLoop]: Abstraction has 228 states and 258 transitions. [2022-07-14 15:07:58,272 INFO L287 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2022-07-14 15:07:58,272 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 228 states and 258 transitions. [2022-07-14 15:07:58,273 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:07:58,273 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:07:58,273 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:07:58,273 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [27, 27, 27, 26, 26, 1, 1, 1, 1] [2022-07-14 15:07:58,273 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-07-14 15:07:58,274 INFO L752 eck$LassoCheckResult]: Stem: 26711#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 26712#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 26717#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26732#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26733#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26720#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26721#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26787#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26786#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26785#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26784#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26783#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26782#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26781#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26780#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26779#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26778#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26777#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26776#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26775#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26774#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26773#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26772#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26771#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26770#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26769#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26768#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26767#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26766#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26765#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26764#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26763#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26762#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26761#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26760#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26759#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26758#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26757#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26756#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26755#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26754#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26753#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26752#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26751#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26750#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26749#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26748#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26747#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26746#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26745#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26744#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26743#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26742#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26741#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26740#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26736#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26735#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 26722#L27-4 main_~i~0#1 := 0; 26723#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26795#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26796#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26797#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26801#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26800#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26933#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26930#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26928#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26927#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26924#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26922#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26921#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26918#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26916#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26915#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26912#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26910#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26909#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26906#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26904#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26903#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26900#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26898#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26897#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26894#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26892#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26891#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26888#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26886#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26885#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26882#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26880#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26879#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26876#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26874#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26873#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26870#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26868#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26867#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26864#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26862#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26861#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26858#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26856#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26855#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26852#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26850#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26849#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26846#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26844#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26843#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26840#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26838#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26837#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26834#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26832#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26831#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26828#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26826#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26825#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26822#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26820#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26819#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26816#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26814#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26813#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26810#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26808#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26807#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26805#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26804#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26803#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26729#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26716#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26726#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26731#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26792#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26791#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26738#L34 [2022-07-14 15:07:58,274 INFO L754 eck$LassoCheckResult]: Loop: 26738#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26739#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26737#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26738#L34 [2022-07-14 15:07:58,274 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:58,274 INFO L85 PathProgramCache]: Analyzing trace with hash -325891465, now seen corresponding path program 52 times [2022-07-14 15:07:58,274 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:58,274 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1590690818] [2022-07-14 15:07:58,274 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:58,274 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:58,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:58,413 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:58,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:58,553 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:58,553 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:58,553 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 28 times [2022-07-14 15:07:58,553 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:58,553 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [531514708] [2022-07-14 15:07:58,553 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:58,553 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:58,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:58,556 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:07:58,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:07:58,559 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:07:58,559 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:07:58,559 INFO L85 PathProgramCache]: Analyzing trace with hash -2006505089, now seen corresponding path program 53 times [2022-07-14 15:07:58,559 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:07:58,559 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [450978187] [2022-07-14 15:07:58,559 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:07:58,559 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:07:58,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:07:59,461 INFO L134 CoverageAnalysis]: Checked inductivity of 1809 backedges. 1001 proven. 808 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:07:59,462 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:07:59,462 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [450978187] [2022-07-14 15:07:59,462 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [450978187] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:07:59,462 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1456590557] [2022-07-14 15:07:59,462 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-07-14 15:07:59,462 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:07:59,462 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:07:59,463 INFO L229 MonitoredProcess]: Starting monitored process 39 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:07:59,464 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (39)] Waiting until timeout for monitored process [2022-07-14 15:08:01,236 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 28 check-sat command(s) [2022-07-14 15:08:01,236 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-07-14 15:08:01,247 INFO L263 TraceCheckSpWp]: Trace formula consists of 612 conjuncts, 58 conjunts are in the unsatisfiable core [2022-07-14 15:08:01,249 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:08:02,394 INFO L134 CoverageAnalysis]: Checked inductivity of 1809 backedges. 1080 proven. 729 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:08:02,395 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:08:02,580 INFO L134 CoverageAnalysis]: Checked inductivity of 1809 backedges. 1080 proven. 729 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:08:02,580 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1456590557] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:08:02,580 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:08:02,580 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 58, 58] total 88 [2022-07-14 15:08:02,580 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2106710979] [2022-07-14 15:08:02,580 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:08:02,620 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:08:02,620 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 89 interpolants. [2022-07-14 15:08:02,621 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1803, Invalid=6029, Unknown=0, NotChecked=0, Total=7832 [2022-07-14 15:08:02,621 INFO L87 Difference]: Start difference. First operand 228 states and 258 transitions. cyclomatic complexity: 33 Second operand has 89 states, 88 states have (on average 2.6136363636363638) internal successors, (230), 89 states have internal predecessors, (230), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:08:03,654 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:08:03,655 INFO L93 Difference]: Finished difference Result 739 states and 854 transitions. [2022-07-14 15:08:03,655 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2022-07-14 15:08:03,655 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 739 states and 854 transitions. [2022-07-14 15:08:03,658 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:08:03,659 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 739 states to 410 states and 470 transitions. [2022-07-14 15:08:03,659 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 353 [2022-07-14 15:08:03,659 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 353 [2022-07-14 15:08:03,659 INFO L73 IsDeterministic]: Start isDeterministic. Operand 410 states and 470 transitions. [2022-07-14 15:08:03,659 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 15:08:03,659 INFO L369 hiAutomatonCegarLoop]: Abstraction has 410 states and 470 transitions. [2022-07-14 15:08:03,659 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 410 states and 470 transitions. [2022-07-14 15:08:03,661 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 410 to 236. [2022-07-14 15:08:03,662 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 236 states, 236 states have (on average 1.13135593220339) internal successors, (267), 235 states have internal predecessors, (267), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:08:03,662 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 236 states to 236 states and 267 transitions. [2022-07-14 15:08:03,662 INFO L392 hiAutomatonCegarLoop]: Abstraction has 236 states and 267 transitions. [2022-07-14 15:08:03,662 INFO L374 stractBuchiCegarLoop]: Abstraction has 236 states and 267 transitions. [2022-07-14 15:08:03,662 INFO L287 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2022-07-14 15:08:03,662 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 236 states and 267 transitions. [2022-07-14 15:08:03,663 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:08:03,663 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:08:03,663 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:08:03,663 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [28, 28, 28, 27, 27, 1, 1, 1, 1] [2022-07-14 15:08:03,663 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-07-14 15:08:03,663 INFO L752 eck$LassoCheckResult]: Stem: 28662#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 28663#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 28668#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28682#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28683#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28671#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28672#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28739#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28738#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28737#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28736#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28735#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28734#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28733#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28732#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28731#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28730#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28729#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28728#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28727#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28726#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28725#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28724#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28723#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28722#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28721#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28720#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28719#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28718#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28717#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28716#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28715#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28714#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28713#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28712#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28711#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28710#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28709#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28708#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28707#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28706#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28705#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28704#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28703#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28702#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28701#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28700#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28699#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28698#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28697#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28696#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28695#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28694#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28693#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28692#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28691#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28690#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28686#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28685#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 28673#L27-4 main_~i~0#1 := 0; 28674#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28893#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28749#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28747#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28748#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28752#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28892#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28889#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28887#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28886#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28883#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28881#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28880#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28877#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28875#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28874#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28871#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28869#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28868#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28865#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28863#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28862#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28859#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28857#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28856#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28853#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28851#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28850#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28847#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28845#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28844#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28841#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28839#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28838#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28835#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28833#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28832#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28829#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28827#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28826#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28823#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28821#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28820#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28817#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28815#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28814#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28811#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28809#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28808#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28805#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28803#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28802#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28799#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28797#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28796#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28793#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28791#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28790#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28787#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28785#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28784#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28781#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28779#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28778#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28775#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28773#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28772#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28769#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28767#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28766#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28763#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28761#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28760#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28758#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28756#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28755#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28679#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28667#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28676#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28681#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28744#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28743#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28688#L34 [2022-07-14 15:08:03,663 INFO L754 eck$LassoCheckResult]: Loop: 28688#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28689#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28687#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28688#L34 [2022-07-14 15:08:03,663 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:08:03,664 INFO L85 PathProgramCache]: Analyzing trace with hash 1979902849, now seen corresponding path program 54 times [2022-07-14 15:08:03,664 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:08:03,664 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1610591576] [2022-07-14 15:08:03,664 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:08:03,664 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:08:03,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:08:03,793 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:08:03,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:08:03,936 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:08:03,937 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:08:03,937 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 29 times [2022-07-14 15:08:03,937 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:08:03,937 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2053482320] [2022-07-14 15:08:03,937 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:08:03,937 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:08:03,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:08:03,941 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:08:03,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:08:03,943 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:08:03,944 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:08:03,944 INFO L85 PathProgramCache]: Analyzing trace with hash 499938357, now seen corresponding path program 55 times [2022-07-14 15:08:03,944 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:08:03,944 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [515946802] [2022-07-14 15:08:03,944 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:08:03,944 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:08:03,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:08:04,831 INFO L134 CoverageAnalysis]: Checked inductivity of 1946 backedges. 1080 proven. 866 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:08:04,832 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:08:04,832 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [515946802] [2022-07-14 15:08:04,832 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [515946802] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:08:04,832 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [575092642] [2022-07-14 15:08:04,832 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-07-14 15:08:04,832 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:08:04,832 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:08:04,834 INFO L229 MonitoredProcess]: Starting monitored process 40 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:08:04,834 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Waiting until timeout for monitored process [2022-07-14 15:08:05,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:08:05,022 INFO L263 TraceCheckSpWp]: Trace formula consists of 633 conjuncts, 60 conjunts are in the unsatisfiable core [2022-07-14 15:08:05,024 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:08:06,199 INFO L134 CoverageAnalysis]: Checked inductivity of 1946 backedges. 1162 proven. 784 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:08:06,199 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:08:06,375 INFO L134 CoverageAnalysis]: Checked inductivity of 1946 backedges. 1162 proven. 784 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:08:06,376 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [575092642] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:08:06,376 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:08:06,376 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [60, 60, 60] total 91 [2022-07-14 15:08:06,376 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1092463948] [2022-07-14 15:08:06,376 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:08:06,405 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:08:06,406 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 92 interpolants. [2022-07-14 15:08:06,407 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1925, Invalid=6447, Unknown=0, NotChecked=0, Total=8372 [2022-07-14 15:08:06,408 INFO L87 Difference]: Start difference. First operand 236 states and 267 transitions. cyclomatic complexity: 34 Second operand has 92 states, 91 states have (on average 2.6153846153846154) internal successors, (238), 92 states have internal predecessors, (238), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:08:07,734 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:08:07,734 INFO L93 Difference]: Finished difference Result 765 states and 884 transitions. [2022-07-14 15:08:07,735 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 62 states. [2022-07-14 15:08:07,735 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 765 states and 884 transitions. [2022-07-14 15:08:07,737 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:08:07,738 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 765 states to 424 states and 486 transitions. [2022-07-14 15:08:07,738 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 365 [2022-07-14 15:08:07,738 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 365 [2022-07-14 15:08:07,738 INFO L73 IsDeterministic]: Start isDeterministic. Operand 424 states and 486 transitions. [2022-07-14 15:08:07,739 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 15:08:07,739 INFO L369 hiAutomatonCegarLoop]: Abstraction has 424 states and 486 transitions. [2022-07-14 15:08:07,739 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 424 states and 486 transitions. [2022-07-14 15:08:07,741 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 424 to 244. [2022-07-14 15:08:07,741 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 244 states, 244 states have (on average 1.1311475409836065) internal successors, (276), 243 states have internal predecessors, (276), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:08:07,742 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 244 states to 244 states and 276 transitions. [2022-07-14 15:08:07,742 INFO L392 hiAutomatonCegarLoop]: Abstraction has 244 states and 276 transitions. [2022-07-14 15:08:07,742 INFO L374 stractBuchiCegarLoop]: Abstraction has 244 states and 276 transitions. [2022-07-14 15:08:07,742 INFO L287 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2022-07-14 15:08:07,742 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 244 states and 276 transitions. [2022-07-14 15:08:07,743 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:08:07,743 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:08:07,743 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:08:07,743 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [29, 29, 29, 28, 28, 1, 1, 1, 1] [2022-07-14 15:08:07,743 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-07-14 15:08:07,744 INFO L752 eck$LassoCheckResult]: Stem: 30682#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 30683#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 30688#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30703#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30704#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30691#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30692#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30762#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30761#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30760#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30759#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30758#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30757#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30756#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30755#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30754#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30753#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30752#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30751#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30750#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30749#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30748#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30747#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30746#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30745#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30744#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30743#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30742#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30741#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30740#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30739#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30738#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30737#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30736#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30735#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30734#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30733#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30732#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30731#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30730#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30729#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30728#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30727#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30726#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30725#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30724#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30723#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30722#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30721#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30720#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30719#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30718#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30717#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30716#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30715#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30714#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30713#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30712#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30711#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30707#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30706#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 30693#L27-4 main_~i~0#1 := 0; 30694#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30770#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30771#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30772#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30776#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30775#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30920#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30917#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30915#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30914#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30911#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30909#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30908#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30905#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30903#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30902#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30899#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30897#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30896#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30893#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30891#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30890#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30887#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30885#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30884#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30881#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30879#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30878#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30875#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30873#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30872#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30869#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30867#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30866#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30863#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30861#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30860#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30857#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30855#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30854#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30851#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30849#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30848#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30845#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30843#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30842#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30839#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30837#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30836#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30833#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30831#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30830#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30827#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30825#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30824#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30821#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30819#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30818#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30815#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30813#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30812#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30809#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30807#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30806#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30803#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30801#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30800#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30797#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30795#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30794#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30791#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30789#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30788#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30785#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30783#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30782#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30780#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30779#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30778#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30700#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30687#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30697#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30702#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30767#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30766#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30709#L34 [2022-07-14 15:08:07,744 INFO L754 eck$LassoCheckResult]: Loop: 30709#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30710#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30708#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30709#L34 [2022-07-14 15:08:07,744 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:08:07,744 INFO L85 PathProgramCache]: Analyzing trace with hash -2002541709, now seen corresponding path program 56 times [2022-07-14 15:08:07,744 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:08:07,744 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1757808541] [2022-07-14 15:08:07,745 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:08:07,745 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:08:07,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:08:07,879 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:08:07,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:08:08,004 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:08:08,005 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:08:08,005 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 30 times [2022-07-14 15:08:08,005 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:08:08,005 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1862131980] [2022-07-14 15:08:08,005 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:08:08,005 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:08:08,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:08:08,009 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:08:08,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:08:08,011 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:08:08,011 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:08:08,011 INFO L85 PathProgramCache]: Analyzing trace with hash -624271613, now seen corresponding path program 57 times [2022-07-14 15:08:08,012 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:08:08,012 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1506105518] [2022-07-14 15:08:08,012 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:08:08,012 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:08:08,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:08:09,010 INFO L134 CoverageAnalysis]: Checked inductivity of 2088 backedges. 1162 proven. 926 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:08:09,011 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:08:09,011 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1506105518] [2022-07-14 15:08:09,011 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1506105518] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:08:09,011 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1910224866] [2022-07-14 15:08:09,011 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-07-14 15:08:09,011 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:08:09,011 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:08:09,013 INFO L229 MonitoredProcess]: Starting monitored process 41 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:08:09,013 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Waiting until timeout for monitored process [2022-07-14 15:08:20,617 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 30 check-sat command(s) [2022-07-14 15:08:20,618 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-07-14 15:08:20,641 INFO L263 TraceCheckSpWp]: Trace formula consists of 654 conjuncts, 62 conjunts are in the unsatisfiable core [2022-07-14 15:08:20,644 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:08:21,896 INFO L134 CoverageAnalysis]: Checked inductivity of 2088 backedges. 1247 proven. 841 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:08:21,896 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:08:22,084 INFO L134 CoverageAnalysis]: Checked inductivity of 2088 backedges. 1247 proven. 841 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:08:22,084 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1910224866] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:08:22,084 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:08:22,084 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 62, 62] total 94 [2022-07-14 15:08:22,085 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1389243926] [2022-07-14 15:08:22,085 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:08:22,115 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:08:22,116 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 95 interpolants. [2022-07-14 15:08:22,117 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2051, Invalid=6879, Unknown=0, NotChecked=0, Total=8930 [2022-07-14 15:08:22,118 INFO L87 Difference]: Start difference. First operand 244 states and 276 transitions. cyclomatic complexity: 35 Second operand has 95 states, 94 states have (on average 2.617021276595745) internal successors, (246), 95 states have internal predecessors, (246), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:08:23,450 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:08:23,450 INFO L93 Difference]: Finished difference Result 791 states and 914 transitions. [2022-07-14 15:08:23,450 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 64 states. [2022-07-14 15:08:23,451 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 791 states and 914 transitions. [2022-07-14 15:08:23,453 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:08:23,454 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 791 states to 438 states and 502 transitions. [2022-07-14 15:08:23,454 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 377 [2022-07-14 15:08:23,454 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 377 [2022-07-14 15:08:23,454 INFO L73 IsDeterministic]: Start isDeterministic. Operand 438 states and 502 transitions. [2022-07-14 15:08:23,455 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 15:08:23,455 INFO L369 hiAutomatonCegarLoop]: Abstraction has 438 states and 502 transitions. [2022-07-14 15:08:23,455 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 438 states and 502 transitions. [2022-07-14 15:08:23,457 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 438 to 252. [2022-07-14 15:08:23,457 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 252 states, 252 states have (on average 1.130952380952381) internal successors, (285), 251 states have internal predecessors, (285), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:08:23,457 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 252 states to 252 states and 285 transitions. [2022-07-14 15:08:23,457 INFO L392 hiAutomatonCegarLoop]: Abstraction has 252 states and 285 transitions. [2022-07-14 15:08:23,457 INFO L374 stractBuchiCegarLoop]: Abstraction has 252 states and 285 transitions. [2022-07-14 15:08:23,457 INFO L287 stractBuchiCegarLoop]: ======== Iteration 32 ============ [2022-07-14 15:08:23,457 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 252 states and 285 transitions. [2022-07-14 15:08:23,458 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:08:23,458 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:08:23,458 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:08:23,458 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [30, 30, 30, 29, 29, 1, 1, 1, 1] [2022-07-14 15:08:23,458 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-07-14 15:08:23,459 INFO L752 eck$LassoCheckResult]: Stem: 32771#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 32772#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 32777#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32791#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32792#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32780#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32781#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32852#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32851#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32850#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32849#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32848#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32847#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32846#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32845#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32844#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32843#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32842#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32841#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32840#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32839#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32838#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32837#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32836#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32835#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32834#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32833#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32832#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32831#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32830#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32829#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32828#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32827#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32826#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32825#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32824#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32823#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32822#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32821#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32820#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32819#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32818#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32817#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32816#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32815#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32814#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32813#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32812#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32811#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32810#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32809#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32808#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32807#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32806#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32805#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32804#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32803#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32802#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32801#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32800#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32799#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32795#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32794#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 32782#L27-4 main_~i~0#1 := 0; 32783#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 33017#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32862#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32860#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32861#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32865#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 33015#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 33012#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 33010#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 33009#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 33006#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 33004#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 33003#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 33000#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32998#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32997#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32994#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32992#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32991#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32988#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32986#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32985#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32982#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32980#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32979#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32976#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32974#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32973#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32970#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32968#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32967#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32964#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32962#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32961#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32958#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32956#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32955#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32952#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32950#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32949#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32946#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32944#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32943#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32940#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32938#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32937#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32934#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32932#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32931#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32928#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32926#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32925#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32922#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32920#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32919#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32916#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32914#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32913#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32910#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32908#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32907#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32904#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32902#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32901#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32898#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32896#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32895#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32892#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32890#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32889#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32886#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32884#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32883#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32880#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32878#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32877#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32874#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32872#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32871#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32870#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32869#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32868#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32788#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32776#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32785#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32790#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32857#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32856#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32797#L34 [2022-07-14 15:08:23,459 INFO L754 eck$LassoCheckResult]: Loop: 32797#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32798#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32796#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32797#L34 [2022-07-14 15:08:23,459 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:08:23,460 INFO L85 PathProgramCache]: Analyzing trace with hash 1004865157, now seen corresponding path program 58 times [2022-07-14 15:08:23,460 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:08:23,460 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1951550550] [2022-07-14 15:08:23,460 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:08:23,460 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:08:23,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:08:23,643 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:08:23,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:08:23,846 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:08:23,846 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:08:23,846 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 31 times [2022-07-14 15:08:23,846 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:08:23,846 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [974348262] [2022-07-14 15:08:23,846 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:08:23,846 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:08:23,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:08:23,850 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:08:23,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:08:23,853 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:08:23,853 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:08:23,853 INFO L85 PathProgramCache]: Analyzing trace with hash 15878833, now seen corresponding path program 59 times [2022-07-14 15:08:23,853 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:08:23,853 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [592745430] [2022-07-14 15:08:23,853 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:08:23,854 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:08:23,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:08:24,899 INFO L134 CoverageAnalysis]: Checked inductivity of 2235 backedges. 1247 proven. 988 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:08:24,900 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:08:24,900 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [592745430] [2022-07-14 15:08:24,900 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [592745430] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:08:24,900 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [337364565] [2022-07-14 15:08:24,900 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-07-14 15:08:24,900 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:08:24,900 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:08:24,902 INFO L229 MonitoredProcess]: Starting monitored process 42 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:08:24,903 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Waiting until timeout for monitored process [2022-07-14 15:08:27,092 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 31 check-sat command(s) [2022-07-14 15:08:27,092 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-07-14 15:08:27,103 INFO L263 TraceCheckSpWp]: Trace formula consists of 675 conjuncts, 64 conjunts are in the unsatisfiable core [2022-07-14 15:08:27,105 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:08:28,448 INFO L134 CoverageAnalysis]: Checked inductivity of 2235 backedges. 1335 proven. 900 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:08:28,449 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:08:28,629 INFO L134 CoverageAnalysis]: Checked inductivity of 2235 backedges. 1335 proven. 900 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:08:28,629 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [337364565] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:08:28,629 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:08:28,629 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 64, 64] total 97 [2022-07-14 15:08:28,629 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [365762886] [2022-07-14 15:08:28,629 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:08:28,664 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:08:28,665 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 98 interpolants. [2022-07-14 15:08:28,666 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2181, Invalid=7325, Unknown=0, NotChecked=0, Total=9506 [2022-07-14 15:08:28,666 INFO L87 Difference]: Start difference. First operand 252 states and 285 transitions. cyclomatic complexity: 36 Second operand has 98 states, 97 states have (on average 2.618556701030928) internal successors, (254), 98 states have internal predecessors, (254), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:08:30,104 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:08:30,104 INFO L93 Difference]: Finished difference Result 817 states and 944 transitions. [2022-07-14 15:08:30,104 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 66 states. [2022-07-14 15:08:30,105 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 817 states and 944 transitions. [2022-07-14 15:08:30,107 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:08:30,108 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 817 states to 452 states and 518 transitions. [2022-07-14 15:08:30,108 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 389 [2022-07-14 15:08:30,108 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 389 [2022-07-14 15:08:30,108 INFO L73 IsDeterministic]: Start isDeterministic. Operand 452 states and 518 transitions. [2022-07-14 15:08:30,109 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 15:08:30,109 INFO L369 hiAutomatonCegarLoop]: Abstraction has 452 states and 518 transitions. [2022-07-14 15:08:30,109 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 452 states and 518 transitions. [2022-07-14 15:08:30,111 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 452 to 260. [2022-07-14 15:08:30,111 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 260 states, 260 states have (on average 1.1307692307692307) internal successors, (294), 259 states have internal predecessors, (294), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:08:30,111 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 260 states to 260 states and 294 transitions. [2022-07-14 15:08:30,111 INFO L392 hiAutomatonCegarLoop]: Abstraction has 260 states and 294 transitions. [2022-07-14 15:08:30,112 INFO L374 stractBuchiCegarLoop]: Abstraction has 260 states and 294 transitions. [2022-07-14 15:08:30,112 INFO L287 stractBuchiCegarLoop]: ======== Iteration 33 ============ [2022-07-14 15:08:30,112 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 260 states and 294 transitions. [2022-07-14 15:08:30,112 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:08:30,112 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:08:30,112 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:08:30,113 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [31, 31, 31, 30, 30, 1, 1, 1, 1] [2022-07-14 15:08:30,113 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-07-14 15:08:30,113 INFO L752 eck$LassoCheckResult]: Stem: 34929#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 34930#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 34935#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34950#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34951#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34938#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34939#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 35013#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 35012#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 35011#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 35010#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 35009#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 35008#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 35007#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 35006#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 35005#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 35004#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 35003#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 35002#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 35001#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 35000#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34999#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34998#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34997#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34996#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34995#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34994#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34993#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34992#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34991#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34990#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34989#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34988#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34987#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34986#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34985#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34984#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34983#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34982#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34981#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34980#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34979#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34978#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34977#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34976#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34975#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34974#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34973#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34972#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34971#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34970#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34969#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34968#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34967#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34966#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34965#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34964#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34963#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34962#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34961#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34960#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34959#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34958#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34954#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34953#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 34940#L27-4 main_~i~0#1 := 0; 34941#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35021#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35022#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35023#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35027#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35026#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35183#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35180#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35178#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35177#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35174#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35172#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35171#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35168#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35166#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35165#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35162#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35160#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35159#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35156#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35154#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35153#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35150#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35148#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35147#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35144#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35142#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35141#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35138#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35136#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35135#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35132#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35130#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35129#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35126#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35124#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35123#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35120#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35118#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35117#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35114#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35112#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35111#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35108#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35106#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35105#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35102#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35100#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35099#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35096#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35094#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35093#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35090#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35088#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35087#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35084#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35082#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35081#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35078#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35076#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35075#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35072#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35070#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35069#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35066#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35064#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35063#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35060#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35058#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35057#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35054#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35052#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35051#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35048#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35046#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35045#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35042#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35040#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35039#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35036#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35034#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35033#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35031#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35030#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35029#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 34947#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 34934#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 34944#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 34949#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35018#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35017#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 34956#L34 [2022-07-14 15:08:30,113 INFO L754 eck$LassoCheckResult]: Loop: 34956#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 34957#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 34955#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 34956#L34 [2022-07-14 15:08:30,113 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:08:30,113 INFO L85 PathProgramCache]: Analyzing trace with hash 389940335, now seen corresponding path program 60 times [2022-07-14 15:08:30,113 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:08:30,113 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [227263031] [2022-07-14 15:08:30,113 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:08:30,114 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:08:30,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:08:30,243 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:08:30,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:08:30,401 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:08:30,401 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:08:30,401 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 32 times [2022-07-14 15:08:30,401 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:08:30,401 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1315889404] [2022-07-14 15:08:30,402 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:08:30,404 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:08:30,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:08:30,407 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:08:30,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:08:30,410 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:08:30,410 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:08:30,410 INFO L85 PathProgramCache]: Analyzing trace with hash -1173975929, now seen corresponding path program 61 times [2022-07-14 15:08:30,410 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:08:30,410 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1657730734] [2022-07-14 15:08:30,411 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:08:30,411 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:08:30,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:08:31,510 INFO L134 CoverageAnalysis]: Checked inductivity of 2387 backedges. 1335 proven. 1052 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:08:31,510 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:08:31,510 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1657730734] [2022-07-14 15:08:31,510 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1657730734] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:08:31,510 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [258851148] [2022-07-14 15:08:31,510 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-07-14 15:08:31,510 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:08:31,510 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:08:31,512 INFO L229 MonitoredProcess]: Starting monitored process 43 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:08:31,512 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (43)] Waiting until timeout for monitored process [2022-07-14 15:08:31,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:08:31,754 INFO L263 TraceCheckSpWp]: Trace formula consists of 696 conjuncts, 66 conjunts are in the unsatisfiable core [2022-07-14 15:08:31,756 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:08:33,202 INFO L134 CoverageAnalysis]: Checked inductivity of 2387 backedges. 1426 proven. 961 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:08:33,202 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:08:33,388 INFO L134 CoverageAnalysis]: Checked inductivity of 2387 backedges. 1426 proven. 961 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:08:33,388 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [258851148] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:08:33,388 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:08:33,389 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [66, 66, 66] total 100 [2022-07-14 15:08:33,389 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1066261293] [2022-07-14 15:08:33,389 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:08:33,422 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:08:33,423 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 101 interpolants. [2022-07-14 15:08:33,425 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2315, Invalid=7785, Unknown=0, NotChecked=0, Total=10100 [2022-07-14 15:08:33,425 INFO L87 Difference]: Start difference. First operand 260 states and 294 transitions. cyclomatic complexity: 37 Second operand has 101 states, 100 states have (on average 2.62) internal successors, (262), 101 states have internal predecessors, (262), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:08:34,848 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:08:34,848 INFO L93 Difference]: Finished difference Result 843 states and 974 transitions. [2022-07-14 15:08:34,849 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2022-07-14 15:08:34,849 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 843 states and 974 transitions. [2022-07-14 15:08:34,852 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:08:34,854 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 843 states to 466 states and 534 transitions. [2022-07-14 15:08:34,854 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 401 [2022-07-14 15:08:34,854 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 401 [2022-07-14 15:08:34,854 INFO L73 IsDeterministic]: Start isDeterministic. Operand 466 states and 534 transitions. [2022-07-14 15:08:34,854 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 15:08:34,854 INFO L369 hiAutomatonCegarLoop]: Abstraction has 466 states and 534 transitions. [2022-07-14 15:08:34,855 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 466 states and 534 transitions. [2022-07-14 15:08:34,857 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 466 to 268. [2022-07-14 15:08:34,857 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 268 states, 268 states have (on average 1.1305970149253732) internal successors, (303), 267 states have internal predecessors, (303), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:08:34,858 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 268 states to 268 states and 303 transitions. [2022-07-14 15:08:34,858 INFO L392 hiAutomatonCegarLoop]: Abstraction has 268 states and 303 transitions. [2022-07-14 15:08:34,858 INFO L374 stractBuchiCegarLoop]: Abstraction has 268 states and 303 transitions. [2022-07-14 15:08:34,858 INFO L287 stractBuchiCegarLoop]: ======== Iteration 34 ============ [2022-07-14 15:08:34,858 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 268 states and 303 transitions. [2022-07-14 15:08:34,859 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:08:34,859 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:08:34,859 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:08:34,860 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [32, 32, 32, 31, 31, 1, 1, 1, 1] [2022-07-14 15:08:34,860 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-07-14 15:08:34,860 INFO L752 eck$LassoCheckResult]: Stem: 37156#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 37157#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 37162#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37176#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37177#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37165#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37166#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37241#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37240#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37239#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37238#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37237#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37236#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37235#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37234#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37233#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37232#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37231#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37230#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37229#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37228#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37227#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37226#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37225#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37224#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37223#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37222#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37221#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37220#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37219#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37218#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37217#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37216#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37215#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37214#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37213#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37212#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37211#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37210#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37209#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37208#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37207#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37206#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37205#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37204#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37203#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37202#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37201#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37200#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37199#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37198#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37197#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37196#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37195#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37194#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37193#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37192#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37191#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37190#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37189#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37188#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37187#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37186#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37185#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37184#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37180#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37179#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 37167#L27-4 main_~i~0#1 := 0; 37168#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37419#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37251#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37249#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37250#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37254#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37418#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37415#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37413#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37412#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37409#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37407#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37406#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37403#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37401#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37400#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37397#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37395#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37394#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37391#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37389#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37388#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37385#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37383#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37382#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37379#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37377#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37376#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37373#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37371#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37370#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37367#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37365#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37364#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37361#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37359#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37358#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37355#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37353#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37352#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37349#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37347#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37346#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37343#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37341#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37340#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37337#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37335#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37334#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37331#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37329#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37328#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37325#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37323#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37322#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37319#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37317#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37316#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37313#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37311#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37310#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37307#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37305#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37304#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37301#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37299#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37298#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37295#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37293#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37292#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37289#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37287#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37286#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37283#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37281#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37280#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37277#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37275#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37274#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37271#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37269#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37268#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37265#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37263#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37262#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37260#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37258#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37257#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37173#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37161#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37170#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37175#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37246#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37245#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37182#L34 [2022-07-14 15:08:34,860 INFO L754 eck$LassoCheckResult]: Loop: 37182#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37183#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37181#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37182#L34 [2022-07-14 15:08:34,860 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:08:34,860 INFO L85 PathProgramCache]: Analyzing trace with hash -815842935, now seen corresponding path program 62 times [2022-07-14 15:08:34,860 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:08:34,860 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [725564237] [2022-07-14 15:08:34,860 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:08:34,860 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:08:35,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:08:35,046 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:08:35,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:08:35,230 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:08:35,230 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:08:35,231 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 33 times [2022-07-14 15:08:35,231 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:08:35,231 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [734095957] [2022-07-14 15:08:35,231 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:08:35,231 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:08:35,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:08:35,235 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:08:35,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:08:35,238 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:08:35,238 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:08:35,238 INFO L85 PathProgramCache]: Analyzing trace with hash 443091245, now seen corresponding path program 63 times [2022-07-14 15:08:35,238 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:08:35,239 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [704150953] [2022-07-14 15:08:35,239 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:08:35,239 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:08:35,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:08:36,393 INFO L134 CoverageAnalysis]: Checked inductivity of 2544 backedges. 1426 proven. 1118 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:08:36,393 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:08:36,393 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [704150953] [2022-07-14 15:08:36,393 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [704150953] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:08:36,393 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [972586651] [2022-07-14 15:08:36,393 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-07-14 15:08:36,393 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:08:36,394 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:08:36,395 INFO L229 MonitoredProcess]: Starting monitored process 44 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:08:36,397 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (44)] Waiting until timeout for monitored process [2022-07-14 15:08:47,062 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 33 check-sat command(s) [2022-07-14 15:08:47,063 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-07-14 15:08:47,082 INFO L263 TraceCheckSpWp]: Trace formula consists of 717 conjuncts, 68 conjunts are in the unsatisfiable core [2022-07-14 15:08:47,084 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:08:48,605 INFO L134 CoverageAnalysis]: Checked inductivity of 2544 backedges. 1520 proven. 1024 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:08:48,605 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:08:48,838 INFO L134 CoverageAnalysis]: Checked inductivity of 2544 backedges. 1520 proven. 1024 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:08:48,838 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [972586651] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:08:48,838 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:08:48,839 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [68, 68, 68] total 103 [2022-07-14 15:08:48,842 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2040073511] [2022-07-14 15:08:48,842 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:08:48,873 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:08:48,874 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 104 interpolants. [2022-07-14 15:08:48,876 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2453, Invalid=8259, Unknown=0, NotChecked=0, Total=10712 [2022-07-14 15:08:48,876 INFO L87 Difference]: Start difference. First operand 268 states and 303 transitions. cyclomatic complexity: 38 Second operand has 104 states, 103 states have (on average 2.621359223300971) internal successors, (270), 104 states have internal predecessors, (270), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:08:50,312 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:08:50,312 INFO L93 Difference]: Finished difference Result 869 states and 1004 transitions. [2022-07-14 15:08:50,312 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 70 states. [2022-07-14 15:08:50,312 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 869 states and 1004 transitions. [2022-07-14 15:08:50,315 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:08:50,316 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 869 states to 480 states and 550 transitions. [2022-07-14 15:08:50,316 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 413 [2022-07-14 15:08:50,316 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 413 [2022-07-14 15:08:50,316 INFO L73 IsDeterministic]: Start isDeterministic. Operand 480 states and 550 transitions. [2022-07-14 15:08:50,317 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 15:08:50,317 INFO L369 hiAutomatonCegarLoop]: Abstraction has 480 states and 550 transitions. [2022-07-14 15:08:50,317 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 480 states and 550 transitions. [2022-07-14 15:08:50,319 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 480 to 276. [2022-07-14 15:08:50,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 276 states, 276 states have (on average 1.1304347826086956) internal successors, (312), 275 states have internal predecessors, (312), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:08:50,319 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 276 states to 276 states and 312 transitions. [2022-07-14 15:08:50,319 INFO L392 hiAutomatonCegarLoop]: Abstraction has 276 states and 312 transitions. [2022-07-14 15:08:50,319 INFO L374 stractBuchiCegarLoop]: Abstraction has 276 states and 312 transitions. [2022-07-14 15:08:50,319 INFO L287 stractBuchiCegarLoop]: ======== Iteration 35 ============ [2022-07-14 15:08:50,320 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 276 states and 312 transitions. [2022-07-14 15:08:50,320 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:08:50,320 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:08:50,320 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:08:50,321 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [33, 33, 33, 32, 32, 1, 1, 1, 1] [2022-07-14 15:08:50,321 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-07-14 15:08:50,321 INFO L752 eck$LassoCheckResult]: Stem: 39452#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 39453#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 39458#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39473#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39474#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39461#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39462#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39540#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39539#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39538#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39537#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39536#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39535#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39534#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39533#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39532#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39531#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39530#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39529#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39528#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39527#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39526#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39525#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39524#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39523#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39522#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39521#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39520#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39519#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39518#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39517#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39516#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39515#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39514#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39513#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39512#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39511#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39510#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39509#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39508#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39507#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39506#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39505#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39504#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39503#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39502#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39501#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39500#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39499#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39498#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39497#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39496#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39495#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39494#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39493#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39492#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39491#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39490#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39489#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39488#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39487#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39486#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39485#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39484#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39483#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39482#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39481#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39477#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39476#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 39463#L27-4 main_~i~0#1 := 0; 39464#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39548#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39549#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39550#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39554#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39553#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39722#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39719#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39717#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39716#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39713#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39711#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39710#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39707#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39705#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39704#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39701#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39699#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39698#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39695#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39693#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39692#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39689#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39687#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39686#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39683#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39681#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39680#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39677#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39675#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39674#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39671#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39669#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39668#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39665#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39663#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39662#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39659#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39657#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39656#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39653#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39651#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39650#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39647#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39645#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39644#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39641#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39639#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39638#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39635#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39633#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39632#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39629#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39627#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39626#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39623#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39621#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39620#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39617#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39615#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39614#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39611#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39609#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39608#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39605#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39603#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39602#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39599#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39597#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39596#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39593#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39591#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39590#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39587#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39585#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39584#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39581#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39579#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39578#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39575#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39573#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39572#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39569#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39567#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39566#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39563#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39561#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39560#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39558#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39557#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39556#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39470#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39457#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39467#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39472#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39545#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39544#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39479#L34 [2022-07-14 15:08:50,321 INFO L754 eck$LassoCheckResult]: Loop: 39479#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39480#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39478#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39479#L34 [2022-07-14 15:08:50,321 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:08:50,321 INFO L85 PathProgramCache]: Analyzing trace with hash -706859669, now seen corresponding path program 64 times [2022-07-14 15:08:50,321 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:08:50,321 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [960485272] [2022-07-14 15:08:50,321 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:08:50,322 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:08:50,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:08:50,482 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:08:50,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:08:50,665 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:08:50,665 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:08:50,665 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 34 times [2022-07-14 15:08:50,665 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:08:50,665 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1166682183] [2022-07-14 15:08:50,665 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:08:50,665 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:08:50,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:08:50,669 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:08:50,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:08:50,672 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:08:50,672 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:08:50,672 INFO L85 PathProgramCache]: Analyzing trace with hash 168292875, now seen corresponding path program 65 times [2022-07-14 15:08:50,672 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:08:50,672 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [175869737] [2022-07-14 15:08:50,672 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:08:50,672 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:08:50,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:08:51,834 INFO L134 CoverageAnalysis]: Checked inductivity of 2706 backedges. 1520 proven. 1186 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:08:51,834 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:08:51,834 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [175869737] [2022-07-14 15:08:51,834 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [175869737] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:08:51,834 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [549759961] [2022-07-14 15:08:51,834 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-07-14 15:08:51,834 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:08:51,835 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:08:51,836 INFO L229 MonitoredProcess]: Starting monitored process 45 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:08:51,837 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (45)] Waiting until timeout for monitored process [2022-07-14 15:08:55,902 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 34 check-sat command(s) [2022-07-14 15:08:55,902 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-07-14 15:08:55,915 INFO L263 TraceCheckSpWp]: Trace formula consists of 738 conjuncts, 70 conjunts are in the unsatisfiable core [2022-07-14 15:08:55,917 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:08:57,493 INFO L134 CoverageAnalysis]: Checked inductivity of 2706 backedges. 1617 proven. 1089 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:08:57,493 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:08:57,708 INFO L134 CoverageAnalysis]: Checked inductivity of 2706 backedges. 1617 proven. 1089 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:08:57,708 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [549759961] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:08:57,708 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:08:57,708 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [70, 70, 70] total 106 [2022-07-14 15:08:57,708 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [883936592] [2022-07-14 15:08:57,708 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:08:57,744 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:08:57,745 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 107 interpolants. [2022-07-14 15:08:57,746 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2595, Invalid=8747, Unknown=0, NotChecked=0, Total=11342 [2022-07-14 15:08:57,746 INFO L87 Difference]: Start difference. First operand 276 states and 312 transitions. cyclomatic complexity: 39 Second operand has 107 states, 106 states have (on average 2.6226415094339623) internal successors, (278), 107 states have internal predecessors, (278), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:08:59,359 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:08:59,359 INFO L93 Difference]: Finished difference Result 895 states and 1034 transitions. [2022-07-14 15:08:59,359 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 72 states. [2022-07-14 15:08:59,360 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 895 states and 1034 transitions. [2022-07-14 15:08:59,362 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:08:59,363 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 895 states to 494 states and 566 transitions. [2022-07-14 15:08:59,363 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 425 [2022-07-14 15:08:59,363 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 425 [2022-07-14 15:08:59,363 INFO L73 IsDeterministic]: Start isDeterministic. Operand 494 states and 566 transitions. [2022-07-14 15:08:59,363 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 15:08:59,364 INFO L369 hiAutomatonCegarLoop]: Abstraction has 494 states and 566 transitions. [2022-07-14 15:08:59,364 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 494 states and 566 transitions. [2022-07-14 15:08:59,366 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 494 to 284. [2022-07-14 15:08:59,366 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 284 states, 284 states have (on average 1.130281690140845) internal successors, (321), 283 states have internal predecessors, (321), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:08:59,366 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 284 states to 284 states and 321 transitions. [2022-07-14 15:08:59,366 INFO L392 hiAutomatonCegarLoop]: Abstraction has 284 states and 321 transitions. [2022-07-14 15:08:59,366 INFO L374 stractBuchiCegarLoop]: Abstraction has 284 states and 321 transitions. [2022-07-14 15:08:59,366 INFO L287 stractBuchiCegarLoop]: ======== Iteration 36 ============ [2022-07-14 15:08:59,366 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 284 states and 321 transitions. [2022-07-14 15:08:59,367 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:08:59,367 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:08:59,367 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:08:59,368 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [34, 34, 34, 33, 33, 1, 1, 1, 1] [2022-07-14 15:08:59,368 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-07-14 15:08:59,368 INFO L752 eck$LassoCheckResult]: Stem: 41817#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 41818#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 41823#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 41837#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 41838#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 41826#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 41827#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 41906#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 41905#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 41904#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 41903#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 41902#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 41901#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 41900#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 41899#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 41898#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 41897#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 41896#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 41895#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 41894#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 41893#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 41892#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 41891#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 41890#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 41889#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 41888#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 41887#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 41886#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 41885#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 41884#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 41883#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 41882#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 41881#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 41880#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 41879#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 41878#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 41877#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 41876#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 41875#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 41874#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 41873#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 41872#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 41871#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 41870#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 41869#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 41868#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 41867#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 41866#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 41865#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 41864#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 41863#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 41862#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 41861#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 41860#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 41859#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 41858#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 41857#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 41856#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 41855#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 41854#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 41853#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 41852#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 41851#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 41850#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 41849#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 41848#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 41847#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 41846#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 41845#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 41841#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 41840#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 41828#L27-4 main_~i~0#1 := 0; 41829#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 42095#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 41916#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 41914#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 41915#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 41919#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 42093#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 42090#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 42088#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 42087#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 42084#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 42082#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 42081#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 42078#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 42076#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 42075#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 42072#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 42070#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 42069#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 42066#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 42064#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 42063#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 42060#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 42058#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 42057#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 42054#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 42052#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 42051#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 42048#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 42046#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 42045#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 42042#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 42040#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 42039#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 42036#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 42034#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 42033#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 42030#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 42028#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 42027#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 42024#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 42022#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 42021#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 42018#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 42016#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 42015#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 42012#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 42010#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 42009#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 42006#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 42004#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 42003#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 42000#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 41998#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 41997#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 41994#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 41992#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 41991#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 41988#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 41986#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 41985#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 41982#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 41980#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 41979#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 41976#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 41974#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 41973#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 41970#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 41968#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 41967#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 41964#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 41962#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 41961#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 41958#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 41956#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 41955#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 41952#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 41950#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 41949#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 41946#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 41944#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 41943#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 41940#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 41938#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 41937#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 41934#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 41932#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 41931#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 41928#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 41926#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 41925#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 41924#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 41923#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 41922#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 41834#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 41822#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 41831#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 41836#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 41911#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 41910#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 41843#L34 [2022-07-14 15:08:59,368 INFO L754 eck$LassoCheckResult]: Loop: 41843#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 41844#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 41842#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 41843#L34 [2022-07-14 15:08:59,369 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:08:59,369 INFO L85 PathProgramCache]: Analyzing trace with hash 133547149, now seen corresponding path program 66 times [2022-07-14 15:08:59,369 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:08:59,369 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [85697265] [2022-07-14 15:08:59,369 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:08:59,369 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:08:59,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:08:59,530 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:08:59,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:08:59,727 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:08:59,727 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:08:59,727 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 35 times [2022-07-14 15:08:59,727 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:08:59,727 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1757854430] [2022-07-14 15:08:59,728 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:08:59,728 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:08:59,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:08:59,732 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:08:59,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:08:59,734 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:08:59,735 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:08:59,735 INFO L85 PathProgramCache]: Analyzing trace with hash 1363439529, now seen corresponding path program 67 times [2022-07-14 15:08:59,735 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:08:59,735 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1973962750] [2022-07-14 15:08:59,735 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:08:59,735 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:08:59,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:09:01,017 INFO L134 CoverageAnalysis]: Checked inductivity of 2873 backedges. 1617 proven. 1256 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:09:01,018 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:09:01,018 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1973962750] [2022-07-14 15:09:01,018 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1973962750] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:09:01,018 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1855406684] [2022-07-14 15:09:01,018 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-07-14 15:09:01,018 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:09:01,018 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:09:01,020 INFO L229 MonitoredProcess]: Starting monitored process 46 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:09:01,020 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (46)] Waiting until timeout for monitored process [2022-07-14 15:09:01,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:09:01,259 INFO L263 TraceCheckSpWp]: Trace formula consists of 759 conjuncts, 72 conjunts are in the unsatisfiable core [2022-07-14 15:09:01,264 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:09:02,952 INFO L134 CoverageAnalysis]: Checked inductivity of 2873 backedges. 1717 proven. 1156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:09:02,952 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:09:03,152 INFO L134 CoverageAnalysis]: Checked inductivity of 2873 backedges. 1717 proven. 1156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:09:03,152 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1855406684] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:09:03,153 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:09:03,153 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [72, 72, 72] total 109 [2022-07-14 15:09:03,153 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1427239646] [2022-07-14 15:09:03,153 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:09:03,196 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:09:03,197 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 110 interpolants. [2022-07-14 15:09:03,199 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2741, Invalid=9249, Unknown=0, NotChecked=0, Total=11990 [2022-07-14 15:09:03,199 INFO L87 Difference]: Start difference. First operand 284 states and 321 transitions. cyclomatic complexity: 40 Second operand has 110 states, 109 states have (on average 2.623853211009174) internal successors, (286), 110 states have internal predecessors, (286), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:09:04,821 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:09:04,821 INFO L93 Difference]: Finished difference Result 921 states and 1064 transitions. [2022-07-14 15:09:04,822 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 74 states. [2022-07-14 15:09:04,822 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 921 states and 1064 transitions. [2022-07-14 15:09:04,825 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:09:04,826 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 921 states to 508 states and 582 transitions. [2022-07-14 15:09:04,826 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 437 [2022-07-14 15:09:04,827 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 437 [2022-07-14 15:09:04,827 INFO L73 IsDeterministic]: Start isDeterministic. Operand 508 states and 582 transitions. [2022-07-14 15:09:04,827 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 15:09:04,827 INFO L369 hiAutomatonCegarLoop]: Abstraction has 508 states and 582 transitions. [2022-07-14 15:09:04,827 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 508 states and 582 transitions. [2022-07-14 15:09:04,846 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 508 to 292. [2022-07-14 15:09:04,846 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 292 states, 292 states have (on average 1.13013698630137) internal successors, (330), 291 states have internal predecessors, (330), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:09:04,846 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 292 states to 292 states and 330 transitions. [2022-07-14 15:09:04,846 INFO L392 hiAutomatonCegarLoop]: Abstraction has 292 states and 330 transitions. [2022-07-14 15:09:04,847 INFO L374 stractBuchiCegarLoop]: Abstraction has 292 states and 330 transitions. [2022-07-14 15:09:04,847 INFO L287 stractBuchiCegarLoop]: ======== Iteration 37 ============ [2022-07-14 15:09:04,847 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 292 states and 330 transitions. [2022-07-14 15:09:04,847 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:09:04,847 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:09:04,847 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:09:04,848 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [35, 35, 35, 34, 34, 1, 1, 1, 1] [2022-07-14 15:09:04,848 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-07-14 15:09:04,848 INFO L752 eck$LassoCheckResult]: Stem: 44251#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 44252#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 44257#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 44272#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 44273#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 44260#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 44261#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 44343#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 44342#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 44341#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 44340#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 44339#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 44338#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 44337#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 44336#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 44335#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 44334#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 44333#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 44332#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 44331#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 44330#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 44329#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 44328#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 44327#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 44326#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 44325#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 44324#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 44323#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 44322#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 44321#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 44320#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 44319#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 44318#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 44317#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 44316#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 44315#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 44314#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 44313#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 44312#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 44311#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 44310#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 44309#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 44308#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 44307#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 44306#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 44305#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 44304#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 44303#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 44302#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 44301#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 44300#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 44299#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 44298#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 44297#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 44296#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 44295#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 44294#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 44293#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 44292#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 44291#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 44290#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 44289#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 44288#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 44287#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 44286#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 44285#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 44284#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 44283#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 44282#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 44281#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 44280#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 44276#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 44275#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 44262#L27-4 main_~i~0#1 := 0; 44263#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 44351#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 44352#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 44353#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 44357#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 44356#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 44537#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 44534#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 44532#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 44531#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 44528#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 44526#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 44525#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 44522#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 44520#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 44519#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 44516#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 44514#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 44513#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 44510#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 44508#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 44507#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 44504#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 44502#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 44501#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 44498#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 44496#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 44495#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 44492#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 44490#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 44489#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 44486#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 44484#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 44483#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 44480#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 44478#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 44477#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 44474#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 44472#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 44471#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 44468#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 44466#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 44465#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 44462#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 44460#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 44459#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 44456#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 44454#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 44453#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 44450#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 44448#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 44447#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 44444#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 44442#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 44441#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 44438#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 44436#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 44435#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 44432#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 44430#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 44429#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 44426#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 44424#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 44423#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 44420#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 44418#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 44417#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 44414#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 44412#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 44411#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 44408#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 44406#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 44405#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 44402#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 44400#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 44399#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 44396#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 44394#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 44393#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 44390#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 44388#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 44387#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 44384#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 44382#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 44381#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 44378#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 44376#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 44375#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 44372#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 44370#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 44369#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 44366#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 44364#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 44363#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 44361#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 44360#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 44359#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 44269#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 44256#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 44266#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 44271#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 44348#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 44347#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 44278#L34 [2022-07-14 15:09:04,848 INFO L754 eck$LassoCheckResult]: Loop: 44278#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 44279#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 44277#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 44278#L34 [2022-07-14 15:09:04,848 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:09:04,848 INFO L85 PathProgramCache]: Analyzing trace with hash 922738279, now seen corresponding path program 68 times [2022-07-14 15:09:04,848 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:09:04,848 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1492251839] [2022-07-14 15:09:04,848 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:09:04,848 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:09:05,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:09:05,064 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:09:05,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:09:05,317 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:09:05,317 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:09:05,317 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 36 times [2022-07-14 15:09:05,317 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:09:05,317 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [163672016] [2022-07-14 15:09:05,318 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:09:05,318 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:09:05,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:09:05,321 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:09:05,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:09:05,324 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:09:05,325 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:09:05,325 INFO L85 PathProgramCache]: Analyzing trace with hash 1505415055, now seen corresponding path program 69 times [2022-07-14 15:09:05,325 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:09:05,325 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [980715624] [2022-07-14 15:09:05,325 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:09:05,325 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:09:05,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:09:06,622 INFO L134 CoverageAnalysis]: Checked inductivity of 3045 backedges. 1717 proven. 1328 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:09:06,622 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:09:06,622 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [980715624] [2022-07-14 15:09:06,622 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [980715624] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:09:06,623 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1590993399] [2022-07-14 15:09:06,623 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-07-14 15:09:06,623 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:09:06,623 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:09:06,624 INFO L229 MonitoredProcess]: Starting monitored process 47 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:09:06,625 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (47)] Waiting until timeout for monitored process [2022-07-14 15:09:22,464 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 36 check-sat command(s) [2022-07-14 15:09:22,464 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-07-14 15:09:22,495 INFO L263 TraceCheckSpWp]: Trace formula consists of 780 conjuncts, 74 conjunts are in the unsatisfiable core [2022-07-14 15:09:22,501 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:09:24,312 INFO L134 CoverageAnalysis]: Checked inductivity of 3045 backedges. 1820 proven. 1225 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:09:24,312 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:09:24,548 INFO L134 CoverageAnalysis]: Checked inductivity of 3045 backedges. 1820 proven. 1225 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:09:24,548 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1590993399] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:09:24,548 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:09:24,548 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [74, 74, 74] total 112 [2022-07-14 15:09:24,548 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1628162342] [2022-07-14 15:09:24,548 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:09:24,578 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:09:24,579 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 113 interpolants. [2022-07-14 15:09:24,580 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2891, Invalid=9765, Unknown=0, NotChecked=0, Total=12656 [2022-07-14 15:09:24,581 INFO L87 Difference]: Start difference. First operand 292 states and 330 transitions. cyclomatic complexity: 41 Second operand has 113 states, 112 states have (on average 2.625) internal successors, (294), 113 states have internal predecessors, (294), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:09:26,307 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:09:26,308 INFO L93 Difference]: Finished difference Result 947 states and 1094 transitions. [2022-07-14 15:09:26,308 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 76 states. [2022-07-14 15:09:26,308 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 947 states and 1094 transitions. [2022-07-14 15:09:26,310 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:09:26,311 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 947 states to 522 states and 598 transitions. [2022-07-14 15:09:26,311 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 449 [2022-07-14 15:09:26,312 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 449 [2022-07-14 15:09:26,312 INFO L73 IsDeterministic]: Start isDeterministic. Operand 522 states and 598 transitions. [2022-07-14 15:09:26,312 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 15:09:26,312 INFO L369 hiAutomatonCegarLoop]: Abstraction has 522 states and 598 transitions. [2022-07-14 15:09:26,312 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 522 states and 598 transitions. [2022-07-14 15:09:26,314 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 522 to 300. [2022-07-14 15:09:26,315 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 300 states, 300 states have (on average 1.13) internal successors, (339), 299 states have internal predecessors, (339), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:09:26,315 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 300 states to 300 states and 339 transitions. [2022-07-14 15:09:26,315 INFO L392 hiAutomatonCegarLoop]: Abstraction has 300 states and 339 transitions. [2022-07-14 15:09:26,315 INFO L374 stractBuchiCegarLoop]: Abstraction has 300 states and 339 transitions. [2022-07-14 15:09:26,315 INFO L287 stractBuchiCegarLoop]: ======== Iteration 38 ============ [2022-07-14 15:09:26,315 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 300 states and 339 transitions. [2022-07-14 15:09:26,316 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:09:26,316 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:09:26,316 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:09:26,316 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [36, 36, 36, 35, 35, 1, 1, 1, 1] [2022-07-14 15:09:26,316 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-07-14 15:09:26,317 INFO L752 eck$LassoCheckResult]: Stem: 46754#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 46755#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 46760#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 46774#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 46775#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 46763#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 46764#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 46847#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 46846#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 46845#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 46844#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 46843#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 46842#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 46841#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 46840#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 46839#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 46838#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 46837#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 46836#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 46835#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 46834#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 46833#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 46832#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 46831#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 46830#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 46829#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 46828#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 46827#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 46826#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 46825#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 46824#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 46823#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 46822#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 46821#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 46820#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 46819#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 46818#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 46817#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 46816#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 46815#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 46814#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 46813#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 46812#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 46811#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 46810#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 46809#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 46808#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 46807#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 46806#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 46805#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 46804#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 46803#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 46802#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 46801#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 46800#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 46799#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 46798#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 46797#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 46796#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 46795#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 46794#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 46793#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 46792#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 46791#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 46790#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 46789#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 46788#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 46787#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 46786#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 46785#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 46784#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 46783#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 46782#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 46778#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 46777#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 46765#L27-4 main_~i~0#1 := 0; 46766#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 47049#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 46857#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 46855#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 46856#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 46860#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 47048#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 47045#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 47043#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 47042#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 47039#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 47037#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 47036#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 47033#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 47031#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 47030#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 47027#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 47025#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 47024#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 47021#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 47019#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 47018#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 47015#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 47013#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 47012#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 47009#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 47007#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 47006#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 47003#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 47001#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 47000#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 46997#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 46995#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 46994#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 46991#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 46989#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 46988#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 46985#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 46983#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 46982#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 46979#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 46977#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 46976#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 46973#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 46971#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 46970#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 46967#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 46965#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 46964#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 46961#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 46959#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 46958#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 46955#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 46953#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 46952#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 46949#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 46947#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 46946#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 46943#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 46941#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 46940#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 46937#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 46935#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 46934#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 46931#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 46929#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 46928#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 46925#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 46923#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 46922#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 46919#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 46917#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 46916#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 46913#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 46911#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 46910#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 46907#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 46905#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 46904#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 46901#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 46899#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 46898#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 46895#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 46893#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 46892#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 46889#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 46887#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 46886#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 46883#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 46881#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 46880#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 46877#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 46875#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 46874#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 46871#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 46869#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 46868#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 46866#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 46864#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 46863#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 46771#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 46759#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 46768#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 46773#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 46852#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 46851#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 46780#L34 [2022-07-14 15:09:26,317 INFO L754 eck$LassoCheckResult]: Loop: 46780#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 46781#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 46779#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 46780#L34 [2022-07-14 15:09:26,317 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:09:26,317 INFO L85 PathProgramCache]: Analyzing trace with hash -903026799, now seen corresponding path program 70 times [2022-07-14 15:09:26,317 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:09:26,317 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [6083078] [2022-07-14 15:09:26,317 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:09:26,317 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:09:26,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:09:26,558 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:09:26,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:09:26,751 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:09:26,751 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:09:26,751 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 37 times [2022-07-14 15:09:26,751 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:09:26,751 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1079323441] [2022-07-14 15:09:26,751 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:09:26,752 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:09:26,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:09:26,755 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:09:26,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:09:26,763 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:09:26,764 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:09:26,764 INFO L85 PathProgramCache]: Analyzing trace with hash 1603812901, now seen corresponding path program 71 times [2022-07-14 15:09:26,764 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:09:26,764 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [102929491] [2022-07-14 15:09:26,764 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:09:26,764 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:09:26,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:09:28,171 INFO L134 CoverageAnalysis]: Checked inductivity of 3222 backedges. 1820 proven. 1402 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:09:28,172 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:09:28,172 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [102929491] [2022-07-14 15:09:28,172 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [102929491] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:09:28,172 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [206701426] [2022-07-14 15:09:28,172 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-07-14 15:09:28,172 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:09:28,172 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:09:28,174 INFO L229 MonitoredProcess]: Starting monitored process 48 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:09:28,174 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (48)] Waiting until timeout for monitored process [2022-07-14 15:09:37,120 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 37 check-sat command(s) [2022-07-14 15:09:37,121 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-07-14 15:09:37,144 INFO L263 TraceCheckSpWp]: Trace formula consists of 801 conjuncts, 76 conjunts are in the unsatisfiable core [2022-07-14 15:09:37,147 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:09:39,017 INFO L134 CoverageAnalysis]: Checked inductivity of 3222 backedges. 1926 proven. 1296 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:09:39,018 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:09:39,252 INFO L134 CoverageAnalysis]: Checked inductivity of 3222 backedges. 1926 proven. 1296 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:09:39,252 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [206701426] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:09:39,252 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:09:39,252 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [76, 76, 76] total 115 [2022-07-14 15:09:39,252 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [227762992] [2022-07-14 15:09:39,252 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:09:39,282 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:09:39,283 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 116 interpolants. [2022-07-14 15:09:39,284 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3045, Invalid=10295, Unknown=0, NotChecked=0, Total=13340 [2022-07-14 15:09:39,284 INFO L87 Difference]: Start difference. First operand 300 states and 339 transitions. cyclomatic complexity: 42 Second operand has 116 states, 115 states have (on average 2.626086956521739) internal successors, (302), 116 states have internal predecessors, (302), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:09:41,194 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:09:41,194 INFO L93 Difference]: Finished difference Result 973 states and 1124 transitions. [2022-07-14 15:09:41,194 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 78 states. [2022-07-14 15:09:41,194 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 973 states and 1124 transitions. [2022-07-14 15:09:41,196 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:09:41,198 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 973 states to 536 states and 614 transitions. [2022-07-14 15:09:41,198 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 461 [2022-07-14 15:09:41,198 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 461 [2022-07-14 15:09:41,198 INFO L73 IsDeterministic]: Start isDeterministic. Operand 536 states and 614 transitions. [2022-07-14 15:09:41,198 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 15:09:41,198 INFO L369 hiAutomatonCegarLoop]: Abstraction has 536 states and 614 transitions. [2022-07-14 15:09:41,198 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 536 states and 614 transitions. [2022-07-14 15:09:41,200 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 536 to 308. [2022-07-14 15:09:41,201 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 308 states, 308 states have (on average 1.12987012987013) internal successors, (348), 307 states have internal predecessors, (348), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:09:41,201 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 308 states to 308 states and 348 transitions. [2022-07-14 15:09:41,201 INFO L392 hiAutomatonCegarLoop]: Abstraction has 308 states and 348 transitions. [2022-07-14 15:09:41,201 INFO L374 stractBuchiCegarLoop]: Abstraction has 308 states and 348 transitions. [2022-07-14 15:09:41,201 INFO L287 stractBuchiCegarLoop]: ======== Iteration 39 ============ [2022-07-14 15:09:41,201 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 308 states and 348 transitions. [2022-07-14 15:09:41,202 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:09:41,202 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:09:41,202 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:09:41,202 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [37, 37, 37, 36, 36, 1, 1, 1, 1] [2022-07-14 15:09:41,202 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-07-14 15:09:41,203 INFO L752 eck$LassoCheckResult]: Stem: 49326#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 49327#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 49332#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 49347#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 49348#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 49335#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 49336#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 49422#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 49421#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 49420#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 49419#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 49418#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 49417#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 49416#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 49415#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 49414#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 49413#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 49412#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 49411#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 49410#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 49409#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 49408#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 49407#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 49406#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 49405#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 49404#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 49403#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 49402#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 49401#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 49400#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 49399#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 49398#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 49397#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 49396#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 49395#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 49394#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 49393#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 49392#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 49391#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 49390#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 49389#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 49388#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 49387#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 49386#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 49385#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 49384#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 49383#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 49382#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 49381#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 49380#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 49379#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 49378#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 49377#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 49376#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 49375#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 49374#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 49373#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 49372#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 49371#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 49370#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 49369#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 49368#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 49367#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 49366#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 49365#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 49364#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 49363#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 49362#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 49361#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 49360#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 49359#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 49358#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 49357#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 49356#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 49355#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 49351#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 49350#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 49337#L27-4 main_~i~0#1 := 0; 49338#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 49430#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 49431#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 49432#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 49436#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 49435#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 49628#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 49625#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 49623#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 49622#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 49619#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 49617#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 49616#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 49613#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 49611#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 49610#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 49607#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 49605#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 49604#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 49601#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 49599#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 49598#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 49595#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 49593#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 49592#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 49589#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 49587#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 49586#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 49583#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 49581#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 49580#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 49577#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 49575#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 49574#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 49571#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 49569#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 49568#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 49565#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 49563#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 49562#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 49559#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 49557#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 49556#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 49553#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 49551#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 49550#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 49547#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 49545#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 49544#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 49541#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 49539#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 49538#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 49535#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 49533#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 49532#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 49529#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 49527#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 49526#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 49523#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 49521#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 49520#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 49517#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 49515#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 49514#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 49511#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 49509#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 49508#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 49505#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 49503#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 49502#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 49499#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 49497#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 49496#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 49493#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 49491#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 49490#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 49487#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 49485#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 49484#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 49481#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 49479#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 49478#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 49475#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 49473#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 49472#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 49469#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 49467#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 49466#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 49463#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 49461#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 49460#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 49457#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 49455#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 49454#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 49451#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 49449#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 49448#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 49445#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 49443#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 49442#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 49440#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 49439#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 49438#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 49344#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 49331#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 49341#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 49346#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 49427#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 49426#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 49353#L34 [2022-07-14 15:09:41,203 INFO L754 eck$LassoCheckResult]: Loop: 49353#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 49354#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 49352#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 49353#L34 [2022-07-14 15:09:41,203 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:09:41,203 INFO L85 PathProgramCache]: Analyzing trace with hash 1579079523, now seen corresponding path program 72 times [2022-07-14 15:09:41,203 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:09:41,203 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [760129188] [2022-07-14 15:09:41,203 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:09:41,203 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:09:41,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:09:41,391 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:09:41,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:09:41,613 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:09:41,613 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:09:41,613 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 38 times [2022-07-14 15:09:41,614 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:09:41,614 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1767369280] [2022-07-14 15:09:41,614 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:09:41,614 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:09:41,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:09:41,618 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:09:41,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:09:41,621 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:09:41,621 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:09:41,621 INFO L85 PathProgramCache]: Analyzing trace with hash -418683629, now seen corresponding path program 73 times [2022-07-14 15:09:41,621 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:09:41,621 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1219235930] [2022-07-14 15:09:41,621 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:09:41,622 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:09:41,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:09:43,133 INFO L134 CoverageAnalysis]: Checked inductivity of 3404 backedges. 1926 proven. 1478 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:09:43,133 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:09:43,133 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1219235930] [2022-07-14 15:09:43,133 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1219235930] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:09:43,134 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [497918427] [2022-07-14 15:09:43,134 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-07-14 15:09:43,134 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:09:43,134 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:09:43,136 INFO L229 MonitoredProcess]: Starting monitored process 49 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:09:43,137 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (49)] Waiting until timeout for monitored process [2022-07-14 15:09:43,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:09:43,412 INFO L263 TraceCheckSpWp]: Trace formula consists of 822 conjuncts, 78 conjunts are in the unsatisfiable core [2022-07-14 15:09:43,414 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:09:45,356 INFO L134 CoverageAnalysis]: Checked inductivity of 3404 backedges. 2035 proven. 1369 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:09:45,356 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:09:45,608 INFO L134 CoverageAnalysis]: Checked inductivity of 3404 backedges. 2035 proven. 1369 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:09:45,609 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [497918427] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:09:45,609 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:09:45,609 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [78, 78, 78] total 118 [2022-07-14 15:09:45,609 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2101590056] [2022-07-14 15:09:45,609 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:09:45,636 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:09:45,637 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 119 interpolants. [2022-07-14 15:09:45,638 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3203, Invalid=10839, Unknown=0, NotChecked=0, Total=14042 [2022-07-14 15:09:45,638 INFO L87 Difference]: Start difference. First operand 308 states and 348 transitions. cyclomatic complexity: 43 Second operand has 119 states, 118 states have (on average 2.6271186440677967) internal successors, (310), 119 states have internal predecessors, (310), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:09:48,190 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:09:48,190 INFO L93 Difference]: Finished difference Result 999 states and 1154 transitions. [2022-07-14 15:09:48,191 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 80 states. [2022-07-14 15:09:48,191 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 999 states and 1154 transitions. [2022-07-14 15:09:48,194 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:09:48,195 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 999 states to 550 states and 630 transitions. [2022-07-14 15:09:48,195 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 473 [2022-07-14 15:09:48,196 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 473 [2022-07-14 15:09:48,196 INFO L73 IsDeterministic]: Start isDeterministic. Operand 550 states and 630 transitions. [2022-07-14 15:09:48,196 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 15:09:48,196 INFO L369 hiAutomatonCegarLoop]: Abstraction has 550 states and 630 transitions. [2022-07-14 15:09:48,196 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 550 states and 630 transitions. [2022-07-14 15:09:48,199 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 550 to 316. [2022-07-14 15:09:48,199 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 316 states, 316 states have (on average 1.129746835443038) internal successors, (357), 315 states have internal predecessors, (357), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:09:48,200 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 316 states to 316 states and 357 transitions. [2022-07-14 15:09:48,200 INFO L392 hiAutomatonCegarLoop]: Abstraction has 316 states and 357 transitions. [2022-07-14 15:09:48,200 INFO L374 stractBuchiCegarLoop]: Abstraction has 316 states and 357 transitions. [2022-07-14 15:09:48,200 INFO L287 stractBuchiCegarLoop]: ======== Iteration 40 ============ [2022-07-14 15:09:48,200 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 316 states and 357 transitions. [2022-07-14 15:09:48,201 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:09:48,201 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:09:48,201 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:09:48,201 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [38, 38, 38, 37, 37, 1, 1, 1, 1] [2022-07-14 15:09:48,201 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-07-14 15:09:48,202 INFO L752 eck$LassoCheckResult]: Stem: 51967#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 51968#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 51973#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 51987#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 51988#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 51976#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 51977#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 52064#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 52063#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 52062#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 52061#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 52060#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 52059#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 52058#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 52057#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 52056#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 52055#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 52054#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 52053#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 52052#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 52051#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 52050#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 52049#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 52048#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 52047#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 52046#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 52045#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 52044#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 52043#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 52042#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 52041#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 52040#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 52039#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 52038#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 52037#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 52036#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 52035#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 52034#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 52033#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 52032#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 52031#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 52030#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 52029#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 52028#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 52027#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 52026#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 52025#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 52024#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 52023#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 52022#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 52021#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 52020#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 52019#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 52018#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 52017#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 52016#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 52015#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 52014#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 52013#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 52012#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 52011#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 52010#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 52009#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 52008#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 52007#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 52006#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 52005#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 52004#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 52003#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 52002#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 52001#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 52000#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 51999#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 51998#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 51997#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 51996#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 51995#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 51991#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 51990#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 51978#L27-4 main_~i~0#1 := 0; 51979#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 52277#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 52074#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 52072#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 52073#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 52077#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 52275#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 52272#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 52270#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 52269#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 52266#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 52264#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 52263#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 52260#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 52258#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 52257#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 52254#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 52252#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 52251#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 52248#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 52246#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 52245#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 52242#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 52240#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 52239#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 52236#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 52234#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 52233#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 52230#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 52228#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 52227#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 52224#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 52222#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 52221#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 52218#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 52216#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 52215#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 52212#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 52210#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 52209#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 52206#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 52204#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 52203#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 52200#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 52198#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 52197#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 52194#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 52192#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 52191#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 52188#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 52186#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 52185#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 52182#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 52180#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 52179#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 52176#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 52174#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 52173#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 52170#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 52168#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 52167#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 52164#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 52162#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 52161#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 52158#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 52156#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 52155#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 52152#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 52150#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 52149#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 52146#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 52144#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 52143#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 52140#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 52138#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 52137#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 52134#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 52132#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 52131#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 52128#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 52126#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 52125#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 52122#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 52120#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 52119#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 52116#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 52114#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 52113#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 52110#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 52108#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 52107#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 52104#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 52102#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 52101#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 52098#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 52096#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 52095#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 52092#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 52090#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 52089#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 52086#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 52084#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 52083#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 52082#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 52081#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 52080#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 51984#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 51972#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 51981#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 51986#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 52069#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 52068#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 51993#L34 [2022-07-14 15:09:48,202 INFO L754 eck$LassoCheckResult]: Loop: 51993#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 51994#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 51992#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 51993#L34 [2022-07-14 15:09:48,202 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:09:48,202 INFO L85 PathProgramCache]: Analyzing trace with hash -1953963371, now seen corresponding path program 74 times [2022-07-14 15:09:48,202 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:09:48,202 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [240514716] [2022-07-14 15:09:48,202 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:09:48,202 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:09:48,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:09:48,577 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:09:48,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:09:48,890 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:09:48,891 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:09:48,891 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 39 times [2022-07-14 15:09:48,891 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:09:48,891 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1708359587] [2022-07-14 15:09:48,891 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:09:48,891 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:09:48,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:09:48,896 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:09:48,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:09:48,900 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:09:48,900 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:09:48,900 INFO L85 PathProgramCache]: Analyzing trace with hash -830983007, now seen corresponding path program 75 times [2022-07-14 15:09:48,900 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:09:48,900 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1719839195] [2022-07-14 15:09:48,900 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:09:48,900 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:09:48,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:09:50,696 INFO L134 CoverageAnalysis]: Checked inductivity of 3591 backedges. 2035 proven. 1556 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:09:50,696 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:09:50,696 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1719839195] [2022-07-14 15:09:50,696 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1719839195] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:09:50,696 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1863769188] [2022-07-14 15:09:50,697 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-07-14 15:09:50,697 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:09:50,697 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:09:50,698 INFO L229 MonitoredProcess]: Starting monitored process 50 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:09:50,699 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (50)] Waiting until timeout for monitored process [2022-07-14 15:10:03,219 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 39 check-sat command(s) [2022-07-14 15:10:03,219 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-07-14 15:10:03,247 INFO L263 TraceCheckSpWp]: Trace formula consists of 843 conjuncts, 80 conjunts are in the unsatisfiable core [2022-07-14 15:10:03,249 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:10:05,254 INFO L134 CoverageAnalysis]: Checked inductivity of 3591 backedges. 2147 proven. 1444 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:10:05,254 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:10:05,494 INFO L134 CoverageAnalysis]: Checked inductivity of 3591 backedges. 2147 proven. 1444 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:10:05,494 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1863769188] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:10:05,494 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:10:05,495 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [80, 80, 80] total 121 [2022-07-14 15:10:05,495 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2036955352] [2022-07-14 15:10:05,495 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:10:05,524 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:10:05,525 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 122 interpolants. [2022-07-14 15:10:05,526 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3365, Invalid=11397, Unknown=0, NotChecked=0, Total=14762 [2022-07-14 15:10:05,527 INFO L87 Difference]: Start difference. First operand 316 states and 357 transitions. cyclomatic complexity: 44 Second operand has 122 states, 121 states have (on average 2.628099173553719) internal successors, (318), 122 states have internal predecessors, (318), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:10:07,457 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:10:07,457 INFO L93 Difference]: Finished difference Result 1025 states and 1184 transitions. [2022-07-14 15:10:07,457 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 82 states. [2022-07-14 15:10:07,457 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1025 states and 1184 transitions. [2022-07-14 15:10:07,460 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:10:07,461 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1025 states to 564 states and 646 transitions. [2022-07-14 15:10:07,461 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 485 [2022-07-14 15:10:07,461 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 485 [2022-07-14 15:10:07,461 INFO L73 IsDeterministic]: Start isDeterministic. Operand 564 states and 646 transitions. [2022-07-14 15:10:07,461 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 15:10:07,461 INFO L369 hiAutomatonCegarLoop]: Abstraction has 564 states and 646 transitions. [2022-07-14 15:10:07,462 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 564 states and 646 transitions. [2022-07-14 15:10:07,464 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 564 to 324. [2022-07-14 15:10:07,464 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 324 states, 324 states have (on average 1.1296296296296295) internal successors, (366), 323 states have internal predecessors, (366), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:10:07,465 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 324 states to 324 states and 366 transitions. [2022-07-14 15:10:07,465 INFO L392 hiAutomatonCegarLoop]: Abstraction has 324 states and 366 transitions. [2022-07-14 15:10:07,465 INFO L374 stractBuchiCegarLoop]: Abstraction has 324 states and 366 transitions. [2022-07-14 15:10:07,465 INFO L287 stractBuchiCegarLoop]: ======== Iteration 41 ============ [2022-07-14 15:10:07,465 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 324 states and 366 transitions. [2022-07-14 15:10:07,466 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-07-14 15:10:07,466 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:10:07,466 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:10:07,466 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [39, 39, 39, 38, 38, 1, 1, 1, 1] [2022-07-14 15:10:07,467 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-07-14 15:10:07,467 INFO L752 eck$LassoCheckResult]: Stem: 54677#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 54678#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 54683#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 54698#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 54699#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 54686#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 54687#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 54777#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 54776#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 54775#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 54774#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 54773#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 54772#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 54771#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 54770#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 54769#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 54768#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 54767#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 54766#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 54765#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 54764#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 54763#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 54762#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 54761#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 54760#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 54759#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 54758#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 54757#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 54756#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 54755#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 54754#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 54753#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 54752#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 54751#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 54750#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 54749#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 54748#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 54747#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 54746#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 54745#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 54744#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 54743#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 54742#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 54741#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 54740#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 54739#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 54738#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 54737#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 54736#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 54735#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 54734#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 54733#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 54732#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 54731#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 54730#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 54729#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 54728#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 54727#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 54726#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 54725#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 54724#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 54723#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 54722#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 54721#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 54720#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 54719#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 54718#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 54717#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 54716#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 54715#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 54714#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 54713#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 54712#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 54711#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 54710#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 54709#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 54708#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 54707#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 54706#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 54702#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 54701#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 54688#L27-4 main_~i~0#1 := 0; 54689#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 54785#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 54786#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 54787#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 54791#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 54790#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 54995#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 54992#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 54990#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 54989#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 54986#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 54984#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 54983#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 54980#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 54978#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 54977#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 54974#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 54972#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 54971#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 54968#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 54966#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 54965#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 54962#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 54960#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 54959#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 54956#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 54954#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 54953#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 54950#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 54948#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 54947#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 54944#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 54942#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 54941#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 54938#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 54936#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 54935#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 54932#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 54930#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 54929#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 54926#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 54924#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 54923#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 54920#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 54918#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 54917#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 54914#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 54912#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 54911#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 54908#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 54906#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 54905#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 54902#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 54900#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 54899#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 54896#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 54894#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 54893#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 54890#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 54888#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 54887#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 54884#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 54882#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 54881#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 54878#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 54876#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 54875#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 54872#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 54870#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 54869#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 54866#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 54864#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 54863#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 54860#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 54858#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 54857#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 54854#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 54852#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 54851#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 54848#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 54846#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 54845#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 54842#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 54840#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 54839#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 54836#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 54834#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 54833#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 54830#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 54828#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 54827#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 54824#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 54822#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 54821#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 54818#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 54816#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 54815#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 54812#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 54810#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 54809#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 54806#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 54804#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 54803#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 54800#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 54798#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 54797#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 54795#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 54794#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 54793#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 54695#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 54682#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 54692#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 54697#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 54782#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 54781#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 54704#L34 [2022-07-14 15:10:07,467 INFO L754 eck$LassoCheckResult]: Loop: 54704#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 54705#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 54703#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 54704#L34 [2022-07-14 15:10:07,467 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:10:07,467 INFO L85 PathProgramCache]: Analyzing trace with hash -1682515873, now seen corresponding path program 76 times [2022-07-14 15:10:07,468 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:10:07,468 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1767466381] [2022-07-14 15:10:07,468 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:10:07,468 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:10:07,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:10:07,731 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:10:07,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:10:07,991 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:10:07,992 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:10:07,992 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 40 times [2022-07-14 15:10:07,992 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:10:07,992 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [545714581] [2022-07-14 15:10:07,992 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:10:07,992 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:10:07,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:10:07,996 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:10:07,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:10:07,999 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:10:07,999 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:10:07,999 INFO L85 PathProgramCache]: Analyzing trace with hash -1561988457, now seen corresponding path program 77 times [2022-07-14 15:10:07,999 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:10:07,999 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2028091854] [2022-07-14 15:10:07,999 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:10:07,999 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:10:08,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:10:09,701 INFO L134 CoverageAnalysis]: Checked inductivity of 3783 backedges. 2147 proven. 1636 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:10:09,701 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:10:09,701 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2028091854] [2022-07-14 15:10:09,701 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2028091854] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:10:09,701 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1051924338] [2022-07-14 15:10:09,701 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-07-14 15:10:09,701 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:10:09,701 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:10:09,703 INFO L229 MonitoredProcess]: Starting monitored process 51 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:10:09,704 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (51)] Waiting until timeout for monitored process