./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/loop-invgen/string_concat-noarr.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version f4b24e32 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/loop-invgen/string_concat-noarr.i -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 30a4b942034eaa47a8fcc8fdf4549d1d63a9a60d59b585da2a353c9626604750 --- Real Ultimate output --- This is Ultimate 0.2.2-?-f4b24e3 [2022-07-14 15:41:10,310 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-07-14 15:41:10,311 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-07-14 15:41:10,341 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-07-14 15:41:10,341 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-07-14 15:41:10,343 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-07-14 15:41:10,347 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-07-14 15:41:10,352 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-07-14 15:41:10,353 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-07-14 15:41:10,356 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-07-14 15:41:10,357 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-07-14 15:41:10,359 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-07-14 15:41:10,359 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-07-14 15:41:10,360 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-07-14 15:41:10,361 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-07-14 15:41:10,362 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-07-14 15:41:10,363 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-07-14 15:41:10,364 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-07-14 15:41:10,367 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-07-14 15:41:10,372 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-07-14 15:41:10,373 INFO L181 SettingsManager]: Resetting HornVerifier preferences to default values [2022-07-14 15:41:10,374 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-07-14 15:41:10,375 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-07-14 15:41:10,376 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-07-14 15:41:10,377 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-07-14 15:41:10,379 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-07-14 15:41:10,379 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-07-14 15:41:10,380 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-07-14 15:41:10,381 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-07-14 15:41:10,381 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-07-14 15:41:10,382 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-07-14 15:41:10,382 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-07-14 15:41:10,383 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-07-14 15:41:10,384 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-07-14 15:41:10,384 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-07-14 15:41:10,385 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-07-14 15:41:10,385 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-07-14 15:41:10,386 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-07-14 15:41:10,386 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-07-14 15:41:10,386 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-07-14 15:41:10,387 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-07-14 15:41:10,388 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-07-14 15:41:10,389 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-07-14 15:41:10,414 INFO L113 SettingsManager]: Loading preferences was successful [2022-07-14 15:41:10,414 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-07-14 15:41:10,414 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-07-14 15:41:10,415 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-07-14 15:41:10,416 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-07-14 15:41:10,416 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-07-14 15:41:10,416 INFO L138 SettingsManager]: * Use SBE=true [2022-07-14 15:41:10,416 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-07-14 15:41:10,416 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-07-14 15:41:10,417 INFO L138 SettingsManager]: * Use old map elimination=false [2022-07-14 15:41:10,417 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-07-14 15:41:10,417 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-07-14 15:41:10,417 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-07-14 15:41:10,417 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-07-14 15:41:10,418 INFO L138 SettingsManager]: * sizeof long=4 [2022-07-14 15:41:10,418 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-07-14 15:41:10,419 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-07-14 15:41:10,419 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-07-14 15:41:10,419 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-07-14 15:41:10,419 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-07-14 15:41:10,419 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-07-14 15:41:10,419 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-07-14 15:41:10,419 INFO L138 SettingsManager]: * sizeof long double=12 [2022-07-14 15:41:10,420 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-07-14 15:41:10,420 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-07-14 15:41:10,420 INFO L138 SettingsManager]: * Use constant arrays=true [2022-07-14 15:41:10,420 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-07-14 15:41:10,420 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-07-14 15:41:10,420 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-07-14 15:41:10,420 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-07-14 15:41:10,421 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-07-14 15:41:10,421 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-07-14 15:41:10,421 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 30a4b942034eaa47a8fcc8fdf4549d1d63a9a60d59b585da2a353c9626604750 [2022-07-14 15:41:10,630 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-07-14 15:41:10,651 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-07-14 15:41:10,652 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-07-14 15:41:10,653 INFO L271 PluginConnector]: Initializing CDTParser... [2022-07-14 15:41:10,654 INFO L275 PluginConnector]: CDTParser initialized [2022-07-14 15:41:10,655 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/loop-invgen/string_concat-noarr.i [2022-07-14 15:41:10,701 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/b8e636f30/7eb46e3966a84aa6b1353af1861e049e/FLAGe0482225b [2022-07-14 15:41:11,084 INFO L306 CDTParser]: Found 1 translation units. [2022-07-14 15:41:11,085 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/loop-invgen/string_concat-noarr.i [2022-07-14 15:41:11,090 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/b8e636f30/7eb46e3966a84aa6b1353af1861e049e/FLAGe0482225b [2022-07-14 15:41:11,107 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/b8e636f30/7eb46e3966a84aa6b1353af1861e049e [2022-07-14 15:41:11,109 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-07-14 15:41:11,110 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-07-14 15:41:11,113 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-07-14 15:41:11,113 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-07-14 15:41:11,116 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-07-14 15:41:11,116 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.07 03:41:11" (1/1) ... [2022-07-14 15:41:11,118 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@a5c4166 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 03:41:11, skipping insertion in model container [2022-07-14 15:41:11,118 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.07 03:41:11" (1/1) ... [2022-07-14 15:41:11,122 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-07-14 15:41:11,136 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-07-14 15:41:11,261 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/loop-invgen/string_concat-noarr.i[893,906] [2022-07-14 15:41:11,269 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-14 15:41:11,275 INFO L203 MainTranslator]: Completed pre-run [2022-07-14 15:41:11,283 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/loop-invgen/string_concat-noarr.i[893,906] [2022-07-14 15:41:11,285 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-14 15:41:11,294 INFO L208 MainTranslator]: Completed translation [2022-07-14 15:41:11,295 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 03:41:11 WrapperNode [2022-07-14 15:41:11,295 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-07-14 15:41:11,296 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-07-14 15:41:11,296 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-07-14 15:41:11,296 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-07-14 15:41:11,301 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 03:41:11" (1/1) ... [2022-07-14 15:41:11,305 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 03:41:11" (1/1) ... [2022-07-14 15:41:11,322 INFO L137 Inliner]: procedures = 16, calls = 7, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 51 [2022-07-14 15:41:11,323 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-07-14 15:41:11,324 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-07-14 15:41:11,324 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-07-14 15:41:11,324 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-07-14 15:41:11,329 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 03:41:11" (1/1) ... [2022-07-14 15:41:11,330 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 03:41:11" (1/1) ... [2022-07-14 15:41:11,338 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 03:41:11" (1/1) ... [2022-07-14 15:41:11,339 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 03:41:11" (1/1) ... [2022-07-14 15:41:11,344 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 03:41:11" (1/1) ... [2022-07-14 15:41:11,347 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 03:41:11" (1/1) ... [2022-07-14 15:41:11,348 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 03:41:11" (1/1) ... [2022-07-14 15:41:11,349 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-07-14 15:41:11,351 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-07-14 15:41:11,351 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-07-14 15:41:11,352 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-07-14 15:41:11,352 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 03:41:11" (1/1) ... [2022-07-14 15:41:11,358 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 15:41:11,366 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:41:11,386 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-14 15:41:11,389 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-07-14 15:41:11,424 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-07-14 15:41:11,424 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-07-14 15:41:11,424 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-07-14 15:41:11,424 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-07-14 15:41:11,464 INFO L234 CfgBuilder]: Building ICFG [2022-07-14 15:41:11,465 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-07-14 15:41:11,583 INFO L275 CfgBuilder]: Performing block encoding [2022-07-14 15:41:11,586 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-07-14 15:41:11,587 INFO L299 CfgBuilder]: Removed 2 assume(true) statements. [2022-07-14 15:41:11,589 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.07 03:41:11 BoogieIcfgContainer [2022-07-14 15:41:11,589 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-07-14 15:41:11,590 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-07-14 15:41:11,590 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-07-14 15:41:11,593 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-07-14 15:41:11,593 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-14 15:41:11,593 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 14.07 03:41:11" (1/3) ... [2022-07-14 15:41:11,594 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3a3d2100 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 14.07 03:41:11, skipping insertion in model container [2022-07-14 15:41:11,594 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-14 15:41:11,594 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 03:41:11" (2/3) ... [2022-07-14 15:41:11,595 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3a3d2100 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 14.07 03:41:11, skipping insertion in model container [2022-07-14 15:41:11,595 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-14 15:41:11,595 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.07 03:41:11" (3/3) ... [2022-07-14 15:41:11,596 INFO L354 chiAutomizerObserver]: Analyzing ICFG string_concat-noarr.i [2022-07-14 15:41:11,674 INFO L255 stractBuchiCegarLoop]: Interprodecural is true [2022-07-14 15:41:11,687 INFO L256 stractBuchiCegarLoop]: Hoare is false [2022-07-14 15:41:11,687 INFO L257 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-07-14 15:41:11,687 INFO L258 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-07-14 15:41:11,688 INFO L259 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-07-14 15:41:11,688 INFO L260 stractBuchiCegarLoop]: Difference is false [2022-07-14 15:41:11,688 INFO L261 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-07-14 15:41:11,688 INFO L265 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-07-14 15:41:11,717 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 14 states, 13 states have (on average 1.5384615384615385) internal successors, (20), 13 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:41:11,731 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2022-07-14 15:41:11,731 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:41:11,731 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:41:11,735 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1] [2022-07-14 15:41:11,735 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-07-14 15:41:11,735 INFO L287 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-07-14 15:41:11,735 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 14 states, 13 states have (on average 1.5384615384615385) internal successors, (20), 13 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:41:11,738 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2022-07-14 15:41:11,738 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:41:11,738 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:41:11,738 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1] [2022-07-14 15:41:11,738 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-07-14 15:41:11,743 INFO L752 eck$LassoCheckResult]: Stem: 3#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 6#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 5#L26true main_~i~0#1 := 0; 4#L29-1true [2022-07-14 15:41:11,744 INFO L754 eck$LassoCheckResult]: Loop: 4#L29-1true assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4#L29-1true [2022-07-14 15:41:11,758 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:41:11,758 INFO L85 PathProgramCache]: Analyzing trace with hash 29857, now seen corresponding path program 1 times [2022-07-14 15:41:11,764 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:41:11,765 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [210967896] [2022-07-14 15:41:11,765 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:41:11,766 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:41:11,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:41:11,825 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:41:11,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:41:11,847 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:41:11,849 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:41:11,849 INFO L85 PathProgramCache]: Analyzing trace with hash 44, now seen corresponding path program 1 times [2022-07-14 15:41:11,850 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:41:11,851 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1674726080] [2022-07-14 15:41:11,851 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:41:11,851 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:41:11,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:41:11,863 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:41:11,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:41:11,872 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:41:11,879 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:41:11,879 INFO L85 PathProgramCache]: Analyzing trace with hash 925580, now seen corresponding path program 1 times [2022-07-14 15:41:11,880 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:41:11,880 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1374957208] [2022-07-14 15:41:11,880 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:41:11,880 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:41:11,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:41:11,898 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:41:11,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:41:11,913 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:41:11,950 INFO L210 LassoAnalysis]: Preferences: [2022-07-14 15:41:11,951 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-07-14 15:41:11,951 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-07-14 15:41:11,951 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-07-14 15:41:11,951 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2022-07-14 15:41:11,951 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 15:41:11,951 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-07-14 15:41:11,952 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-07-14 15:41:11,952 INFO L133 ssoRankerPreferences]: Filename of dumped script: string_concat-noarr.i_Iteration1_Loop [2022-07-14 15:41:11,952 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-07-14 15:41:11,952 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-07-14 15:41:11,962 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 15:41:11,966 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 15:41:11,972 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 15:41:12,003 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-07-14 15:41:12,004 INFO L404 LassoAnalysis]: Checking for nontermination... [2022-07-14 15:41:12,006 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 15:41:12,006 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:41:12,020 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-14 15:41:12,023 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2022-07-14 15:41:12,024 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2022-07-14 15:41:12,024 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-07-14 15:41:12,050 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2022-07-14 15:41:12,051 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_main_#t~post2#1=0} Honda state: {ULTIMATE.start_main_#t~post2#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2022-07-14 15:41:12,067 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2022-07-14 15:41:12,067 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 15:41:12,068 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:41:12,069 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-14 15:41:12,070 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2022-07-14 15:41:12,074 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2022-07-14 15:41:12,074 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-07-14 15:41:12,096 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2022-07-14 15:41:12,097 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_main_#t~nondet1#1=-1} Honda state: {ULTIMATE.start_main_#t~nondet1#1=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2022-07-14 15:41:12,113 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2022-07-14 15:41:12,113 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 15:41:12,113 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:41:12,115 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-14 15:41:12,116 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2022-07-14 15:41:12,149 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2022-07-14 15:41:12,149 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-07-14 15:41:12,187 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2022-07-14 15:41:12,188 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 15:41:12,188 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:41:12,190 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-14 15:41:12,191 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2022-07-14 15:41:12,192 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2022-07-14 15:41:12,192 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-07-14 15:41:12,219 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2022-07-14 15:41:12,226 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2022-07-14 15:41:12,226 INFO L210 LassoAnalysis]: Preferences: [2022-07-14 15:41:12,228 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-07-14 15:41:12,228 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-07-14 15:41:12,228 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-07-14 15:41:12,228 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2022-07-14 15:41:12,228 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 15:41:12,228 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-07-14 15:41:12,228 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-07-14 15:41:12,228 INFO L133 ssoRankerPreferences]: Filename of dumped script: string_concat-noarr.i_Iteration1_Loop [2022-07-14 15:41:12,228 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-07-14 15:41:12,228 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-07-14 15:41:12,229 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 15:41:12,234 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 15:41:12,239 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-07-14 15:41:12,292 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-07-14 15:41:12,295 INFO L490 LassoAnalysis]: Using template 'affine'. [2022-07-14 15:41:12,296 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 15:41:12,297 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:41:12,312 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-14 15:41:12,345 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2022-07-14 15:41:12,346 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-07-14 15:41:12,352 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-07-14 15:41:12,352 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-07-14 15:41:12,353 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-07-14 15:41:12,353 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-07-14 15:41:12,353 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-07-14 15:41:12,355 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-07-14 15:41:12,355 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-07-14 15:41:12,367 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-07-14 15:41:12,383 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2022-07-14 15:41:12,383 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 15:41:12,384 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:41:12,385 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-14 15:41:12,386 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2022-07-14 15:41:12,387 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-07-14 15:41:12,394 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-07-14 15:41:12,394 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-07-14 15:41:12,394 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-07-14 15:41:12,394 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-07-14 15:41:12,394 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-07-14 15:41:12,399 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-07-14 15:41:12,399 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-07-14 15:41:12,403 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2022-07-14 15:41:12,407 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2022-07-14 15:41:12,407 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2022-07-14 15:41:12,409 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 15:41:12,409 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:41:12,410 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-14 15:41:12,412 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2022-07-14 15:41:12,412 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2022-07-14 15:41:12,412 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2022-07-14 15:41:12,412 INFO L513 LassoAnalysis]: Proved termination. [2022-07-14 15:41:12,413 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0#1) = -2*ULTIMATE.start_main_~i~0#1 + 1999999 Supporting invariants [] [2022-07-14 15:41:12,431 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2022-07-14 15:41:12,434 INFO L293 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2022-07-14 15:41:12,470 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:41:12,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:41:12,488 INFO L263 TraceCheckSpWp]: Trace formula consists of 24 conjuncts, 2 conjunts are in the unsatisfiable core [2022-07-14 15:41:12,488 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:41:12,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:41:12,498 WARN L261 TraceCheckSpWp]: Trace formula consists of 6 conjuncts, 4 conjunts are in the unsatisfiable core [2022-07-14 15:41:12,498 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:41:12,499 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:41:12,519 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 1 loop predicates [2022-07-14 15:41:12,520 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 14 states, 13 states have (on average 1.5384615384615385) internal successors, (20), 13 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 2.0) internal successors, (4), 2 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:41:12,548 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 14 states, 13 states have (on average 1.5384615384615385) internal successors, (20), 13 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 2 states, 2 states have (on average 2.0) internal successors, (4), 2 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 37 states and 56 transitions. Complement of second has 5 states. [2022-07-14 15:41:12,550 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2022-07-14 15:41:12,553 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2 states, 2 states have (on average 2.0) internal successors, (4), 2 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:41:12,554 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 37 transitions. [2022-07-14 15:41:12,555 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 37 transitions. Stem has 3 letters. Loop has 1 letters. [2022-07-14 15:41:12,555 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-07-14 15:41:12,555 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 37 transitions. Stem has 4 letters. Loop has 1 letters. [2022-07-14 15:41:12,556 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-07-14 15:41:12,556 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 37 transitions. Stem has 3 letters. Loop has 2 letters. [2022-07-14 15:41:12,556 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-07-14 15:41:12,556 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37 states and 56 transitions. [2022-07-14 15:41:12,558 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-07-14 15:41:12,561 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37 states to 13 states and 19 transitions. [2022-07-14 15:41:12,562 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2022-07-14 15:41:12,562 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2022-07-14 15:41:12,562 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13 states and 19 transitions. [2022-07-14 15:41:12,562 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-07-14 15:41:12,562 INFO L369 hiAutomatonCegarLoop]: Abstraction has 13 states and 19 transitions. [2022-07-14 15:41:12,572 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13 states and 19 transitions. [2022-07-14 15:41:12,577 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13 to 12. [2022-07-14 15:41:12,577 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12 states, 12 states have (on average 1.5) internal successors, (18), 11 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:41:12,578 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 18 transitions. [2022-07-14 15:41:12,578 INFO L392 hiAutomatonCegarLoop]: Abstraction has 12 states and 18 transitions. [2022-07-14 15:41:12,578 INFO L374 stractBuchiCegarLoop]: Abstraction has 12 states and 18 transitions. [2022-07-14 15:41:12,579 INFO L287 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-07-14 15:41:12,579 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12 states and 18 transitions. [2022-07-14 15:41:12,579 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-07-14 15:41:12,579 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:41:12,579 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:41:12,580 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2022-07-14 15:41:12,580 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-07-14 15:41:12,580 INFO L752 eck$LassoCheckResult]: Stem: 90#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 91#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 97#L26 main_~i~0#1 := 0; 92#L29-1 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 94#L29-2 assume main_~i~0#1 >= 100; 96#L39 [2022-07-14 15:41:12,580 INFO L754 eck$LassoCheckResult]: Loop: 96#L39 assume true; 96#L39 [2022-07-14 15:41:12,581 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:41:12,581 INFO L85 PathProgramCache]: Analyzing trace with hash 28692937, now seen corresponding path program 1 times [2022-07-14 15:41:12,581 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:41:12,581 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1795552751] [2022-07-14 15:41:12,581 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:41:12,582 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:41:12,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:41:12,605 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:41:12,605 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:41:12,605 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1795552751] [2022-07-14 15:41:12,606 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1795552751] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 15:41:12,606 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 15:41:12,606 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-14 15:41:12,606 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1523309630] [2022-07-14 15:41:12,607 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 15:41:12,608 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 15:41:12,608 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:41:12,608 INFO L85 PathProgramCache]: Analyzing trace with hash 84, now seen corresponding path program 1 times [2022-07-14 15:41:12,609 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:41:12,609 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [270393400] [2022-07-14 15:41:12,609 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:41:12,609 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:41:12,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:41:12,611 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:41:12,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:41:12,615 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:41:12,618 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:41:12,620 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 15:41:12,620 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 15:41:12,621 INFO L87 Difference]: Start difference. First operand 12 states and 18 transitions. cyclomatic complexity: 9 Second operand has 3 states, 2 states have (on average 2.5) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:41:12,639 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:41:12,642 INFO L93 Difference]: Finished difference Result 18 states and 24 transitions. [2022-07-14 15:41:12,643 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 15:41:12,643 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18 states and 24 transitions. [2022-07-14 15:41:12,648 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2 [2022-07-14 15:41:12,649 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18 states to 18 states and 24 transitions. [2022-07-14 15:41:12,649 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12 [2022-07-14 15:41:12,649 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12 [2022-07-14 15:41:12,649 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18 states and 24 transitions. [2022-07-14 15:41:12,649 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-07-14 15:41:12,649 INFO L369 hiAutomatonCegarLoop]: Abstraction has 18 states and 24 transitions. [2022-07-14 15:41:12,649 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18 states and 24 transitions. [2022-07-14 15:41:12,651 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18 to 13. [2022-07-14 15:41:12,651 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13 states, 13 states have (on average 1.4615384615384615) internal successors, (19), 12 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:41:12,652 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 19 transitions. [2022-07-14 15:41:12,652 INFO L392 hiAutomatonCegarLoop]: Abstraction has 13 states and 19 transitions. [2022-07-14 15:41:12,652 INFO L374 stractBuchiCegarLoop]: Abstraction has 13 states and 19 transitions. [2022-07-14 15:41:12,652 INFO L287 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-07-14 15:41:12,652 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13 states and 19 transitions. [2022-07-14 15:41:12,654 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-07-14 15:41:12,654 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:41:12,654 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:41:12,654 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1] [2022-07-14 15:41:12,654 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-07-14 15:41:12,654 INFO L752 eck$LassoCheckResult]: Stem: 126#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 127#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 134#L26 main_~i~0#1 := 0; 128#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 131#L29-1 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 132#L29-2 assume main_~i~0#1 >= 100; 133#L39 [2022-07-14 15:41:12,654 INFO L754 eck$LassoCheckResult]: Loop: 133#L39 assume true; 133#L39 [2022-07-14 15:41:12,655 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:41:12,655 INFO L85 PathProgramCache]: Analyzing trace with hash 889482740, now seen corresponding path program 1 times [2022-07-14 15:41:12,655 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:41:12,655 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1797249847] [2022-07-14 15:41:12,655 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:41:12,655 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:41:12,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:41:12,676 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:41:12,676 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:41:12,676 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1797249847] [2022-07-14 15:41:12,676 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1797249847] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:41:12,676 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [453705446] [2022-07-14 15:41:12,677 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:41:12,677 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:41:12,677 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:41:12,678 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:41:12,679 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2022-07-14 15:41:12,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:41:12,737 INFO L263 TraceCheckSpWp]: Trace formula consists of 30 conjuncts, 3 conjunts are in the unsatisfiable core [2022-07-14 15:41:12,738 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:41:12,772 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:41:12,772 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:41:12,786 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:41:12,786 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [453705446] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:41:12,786 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:41:12,786 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 6 [2022-07-14 15:41:12,786 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1887429403] [2022-07-14 15:41:12,786 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:41:12,787 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 15:41:12,787 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:41:12,787 INFO L85 PathProgramCache]: Analyzing trace with hash 84, now seen corresponding path program 2 times [2022-07-14 15:41:12,787 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:41:12,787 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1030767518] [2022-07-14 15:41:12,787 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:41:12,787 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:41:12,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:41:12,789 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:41:12,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:41:12,790 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:41:12,791 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:41:12,792 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-07-14 15:41:12,792 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2022-07-14 15:41:12,792 INFO L87 Difference]: Start difference. First operand 13 states and 19 transitions. cyclomatic complexity: 9 Second operand has 7 states, 6 states have (on average 2.0) internal successors, (12), 7 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:41:12,829 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:41:12,830 INFO L93 Difference]: Finished difference Result 40 states and 55 transitions. [2022-07-14 15:41:12,830 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-07-14 15:41:12,830 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 40 states and 55 transitions. [2022-07-14 15:41:12,832 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 5 [2022-07-14 15:41:12,833 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 40 states to 40 states and 55 transitions. [2022-07-14 15:41:12,833 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23 [2022-07-14 15:41:12,833 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23 [2022-07-14 15:41:12,834 INFO L73 IsDeterministic]: Start isDeterministic. Operand 40 states and 55 transitions. [2022-07-14 15:41:12,834 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-07-14 15:41:12,834 INFO L369 hiAutomatonCegarLoop]: Abstraction has 40 states and 55 transitions. [2022-07-14 15:41:12,834 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states and 55 transitions. [2022-07-14 15:41:12,835 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 16. [2022-07-14 15:41:12,835 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 1.75) internal successors, (28), 15 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:41:12,836 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 28 transitions. [2022-07-14 15:41:12,836 INFO L392 hiAutomatonCegarLoop]: Abstraction has 16 states and 28 transitions. [2022-07-14 15:41:12,836 INFO L374 stractBuchiCegarLoop]: Abstraction has 16 states and 28 transitions. [2022-07-14 15:41:12,836 INFO L287 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-07-14 15:41:12,836 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16 states and 28 transitions. [2022-07-14 15:41:12,837 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-07-14 15:41:12,837 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:41:12,837 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:41:12,837 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1] [2022-07-14 15:41:12,837 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-07-14 15:41:12,837 INFO L752 eck$LassoCheckResult]: Stem: 219#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 220#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 227#L26 main_~i~0#1 := 0; 221#L29-1 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 223#L29-2 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 215#L35-1 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 216#L35-2 assume main_~j~0#1 >= 100; 226#L39 [2022-07-14 15:41:12,838 INFO L754 eck$LassoCheckResult]: Loop: 226#L39 assume true; 226#L39 [2022-07-14 15:41:12,838 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:41:12,838 INFO L85 PathProgramCache]: Analyzing trace with hash 1804112500, now seen corresponding path program 1 times [2022-07-14 15:41:12,838 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:41:12,838 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1804843537] [2022-07-14 15:41:12,838 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:41:12,839 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:41:12,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:41:12,850 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:41:12,851 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:41:12,851 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1804843537] [2022-07-14 15:41:12,851 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1804843537] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 15:41:12,851 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 15:41:12,851 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-14 15:41:12,852 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1582965449] [2022-07-14 15:41:12,852 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 15:41:12,852 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 15:41:12,852 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:41:12,852 INFO L85 PathProgramCache]: Analyzing trace with hash 84, now seen corresponding path program 3 times [2022-07-14 15:41:12,853 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:41:12,853 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1266629957] [2022-07-14 15:41:12,853 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:41:12,853 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:41:12,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:41:12,855 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:41:12,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:41:12,856 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:41:12,858 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:41:12,858 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 15:41:12,858 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 15:41:12,859 INFO L87 Difference]: Start difference. First operand 16 states and 28 transitions. cyclomatic complexity: 15 Second operand has 3 states, 2 states have (on average 3.5) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:41:12,863 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:41:12,863 INFO L93 Difference]: Finished difference Result 17 states and 28 transitions. [2022-07-14 15:41:12,863 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 15:41:12,864 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17 states and 28 transitions. [2022-07-14 15:41:12,864 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-07-14 15:41:12,864 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17 states to 14 states and 21 transitions. [2022-07-14 15:41:12,865 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2022-07-14 15:41:12,865 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2022-07-14 15:41:12,865 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14 states and 21 transitions. [2022-07-14 15:41:12,865 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-07-14 15:41:12,865 INFO L369 hiAutomatonCegarLoop]: Abstraction has 14 states and 21 transitions. [2022-07-14 15:41:12,865 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14 states and 21 transitions. [2022-07-14 15:41:12,866 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14 to 14. [2022-07-14 15:41:12,866 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 1.5) internal successors, (21), 13 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:41:12,866 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 21 transitions. [2022-07-14 15:41:12,866 INFO L392 hiAutomatonCegarLoop]: Abstraction has 14 states and 21 transitions. [2022-07-14 15:41:12,867 INFO L374 stractBuchiCegarLoop]: Abstraction has 14 states and 21 transitions. [2022-07-14 15:41:12,867 INFO L287 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-07-14 15:41:12,867 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14 states and 21 transitions. [2022-07-14 15:41:12,867 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-07-14 15:41:12,867 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:41:12,867 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:41:12,868 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 15:41:12,868 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-07-14 15:41:12,868 INFO L752 eck$LassoCheckResult]: Stem: 256#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 257#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 264#L26 main_~i~0#1 := 0; 258#L29-1 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 259#L29-2 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 254#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 255#L35-1 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 262#L35-2 assume main_~j~0#1 >= 100; 263#L39 [2022-07-14 15:41:12,868 INFO L754 eck$LassoCheckResult]: Loop: 263#L39 assume true; 263#L39 [2022-07-14 15:41:12,868 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:41:12,868 INFO L85 PathProgramCache]: Analyzing trace with hash 92914363, now seen corresponding path program 1 times [2022-07-14 15:41:12,869 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:41:12,869 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [519112819] [2022-07-14 15:41:12,869 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:41:12,869 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:41:12,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:41:12,885 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:41:12,886 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:41:12,886 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [519112819] [2022-07-14 15:41:12,886 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [519112819] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:41:12,886 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1641657691] [2022-07-14 15:41:12,886 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:41:12,886 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:41:12,887 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:41:12,900 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:41:12,901 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2022-07-14 15:41:12,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:41:12,929 INFO L263 TraceCheckSpWp]: Trace formula consists of 36 conjuncts, 3 conjunts are in the unsatisfiable core [2022-07-14 15:41:12,930 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:41:12,945 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:41:12,945 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:41:12,964 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:41:12,964 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1641657691] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:41:12,965 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:41:12,965 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 6 [2022-07-14 15:41:12,965 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [874731853] [2022-07-14 15:41:12,965 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:41:12,966 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 15:41:12,967 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:41:12,967 INFO L85 PathProgramCache]: Analyzing trace with hash 84, now seen corresponding path program 4 times [2022-07-14 15:41:12,967 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:41:12,967 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1366126672] [2022-07-14 15:41:12,967 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:41:12,967 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:41:12,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:41:12,970 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:41:12,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:41:12,971 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:41:12,974 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:41:12,975 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-07-14 15:41:12,975 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2022-07-14 15:41:12,975 INFO L87 Difference]: Start difference. First operand 14 states and 21 transitions. cyclomatic complexity: 10 Second operand has 7 states, 6 states have (on average 2.3333333333333335) internal successors, (14), 7 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:41:12,991 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:41:12,991 INFO L93 Difference]: Finished difference Result 20 states and 27 transitions. [2022-07-14 15:41:12,991 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-07-14 15:41:12,993 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20 states and 27 transitions. [2022-07-14 15:41:12,994 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-07-14 15:41:12,995 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20 states to 17 states and 24 transitions. [2022-07-14 15:41:12,995 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2022-07-14 15:41:12,995 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2022-07-14 15:41:12,995 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17 states and 24 transitions. [2022-07-14 15:41:12,995 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-07-14 15:41:12,995 INFO L369 hiAutomatonCegarLoop]: Abstraction has 17 states and 24 transitions. [2022-07-14 15:41:12,995 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17 states and 24 transitions. [2022-07-14 15:41:12,997 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17 to 17. [2022-07-14 15:41:12,997 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17 states, 17 states have (on average 1.411764705882353) internal successors, (24), 16 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:41:12,998 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 24 transitions. [2022-07-14 15:41:12,998 INFO L392 hiAutomatonCegarLoop]: Abstraction has 17 states and 24 transitions. [2022-07-14 15:41:12,998 INFO L374 stractBuchiCegarLoop]: Abstraction has 17 states and 24 transitions. [2022-07-14 15:41:12,999 INFO L287 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-07-14 15:41:12,999 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17 states and 24 transitions. [2022-07-14 15:41:12,999 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-07-14 15:41:12,999 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:41:12,999 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:41:13,000 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 1, 1, 1, 1, 1] [2022-07-14 15:41:13,000 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-07-14 15:41:13,000 INFO L752 eck$LassoCheckResult]: Stem: 342#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 343#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 350#L26 main_~i~0#1 := 0; 344#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 346#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 347#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 355#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 353#L29-1 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 351#L29-2 assume main_~i~0#1 >= 100; 349#L39 [2022-07-14 15:41:13,000 INFO L754 eck$LassoCheckResult]: Loop: 349#L39 assume true; 349#L39 [2022-07-14 15:41:13,001 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:41:13,001 INFO L85 PathProgramCache]: Analyzing trace with hash -1366227831, now seen corresponding path program 2 times [2022-07-14 15:41:13,001 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:41:13,001 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [926154409] [2022-07-14 15:41:13,001 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:41:13,002 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:41:13,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:41:13,052 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:41:13,053 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:41:13,053 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [926154409] [2022-07-14 15:41:13,053 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [926154409] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:41:13,053 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1567048141] [2022-07-14 15:41:13,053 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-07-14 15:41:13,053 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:41:13,053 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:41:13,066 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:41:13,067 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2022-07-14 15:41:13,095 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-07-14 15:41:13,095 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-07-14 15:41:13,095 INFO L263 TraceCheckSpWp]: Trace formula consists of 42 conjuncts, 6 conjunts are in the unsatisfiable core [2022-07-14 15:41:13,116 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:41:13,130 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2022-07-14 15:41:13,139 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:41:13,139 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:41:13,181 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:41:13,181 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1567048141] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:41:13,181 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:41:13,181 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 12 [2022-07-14 15:41:13,182 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [709139745] [2022-07-14 15:41:13,182 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:41:13,182 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 15:41:13,182 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:41:13,182 INFO L85 PathProgramCache]: Analyzing trace with hash 84, now seen corresponding path program 5 times [2022-07-14 15:41:13,183 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:41:13,183 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [111021733] [2022-07-14 15:41:13,183 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:41:13,183 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:41:13,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:41:13,185 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:41:13,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:41:13,186 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:41:13,187 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:41:13,188 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2022-07-14 15:41:13,188 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2022-07-14 15:41:13,188 INFO L87 Difference]: Start difference. First operand 17 states and 24 transitions. cyclomatic complexity: 10 Second operand has 13 states, 12 states have (on average 1.5) internal successors, (18), 13 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:41:13,245 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:41:13,246 INFO L93 Difference]: Finished difference Result 90 states and 109 transitions. [2022-07-14 15:41:13,246 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-07-14 15:41:13,247 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 90 states and 109 transitions. [2022-07-14 15:41:13,248 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 7 [2022-07-14 15:41:13,249 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 90 states to 84 states and 103 transitions. [2022-07-14 15:41:13,249 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19 [2022-07-14 15:41:13,249 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2022-07-14 15:41:13,249 INFO L73 IsDeterministic]: Start isDeterministic. Operand 84 states and 103 transitions. [2022-07-14 15:41:13,249 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-07-14 15:41:13,249 INFO L369 hiAutomatonCegarLoop]: Abstraction has 84 states and 103 transitions. [2022-07-14 15:41:13,250 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84 states and 103 transitions. [2022-07-14 15:41:13,251 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84 to 23. [2022-07-14 15:41:13,251 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23 states, 23 states have (on average 1.565217391304348) internal successors, (36), 22 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:41:13,252 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23 states to 23 states and 36 transitions. [2022-07-14 15:41:13,252 INFO L392 hiAutomatonCegarLoop]: Abstraction has 23 states and 36 transitions. [2022-07-14 15:41:13,252 INFO L374 stractBuchiCegarLoop]: Abstraction has 23 states and 36 transitions. [2022-07-14 15:41:13,252 INFO L287 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-07-14 15:41:13,252 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23 states and 36 transitions. [2022-07-14 15:41:13,252 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-07-14 15:41:13,253 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:41:13,253 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:41:13,253 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 15:41:13,253 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-07-14 15:41:13,253 INFO L752 eck$LassoCheckResult]: Stem: 513#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 514#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 521#L26 main_~i~0#1 := 0; 515#L29-1 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 516#L29-2 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 511#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 512#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 533#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 532#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 531#L35-1 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 519#L35-2 assume main_~j~0#1 >= 100; 520#L39 [2022-07-14 15:41:13,253 INFO L754 eck$LassoCheckResult]: Loop: 520#L39 assume true; 520#L39 [2022-07-14 15:41:13,254 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:41:13,254 INFO L85 PathProgramCache]: Analyzing trace with hash 2054548532, now seen corresponding path program 2 times [2022-07-14 15:41:13,254 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:41:13,254 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1189184849] [2022-07-14 15:41:13,254 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:41:13,255 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:41:13,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:41:13,288 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:41:13,288 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:41:13,288 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1189184849] [2022-07-14 15:41:13,288 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1189184849] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:41:13,289 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [364915064] [2022-07-14 15:41:13,289 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-07-14 15:41:13,289 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:41:13,289 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:41:13,290 INFO L229 MonitoredProcess]: Starting monitored process 12 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:41:13,291 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2022-07-14 15:41:13,316 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-07-14 15:41:13,316 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-07-14 15:41:13,317 INFO L263 TraceCheckSpWp]: Trace formula consists of 54 conjuncts, 6 conjunts are in the unsatisfiable core [2022-07-14 15:41:13,318 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:41:13,331 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:41:13,332 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:41:13,377 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:41:13,377 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [364915064] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:41:13,377 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:41:13,377 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 12 [2022-07-14 15:41:13,379 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1111279959] [2022-07-14 15:41:13,379 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:41:13,380 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 15:41:13,380 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:41:13,380 INFO L85 PathProgramCache]: Analyzing trace with hash 84, now seen corresponding path program 6 times [2022-07-14 15:41:13,380 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:41:13,381 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [795829363] [2022-07-14 15:41:13,381 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:41:13,381 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:41:13,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:41:13,385 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:41:13,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:41:13,390 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:41:13,392 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:41:13,393 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2022-07-14 15:41:13,394 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2022-07-14 15:41:13,394 INFO L87 Difference]: Start difference. First operand 23 states and 36 transitions. cyclomatic complexity: 16 Second operand has 13 states, 12 states have (on average 1.6666666666666667) internal successors, (20), 13 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:41:13,413 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:41:13,413 INFO L93 Difference]: Finished difference Result 35 states and 48 transitions. [2022-07-14 15:41:13,413 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-07-14 15:41:13,415 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35 states and 48 transitions. [2022-07-14 15:41:13,418 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-07-14 15:41:13,419 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35 states to 29 states and 42 transitions. [2022-07-14 15:41:13,419 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2022-07-14 15:41:13,419 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2022-07-14 15:41:13,420 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29 states and 42 transitions. [2022-07-14 15:41:13,420 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-07-14 15:41:13,420 INFO L369 hiAutomatonCegarLoop]: Abstraction has 29 states and 42 transitions. [2022-07-14 15:41:13,420 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states and 42 transitions. [2022-07-14 15:41:13,422 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 29. [2022-07-14 15:41:13,423 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29 states, 29 states have (on average 1.4482758620689655) internal successors, (42), 28 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:41:13,423 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 42 transitions. [2022-07-14 15:41:13,423 INFO L392 hiAutomatonCegarLoop]: Abstraction has 29 states and 42 transitions. [2022-07-14 15:41:13,423 INFO L374 stractBuchiCegarLoop]: Abstraction has 29 states and 42 transitions. [2022-07-14 15:41:13,423 INFO L287 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-07-14 15:41:13,423 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 29 states and 42 transitions. [2022-07-14 15:41:13,424 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-07-14 15:41:13,424 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:41:13,424 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:41:13,424 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 1, 1, 1, 1, 1] [2022-07-14 15:41:13,424 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-07-14 15:41:13,424 INFO L752 eck$LassoCheckResult]: Stem: 647#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 648#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 655#L26 main_~i~0#1 := 0; 649#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 651#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 652#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 673#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 672#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 670#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 668#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 666#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 664#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 660#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 658#L29-1 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 656#L29-2 assume main_~i~0#1 >= 100; 654#L39 [2022-07-14 15:41:13,425 INFO L754 eck$LassoCheckResult]: Loop: 654#L39 assume true; 654#L39 [2022-07-14 15:41:13,425 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:41:13,425 INFO L85 PathProgramCache]: Analyzing trace with hash 1329396905, now seen corresponding path program 3 times [2022-07-14 15:41:13,425 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:41:13,427 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [435253518] [2022-07-14 15:41:13,427 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:41:13,427 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:41:13,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:41:13,507 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:41:13,508 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:41:13,508 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [435253518] [2022-07-14 15:41:13,508 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [435253518] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:41:13,508 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [733328161] [2022-07-14 15:41:13,508 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-07-14 15:41:13,508 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:41:13,508 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:41:13,510 INFO L229 MonitoredProcess]: Starting monitored process 13 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:41:13,511 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2022-07-14 15:41:13,538 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2022-07-14 15:41:13,539 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-07-14 15:41:13,539 INFO L263 TraceCheckSpWp]: Trace formula consists of 66 conjuncts, 12 conjunts are in the unsatisfiable core [2022-07-14 15:41:13,540 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:41:13,574 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:41:13,574 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:41:13,725 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:41:13,725 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [733328161] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:41:13,725 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:41:13,725 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12] total 24 [2022-07-14 15:41:13,725 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1160266012] [2022-07-14 15:41:13,725 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:41:13,726 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 15:41:13,726 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:41:13,726 INFO L85 PathProgramCache]: Analyzing trace with hash 84, now seen corresponding path program 7 times [2022-07-14 15:41:13,726 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:41:13,726 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [473012309] [2022-07-14 15:41:13,726 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:41:13,726 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:41:13,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:41:13,728 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:41:13,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:41:13,728 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:41:13,730 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:41:13,730 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2022-07-14 15:41:13,730 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2022-07-14 15:41:13,731 INFO L87 Difference]: Start difference. First operand 29 states and 42 transitions. cyclomatic complexity: 16 Second operand has 25 states, 24 states have (on average 1.25) internal successors, (30), 25 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:41:13,878 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:41:13,878 INFO L93 Difference]: Finished difference Result 285 states and 322 transitions. [2022-07-14 15:41:13,878 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2022-07-14 15:41:13,880 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 285 states and 322 transitions. [2022-07-14 15:41:13,884 INFO L131 ngComponentsAnalysis]: Automaton has 13 accepting balls. 13 [2022-07-14 15:41:13,888 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 285 states to 273 states and 310 transitions. [2022-07-14 15:41:13,888 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 31 [2022-07-14 15:41:13,888 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 31 [2022-07-14 15:41:13,888 INFO L73 IsDeterministic]: Start isDeterministic. Operand 273 states and 310 transitions. [2022-07-14 15:41:13,888 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-07-14 15:41:13,888 INFO L369 hiAutomatonCegarLoop]: Abstraction has 273 states and 310 transitions. [2022-07-14 15:41:13,888 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 273 states and 310 transitions. [2022-07-14 15:41:13,897 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 273 to 41. [2022-07-14 15:41:13,898 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41 states, 41 states have (on average 1.6097560975609757) internal successors, (66), 40 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:41:13,899 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 66 transitions. [2022-07-14 15:41:13,899 INFO L392 hiAutomatonCegarLoop]: Abstraction has 41 states and 66 transitions. [2022-07-14 15:41:13,899 INFO L374 stractBuchiCegarLoop]: Abstraction has 41 states and 66 transitions. [2022-07-14 15:41:13,899 INFO L287 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-07-14 15:41:13,900 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41 states and 66 transitions. [2022-07-14 15:41:13,900 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-07-14 15:41:13,900 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:41:13,900 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:41:13,901 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 15:41:13,901 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-07-14 15:41:13,901 INFO L752 eck$LassoCheckResult]: Stem: 1073#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 1074#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 1081#L26 main_~i~0#1 := 0; 1075#L29-1 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 1076#L29-2 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 1071#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1072#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1111#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1110#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1109#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1108#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1107#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1106#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1105#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1104#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1103#L35-1 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 1079#L35-2 assume main_~j~0#1 >= 100; 1080#L39 [2022-07-14 15:41:13,901 INFO L754 eck$LassoCheckResult]: Loop: 1080#L39 assume true; 1080#L39 [2022-07-14 15:41:13,901 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:41:13,901 INFO L85 PathProgramCache]: Analyzing trace with hash -719352108, now seen corresponding path program 3 times [2022-07-14 15:41:13,901 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:41:13,901 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1414282740] [2022-07-14 15:41:13,901 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:41:13,901 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:41:13,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:41:13,989 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:41:13,989 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:41:13,989 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1414282740] [2022-07-14 15:41:13,989 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1414282740] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:41:13,989 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1755741855] [2022-07-14 15:41:13,989 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-07-14 15:41:13,990 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:41:13,990 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:41:13,991 INFO L229 MonitoredProcess]: Starting monitored process 14 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:41:13,996 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2022-07-14 15:41:14,031 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2022-07-14 15:41:14,031 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-07-14 15:41:14,032 INFO L263 TraceCheckSpWp]: Trace formula consists of 90 conjuncts, 12 conjunts are in the unsatisfiable core [2022-07-14 15:41:14,033 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:41:14,066 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:41:14,067 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:41:14,224 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:41:14,224 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1755741855] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:41:14,224 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:41:14,225 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12] total 24 [2022-07-14 15:41:14,225 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [968062913] [2022-07-14 15:41:14,225 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:41:14,225 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 15:41:14,225 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:41:14,225 INFO L85 PathProgramCache]: Analyzing trace with hash 84, now seen corresponding path program 8 times [2022-07-14 15:41:14,226 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:41:14,226 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1130633249] [2022-07-14 15:41:14,226 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:41:14,226 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:41:14,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:41:14,228 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:41:14,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:41:14,229 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:41:14,230 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:41:14,231 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2022-07-14 15:41:14,231 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2022-07-14 15:41:14,231 INFO L87 Difference]: Start difference. First operand 41 states and 66 transitions. cyclomatic complexity: 28 Second operand has 25 states, 24 states have (on average 1.3333333333333333) internal successors, (32), 25 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:41:14,254 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:41:14,254 INFO L93 Difference]: Finished difference Result 65 states and 90 transitions. [2022-07-14 15:41:14,255 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2022-07-14 15:41:14,255 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 65 states and 90 transitions. [2022-07-14 15:41:14,256 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-07-14 15:41:14,256 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 65 states to 53 states and 78 transitions. [2022-07-14 15:41:14,256 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2022-07-14 15:41:14,256 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2022-07-14 15:41:14,256 INFO L73 IsDeterministic]: Start isDeterministic. Operand 53 states and 78 transitions. [2022-07-14 15:41:14,256 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-07-14 15:41:14,256 INFO L369 hiAutomatonCegarLoop]: Abstraction has 53 states and 78 transitions. [2022-07-14 15:41:14,257 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53 states and 78 transitions. [2022-07-14 15:41:14,258 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53 to 53. [2022-07-14 15:41:14,258 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 53 states, 53 states have (on average 1.471698113207547) internal successors, (78), 52 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:41:14,258 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53 states to 53 states and 78 transitions. [2022-07-14 15:41:14,258 INFO L392 hiAutomatonCegarLoop]: Abstraction has 53 states and 78 transitions. [2022-07-14 15:41:14,259 INFO L374 stractBuchiCegarLoop]: Abstraction has 53 states and 78 transitions. [2022-07-14 15:41:14,259 INFO L287 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-07-14 15:41:14,259 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 53 states and 78 transitions. [2022-07-14 15:41:14,259 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-07-14 15:41:14,259 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:41:14,259 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:41:14,260 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [22, 1, 1, 1, 1, 1] [2022-07-14 15:41:14,260 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-07-14 15:41:14,260 INFO L752 eck$LassoCheckResult]: Stem: 1303#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 1304#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 1311#L26 main_~i~0#1 := 0; 1305#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1307#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1308#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1353#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1352#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1350#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1348#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1346#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1344#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1342#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1340#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1338#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1336#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1334#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1332#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1330#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1328#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1326#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1324#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1322#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1320#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1316#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1314#L29-1 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 1312#L29-2 assume main_~i~0#1 >= 100; 1310#L39 [2022-07-14 15:41:14,260 INFO L754 eck$LassoCheckResult]: Loop: 1310#L39 assume true; 1310#L39 [2022-07-14 15:41:14,260 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:41:14,261 INFO L85 PathProgramCache]: Analyzing trace with hash -525392663, now seen corresponding path program 4 times [2022-07-14 15:41:14,261 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:41:14,261 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [552162602] [2022-07-14 15:41:14,261 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:41:14,261 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:41:14,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:41:14,487 INFO L134 CoverageAnalysis]: Checked inductivity of 253 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:41:14,487 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:41:14,487 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [552162602] [2022-07-14 15:41:14,487 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [552162602] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:41:14,488 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [640090346] [2022-07-14 15:41:14,488 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-07-14 15:41:14,488 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:41:14,488 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:41:14,489 INFO L229 MonitoredProcess]: Starting monitored process 15 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:41:14,490 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2022-07-14 15:41:14,521 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-07-14 15:41:14,521 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-07-14 15:41:14,522 INFO L263 TraceCheckSpWp]: Trace formula consists of 114 conjuncts, 24 conjunts are in the unsatisfiable core [2022-07-14 15:41:14,523 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:41:14,566 INFO L134 CoverageAnalysis]: Checked inductivity of 253 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:41:14,566 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:41:15,083 INFO L134 CoverageAnalysis]: Checked inductivity of 253 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:41:15,083 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [640090346] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:41:15,083 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:41:15,084 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24] total 48 [2022-07-14 15:41:15,084 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1051780124] [2022-07-14 15:41:15,084 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:41:15,085 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 15:41:15,086 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:41:15,086 INFO L85 PathProgramCache]: Analyzing trace with hash 84, now seen corresponding path program 9 times [2022-07-14 15:41:15,086 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:41:15,086 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2058562592] [2022-07-14 15:41:15,086 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:41:15,086 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:41:15,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:41:15,088 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:41:15,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:41:15,090 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:41:15,092 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:41:15,093 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2022-07-14 15:41:15,094 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2022-07-14 15:41:15,095 INFO L87 Difference]: Start difference. First operand 53 states and 78 transitions. cyclomatic complexity: 28 Second operand has 49 states, 48 states have (on average 1.125) internal successors, (54), 49 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:41:15,367 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:41:15,367 INFO L93 Difference]: Finished difference Result 999 states and 1072 transitions. [2022-07-14 15:41:15,367 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2022-07-14 15:41:15,368 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 999 states and 1072 transitions. [2022-07-14 15:41:15,373 INFO L131 ngComponentsAnalysis]: Automaton has 25 accepting balls. 25 [2022-07-14 15:41:15,377 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 999 states to 975 states and 1048 transitions. [2022-07-14 15:41:15,377 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 55 [2022-07-14 15:41:15,378 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 55 [2022-07-14 15:41:15,378 INFO L73 IsDeterministic]: Start isDeterministic. Operand 975 states and 1048 transitions. [2022-07-14 15:41:15,382 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-07-14 15:41:15,383 INFO L369 hiAutomatonCegarLoop]: Abstraction has 975 states and 1048 transitions. [2022-07-14 15:41:15,383 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 975 states and 1048 transitions. [2022-07-14 15:41:15,395 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 975 to 77. [2022-07-14 15:41:15,395 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 77 states, 77 states have (on average 1.6363636363636365) internal successors, (126), 76 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:41:15,395 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 126 transitions. [2022-07-14 15:41:15,396 INFO L392 hiAutomatonCegarLoop]: Abstraction has 77 states and 126 transitions. [2022-07-14 15:41:15,396 INFO L374 stractBuchiCegarLoop]: Abstraction has 77 states and 126 transitions. [2022-07-14 15:41:15,396 INFO L287 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-07-14 15:41:15,396 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 77 states and 126 transitions. [2022-07-14 15:41:15,396 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-07-14 15:41:15,396 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:41:15,396 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:41:15,398 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [22, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 15:41:15,398 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-07-14 15:41:15,398 INFO L752 eck$LassoCheckResult]: Stem: 2563#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 2564#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 2571#L26 main_~i~0#1 := 0; 2565#L29-1 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 2566#L29-2 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 2561#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2562#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2637#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2636#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2635#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2634#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2633#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2632#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2631#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2630#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2629#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2628#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2627#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2626#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2625#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2624#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2623#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2622#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2621#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2620#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2619#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2618#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2617#L35-1 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 2569#L35-2 assume main_~j~0#1 >= 100; 2570#L39 [2022-07-14 15:41:15,398 INFO L754 eck$LassoCheckResult]: Loop: 2570#L39 assume true; 2570#L39 [2022-07-14 15:41:15,400 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:41:15,400 INFO L85 PathProgramCache]: Analyzing trace with hash 798452756, now seen corresponding path program 4 times [2022-07-14 15:41:15,400 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:41:15,400 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1068086040] [2022-07-14 15:41:15,400 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:41:15,400 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:41:15,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:41:15,657 INFO L134 CoverageAnalysis]: Checked inductivity of 253 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:41:15,658 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:41:15,658 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1068086040] [2022-07-14 15:41:15,658 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1068086040] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:41:15,658 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [587051327] [2022-07-14 15:41:15,658 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-07-14 15:41:15,658 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:41:15,659 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:41:15,660 INFO L229 MonitoredProcess]: Starting monitored process 16 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:41:15,662 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2022-07-14 15:41:15,701 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-07-14 15:41:15,702 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-07-14 15:41:15,703 INFO L263 TraceCheckSpWp]: Trace formula consists of 162 conjuncts, 24 conjunts are in the unsatisfiable core [2022-07-14 15:41:15,704 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:41:15,746 INFO L134 CoverageAnalysis]: Checked inductivity of 253 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:41:15,747 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:41:16,263 INFO L134 CoverageAnalysis]: Checked inductivity of 253 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:41:16,263 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [587051327] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:41:16,263 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:41:16,264 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24] total 48 [2022-07-14 15:41:16,264 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1668141109] [2022-07-14 15:41:16,264 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:41:16,264 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 15:41:16,264 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:41:16,265 INFO L85 PathProgramCache]: Analyzing trace with hash 84, now seen corresponding path program 10 times [2022-07-14 15:41:16,266 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:41:16,267 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1138033257] [2022-07-14 15:41:16,267 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:41:16,267 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:41:16,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:41:16,269 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:41:16,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:41:16,270 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:41:16,272 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:41:16,273 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2022-07-14 15:41:16,274 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2022-07-14 15:41:16,274 INFO L87 Difference]: Start difference. First operand 77 states and 126 transitions. cyclomatic complexity: 52 Second operand has 49 states, 48 states have (on average 1.1666666666666667) internal successors, (56), 49 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:41:16,323 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:41:16,323 INFO L93 Difference]: Finished difference Result 125 states and 174 transitions. [2022-07-14 15:41:16,324 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2022-07-14 15:41:16,324 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 125 states and 174 transitions. [2022-07-14 15:41:16,325 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-07-14 15:41:16,325 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 125 states to 101 states and 150 transitions. [2022-07-14 15:41:16,326 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2022-07-14 15:41:16,326 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2022-07-14 15:41:16,326 INFO L73 IsDeterministic]: Start isDeterministic. Operand 101 states and 150 transitions. [2022-07-14 15:41:16,326 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-07-14 15:41:16,326 INFO L369 hiAutomatonCegarLoop]: Abstraction has 101 states and 150 transitions. [2022-07-14 15:41:16,326 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 101 states and 150 transitions. [2022-07-14 15:41:16,332 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 101 to 101. [2022-07-14 15:41:16,333 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 101 states, 101 states have (on average 1.4851485148514851) internal successors, (150), 100 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:41:16,334 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101 states to 101 states and 150 transitions. [2022-07-14 15:41:16,334 INFO L392 hiAutomatonCegarLoop]: Abstraction has 101 states and 150 transitions. [2022-07-14 15:41:16,334 INFO L374 stractBuchiCegarLoop]: Abstraction has 101 states and 150 transitions. [2022-07-14 15:41:16,335 INFO L287 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-07-14 15:41:16,335 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 101 states and 150 transitions. [2022-07-14 15:41:16,335 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-07-14 15:41:16,335 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:41:16,336 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:41:16,338 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [46, 1, 1, 1, 1, 1] [2022-07-14 15:41:16,338 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-07-14 15:41:16,338 INFO L752 eck$LassoCheckResult]: Stem: 2985#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 2986#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 2993#L26 main_~i~0#1 := 0; 2987#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2989#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2990#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3083#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3082#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3080#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3078#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3076#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3074#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3072#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3070#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3068#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3066#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3064#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3062#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3060#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3058#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3056#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3054#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3052#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3050#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3048#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3046#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3044#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3042#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3040#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3038#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3036#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3034#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3032#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3030#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3028#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3026#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3024#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3022#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3020#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3018#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3016#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3014#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3012#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3010#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3008#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3006#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3004#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3002#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2998#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2996#L29-1 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 2994#L29-2 assume main_~i~0#1 >= 100; 2992#L39 [2022-07-14 15:41:16,340 INFO L754 eck$LassoCheckResult]: Loop: 2992#L39 assume true; 2992#L39 [2022-07-14 15:41:16,343 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:41:16,343 INFO L85 PathProgramCache]: Analyzing trace with hash 1685345641, now seen corresponding path program 5 times [2022-07-14 15:41:16,343 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:41:16,343 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1915093827] [2022-07-14 15:41:16,343 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:41:16,343 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:41:16,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:41:17,132 INFO L134 CoverageAnalysis]: Checked inductivity of 1081 backedges. 0 proven. 1081 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:41:17,132 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:41:17,132 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1915093827] [2022-07-14 15:41:17,133 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1915093827] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:41:17,133 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1960362818] [2022-07-14 15:41:17,133 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-07-14 15:41:17,133 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:41:17,133 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:41:17,135 INFO L229 MonitoredProcess]: Starting monitored process 17 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:41:17,135 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2022-07-14 15:41:17,197 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 24 check-sat command(s) [2022-07-14 15:41:17,197 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-07-14 15:41:17,198 INFO L263 TraceCheckSpWp]: Trace formula consists of 210 conjuncts, 48 conjunts are in the unsatisfiable core [2022-07-14 15:41:17,200 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:41:17,283 INFO L134 CoverageAnalysis]: Checked inductivity of 1081 backedges. 0 proven. 1081 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:41:17,283 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:41:18,984 INFO L134 CoverageAnalysis]: Checked inductivity of 1081 backedges. 0 proven. 1081 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:41:18,984 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1960362818] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:41:18,984 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:41:18,984 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48, 48] total 96 [2022-07-14 15:41:18,985 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1724071290] [2022-07-14 15:41:18,985 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:41:18,985 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 15:41:18,985 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:41:18,985 INFO L85 PathProgramCache]: Analyzing trace with hash 84, now seen corresponding path program 11 times [2022-07-14 15:41:18,986 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:41:18,986 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1956090721] [2022-07-14 15:41:18,986 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:41:18,986 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:41:18,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:41:18,987 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:41:18,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:41:18,988 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:41:18,998 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:41:18,999 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 97 interpolants. [2022-07-14 15:41:19,001 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4656, Invalid=4656, Unknown=0, NotChecked=0, Total=9312 [2022-07-14 15:41:19,002 INFO L87 Difference]: Start difference. First operand 101 states and 150 transitions. cyclomatic complexity: 52 Second operand has 97 states, 96 states have (on average 1.0625) internal successors, (102), 97 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:41:20,003 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:41:20,003 INFO L93 Difference]: Finished difference Result 3723 states and 3868 transitions. [2022-07-14 15:41:20,003 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2022-07-14 15:41:20,004 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3723 states and 3868 transitions. [2022-07-14 15:41:20,020 INFO L131 ngComponentsAnalysis]: Automaton has 49 accepting balls. 49 [2022-07-14 15:41:20,031 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3723 states to 3675 states and 3820 transitions. [2022-07-14 15:41:20,031 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 103 [2022-07-14 15:41:20,032 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 103 [2022-07-14 15:41:20,033 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3675 states and 3820 transitions. [2022-07-14 15:41:20,035 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-07-14 15:41:20,035 INFO L369 hiAutomatonCegarLoop]: Abstraction has 3675 states and 3820 transitions. [2022-07-14 15:41:20,036 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3675 states and 3820 transitions. [2022-07-14 15:41:20,044 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3675 to 149. [2022-07-14 15:41:20,045 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 149 states, 149 states have (on average 1.651006711409396) internal successors, (246), 148 states have internal predecessors, (246), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:41:20,045 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149 states to 149 states and 246 transitions. [2022-07-14 15:41:20,045 INFO L392 hiAutomatonCegarLoop]: Abstraction has 149 states and 246 transitions. [2022-07-14 15:41:20,046 INFO L374 stractBuchiCegarLoop]: Abstraction has 149 states and 246 transitions. [2022-07-14 15:41:20,046 INFO L287 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-07-14 15:41:20,046 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 149 states and 246 transitions. [2022-07-14 15:41:20,046 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-07-14 15:41:20,047 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:41:20,047 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:41:20,049 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [46, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 15:41:20,049 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-07-14 15:41:20,050 INFO L752 eck$LassoCheckResult]: Stem: 7209#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 7210#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 7217#L26 main_~i~0#1 := 0; 7211#L29-1 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 7212#L29-2 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 7207#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7208#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7355#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7354#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7353#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7352#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7351#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7350#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7349#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7348#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7347#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7346#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7345#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7344#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7343#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7342#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7341#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7340#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7339#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7338#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7337#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7336#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7335#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7334#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7333#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7332#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7331#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7330#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7329#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7328#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7327#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7326#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7325#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7324#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7323#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7322#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7321#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7320#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7319#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7318#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7317#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7316#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7315#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7314#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7313#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7312#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7311#L35-1 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 7215#L35-2 assume main_~j~0#1 >= 100; 7216#L39 [2022-07-14 15:41:20,051 INFO L754 eck$LassoCheckResult]: Loop: 7216#L39 assume true; 7216#L39 [2022-07-14 15:41:20,051 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:41:20,051 INFO L85 PathProgramCache]: Analyzing trace with hash 821134996, now seen corresponding path program 5 times [2022-07-14 15:41:20,051 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:41:20,051 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [654597708] [2022-07-14 15:41:20,051 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:41:20,051 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:41:20,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:41:20,751 INFO L134 CoverageAnalysis]: Checked inductivity of 1081 backedges. 0 proven. 1081 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:41:20,751 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:41:20,751 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [654597708] [2022-07-14 15:41:20,751 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [654597708] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:41:20,751 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1121364679] [2022-07-14 15:41:20,752 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-07-14 15:41:20,752 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:41:20,752 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:41:20,754 INFO L229 MonitoredProcess]: Starting monitored process 18 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:41:20,757 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2022-07-14 15:41:20,817 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 24 check-sat command(s) [2022-07-14 15:41:20,817 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-07-14 15:41:20,818 INFO L263 TraceCheckSpWp]: Trace formula consists of 306 conjuncts, 48 conjunts are in the unsatisfiable core [2022-07-14 15:41:20,820 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:41:20,899 INFO L134 CoverageAnalysis]: Checked inductivity of 1081 backedges. 0 proven. 1081 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:41:20,899 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:41:22,958 INFO L134 CoverageAnalysis]: Checked inductivity of 1081 backedges. 0 proven. 1081 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:41:22,958 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1121364679] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:41:22,958 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:41:22,958 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48, 48] total 96 [2022-07-14 15:41:22,958 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [614444540] [2022-07-14 15:41:22,958 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:41:22,959 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 15:41:22,959 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:41:22,959 INFO L85 PathProgramCache]: Analyzing trace with hash 84, now seen corresponding path program 12 times [2022-07-14 15:41:22,959 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:41:22,959 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [938975127] [2022-07-14 15:41:22,959 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:41:22,959 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:41:22,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:41:22,960 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:41:22,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:41:22,961 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:41:22,963 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:41:22,964 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 97 interpolants. [2022-07-14 15:41:22,966 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4656, Invalid=4656, Unknown=0, NotChecked=0, Total=9312 [2022-07-14 15:41:22,966 INFO L87 Difference]: Start difference. First operand 149 states and 246 transitions. cyclomatic complexity: 100 Second operand has 97 states, 96 states have (on average 1.0833333333333333) internal successors, (104), 97 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:41:23,066 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:41:23,067 INFO L93 Difference]: Finished difference Result 245 states and 342 transitions. [2022-07-14 15:41:23,067 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2022-07-14 15:41:23,067 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 245 states and 342 transitions. [2022-07-14 15:41:23,068 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-07-14 15:41:23,069 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 245 states to 197 states and 294 transitions. [2022-07-14 15:41:23,069 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2022-07-14 15:41:23,069 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2022-07-14 15:41:23,069 INFO L73 IsDeterministic]: Start isDeterministic. Operand 197 states and 294 transitions. [2022-07-14 15:41:23,070 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-07-14 15:41:23,070 INFO L369 hiAutomatonCegarLoop]: Abstraction has 197 states and 294 transitions. [2022-07-14 15:41:23,070 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 197 states and 294 transitions. [2022-07-14 15:41:23,071 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 197 to 197. [2022-07-14 15:41:23,071 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 197 states, 197 states have (on average 1.4923857868020305) internal successors, (294), 196 states have internal predecessors, (294), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:41:23,072 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 197 states to 197 states and 294 transitions. [2022-07-14 15:41:23,072 INFO L392 hiAutomatonCegarLoop]: Abstraction has 197 states and 294 transitions. [2022-07-14 15:41:23,072 INFO L374 stractBuchiCegarLoop]: Abstraction has 197 states and 294 transitions. [2022-07-14 15:41:23,072 INFO L287 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-07-14 15:41:23,072 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 197 states and 294 transitions. [2022-07-14 15:41:23,073 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-07-14 15:41:23,073 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:41:23,073 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:41:23,074 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [94, 1, 1, 1, 1, 1] [2022-07-14 15:41:23,074 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-07-14 15:41:23,074 INFO L752 eck$LassoCheckResult]: Stem: 8015#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 8016#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 8023#L26 main_~i~0#1 := 0; 8017#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8019#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8020#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8209#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8208#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8206#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8204#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8202#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8200#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8198#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8196#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8194#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8192#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8190#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8188#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8186#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8184#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8182#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8180#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8178#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8176#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8174#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8172#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8170#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8168#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8166#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8164#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8162#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8160#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8158#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8156#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8154#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8152#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8150#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8148#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8146#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8144#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8142#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8140#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8138#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8136#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8134#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8132#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8130#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8128#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8126#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8124#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8122#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8120#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8118#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8116#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8114#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8112#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8110#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8108#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8106#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8104#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8102#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8100#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8098#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8096#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8094#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8092#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8090#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8088#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8086#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8084#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8082#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8080#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8078#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8076#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8074#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8072#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8070#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8068#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8066#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8064#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8062#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8060#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8058#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8056#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8054#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8052#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8050#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8048#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8046#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8044#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8042#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8040#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8038#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8036#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8034#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8032#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8028#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8026#L29-1 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 8024#L29-2 assume main_~i~0#1 >= 100; 8022#L39 [2022-07-14 15:41:23,074 INFO L754 eck$LassoCheckResult]: Loop: 8022#L39 assume true; 8022#L39 [2022-07-14 15:41:23,075 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:41:23,075 INFO L85 PathProgramCache]: Analyzing trace with hash -415091095, now seen corresponding path program 6 times [2022-07-14 15:41:23,075 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:41:23,075 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [721525853] [2022-07-14 15:41:23,075 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:41:23,075 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:41:23,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:41:25,476 INFO L134 CoverageAnalysis]: Checked inductivity of 4465 backedges. 0 proven. 4465 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:41:25,476 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:41:25,476 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [721525853] [2022-07-14 15:41:25,476 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [721525853] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:41:25,477 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [284598000] [2022-07-14 15:41:25,477 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-07-14 15:41:25,477 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:41:25,477 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:41:25,478 INFO L229 MonitoredProcess]: Starting monitored process 19 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:41:25,479 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2022-07-14 15:41:25,557 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 48 check-sat command(s) [2022-07-14 15:41:25,557 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-07-14 15:41:25,559 INFO L263 TraceCheckSpWp]: Trace formula consists of 402 conjuncts, 96 conjunts are in the unsatisfiable core [2022-07-14 15:41:25,562 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:41:25,688 INFO L134 CoverageAnalysis]: Checked inductivity of 4465 backedges. 0 proven. 4465 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:41:25,689 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:41:25,967 INFO L134 CoverageAnalysis]: Checked inductivity of 4465 backedges. 0 proven. 4465 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:41:25,968 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [284598000] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:41:25,968 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:41:25,968 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [96, 96, 96] total 102 [2022-07-14 15:41:25,968 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [293800714] [2022-07-14 15:41:25,968 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:41:25,968 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 15:41:25,974 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:41:25,974 INFO L85 PathProgramCache]: Analyzing trace with hash 84, now seen corresponding path program 13 times [2022-07-14 15:41:25,975 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:41:25,975 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1466882134] [2022-07-14 15:41:25,975 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:41:25,975 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:41:25,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:41:25,977 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:41:25,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:41:25,979 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:41:25,980 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:41:25,981 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 103 interpolants. [2022-07-14 15:41:25,983 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5253, Invalid=5253, Unknown=0, NotChecked=0, Total=10506 [2022-07-14 15:41:25,989 INFO L87 Difference]: Start difference. First operand 197 states and 294 transitions. cyclomatic complexity: 100 Second operand has 103 states, 102 states have (on average 1.0686274509803921) internal successors, (109), 103 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:41:27,231 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:41:27,231 INFO L93 Difference]: Finished difference Result 5355 states and 5464 transitions. [2022-07-14 15:41:27,232 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 102 states. [2022-07-14 15:41:27,232 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5355 states and 5464 transitions. [2022-07-14 15:41:27,251 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 7 [2022-07-14 15:41:27,265 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5355 states to 5349 states and 5458 transitions. [2022-07-14 15:41:27,266 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19 [2022-07-14 15:41:27,266 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2022-07-14 15:41:27,266 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5349 states and 5458 transitions. [2022-07-14 15:41:27,269 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-07-14 15:41:27,269 INFO L369 hiAutomatonCegarLoop]: Abstraction has 5349 states and 5458 transitions. [2022-07-14 15:41:27,271 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5349 states and 5458 transitions. [2022-07-14 15:41:27,282 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5349 to 203. [2022-07-14 15:41:27,283 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 203 states, 203 states have (on average 1.5073891625615763) internal successors, (306), 202 states have internal predecessors, (306), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:41:27,283 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 203 states to 203 states and 306 transitions. [2022-07-14 15:41:27,283 INFO L392 hiAutomatonCegarLoop]: Abstraction has 203 states and 306 transitions. [2022-07-14 15:41:27,283 INFO L374 stractBuchiCegarLoop]: Abstraction has 203 states and 306 transitions. [2022-07-14 15:41:27,283 INFO L287 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-07-14 15:41:27,284 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 203 states and 306 transitions. [2022-07-14 15:41:27,284 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-07-14 15:41:27,284 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:41:27,284 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:41:27,285 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [94, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 15:41:27,285 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-07-14 15:41:27,285 INFO L752 eck$LassoCheckResult]: Stem: 14261#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 14262#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 14269#L26 main_~i~0#1 := 0; 14263#L29-1 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 14264#L29-2 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 14259#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14260#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14461#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14460#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14459#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14458#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14457#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14456#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14455#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14454#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14453#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14452#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14451#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14450#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14449#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14448#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14447#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14446#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14445#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14444#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14443#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14442#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14441#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14440#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14439#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14438#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14437#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14436#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14435#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14434#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14433#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14432#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14431#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14430#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14429#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14428#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14427#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14426#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14425#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14424#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14423#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14422#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14421#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14420#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14419#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14418#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14417#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14416#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14415#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14414#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14413#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14412#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14411#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14410#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14409#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14408#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14407#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14406#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14405#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14404#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14403#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14402#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14401#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14400#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14399#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14398#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14397#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14396#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14395#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14394#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14393#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14392#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14391#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14390#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14389#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14388#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14387#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14386#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14385#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14384#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14383#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14382#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14381#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14380#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14379#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14378#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14377#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14376#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14375#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14374#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14373#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14372#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14371#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14370#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 14369#L35-1 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 14267#L35-2 assume main_~j~0#1 >= 100; 14268#L39 [2022-07-14 15:41:27,286 INFO L754 eck$LassoCheckResult]: Loop: 14268#L39 assume true; 14268#L39 [2022-07-14 15:41:27,286 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:41:27,286 INFO L85 PathProgramCache]: Analyzing trace with hash 672086932, now seen corresponding path program 6 times [2022-07-14 15:41:27,286 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:41:27,286 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [438327266] [2022-07-14 15:41:27,287 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:41:27,287 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:41:27,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 15:41:29,589 INFO L134 CoverageAnalysis]: Checked inductivity of 4465 backedges. 0 proven. 4465 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:41:29,589 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 15:41:29,589 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [438327266] [2022-07-14 15:41:29,589 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [438327266] provided 0 perfect and 1 imperfect interpolant sequences [2022-07-14 15:41:29,589 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [662357532] [2022-07-14 15:41:29,589 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-07-14 15:41:29,590 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-07-14 15:41:29,590 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 15:41:29,599 INFO L229 MonitoredProcess]: Starting monitored process 20 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-07-14 15:41:29,617 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2022-07-14 15:41:29,727 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 48 check-sat command(s) [2022-07-14 15:41:29,727 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-07-14 15:41:29,730 INFO L263 TraceCheckSpWp]: Trace formula consists of 594 conjuncts, 96 conjunts are in the unsatisfiable core [2022-07-14 15:41:29,733 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-07-14 15:41:29,828 INFO L134 CoverageAnalysis]: Checked inductivity of 4465 backedges. 0 proven. 4465 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:41:29,828 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-07-14 15:41:30,124 INFO L134 CoverageAnalysis]: Checked inductivity of 4465 backedges. 0 proven. 4465 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 15:41:30,124 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [662357532] provided 0 perfect and 2 imperfect interpolant sequences [2022-07-14 15:41:30,124 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-07-14 15:41:30,124 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [96, 96, 96] total 102 [2022-07-14 15:41:30,125 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1932103355] [2022-07-14 15:41:30,125 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-07-14 15:41:30,125 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 15:41:30,125 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:41:30,125 INFO L85 PathProgramCache]: Analyzing trace with hash 84, now seen corresponding path program 14 times [2022-07-14 15:41:30,125 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:41:30,125 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1153668056] [2022-07-14 15:41:30,125 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:41:30,125 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:41:30,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:41:30,127 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:41:30,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:41:30,127 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:41:30,141 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 15:41:30,142 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 103 interpolants. [2022-07-14 15:41:30,143 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5253, Invalid=5253, Unknown=0, NotChecked=0, Total=10506 [2022-07-14 15:41:30,144 INFO L87 Difference]: Start difference. First operand 203 states and 306 transitions. cyclomatic complexity: 106 Second operand has 103 states, 102 states have (on average 1.088235294117647) internal successors, (111), 103 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:41:30,213 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 15:41:30,213 INFO L93 Difference]: Finished difference Result 215 states and 318 transitions. [2022-07-14 15:41:30,213 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 102 states. [2022-07-14 15:41:30,213 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 215 states and 318 transitions. [2022-07-14 15:41:30,215 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-07-14 15:41:30,216 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 215 states to 209 states and 312 transitions. [2022-07-14 15:41:30,216 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2022-07-14 15:41:30,216 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2022-07-14 15:41:30,216 INFO L73 IsDeterministic]: Start isDeterministic. Operand 209 states and 312 transitions. [2022-07-14 15:41:30,217 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-07-14 15:41:30,217 INFO L369 hiAutomatonCegarLoop]: Abstraction has 209 states and 312 transitions. [2022-07-14 15:41:30,217 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 209 states and 312 transitions. [2022-07-14 15:41:30,218 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 209 to 209. [2022-07-14 15:41:30,219 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 209 states, 209 states have (on average 1.492822966507177) internal successors, (312), 208 states have internal predecessors, (312), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 15:41:30,219 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 209 states to 209 states and 312 transitions. [2022-07-14 15:41:30,219 INFO L392 hiAutomatonCegarLoop]: Abstraction has 209 states and 312 transitions. [2022-07-14 15:41:30,219 INFO L374 stractBuchiCegarLoop]: Abstraction has 209 states and 312 transitions. [2022-07-14 15:41:30,219 INFO L287 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-07-14 15:41:30,220 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 209 states and 312 transitions. [2022-07-14 15:41:30,220 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-07-14 15:41:30,220 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 15:41:30,221 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 15:41:30,223 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [100, 1, 1, 1, 1, 1] [2022-07-14 15:41:30,223 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-07-14 15:41:30,223 INFO L752 eck$LassoCheckResult]: Stem: 15385#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 15386#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 15393#L26 main_~i~0#1 := 0; 15387#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15389#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15390#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15591#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15590#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15588#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15586#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15584#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15582#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15580#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15578#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15576#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15574#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15572#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15570#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15568#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15566#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15564#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15562#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15560#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15558#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15556#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15554#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15552#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15550#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15548#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15546#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15544#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15542#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15540#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15538#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15536#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15534#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15532#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15530#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15528#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15526#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15524#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15522#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15520#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15518#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15516#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15514#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15512#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15510#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15508#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15506#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15504#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15502#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15500#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15498#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15496#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15494#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15492#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15490#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15488#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15486#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15484#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15482#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15480#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15478#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15476#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15474#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15472#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15470#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15468#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15466#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15464#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15462#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15460#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15458#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15456#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15454#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15452#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15450#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15448#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15446#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15444#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15442#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15440#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15438#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15436#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15434#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15432#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15430#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15428#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15426#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15424#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15422#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15420#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15418#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15416#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15414#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15412#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15410#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15408#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15406#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15404#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15402#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15398#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15396#L29-1 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 15394#L29-2 assume main_~i~0#1 >= 100; 15392#L39 [2022-07-14 15:41:30,223 INFO L754 eck$LassoCheckResult]: Loop: 15392#L39 assume true; 15392#L39 [2022-07-14 15:41:30,223 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:41:30,224 INFO L85 PathProgramCache]: Analyzing trace with hash -637974903, now seen corresponding path program 7 times [2022-07-14 15:41:30,224 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:41:30,224 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1113186102] [2022-07-14 15:41:30,224 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:41:30,224 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:41:30,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:41:30,251 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:41:30,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:41:30,284 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:41:30,284 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:41:30,285 INFO L85 PathProgramCache]: Analyzing trace with hash 84, now seen corresponding path program 15 times [2022-07-14 15:41:30,285 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:41:30,285 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [125112635] [2022-07-14 15:41:30,285 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:41:30,285 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:41:30,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:41:30,286 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:41:30,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:41:30,287 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:41:30,287 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 15:41:30,288 INFO L85 PathProgramCache]: Analyzing trace with hash 1697614540, now seen corresponding path program 1 times [2022-07-14 15:41:30,288 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 15:41:30,288 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1079424929] [2022-07-14 15:41:30,288 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 15:41:30,288 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 15:41:30,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:41:30,313 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 15:41:30,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 15:41:30,343 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 15:41:34,913 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 14.07 03:41:34 BoogieIcfgContainer [2022-07-14 15:41:34,931 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-07-14 15:41:34,932 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-07-14 15:41:34,932 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-07-14 15:41:34,932 INFO L275 PluginConnector]: Witness Printer initialized [2022-07-14 15:41:34,932 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.07 03:41:11" (3/4) ... [2022-07-14 15:41:34,934 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-07-14 15:41:35,016 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2022-07-14 15:41:35,026 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-07-14 15:41:35,027 INFO L158 Benchmark]: Toolchain (without parser) took 23916.96ms. Allocated memory was 125.8MB in the beginning and 285.2MB in the end (delta: 159.4MB). Free memory was 94.2MB in the beginning and 157.5MB in the end (delta: -63.3MB). Peak memory consumption was 96.5MB. Max. memory is 16.1GB. [2022-07-14 15:41:35,027 INFO L158 Benchmark]: CDTParser took 0.13ms. Allocated memory is still 92.3MB. Free memory was 55.8MB in the beginning and 55.7MB in the end (delta: 43.8kB). There was no memory consumed. Max. memory is 16.1GB. [2022-07-14 15:41:35,028 INFO L158 Benchmark]: CACSL2BoogieTranslator took 182.33ms. Allocated memory is still 125.8MB. Free memory was 93.9MB in the beginning and 100.8MB in the end (delta: -7.0MB). Peak memory consumption was 9.6MB. Max. memory is 16.1GB. [2022-07-14 15:41:35,028 INFO L158 Benchmark]: Boogie Procedure Inliner took 26.99ms. Allocated memory is still 125.8MB. Free memory was 100.8MB in the beginning and 99.4MB in the end (delta: 1.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-07-14 15:41:35,028 INFO L158 Benchmark]: Boogie Preprocessor took 26.02ms. Allocated memory is still 125.8MB. Free memory was 99.4MB in the beginning and 98.4MB in the end (delta: 994.8kB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-07-14 15:41:35,028 INFO L158 Benchmark]: RCFGBuilder took 238.32ms. Allocated memory is still 125.8MB. Free memory was 98.4MB in the beginning and 89.6MB in the end (delta: 8.8MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2022-07-14 15:41:35,029 INFO L158 Benchmark]: BuchiAutomizer took 23341.07ms. Allocated memory was 125.8MB in the beginning and 285.2MB in the end (delta: 159.4MB). Free memory was 89.3MB in the beginning and 161.7MB in the end (delta: -72.4MB). Peak memory consumption was 160.4MB. Max. memory is 16.1GB. [2022-07-14 15:41:35,029 INFO L158 Benchmark]: Witness Printer took 94.86ms. Allocated memory is still 285.2MB. Free memory was 161.7MB in the beginning and 157.5MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-07-14 15:41:35,030 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.13ms. Allocated memory is still 92.3MB. Free memory was 55.8MB in the beginning and 55.7MB in the end (delta: 43.8kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 182.33ms. Allocated memory is still 125.8MB. Free memory was 93.9MB in the beginning and 100.8MB in the end (delta: -7.0MB). Peak memory consumption was 9.6MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 26.99ms. Allocated memory is still 125.8MB. Free memory was 100.8MB in the beginning and 99.4MB in the end (delta: 1.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 26.02ms. Allocated memory is still 125.8MB. Free memory was 99.4MB in the beginning and 98.4MB in the end (delta: 994.8kB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 238.32ms. Allocated memory is still 125.8MB. Free memory was 98.4MB in the beginning and 89.6MB in the end (delta: 8.8MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * BuchiAutomizer took 23341.07ms. Allocated memory was 125.8MB in the beginning and 285.2MB in the end (delta: 159.4MB). Free memory was 89.3MB in the beginning and 161.7MB in the end (delta: -72.4MB). Peak memory consumption was 160.4MB. Max. memory is 16.1GB. * Witness Printer took 94.86ms. Allocated memory is still 285.2MB. Free memory was 161.7MB in the beginning and 157.5MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 15 terminating modules (14 trivial, 1 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function -2 * i + 1999999 and consists of 4 locations. 14 modules have a trivial ranking function, the largest among these consists of 103 locations. The remainder module has 209 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 23.2s and 16 iterations. TraceHistogramMax:100. Analysis of lassos took 19.6s. Construction of modules took 1.0s. Büchi inclusion checks took 2.1s. Highest rank in rank-based complementation 3. Minimization of det autom 0. Minimization of nondet autom 15. Automata minimization 0.1s AutomataMinimizationTime, 15 MinimizatonAttempts, 9893 StatesRemovedByMinimization, 8 NontrivialMinimizations. Non-live state removal took 0.1s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [1, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 3272 SdHoareTripleChecker+Valid, 1.4s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 3271 mSDsluCounter, 690 SdHoareTripleChecker+Invalid, 1.0s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 567 mSDsCounter, 1245 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 1670 IncrementalHoareTripleChecker+Invalid, 2915 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 1245 mSolverCounterUnsat, 123 mSDtfsCounter, 1670 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI0 SFLT1 conc0 concLT0 SILN14 SILU0 SILI0 SILT0 lasso0 LassoPreprocessingBenchmarks: Lassos: inital14 mio100 ax100 hnf100 lsp71 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq160 hnf93 smp100 dnf100 smp100 tf113 neg100 sie111 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 70ms VariablesStem: 0 VariablesLoop: 0 DisjunctsStem: 1 DisjunctsLoop: 1 SupportingInvariants: 0 MotzkinApplications: 2 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 2 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 1 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.1s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 24]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=1} State at position 1 is {j=0, i=100, NULL=0, NULL=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTUnaryExpression@57d50bae=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7c175c2=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@10959c2c=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTUnaryExpression@103aa571=0, NULL=1, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTUnaryExpression@294718d6=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 24]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int i, j; [L27] i = 0 [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ [L29] COND FALSE !(__VERIFIER_nondet_int() && i < 1000000) [L32] COND TRUE i >= 100 Loop: [L32] STUCK: goto STUCK; End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-07-14 15:41:35,081 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Forceful destruction successful, exit code 0 [2022-07-14 15:41:35,293 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Ended with exit code 0 [2022-07-14 15:41:35,497 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Ended with exit code 0 [2022-07-14 15:41:35,694 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Forceful destruction successful, exit code 0 [2022-07-14 15:41:35,894 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Forceful destruction successful, exit code 0 [2022-07-14 15:41:36,094 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Forceful destruction successful, exit code 0 [2022-07-14 15:41:36,295 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Ended with exit code 0 [2022-07-14 15:41:36,497 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Forceful destruction successful, exit code 0 [2022-07-14 15:41:36,694 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Forceful destruction successful, exit code 0 [2022-07-14 15:41:36,897 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Forceful destruction successful, exit code 0 [2022-07-14 15:41:37,099 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Forceful destruction successful, exit code 0 [2022-07-14 15:41:37,297 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Forceful destruction successful, exit code 0 [2022-07-14 15:41:37,496 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)