./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.06.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version f4b24e32 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.06.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 4ff0d99c6257365cafb7459615c8e1194d53bcc0d71dc100705abd4bb2d65c37 --- Real Ultimate output --- This is Ultimate 0.2.2-?-f4b24e3 [2022-07-14 16:02:22,833 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-07-14 16:02:22,848 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-07-14 16:02:22,907 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-07-14 16:02:22,907 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-07-14 16:02:22,909 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-07-14 16:02:22,910 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-07-14 16:02:22,913 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-07-14 16:02:22,914 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-07-14 16:02:22,919 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-07-14 16:02:22,920 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-07-14 16:02:22,922 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-07-14 16:02:22,922 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-07-14 16:02:22,924 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-07-14 16:02:22,926 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-07-14 16:02:22,928 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-07-14 16:02:22,929 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-07-14 16:02:22,931 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-07-14 16:02:22,932 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-07-14 16:02:22,937 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-07-14 16:02:22,938 INFO L181 SettingsManager]: Resetting HornVerifier preferences to default values [2022-07-14 16:02:22,939 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-07-14 16:02:22,940 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-07-14 16:02:22,941 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-07-14 16:02:22,942 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-07-14 16:02:22,948 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-07-14 16:02:22,948 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-07-14 16:02:22,949 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-07-14 16:02:22,950 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-07-14 16:02:22,951 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-07-14 16:02:22,952 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-07-14 16:02:22,952 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-07-14 16:02:22,953 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-07-14 16:02:22,954 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-07-14 16:02:22,954 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-07-14 16:02:22,956 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-07-14 16:02:22,956 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-07-14 16:02:22,957 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-07-14 16:02:22,957 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-07-14 16:02:22,957 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-07-14 16:02:22,958 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-07-14 16:02:22,959 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-07-14 16:02:22,960 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-07-14 16:02:22,995 INFO L113 SettingsManager]: Loading preferences was successful [2022-07-14 16:02:22,995 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-07-14 16:02:22,995 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-07-14 16:02:22,996 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-07-14 16:02:22,997 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-07-14 16:02:22,997 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-07-14 16:02:22,997 INFO L138 SettingsManager]: * Use SBE=true [2022-07-14 16:02:22,997 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-07-14 16:02:22,997 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-07-14 16:02:22,998 INFO L138 SettingsManager]: * Use old map elimination=false [2022-07-14 16:02:22,998 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-07-14 16:02:22,999 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-07-14 16:02:22,999 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-07-14 16:02:22,999 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-07-14 16:02:22,999 INFO L138 SettingsManager]: * sizeof long=4 [2022-07-14 16:02:22,999 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-07-14 16:02:23,000 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-07-14 16:02:23,001 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-07-14 16:02:23,001 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-07-14 16:02:23,001 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-07-14 16:02:23,001 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-07-14 16:02:23,001 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-07-14 16:02:23,002 INFO L138 SettingsManager]: * sizeof long double=12 [2022-07-14 16:02:23,002 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-07-14 16:02:23,002 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-07-14 16:02:23,002 INFO L138 SettingsManager]: * Use constant arrays=true [2022-07-14 16:02:23,002 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-07-14 16:02:23,002 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-07-14 16:02:23,003 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-07-14 16:02:23,003 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-07-14 16:02:23,003 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-07-14 16:02:23,004 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-07-14 16:02:23,004 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4ff0d99c6257365cafb7459615c8e1194d53bcc0d71dc100705abd4bb2d65c37 [2022-07-14 16:02:23,247 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-07-14 16:02:23,270 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-07-14 16:02:23,273 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-07-14 16:02:23,274 INFO L271 PluginConnector]: Initializing CDTParser... [2022-07-14 16:02:23,274 INFO L275 PluginConnector]: CDTParser initialized [2022-07-14 16:02:23,275 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.06.cil-1.c [2022-07-14 16:02:23,333 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/8705765a7/cceacedf41e942659059e203c3c6b8cd/FLAGe801cc4ce [2022-07-14 16:02:23,792 INFO L306 CDTParser]: Found 1 translation units. [2022-07-14 16:02:23,792 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.06.cil-1.c [2022-07-14 16:02:23,807 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/8705765a7/cceacedf41e942659059e203c3c6b8cd/FLAGe801cc4ce [2022-07-14 16:02:24,153 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/8705765a7/cceacedf41e942659059e203c3c6b8cd [2022-07-14 16:02:24,155 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-07-14 16:02:24,156 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-07-14 16:02:24,159 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-07-14 16:02:24,159 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-07-14 16:02:24,161 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-07-14 16:02:24,162 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.07 04:02:24" (1/1) ... [2022-07-14 16:02:24,163 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@77bcaa91 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:24, skipping insertion in model container [2022-07-14 16:02:24,163 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.07 04:02:24" (1/1) ... [2022-07-14 16:02:24,170 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-07-14 16:02:24,218 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-07-14 16:02:24,422 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.06.cil-1.c[671,684] [2022-07-14 16:02:24,533 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-14 16:02:24,548 INFO L203 MainTranslator]: Completed pre-run [2022-07-14 16:02:24,559 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.06.cil-1.c[671,684] [2022-07-14 16:02:24,610 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-14 16:02:24,632 INFO L208 MainTranslator]: Completed translation [2022-07-14 16:02:24,632 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:24 WrapperNode [2022-07-14 16:02:24,633 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-07-14 16:02:24,633 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-07-14 16:02:24,634 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-07-14 16:02:24,634 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-07-14 16:02:24,640 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:24" (1/1) ... [2022-07-14 16:02:24,665 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:24" (1/1) ... [2022-07-14 16:02:24,728 INFO L137 Inliner]: procedures = 40, calls = 50, calls flagged for inlining = 45, calls inlined = 114, statements flattened = 1662 [2022-07-14 16:02:24,729 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-07-14 16:02:24,730 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-07-14 16:02:24,730 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-07-14 16:02:24,730 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-07-14 16:02:24,744 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:24" (1/1) ... [2022-07-14 16:02:24,744 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:24" (1/1) ... [2022-07-14 16:02:24,748 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:24" (1/1) ... [2022-07-14 16:02:24,751 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:24" (1/1) ... [2022-07-14 16:02:24,769 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:24" (1/1) ... [2022-07-14 16:02:24,823 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:24" (1/1) ... [2022-07-14 16:02:24,827 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:24" (1/1) ... [2022-07-14 16:02:24,833 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-07-14 16:02:24,834 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-07-14 16:02:24,834 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-07-14 16:02:24,834 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-07-14 16:02:24,846 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:24" (1/1) ... [2022-07-14 16:02:24,852 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 16:02:24,863 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 16:02:24,881 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-14 16:02:24,918 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-07-14 16:02:24,941 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-07-14 16:02:24,941 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-07-14 16:02:24,942 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-07-14 16:02:24,942 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-07-14 16:02:25,065 INFO L234 CfgBuilder]: Building ICFG [2022-07-14 16:02:25,066 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-07-14 16:02:25,996 INFO L275 CfgBuilder]: Performing block encoding [2022-07-14 16:02:26,014 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-07-14 16:02:26,014 INFO L299 CfgBuilder]: Removed 9 assume(true) statements. [2022-07-14 16:02:26,017 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.07 04:02:26 BoogieIcfgContainer [2022-07-14 16:02:26,018 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-07-14 16:02:26,019 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-07-14 16:02:26,019 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-07-14 16:02:26,022 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-07-14 16:02:26,022 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-14 16:02:26,022 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 14.07 04:02:24" (1/3) ... [2022-07-14 16:02:26,023 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@55bfe4ea and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 14.07 04:02:26, skipping insertion in model container [2022-07-14 16:02:26,024 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-14 16:02:26,024 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:24" (2/3) ... [2022-07-14 16:02:26,024 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@55bfe4ea and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 14.07 04:02:26, skipping insertion in model container [2022-07-14 16:02:26,024 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-14 16:02:26,024 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.07 04:02:26" (3/3) ... [2022-07-14 16:02:26,025 INFO L354 chiAutomizerObserver]: Analyzing ICFG token_ring.06.cil-1.c [2022-07-14 16:02:26,091 INFO L255 stractBuchiCegarLoop]: Interprodecural is true [2022-07-14 16:02:26,091 INFO L256 stractBuchiCegarLoop]: Hoare is false [2022-07-14 16:02:26,091 INFO L257 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-07-14 16:02:26,091 INFO L258 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-07-14 16:02:26,091 INFO L259 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-07-14 16:02:26,091 INFO L260 stractBuchiCegarLoop]: Difference is false [2022-07-14 16:02:26,092 INFO L261 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-07-14 16:02:26,092 INFO L265 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-07-14 16:02:26,098 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 694 states, 693 states have (on average 1.5252525252525253) internal successors, (1057), 693 states have internal predecessors, (1057), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:26,151 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 599 [2022-07-14 16:02:26,152 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:26,152 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:26,163 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:26,164 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:26,164 INFO L287 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-07-14 16:02:26,166 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 694 states, 693 states have (on average 1.5252525252525253) internal successors, (1057), 693 states have internal predecessors, (1057), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:26,178 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 599 [2022-07-14 16:02:26,178 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:26,178 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:26,182 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:26,183 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:26,189 INFO L752 eck$LassoCheckResult]: Stem: 669#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 557#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 486#L1028true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 399#L480true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 513#L487true assume !(1 == ~m_i~0);~m_st~0 := 2; 124#L487-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 260#L492-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 46#L497-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 142#L502-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 32#L507-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 112#L512-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 531#L517-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 216#L696true assume !(0 == ~M_E~0); 525#L696-2true assume !(0 == ~T1_E~0); 528#L701-1true assume !(0 == ~T2_E~0); 556#L706-1true assume !(0 == ~T3_E~0); 298#L711-1true assume !(0 == ~T4_E~0); 144#L716-1true assume !(0 == ~T5_E~0); 576#L721-1true assume !(0 == ~T6_E~0); 265#L726-1true assume 0 == ~E_M~0;~E_M~0 := 1; 462#L731-1true assume !(0 == ~E_1~0); 241#L736-1true assume !(0 == ~E_2~0); 308#L741-1true assume !(0 == ~E_3~0); 617#L746-1true assume !(0 == ~E_4~0); 165#L751-1true assume !(0 == ~E_5~0); 226#L756-1true assume !(0 == ~E_6~0); 141#L761-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54#L346true assume !(1 == ~m_pc~0); 173#L346-2true is_master_triggered_~__retres1~0#1 := 0; 412#L357true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11#L358true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 545#L861true assume !(0 != activate_threads_~tmp~1#1); 460#L861-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69#L365true assume 1 == ~t1_pc~0; 131#L366true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 507#L376true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 487#L377true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 65#L869true assume !(0 != activate_threads_~tmp___0~0#1); 360#L869-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 491#L384true assume !(1 == ~t2_pc~0); 355#L384-2true is_transmit2_triggered_~__retres1~2#1 := 0; 619#L395true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 110#L396true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 23#L877true assume !(0 != activate_threads_~tmp___1~0#1); 230#L877-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 227#L403true assume 1 == ~t3_pc~0; 145#L404true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 672#L414true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 136#L415true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 409#L885true assume !(0 != activate_threads_~tmp___2~0#1); 220#L885-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 515#L422true assume 1 == ~t4_pc~0; 21#L423true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 426#L433true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 358#L434true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 437#L893true assume !(0 != activate_threads_~tmp___3~0#1); 285#L893-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33#L441true assume !(1 == ~t5_pc~0); 452#L441-2true is_transmit5_triggered_~__retres1~5#1 := 0; 607#L452true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 559#L453true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 690#L901true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 292#L901-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 416#L460true assume 1 == ~t6_pc~0; 4#L461true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 36#L471true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 548#L472true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 413#L909true assume !(0 != activate_threads_~tmp___5~0#1); 541#L909-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 273#L774true assume !(1 == ~M_E~0); 581#L774-2true assume !(1 == ~T1_E~0); 430#L779-1true assume !(1 == ~T2_E~0); 203#L784-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 577#L789-1true assume !(1 == ~T4_E~0); 61#L794-1true assume !(1 == ~T5_E~0); 656#L799-1true assume !(1 == ~T6_E~0); 592#L804-1true assume !(1 == ~E_M~0); 649#L809-1true assume !(1 == ~E_1~0); 262#L814-1true assume !(1 == ~E_2~0); 12#L819-1true assume !(1 == ~E_3~0); 318#L824-1true assume 1 == ~E_4~0;~E_4~0 := 2; 638#L829-1true assume !(1 == ~E_5~0); 419#L834-1true assume !(1 == ~E_6~0); 132#L839-1true assume { :end_inline_reset_delta_events } true; 126#L1065-2true [2022-07-14 16:02:26,191 INFO L754 eck$LassoCheckResult]: Loop: 126#L1065-2true assume !false; 335#L1066true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 474#L671true assume false; 596#L686true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 325#L480-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 157#L696-3true assume 0 == ~M_E~0;~M_E~0 := 1; 571#L696-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 191#L701-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 664#L706-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 540#L711-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 526#L716-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 314#L721-3true assume !(0 == ~T6_E~0); 177#L726-3true assume 0 == ~E_M~0;~E_M~0 := 1; 302#L731-3true assume 0 == ~E_1~0;~E_1~0 := 1; 500#L736-3true assume 0 == ~E_2~0;~E_2~0 := 1; 303#L741-3true assume 0 == ~E_3~0;~E_3~0 := 1; 139#L746-3true assume 0 == ~E_4~0;~E_4~0 := 1; 222#L751-3true assume 0 == ~E_5~0;~E_5~0 := 1; 420#L756-3true assume 0 == ~E_6~0;~E_6~0 := 1; 75#L761-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 91#L346-24true assume 1 == ~m_pc~0; 405#L347-8true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 304#L357-8true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 533#L358-8true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 488#L861-24true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 427#L861-26true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 108#L365-24true assume !(1 == ~t1_pc~0); 686#L365-26true is_transmit1_triggered_~__retres1~1#1 := 0; 645#L376-8true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 215#L377-8true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 384#L869-24true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 575#L869-26true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 83#L384-24true assume 1 == ~t2_pc~0; 693#L385-8true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 630#L395-8true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 490#L396-8true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 294#L877-24true assume !(0 != activate_threads_~tmp___1~0#1); 96#L877-26true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 167#L403-24true assume !(1 == ~t3_pc~0); 586#L403-26true is_transmit3_triggered_~__retres1~3#1 := 0; 192#L414-8true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 625#L415-8true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 258#L885-24true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 565#L885-26true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 125#L422-24true assume !(1 == ~t4_pc~0); 288#L422-26true is_transmit4_triggered_~__retres1~4#1 := 0; 101#L433-8true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 608#L434-8true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 530#L893-24true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 435#L893-26true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 133#L441-24true assume 1 == ~t5_pc~0; 362#L442-8true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 279#L452-8true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 372#L453-8true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 66#L901-24true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 366#L901-26true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 363#L460-24true assume 1 == ~t6_pc~0; 579#L461-8true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 678#L471-8true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 394#L472-8true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 451#L909-24true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 356#L909-26true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 627#L774-3true assume 1 == ~M_E~0;~M_E~0 := 2; 293#L774-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 176#L779-3true assume !(1 == ~T2_E~0); 22#L784-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 677#L789-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 13#L794-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 70#L799-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 277#L804-3true assume 1 == ~E_M~0;~E_M~0 := 2; 509#L809-3true assume 1 == ~E_1~0;~E_1~0 := 2; 68#L814-3true assume 1 == ~E_2~0;~E_2~0 := 2; 214#L819-3true assume !(1 == ~E_3~0); 150#L824-3true assume 1 == ~E_4~0;~E_4~0 := 2; 138#L829-3true assume 1 == ~E_5~0;~E_5~0 := 2; 341#L834-3true assume 1 == ~E_6~0;~E_6~0 := 2; 60#L839-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 439#L530-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 106#L567-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 266#L568-1true start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 31#L1084true assume !(0 == start_simulation_~tmp~3#1); 477#L1084-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 163#L530-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 81#L567-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 382#L568-2true stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 166#L1039true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 78#L1046true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 74#L1047true start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 170#L1097true assume !(0 != start_simulation_~tmp___0~1#1); 126#L1065-2true [2022-07-14 16:02:26,196 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:26,196 INFO L85 PathProgramCache]: Analyzing trace with hash -376834623, now seen corresponding path program 1 times [2022-07-14 16:02:26,204 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:26,204 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1309684973] [2022-07-14 16:02:26,204 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:26,205 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:26,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:26,370 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:26,371 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:26,372 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1309684973] [2022-07-14 16:02:26,373 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1309684973] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:26,373 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:26,374 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:26,375 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1289391957] [2022-07-14 16:02:26,376 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:26,379 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:26,380 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:26,380 INFO L85 PathProgramCache]: Analyzing trace with hash 96850367, now seen corresponding path program 1 times [2022-07-14 16:02:26,380 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:26,380 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1776312758] [2022-07-14 16:02:26,380 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:26,381 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:26,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:26,419 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:26,420 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:26,420 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1776312758] [2022-07-14 16:02:26,420 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1776312758] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:26,420 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:26,421 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-14 16:02:26,421 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1381726807] [2022-07-14 16:02:26,421 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:26,422 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:26,423 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:26,448 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:02:26,449 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:02:26,452 INFO L87 Difference]: Start difference. First operand has 694 states, 693 states have (on average 1.5252525252525253) internal successors, (1057), 693 states have internal predecessors, (1057), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:26,506 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:26,507 INFO L93 Difference]: Finished difference Result 692 states and 1034 transitions. [2022-07-14 16:02:26,512 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:02:26,516 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 692 states and 1034 transitions. [2022-07-14 16:02:26,522 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2022-07-14 16:02:26,531 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 692 states to 686 states and 1028 transitions. [2022-07-14 16:02:26,532 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 686 [2022-07-14 16:02:26,535 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 686 [2022-07-14 16:02:26,535 INFO L73 IsDeterministic]: Start isDeterministic. Operand 686 states and 1028 transitions. [2022-07-14 16:02:26,539 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:26,540 INFO L369 hiAutomatonCegarLoop]: Abstraction has 686 states and 1028 transitions. [2022-07-14 16:02:26,554 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 686 states and 1028 transitions. [2022-07-14 16:02:26,596 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 686 to 686. [2022-07-14 16:02:26,598 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 686 states, 686 states have (on average 1.498542274052478) internal successors, (1028), 685 states have internal predecessors, (1028), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:26,600 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 686 states to 686 states and 1028 transitions. [2022-07-14 16:02:26,601 INFO L392 hiAutomatonCegarLoop]: Abstraction has 686 states and 1028 transitions. [2022-07-14 16:02:26,602 INFO L374 stractBuchiCegarLoop]: Abstraction has 686 states and 1028 transitions. [2022-07-14 16:02:26,602 INFO L287 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-07-14 16:02:26,602 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 686 states and 1028 transitions. [2022-07-14 16:02:26,606 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2022-07-14 16:02:26,606 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:26,606 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:26,609 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:26,609 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:26,610 INFO L752 eck$LassoCheckResult]: Stem: 2080#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 2058#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 2033#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1979#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1980#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 1644#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1645#L492-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1494#L497-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1495#L502-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1461#L507-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1462#L512-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1622#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1782#L696 assume !(0 == ~M_E~0); 1783#L696-2 assume !(0 == ~T1_E~0); 2048#L701-1 assume !(0 == ~T2_E~0); 2050#L706-1 assume !(0 == ~T3_E~0); 1893#L711-1 assume !(0 == ~T4_E~0); 1678#L716-1 assume !(0 == ~T5_E~0); 1679#L721-1 assume !(0 == ~T6_E~0); 1849#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 1850#L731-1 assume !(0 == ~E_1~0); 1821#L736-1 assume !(0 == ~E_2~0); 1822#L741-1 assume !(0 == ~E_3~0); 1900#L746-1 assume !(0 == ~E_4~0); 1712#L751-1 assume !(0 == ~E_5~0); 1713#L756-1 assume !(0 == ~E_6~0); 1675#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1509#L346 assume !(1 == ~m_pc~0); 1510#L346-2 is_master_triggered_~__retres1~0#1 := 0; 1723#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1419#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1420#L861 assume !(0 != activate_threads_~tmp~1#1); 2020#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1541#L365 assume 1 == ~t1_pc~0; 1542#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1662#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2036#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1531#L869 assume !(0 != activate_threads_~tmp___0~0#1); 1532#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1947#L384 assume !(1 == ~t2_pc~0); 1939#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1940#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1618#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1443#L877 assume !(0 != activate_threads_~tmp___1~0#1); 1444#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1800#L403 assume 1 == ~t3_pc~0; 1680#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1681#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1671#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1672#L885 assume !(0 != activate_threads_~tmp___2~0#1); 1793#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1794#L422 assume 1 == ~t4_pc~0; 1440#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1441#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1943#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1944#L893 assume !(0 != activate_threads_~tmp___3~0#1); 1877#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1463#L441 assume !(1 == ~t5_pc~0); 1464#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2017#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2060#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2061#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1886#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1887#L460 assume 1 == ~t6_pc~0; 1403#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1404#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1471#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1988#L909 assume !(0 != activate_threads_~tmp___5~0#1); 1989#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1859#L774 assume !(1 == ~M_E~0); 1860#L774-2 assume !(1 == ~T1_E~0); 2003#L779-1 assume !(1 == ~T2_E~0); 1764#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1765#L789-1 assume !(1 == ~T4_E~0); 1525#L794-1 assume !(1 == ~T5_E~0); 1526#L799-1 assume !(1 == ~T6_E~0); 2071#L804-1 assume !(1 == ~E_M~0); 2072#L809-1 assume !(1 == ~E_1~0); 1847#L814-1 assume !(1 == ~E_2~0); 1421#L819-1 assume !(1 == ~E_3~0); 1422#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1907#L829-1 assume !(1 == ~E_5~0); 1995#L834-1 assume !(1 == ~E_6~0); 1663#L839-1 assume { :end_inline_reset_delta_events } true; 1649#L1065-2 [2022-07-14 16:02:26,611 INFO L754 eck$LassoCheckResult]: Loop: 1649#L1065-2 assume !false; 1650#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1702#L671 assume !false; 2029#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1975#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1502#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1512#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1923#L582 assume !(0 != eval_~tmp~0#1); 2073#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1910#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1698#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1699#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1744#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1745#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2054#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2049#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1903#L721-3 assume !(0 == ~T6_E~0); 1727#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1728#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1897#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1898#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1673#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1674#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1795#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1551#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1552#L346-24 assume 1 == ~m_pc~0; 1585#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1666#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1899#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2037#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2001#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1613#L365-24 assume 1 == ~t1_pc~0; 1614#L366-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1902#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1780#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1781#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1966#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1567#L384-24 assume !(1 == ~t2_pc~0); 1568#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 1587#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2038#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1888#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 1592#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1593#L403-24 assume 1 == ~t3_pc~0; 1715#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1746#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1747#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1845#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1846#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1646#L422-24 assume 1 == ~t4_pc~0; 1648#L423-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1599#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1600#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2051#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2009#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1659#L441-24 assume 1 == ~t5_pc~0; 1660#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1865#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1866#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1533#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1534#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1948#L460-24 assume !(1 == ~t6_pc~0); 1949#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 2004#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1977#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1978#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1937#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1938#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1885#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1726#L779-3 assume !(1 == ~T2_E~0); 1438#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1439#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1417#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1418#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1540#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1864#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1538#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1539#L819-3 assume !(1 == ~E_3~0); 1688#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1669#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1670#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1523#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1524#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1521#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1609#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1456#L1084 assume !(0 == start_simulation_~tmp~3#1); 1458#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1708#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1424#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1563#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 1714#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1556#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1549#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1550#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 1649#L1065-2 [2022-07-14 16:02:26,611 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:26,612 INFO L85 PathProgramCache]: Analyzing trace with hash 765667843, now seen corresponding path program 1 times [2022-07-14 16:02:26,612 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:26,612 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2112042174] [2022-07-14 16:02:26,612 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:26,613 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:26,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:26,658 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:26,659 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:26,659 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2112042174] [2022-07-14 16:02:26,659 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2112042174] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:26,659 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:26,660 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:26,660 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [345565825] [2022-07-14 16:02:26,660 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:26,661 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:26,661 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:26,661 INFO L85 PathProgramCache]: Analyzing trace with hash 1167110331, now seen corresponding path program 1 times [2022-07-14 16:02:26,662 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:26,662 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1688124642] [2022-07-14 16:02:26,662 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:26,662 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:26,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:26,773 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:26,773 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:26,774 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1688124642] [2022-07-14 16:02:26,774 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1688124642] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:26,774 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:26,774 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:26,774 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1154028792] [2022-07-14 16:02:26,774 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:26,775 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:26,775 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:26,776 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:02:26,776 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:02:26,776 INFO L87 Difference]: Start difference. First operand 686 states and 1028 transitions. cyclomatic complexity: 343 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:26,805 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:26,805 INFO L93 Difference]: Finished difference Result 686 states and 1027 transitions. [2022-07-14 16:02:26,805 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:02:26,806 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 686 states and 1027 transitions. [2022-07-14 16:02:26,811 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2022-07-14 16:02:26,816 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 686 states to 686 states and 1027 transitions. [2022-07-14 16:02:26,816 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 686 [2022-07-14 16:02:26,817 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 686 [2022-07-14 16:02:26,817 INFO L73 IsDeterministic]: Start isDeterministic. Operand 686 states and 1027 transitions. [2022-07-14 16:02:26,826 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:26,826 INFO L369 hiAutomatonCegarLoop]: Abstraction has 686 states and 1027 transitions. [2022-07-14 16:02:26,827 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 686 states and 1027 transitions. [2022-07-14 16:02:26,844 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 686 to 686. [2022-07-14 16:02:26,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 686 states, 686 states have (on average 1.4970845481049562) internal successors, (1027), 685 states have internal predecessors, (1027), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:26,847 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 686 states to 686 states and 1027 transitions. [2022-07-14 16:02:26,848 INFO L392 hiAutomatonCegarLoop]: Abstraction has 686 states and 1027 transitions. [2022-07-14 16:02:26,848 INFO L374 stractBuchiCegarLoop]: Abstraction has 686 states and 1027 transitions. [2022-07-14 16:02:26,848 INFO L287 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-07-14 16:02:26,848 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 686 states and 1027 transitions. [2022-07-14 16:02:26,851 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2022-07-14 16:02:26,852 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:26,852 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:26,854 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:26,854 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:26,854 INFO L752 eck$LassoCheckResult]: Stem: 3459#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 3437#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 3412#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3358#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3359#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 3023#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3024#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2871#L497-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2872#L502-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2840#L507-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2841#L512-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3001#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3161#L696 assume !(0 == ~M_E~0); 3162#L696-2 assume !(0 == ~T1_E~0); 3427#L701-1 assume !(0 == ~T2_E~0); 3429#L706-1 assume !(0 == ~T3_E~0); 3272#L711-1 assume !(0 == ~T4_E~0); 3057#L716-1 assume !(0 == ~T5_E~0); 3058#L721-1 assume !(0 == ~T6_E~0); 3228#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 3229#L731-1 assume !(0 == ~E_1~0); 3200#L736-1 assume !(0 == ~E_2~0); 3201#L741-1 assume !(0 == ~E_3~0); 3279#L746-1 assume !(0 == ~E_4~0); 3091#L751-1 assume !(0 == ~E_5~0); 3092#L756-1 assume !(0 == ~E_6~0); 3054#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2888#L346 assume !(1 == ~m_pc~0); 2889#L346-2 is_master_triggered_~__retres1~0#1 := 0; 3102#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2796#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2797#L861 assume !(0 != activate_threads_~tmp~1#1); 3399#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2919#L365 assume 1 == ~t1_pc~0; 2920#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3038#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3413#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2910#L869 assume !(0 != activate_threads_~tmp___0~0#1); 2911#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3326#L384 assume !(1 == ~t2_pc~0); 3316#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3317#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2997#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2822#L877 assume !(0 != activate_threads_~tmp___1~0#1); 2823#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3178#L403 assume 1 == ~t3_pc~0; 3059#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3060#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3046#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3047#L885 assume !(0 != activate_threads_~tmp___2~0#1); 3169#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3170#L422 assume 1 == ~t4_pc~0; 2817#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2818#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3322#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3323#L893 assume !(0 != activate_threads_~tmp___3~0#1); 3256#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2842#L441 assume !(1 == ~t5_pc~0); 2843#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3396#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3439#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3440#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3264#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3265#L460 assume 1 == ~t6_pc~0; 2779#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2780#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2850#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3367#L909 assume !(0 != activate_threads_~tmp___5~0#1); 3368#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3238#L774 assume !(1 == ~M_E~0); 3239#L774-2 assume !(1 == ~T1_E~0); 3382#L779-1 assume !(1 == ~T2_E~0); 3143#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3144#L789-1 assume !(1 == ~T4_E~0); 2904#L794-1 assume !(1 == ~T5_E~0); 2905#L799-1 assume !(1 == ~T6_E~0); 3450#L804-1 assume !(1 == ~E_M~0); 3451#L809-1 assume !(1 == ~E_1~0); 3226#L814-1 assume !(1 == ~E_2~0); 2798#L819-1 assume !(1 == ~E_3~0); 2799#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 3286#L829-1 assume !(1 == ~E_5~0); 3374#L834-1 assume !(1 == ~E_6~0); 3039#L839-1 assume { :end_inline_reset_delta_events } true; 3028#L1065-2 [2022-07-14 16:02:26,855 INFO L754 eck$LassoCheckResult]: Loop: 3028#L1065-2 assume !false; 3029#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3081#L671 assume !false; 3408#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3354#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2881#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2891#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3301#L582 assume !(0 != eval_~tmp~0#1); 3452#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3289#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3077#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3078#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3123#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3124#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3433#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3428#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3281#L721-3 assume !(0 == ~T6_E~0); 3106#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3107#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3276#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3277#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3052#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3053#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3174#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2930#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2931#L346-24 assume 1 == ~m_pc~0; 2961#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3045#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3278#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3414#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3380#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2992#L365-24 assume 1 == ~t1_pc~0; 2993#L366-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3282#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3159#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3160#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3346#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2946#L384-24 assume !(1 == ~t2_pc~0); 2947#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 2966#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3417#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3267#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 2972#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2973#L403-24 assume 1 == ~t3_pc~0; 3094#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3125#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3126#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3224#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3225#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3025#L422-24 assume !(1 == ~t4_pc~0); 3026#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 2979#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2980#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3430#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3388#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3040#L441-24 assume 1 == ~t5_pc~0; 3041#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3245#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3246#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2912#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2913#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3327#L460-24 assume !(1 == ~t6_pc~0); 3328#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 3383#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3356#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3357#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3318#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3319#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3266#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3105#L779-3 assume !(1 == ~T2_E~0); 2820#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2821#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2800#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2801#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2922#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3243#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2917#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2918#L819-3 assume !(1 == ~E_3~0); 3067#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3050#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3051#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2902#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2903#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2900#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2988#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 2837#L1084 assume !(0 == start_simulation_~tmp~3#1); 2839#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3087#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2803#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2942#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 3093#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2936#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2928#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 2929#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 3028#L1065-2 [2022-07-14 16:02:26,856 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:26,856 INFO L85 PathProgramCache]: Analyzing trace with hash -73365819, now seen corresponding path program 1 times [2022-07-14 16:02:26,856 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:26,856 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [228277053] [2022-07-14 16:02:26,857 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:26,857 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:26,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:26,889 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:26,889 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:26,889 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [228277053] [2022-07-14 16:02:26,890 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [228277053] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:26,890 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:26,890 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:26,890 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [317266405] [2022-07-14 16:02:26,891 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:26,891 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:26,892 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:26,892 INFO L85 PathProgramCache]: Analyzing trace with hash 293632636, now seen corresponding path program 1 times [2022-07-14 16:02:26,892 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:26,892 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [341740653] [2022-07-14 16:02:26,892 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:26,893 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:26,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:26,940 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:26,940 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:26,940 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [341740653] [2022-07-14 16:02:26,941 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [341740653] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:26,941 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:26,941 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:26,941 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1767535222] [2022-07-14 16:02:26,941 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:26,942 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:26,942 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:26,943 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:02:26,943 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:02:26,943 INFO L87 Difference]: Start difference. First operand 686 states and 1027 transitions. cyclomatic complexity: 342 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:26,957 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:26,963 INFO L93 Difference]: Finished difference Result 686 states and 1026 transitions. [2022-07-14 16:02:26,967 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:02:26,968 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 686 states and 1026 transitions. [2022-07-14 16:02:26,972 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2022-07-14 16:02:26,976 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 686 states to 686 states and 1026 transitions. [2022-07-14 16:02:26,977 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 686 [2022-07-14 16:02:26,977 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 686 [2022-07-14 16:02:26,978 INFO L73 IsDeterministic]: Start isDeterministic. Operand 686 states and 1026 transitions. [2022-07-14 16:02:26,979 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:26,979 INFO L369 hiAutomatonCegarLoop]: Abstraction has 686 states and 1026 transitions. [2022-07-14 16:02:26,980 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 686 states and 1026 transitions. [2022-07-14 16:02:26,986 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 686 to 686. [2022-07-14 16:02:26,988 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 686 states, 686 states have (on average 1.4956268221574345) internal successors, (1026), 685 states have internal predecessors, (1026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:26,990 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 686 states to 686 states and 1026 transitions. [2022-07-14 16:02:26,990 INFO L392 hiAutomatonCegarLoop]: Abstraction has 686 states and 1026 transitions. [2022-07-14 16:02:26,990 INFO L374 stractBuchiCegarLoop]: Abstraction has 686 states and 1026 transitions. [2022-07-14 16:02:26,990 INFO L287 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-07-14 16:02:26,991 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 686 states and 1026 transitions. [2022-07-14 16:02:26,993 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2022-07-14 16:02:26,994 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:26,994 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:26,995 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:26,995 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:26,996 INFO L752 eck$LassoCheckResult]: Stem: 4838#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 4816#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 4791#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4737#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4738#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 4402#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4403#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4250#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4251#L502-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4219#L507-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4220#L512-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4380#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4540#L696 assume !(0 == ~M_E~0); 4541#L696-2 assume !(0 == ~T1_E~0); 4806#L701-1 assume !(0 == ~T2_E~0); 4808#L706-1 assume !(0 == ~T3_E~0); 4651#L711-1 assume !(0 == ~T4_E~0); 4436#L716-1 assume !(0 == ~T5_E~0); 4437#L721-1 assume !(0 == ~T6_E~0); 4607#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 4608#L731-1 assume !(0 == ~E_1~0); 4579#L736-1 assume !(0 == ~E_2~0); 4580#L741-1 assume !(0 == ~E_3~0); 4658#L746-1 assume !(0 == ~E_4~0); 4470#L751-1 assume !(0 == ~E_5~0); 4471#L756-1 assume !(0 == ~E_6~0); 4433#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4267#L346 assume !(1 == ~m_pc~0); 4268#L346-2 is_master_triggered_~__retres1~0#1 := 0; 4481#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4175#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4176#L861 assume !(0 != activate_threads_~tmp~1#1); 4778#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4298#L365 assume 1 == ~t1_pc~0; 4299#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4417#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4792#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4289#L869 assume !(0 != activate_threads_~tmp___0~0#1); 4290#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4705#L384 assume !(1 == ~t2_pc~0); 4695#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4696#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4376#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4201#L877 assume !(0 != activate_threads_~tmp___1~0#1); 4202#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4557#L403 assume 1 == ~t3_pc~0; 4438#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4439#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4425#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4426#L885 assume !(0 != activate_threads_~tmp___2~0#1); 4548#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4549#L422 assume 1 == ~t4_pc~0; 4196#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4197#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4701#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4702#L893 assume !(0 != activate_threads_~tmp___3~0#1); 4635#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4221#L441 assume !(1 == ~t5_pc~0); 4222#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4775#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4818#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4819#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4643#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4644#L460 assume 1 == ~t6_pc~0; 4158#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4159#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4229#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4746#L909 assume !(0 != activate_threads_~tmp___5~0#1); 4747#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4617#L774 assume !(1 == ~M_E~0); 4618#L774-2 assume !(1 == ~T1_E~0); 4761#L779-1 assume !(1 == ~T2_E~0); 4522#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4523#L789-1 assume !(1 == ~T4_E~0); 4283#L794-1 assume !(1 == ~T5_E~0); 4284#L799-1 assume !(1 == ~T6_E~0); 4829#L804-1 assume !(1 == ~E_M~0); 4830#L809-1 assume !(1 == ~E_1~0); 4605#L814-1 assume !(1 == ~E_2~0); 4177#L819-1 assume !(1 == ~E_3~0); 4178#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 4665#L829-1 assume !(1 == ~E_5~0); 4753#L834-1 assume !(1 == ~E_6~0); 4418#L839-1 assume { :end_inline_reset_delta_events } true; 4407#L1065-2 [2022-07-14 16:02:26,996 INFO L754 eck$LassoCheckResult]: Loop: 4407#L1065-2 assume !false; 4408#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4460#L671 assume !false; 4787#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4733#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4260#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4270#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4680#L582 assume !(0 != eval_~tmp~0#1); 4831#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4668#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4456#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4457#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4502#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4503#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4812#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4807#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4660#L721-3 assume !(0 == ~T6_E~0); 4485#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4486#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4655#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4656#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4431#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4432#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4553#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4309#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4310#L346-24 assume 1 == ~m_pc~0; 4340#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4424#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4657#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4793#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4759#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4371#L365-24 assume 1 == ~t1_pc~0; 4372#L366-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4661#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4538#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4539#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4725#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4327#L384-24 assume !(1 == ~t2_pc~0); 4328#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 4345#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4796#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4646#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 4351#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4352#L403-24 assume 1 == ~t3_pc~0; 4473#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4504#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4505#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4603#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4604#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4404#L422-24 assume !(1 == ~t4_pc~0); 4405#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 4358#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4359#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4809#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4767#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4419#L441-24 assume 1 == ~t5_pc~0; 4420#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4624#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4625#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4291#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4292#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4706#L460-24 assume !(1 == ~t6_pc~0); 4707#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 4762#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4735#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4736#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4697#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4698#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4645#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4484#L779-3 assume !(1 == ~T2_E~0); 4199#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4200#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4179#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4180#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4301#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4622#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4296#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4297#L819-3 assume !(1 == ~E_3~0); 4446#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4429#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4430#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4281#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4282#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4279#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4367#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 4216#L1084 assume !(0 == start_simulation_~tmp~3#1); 4218#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4466#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4182#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4321#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 4472#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4315#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4307#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 4308#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 4407#L1065-2 [2022-07-14 16:02:26,997 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:26,997 INFO L85 PathProgramCache]: Analyzing trace with hash -100431421, now seen corresponding path program 1 times [2022-07-14 16:02:26,998 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:26,998 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [850956313] [2022-07-14 16:02:26,998 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:26,998 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:27,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:27,051 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:27,052 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:27,053 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [850956313] [2022-07-14 16:02:27,053 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [850956313] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:27,053 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:27,054 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:27,055 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [493118724] [2022-07-14 16:02:27,055 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:27,056 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:27,056 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:27,056 INFO L85 PathProgramCache]: Analyzing trace with hash 293632636, now seen corresponding path program 2 times [2022-07-14 16:02:27,056 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:27,057 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [223984618] [2022-07-14 16:02:27,057 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:27,057 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:27,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:27,104 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:27,105 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:27,105 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [223984618] [2022-07-14 16:02:27,105 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [223984618] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:27,105 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:27,105 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:27,106 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1148142230] [2022-07-14 16:02:27,106 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:27,106 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:27,106 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:27,107 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:02:27,107 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:02:27,107 INFO L87 Difference]: Start difference. First operand 686 states and 1026 transitions. cyclomatic complexity: 341 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:27,120 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:27,121 INFO L93 Difference]: Finished difference Result 686 states and 1025 transitions. [2022-07-14 16:02:27,121 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:02:27,122 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 686 states and 1025 transitions. [2022-07-14 16:02:27,126 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2022-07-14 16:02:27,129 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 686 states to 686 states and 1025 transitions. [2022-07-14 16:02:27,129 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 686 [2022-07-14 16:02:27,130 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 686 [2022-07-14 16:02:27,130 INFO L73 IsDeterministic]: Start isDeterministic. Operand 686 states and 1025 transitions. [2022-07-14 16:02:27,131 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:27,131 INFO L369 hiAutomatonCegarLoop]: Abstraction has 686 states and 1025 transitions. [2022-07-14 16:02:27,132 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 686 states and 1025 transitions. [2022-07-14 16:02:27,139 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 686 to 686. [2022-07-14 16:02:27,140 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 686 states, 686 states have (on average 1.4941690962099126) internal successors, (1025), 685 states have internal predecessors, (1025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:27,142 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 686 states to 686 states and 1025 transitions. [2022-07-14 16:02:27,143 INFO L392 hiAutomatonCegarLoop]: Abstraction has 686 states and 1025 transitions. [2022-07-14 16:02:27,143 INFO L374 stractBuchiCegarLoop]: Abstraction has 686 states and 1025 transitions. [2022-07-14 16:02:27,143 INFO L287 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-07-14 16:02:27,143 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 686 states and 1025 transitions. [2022-07-14 16:02:27,146 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2022-07-14 16:02:27,146 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:27,146 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:27,148 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:27,148 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:27,148 INFO L752 eck$LassoCheckResult]: Stem: 6217#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 6195#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 6170#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6116#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6117#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 5781#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5782#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5631#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5632#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5598#L507-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5599#L512-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5759#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5919#L696 assume !(0 == ~M_E~0); 5920#L696-2 assume !(0 == ~T1_E~0); 6185#L701-1 assume !(0 == ~T2_E~0); 6187#L706-1 assume !(0 == ~T3_E~0); 6030#L711-1 assume !(0 == ~T4_E~0); 5815#L716-1 assume !(0 == ~T5_E~0); 5816#L721-1 assume !(0 == ~T6_E~0); 5986#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 5987#L731-1 assume !(0 == ~E_1~0); 5958#L736-1 assume !(0 == ~E_2~0); 5959#L741-1 assume !(0 == ~E_3~0); 6037#L746-1 assume !(0 == ~E_4~0); 5849#L751-1 assume !(0 == ~E_5~0); 5850#L756-1 assume !(0 == ~E_6~0); 5812#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5646#L346 assume !(1 == ~m_pc~0); 5647#L346-2 is_master_triggered_~__retres1~0#1 := 0; 5860#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5556#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5557#L861 assume !(0 != activate_threads_~tmp~1#1); 6157#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5678#L365 assume 1 == ~t1_pc~0; 5679#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5799#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6174#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5668#L869 assume !(0 != activate_threads_~tmp___0~0#1); 5669#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6084#L384 assume !(1 == ~t2_pc~0); 6076#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6077#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5755#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5582#L877 assume !(0 != activate_threads_~tmp___1~0#1); 5583#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5937#L403 assume 1 == ~t3_pc~0; 5817#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5818#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5808#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5809#L885 assume !(0 != activate_threads_~tmp___2~0#1); 5930#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5931#L422 assume 1 == ~t4_pc~0; 5577#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5578#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6080#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6081#L893 assume !(0 != activate_threads_~tmp___3~0#1); 6014#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5600#L441 assume !(1 == ~t5_pc~0); 5601#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 6154#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6197#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6198#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6023#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6024#L460 assume 1 == ~t6_pc~0; 5540#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5541#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5608#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6125#L909 assume !(0 != activate_threads_~tmp___5~0#1); 6126#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5996#L774 assume !(1 == ~M_E~0); 5997#L774-2 assume !(1 == ~T1_E~0); 6140#L779-1 assume !(1 == ~T2_E~0); 5901#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5902#L789-1 assume !(1 == ~T4_E~0); 5662#L794-1 assume !(1 == ~T5_E~0); 5663#L799-1 assume !(1 == ~T6_E~0); 6208#L804-1 assume !(1 == ~E_M~0); 6209#L809-1 assume !(1 == ~E_1~0); 5984#L814-1 assume !(1 == ~E_2~0); 5558#L819-1 assume !(1 == ~E_3~0); 5559#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 6044#L829-1 assume !(1 == ~E_5~0); 6132#L834-1 assume !(1 == ~E_6~0); 5800#L839-1 assume { :end_inline_reset_delta_events } true; 5789#L1065-2 [2022-07-14 16:02:27,150 INFO L754 eck$LassoCheckResult]: Loop: 5789#L1065-2 assume !false; 5790#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5839#L671 assume !false; 6166#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 6112#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5639#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5649#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 6060#L582 assume !(0 != eval_~tmp~0#1); 6210#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6047#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5835#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5836#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5881#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5882#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6191#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6186#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6040#L721-3 assume !(0 == ~T6_E~0); 5864#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5865#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6034#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6035#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5810#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5811#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5932#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5688#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5689#L346-24 assume 1 == ~m_pc~0; 5722#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5801#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6036#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6171#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6138#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5750#L365-24 assume 1 == ~t1_pc~0; 5751#L366-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6039#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5917#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5918#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6103#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5704#L384-24 assume !(1 == ~t2_pc~0); 5705#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 5724#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6175#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6025#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 5729#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5730#L403-24 assume 1 == ~t3_pc~0; 5852#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5883#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5884#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5982#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5983#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5783#L422-24 assume !(1 == ~t4_pc~0); 5784#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 5736#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5737#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6188#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6146#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5796#L441-24 assume 1 == ~t5_pc~0; 5797#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6002#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6003#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5670#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5671#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6085#L460-24 assume !(1 == ~t6_pc~0); 6086#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 6141#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6114#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6115#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6074#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6075#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6022#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5863#L779-3 assume !(1 == ~T2_E~0); 5575#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5576#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5554#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5555#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5677#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6001#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5675#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5676#L819-3 assume !(1 == ~E_3~0); 5825#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5806#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5807#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5660#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5661#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5658#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5746#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 5595#L1084 assume !(0 == start_simulation_~tmp~3#1); 5597#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5845#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5561#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5700#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 5851#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5693#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5686#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 5687#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 5789#L1065-2 [2022-07-14 16:02:27,151 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:27,151 INFO L85 PathProgramCache]: Analyzing trace with hash 1976905477, now seen corresponding path program 1 times [2022-07-14 16:02:27,151 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:27,151 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [988668816] [2022-07-14 16:02:27,152 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:27,152 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:27,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:27,201 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:27,202 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:27,202 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [988668816] [2022-07-14 16:02:27,202 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [988668816] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:27,202 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:27,203 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:27,203 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [931040803] [2022-07-14 16:02:27,203 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:27,203 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:27,204 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:27,204 INFO L85 PathProgramCache]: Analyzing trace with hash 293632636, now seen corresponding path program 3 times [2022-07-14 16:02:27,204 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:27,205 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1276932393] [2022-07-14 16:02:27,205 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:27,205 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:27,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:27,260 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:27,261 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:27,262 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1276932393] [2022-07-14 16:02:27,263 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1276932393] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:27,263 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:27,263 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:27,263 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1382775144] [2022-07-14 16:02:27,263 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:27,264 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:27,264 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:27,264 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:02:27,264 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:02:27,265 INFO L87 Difference]: Start difference. First operand 686 states and 1025 transitions. cyclomatic complexity: 340 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:27,279 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:27,279 INFO L93 Difference]: Finished difference Result 686 states and 1024 transitions. [2022-07-14 16:02:27,280 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:02:27,282 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 686 states and 1024 transitions. [2022-07-14 16:02:27,286 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2022-07-14 16:02:27,290 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 686 states to 686 states and 1024 transitions. [2022-07-14 16:02:27,290 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 686 [2022-07-14 16:02:27,291 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 686 [2022-07-14 16:02:27,291 INFO L73 IsDeterministic]: Start isDeterministic. Operand 686 states and 1024 transitions. [2022-07-14 16:02:27,292 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:27,292 INFO L369 hiAutomatonCegarLoop]: Abstraction has 686 states and 1024 transitions. [2022-07-14 16:02:27,292 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 686 states and 1024 transitions. [2022-07-14 16:02:27,299 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 686 to 686. [2022-07-14 16:02:27,300 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 686 states, 686 states have (on average 1.4927113702623906) internal successors, (1024), 685 states have internal predecessors, (1024), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:27,302 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 686 states to 686 states and 1024 transitions. [2022-07-14 16:02:27,302 INFO L392 hiAutomatonCegarLoop]: Abstraction has 686 states and 1024 transitions. [2022-07-14 16:02:27,302 INFO L374 stractBuchiCegarLoop]: Abstraction has 686 states and 1024 transitions. [2022-07-14 16:02:27,302 INFO L287 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-07-14 16:02:27,303 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 686 states and 1024 transitions. [2022-07-14 16:02:27,305 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2022-07-14 16:02:27,305 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:27,306 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:27,307 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:27,307 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:27,307 INFO L752 eck$LassoCheckResult]: Stem: 7596#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 7574#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 7549#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7495#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7496#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 7160#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7161#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7008#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7009#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6977#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6978#L512-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7138#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7298#L696 assume !(0 == ~M_E~0); 7299#L696-2 assume !(0 == ~T1_E~0); 7564#L701-1 assume !(0 == ~T2_E~0); 7566#L706-1 assume !(0 == ~T3_E~0); 7409#L711-1 assume !(0 == ~T4_E~0); 7194#L716-1 assume !(0 == ~T5_E~0); 7195#L721-1 assume !(0 == ~T6_E~0); 7365#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 7366#L731-1 assume !(0 == ~E_1~0); 7337#L736-1 assume !(0 == ~E_2~0); 7338#L741-1 assume !(0 == ~E_3~0); 7416#L746-1 assume !(0 == ~E_4~0); 7228#L751-1 assume !(0 == ~E_5~0); 7229#L756-1 assume !(0 == ~E_6~0); 7191#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7025#L346 assume !(1 == ~m_pc~0); 7026#L346-2 is_master_triggered_~__retres1~0#1 := 0; 7239#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6933#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6934#L861 assume !(0 != activate_threads_~tmp~1#1); 7536#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7056#L365 assume 1 == ~t1_pc~0; 7057#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7175#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7550#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7047#L869 assume !(0 != activate_threads_~tmp___0~0#1); 7048#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7463#L384 assume !(1 == ~t2_pc~0); 7453#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7454#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7134#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6959#L877 assume !(0 != activate_threads_~tmp___1~0#1); 6960#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7315#L403 assume 1 == ~t3_pc~0; 7196#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7197#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7183#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7184#L885 assume !(0 != activate_threads_~tmp___2~0#1); 7306#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7307#L422 assume 1 == ~t4_pc~0; 6954#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6955#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7459#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7460#L893 assume !(0 != activate_threads_~tmp___3~0#1); 7393#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6979#L441 assume !(1 == ~t5_pc~0); 6980#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7533#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7576#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7577#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7401#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7402#L460 assume 1 == ~t6_pc~0; 6916#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6917#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6987#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7504#L909 assume !(0 != activate_threads_~tmp___5~0#1); 7505#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7375#L774 assume !(1 == ~M_E~0); 7376#L774-2 assume !(1 == ~T1_E~0); 7519#L779-1 assume !(1 == ~T2_E~0); 7280#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7281#L789-1 assume !(1 == ~T4_E~0); 7041#L794-1 assume !(1 == ~T5_E~0); 7042#L799-1 assume !(1 == ~T6_E~0); 7587#L804-1 assume !(1 == ~E_M~0); 7588#L809-1 assume !(1 == ~E_1~0); 7363#L814-1 assume !(1 == ~E_2~0); 6935#L819-1 assume !(1 == ~E_3~0); 6936#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 7423#L829-1 assume !(1 == ~E_5~0); 7511#L834-1 assume !(1 == ~E_6~0); 7176#L839-1 assume { :end_inline_reset_delta_events } true; 7165#L1065-2 [2022-07-14 16:02:27,307 INFO L754 eck$LassoCheckResult]: Loop: 7165#L1065-2 assume !false; 7166#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7218#L671 assume !false; 7545#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7491#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7018#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7028#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 7438#L582 assume !(0 != eval_~tmp~0#1); 7589#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7426#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7214#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7215#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7260#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7261#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7570#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7565#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7418#L721-3 assume !(0 == ~T6_E~0); 7243#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7244#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7413#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7414#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7189#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7190#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7311#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7067#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7068#L346-24 assume 1 == ~m_pc~0; 7098#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7182#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7415#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7551#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7517#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7129#L365-24 assume 1 == ~t1_pc~0; 7130#L366-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7419#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7296#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7297#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7483#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7083#L384-24 assume !(1 == ~t2_pc~0); 7084#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 7103#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7554#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7404#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 7109#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7110#L403-24 assume !(1 == ~t3_pc~0); 7232#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 7262#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7263#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7361#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7362#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7162#L422-24 assume !(1 == ~t4_pc~0); 7163#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 7116#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7117#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7567#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7525#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7177#L441-24 assume 1 == ~t5_pc~0; 7178#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7382#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7383#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7049#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7050#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7464#L460-24 assume !(1 == ~t6_pc~0); 7465#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 7520#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7493#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7494#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7455#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7456#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7403#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7242#L779-3 assume !(1 == ~T2_E~0); 6957#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6958#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6937#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6938#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7059#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7380#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7054#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7055#L819-3 assume !(1 == ~E_3~0); 7204#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7187#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7188#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7039#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7040#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7037#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7125#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 6974#L1084 assume !(0 == start_simulation_~tmp~3#1); 6976#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7224#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 6940#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7079#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 7230#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7073#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7065#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 7066#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 7165#L1065-2 [2022-07-14 16:02:27,308 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:27,308 INFO L85 PathProgramCache]: Analyzing trace with hash 242801027, now seen corresponding path program 1 times [2022-07-14 16:02:27,308 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:27,308 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [243468044] [2022-07-14 16:02:27,308 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:27,308 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:27,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:27,336 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:27,336 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:27,337 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [243468044] [2022-07-14 16:02:27,338 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [243468044] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:27,338 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:27,338 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:27,341 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1907296258] [2022-07-14 16:02:27,342 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:27,343 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:27,346 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:27,346 INFO L85 PathProgramCache]: Analyzing trace with hash -1807208579, now seen corresponding path program 1 times [2022-07-14 16:02:27,346 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:27,346 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1869655426] [2022-07-14 16:02:27,347 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:27,347 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:27,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:27,391 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:27,391 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:27,392 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1869655426] [2022-07-14 16:02:27,394 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1869655426] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:27,394 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:27,394 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:27,394 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [248936347] [2022-07-14 16:02:27,395 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:27,395 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:27,395 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:27,396 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:02:27,396 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:02:27,397 INFO L87 Difference]: Start difference. First operand 686 states and 1024 transitions. cyclomatic complexity: 339 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:27,409 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:27,409 INFO L93 Difference]: Finished difference Result 686 states and 1023 transitions. [2022-07-14 16:02:27,409 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:02:27,411 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 686 states and 1023 transitions. [2022-07-14 16:02:27,415 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2022-07-14 16:02:27,418 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 686 states to 686 states and 1023 transitions. [2022-07-14 16:02:27,418 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 686 [2022-07-14 16:02:27,419 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 686 [2022-07-14 16:02:27,419 INFO L73 IsDeterministic]: Start isDeterministic. Operand 686 states and 1023 transitions. [2022-07-14 16:02:27,420 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:27,420 INFO L369 hiAutomatonCegarLoop]: Abstraction has 686 states and 1023 transitions. [2022-07-14 16:02:27,421 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 686 states and 1023 transitions. [2022-07-14 16:02:27,428 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 686 to 686. [2022-07-14 16:02:27,429 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 686 states, 686 states have (on average 1.4912536443148687) internal successors, (1023), 685 states have internal predecessors, (1023), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:27,431 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 686 states to 686 states and 1023 transitions. [2022-07-14 16:02:27,431 INFO L392 hiAutomatonCegarLoop]: Abstraction has 686 states and 1023 transitions. [2022-07-14 16:02:27,431 INFO L374 stractBuchiCegarLoop]: Abstraction has 686 states and 1023 transitions. [2022-07-14 16:02:27,432 INFO L287 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-07-14 16:02:27,432 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 686 states and 1023 transitions. [2022-07-14 16:02:27,434 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2022-07-14 16:02:27,435 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:27,435 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:27,436 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:27,436 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:27,436 INFO L752 eck$LassoCheckResult]: Stem: 8975#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 8953#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 8928#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8874#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8875#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 8539#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8540#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8387#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8388#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8356#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8357#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 8517#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8677#L696 assume !(0 == ~M_E~0); 8678#L696-2 assume !(0 == ~T1_E~0); 8943#L701-1 assume !(0 == ~T2_E~0); 8945#L706-1 assume !(0 == ~T3_E~0); 8788#L711-1 assume !(0 == ~T4_E~0); 8573#L716-1 assume !(0 == ~T5_E~0); 8574#L721-1 assume !(0 == ~T6_E~0); 8744#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 8745#L731-1 assume !(0 == ~E_1~0); 8716#L736-1 assume !(0 == ~E_2~0); 8717#L741-1 assume !(0 == ~E_3~0); 8795#L746-1 assume !(0 == ~E_4~0); 8607#L751-1 assume !(0 == ~E_5~0); 8608#L756-1 assume !(0 == ~E_6~0); 8570#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8404#L346 assume !(1 == ~m_pc~0); 8405#L346-2 is_master_triggered_~__retres1~0#1 := 0; 8618#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8312#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8313#L861 assume !(0 != activate_threads_~tmp~1#1); 8915#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8436#L365 assume 1 == ~t1_pc~0; 8437#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8554#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8929#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8426#L869 assume !(0 != activate_threads_~tmp___0~0#1); 8427#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8842#L384 assume !(1 == ~t2_pc~0); 8832#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8833#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8513#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8338#L877 assume !(0 != activate_threads_~tmp___1~0#1); 8339#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8694#L403 assume 1 == ~t3_pc~0; 8575#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8576#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8564#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8565#L885 assume !(0 != activate_threads_~tmp___2~0#1); 8685#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8686#L422 assume 1 == ~t4_pc~0; 8333#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8334#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8838#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8839#L893 assume !(0 != activate_threads_~tmp___3~0#1); 8772#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8358#L441 assume !(1 == ~t5_pc~0); 8359#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 8912#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8955#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8956#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8780#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8781#L460 assume 1 == ~t6_pc~0; 8295#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8296#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8366#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8883#L909 assume !(0 != activate_threads_~tmp___5~0#1); 8884#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8754#L774 assume !(1 == ~M_E~0); 8755#L774-2 assume !(1 == ~T1_E~0); 8898#L779-1 assume !(1 == ~T2_E~0); 8659#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8660#L789-1 assume !(1 == ~T4_E~0); 8420#L794-1 assume !(1 == ~T5_E~0); 8421#L799-1 assume !(1 == ~T6_E~0); 8966#L804-1 assume !(1 == ~E_M~0); 8967#L809-1 assume !(1 == ~E_1~0); 8742#L814-1 assume !(1 == ~E_2~0); 8314#L819-1 assume !(1 == ~E_3~0); 8315#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 8802#L829-1 assume !(1 == ~E_5~0); 8890#L834-1 assume !(1 == ~E_6~0); 8555#L839-1 assume { :end_inline_reset_delta_events } true; 8544#L1065-2 [2022-07-14 16:02:27,437 INFO L754 eck$LassoCheckResult]: Loop: 8544#L1065-2 assume !false; 8545#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8597#L671 assume !false; 8924#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8870#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8397#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8407#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8817#L582 assume !(0 != eval_~tmp~0#1); 8968#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8805#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8593#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8594#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8639#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8640#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8949#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8944#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8797#L721-3 assume !(0 == ~T6_E~0); 8622#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8623#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8792#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8793#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8568#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8569#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8690#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8446#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8447#L346-24 assume 1 == ~m_pc~0; 8477#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8561#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8794#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8930#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8896#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8510#L365-24 assume !(1 == ~t1_pc~0); 8512#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 8798#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8675#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8676#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8862#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8464#L384-24 assume !(1 == ~t2_pc~0); 8465#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 8482#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8933#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8783#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 8488#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8489#L403-24 assume 1 == ~t3_pc~0; 8610#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8641#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8642#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8740#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8741#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8541#L422-24 assume !(1 == ~t4_pc~0); 8542#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 8495#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8496#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8946#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8904#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8556#L441-24 assume 1 == ~t5_pc~0; 8557#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8761#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8762#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8428#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8429#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8843#L460-24 assume !(1 == ~t6_pc~0); 8844#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 8899#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8872#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8873#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8834#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8835#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8782#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8621#L779-3 assume !(1 == ~T2_E~0); 8336#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8337#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8316#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8317#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8435#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8759#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8430#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8431#L819-3 assume !(1 == ~E_3~0); 8581#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8562#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8563#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8418#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8419#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8416#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8503#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 8351#L1084 assume !(0 == start_simulation_~tmp~3#1); 8353#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8603#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8319#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8458#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 8609#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8448#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8444#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 8445#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 8544#L1065-2 [2022-07-14 16:02:27,437 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:27,437 INFO L85 PathProgramCache]: Analyzing trace with hash -644421819, now seen corresponding path program 1 times [2022-07-14 16:02:27,437 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:27,438 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1870553003] [2022-07-14 16:02:27,438 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:27,438 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:27,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:27,485 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:27,486 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:27,486 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1870553003] [2022-07-14 16:02:27,486 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1870553003] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:27,486 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:27,486 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:27,486 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [687652154] [2022-07-14 16:02:27,487 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:27,487 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:27,487 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:27,488 INFO L85 PathProgramCache]: Analyzing trace with hash 870561277, now seen corresponding path program 1 times [2022-07-14 16:02:27,488 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:27,488 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2109401655] [2022-07-14 16:02:27,488 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:27,488 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:27,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:27,513 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:27,513 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:27,513 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2109401655] [2022-07-14 16:02:27,514 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2109401655] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:27,514 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:27,514 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:27,514 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1199584580] [2022-07-14 16:02:27,514 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:27,514 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:27,515 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:27,515 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:02:27,515 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:02:27,515 INFO L87 Difference]: Start difference. First operand 686 states and 1023 transitions. cyclomatic complexity: 338 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:27,627 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:27,628 INFO L93 Difference]: Finished difference Result 1180 states and 1756 transitions. [2022-07-14 16:02:27,628 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:02:27,630 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1180 states and 1756 transitions. [2022-07-14 16:02:27,636 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1074 [2022-07-14 16:02:27,642 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1180 states to 1180 states and 1756 transitions. [2022-07-14 16:02:27,642 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1180 [2022-07-14 16:02:27,643 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1180 [2022-07-14 16:02:27,643 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1180 states and 1756 transitions. [2022-07-14 16:02:27,645 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:27,645 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1756 transitions. [2022-07-14 16:02:27,646 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1180 states and 1756 transitions. [2022-07-14 16:02:27,662 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1180 to 1179. [2022-07-14 16:02:27,664 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1179 states, 1179 states have (on average 1.4885496183206106) internal successors, (1755), 1178 states have internal predecessors, (1755), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:27,667 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1179 states to 1179 states and 1755 transitions. [2022-07-14 16:02:27,670 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1179 states and 1755 transitions. [2022-07-14 16:02:27,670 INFO L374 stractBuchiCegarLoop]: Abstraction has 1179 states and 1755 transitions. [2022-07-14 16:02:27,670 INFO L287 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-07-14 16:02:27,670 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1179 states and 1755 transitions. [2022-07-14 16:02:27,679 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1074 [2022-07-14 16:02:27,679 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:27,679 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:27,680 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:27,680 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:27,681 INFO L752 eck$LassoCheckResult]: Stem: 10911#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 10873#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 10844#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10778#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10779#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 10418#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10419#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10263#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10264#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10232#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10233#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10396#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10562#L696 assume !(0 == ~M_E~0); 10563#L696-2 assume !(0 == ~T1_E~0); 10862#L701-1 assume !(0 == ~T2_E~0); 10864#L706-1 assume !(0 == ~T3_E~0); 10677#L711-1 assume !(0 == ~T4_E~0); 10452#L716-1 assume !(0 == ~T5_E~0); 10453#L721-1 assume !(0 == ~T6_E~0); 10631#L726-1 assume !(0 == ~E_M~0); 10632#L731-1 assume !(0 == ~E_1~0); 10602#L736-1 assume !(0 == ~E_2~0); 10603#L741-1 assume !(0 == ~E_3~0); 10685#L746-1 assume !(0 == ~E_4~0); 10487#L751-1 assume !(0 == ~E_5~0); 10488#L756-1 assume !(0 == ~E_6~0); 10449#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10280#L346 assume !(1 == ~m_pc~0); 10281#L346-2 is_master_triggered_~__retres1~0#1 := 0; 10500#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10188#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10189#L861 assume !(0 != activate_threads_~tmp~1#1); 10825#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10312#L365 assume 1 == ~t1_pc~0; 10313#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10433#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10845#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10303#L869 assume !(0 != activate_threads_~tmp___0~0#1); 10304#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10740#L384 assume !(1 == ~t2_pc~0); 10729#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10730#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10392#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10214#L877 assume !(0 != activate_threads_~tmp___1~0#1); 10215#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10580#L403 assume 1 == ~t3_pc~0; 10454#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10455#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10441#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10442#L885 assume !(0 != activate_threads_~tmp___2~0#1); 10571#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10572#L422 assume 1 == ~t4_pc~0; 10209#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10210#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10736#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10737#L893 assume !(0 != activate_threads_~tmp___3~0#1); 10661#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10234#L441 assume !(1 == ~t5_pc~0); 10235#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 10822#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10875#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10876#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10669#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10670#L460 assume 1 == ~t6_pc~0; 10171#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10172#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10242#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10787#L909 assume !(0 != activate_threads_~tmp___5~0#1); 10788#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10641#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 10642#L774-2 assume !(1 == ~T1_E~0); 10989#L779-1 assume !(1 == ~T2_E~0); 10988#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10981#L789-1 assume !(1 == ~T4_E~0); 10297#L794-1 assume !(1 == ~T5_E~0); 10298#L799-1 assume !(1 == ~T6_E~0); 10945#L804-1 assume !(1 == ~E_M~0); 10893#L809-1 assume !(1 == ~E_1~0); 10942#L814-1 assume !(1 == ~E_2~0); 10940#L819-1 assume !(1 == ~E_3~0); 10939#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 10938#L829-1 assume !(1 == ~E_5~0); 10794#L834-1 assume !(1 == ~E_6~0); 10795#L839-1 assume { :end_inline_reset_delta_events } true; 10931#L1065-2 [2022-07-14 16:02:27,681 INFO L754 eck$LassoCheckResult]: Loop: 10931#L1065-2 assume !false; 10710#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10477#L671 assume !false; 10877#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 10878#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 10283#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 10284#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 10913#L582 assume !(0 != eval_~tmp~0#1); 10915#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10696#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10697#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10916#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11074#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11073#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11072#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11071#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11070#L721-3 assume !(0 == ~T6_E~0); 11069#L726-3 assume !(0 == ~E_M~0); 11068#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11067#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11066#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11065#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11064#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11063#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11062#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11061#L346-24 assume 1 == ~m_pc~0; 11059#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11058#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11057#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11056#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11055#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11054#L365-24 assume !(1 == ~t1_pc~0); 11052#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 11051#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11050#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11049#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11048#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11047#L384-24 assume 1 == ~t2_pc~0; 11045#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11044#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11043#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11042#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 11041#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11040#L403-24 assume 1 == ~t3_pc~0; 11038#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11037#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11036#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11035#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11034#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11033#L422-24 assume 1 == ~t4_pc~0; 11031#L423-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11030#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11029#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11028#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11027#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11026#L441-24 assume 1 == ~t5_pc~0; 11024#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11023#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11022#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11021#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11020#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11019#L460-24 assume !(1 == ~t6_pc~0); 11017#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 11016#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11015#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11014#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11013#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11012#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10902#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11011#L779-3 assume !(1 == ~T2_E~0); 11010#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11009#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11008#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11007#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11006#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10647#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11005#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11004#L819-3 assume !(1 == ~E_3~0); 11003#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11002#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11001#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11000#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 10998#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 10992#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 10991#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 10990#L1084 assume !(0 == start_simulation_~tmp~3#1); 10817#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 10483#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 10195#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 10762#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 10763#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10329#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10321#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 10322#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 10931#L1065-2 [2022-07-14 16:02:27,682 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:27,682 INFO L85 PathProgramCache]: Analyzing trace with hash -1050737979, now seen corresponding path program 1 times [2022-07-14 16:02:27,682 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:27,682 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1841472199] [2022-07-14 16:02:27,682 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:27,683 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:27,691 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:27,707 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:27,707 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:27,707 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1841472199] [2022-07-14 16:02:27,711 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1841472199] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:27,711 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:27,711 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:27,712 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1706062544] [2022-07-14 16:02:27,713 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:27,713 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:27,714 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:27,714 INFO L85 PathProgramCache]: Analyzing trace with hash 1530837245, now seen corresponding path program 1 times [2022-07-14 16:02:27,714 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:27,714 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1863434170] [2022-07-14 16:02:27,714 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:27,715 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:27,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:27,739 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:27,740 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:27,740 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1863434170] [2022-07-14 16:02:27,741 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1863434170] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:27,741 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:27,742 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:27,742 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1877407699] [2022-07-14 16:02:27,743 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:27,743 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:27,743 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:27,744 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:02:27,744 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:02:27,744 INFO L87 Difference]: Start difference. First operand 1179 states and 1755 transitions. cyclomatic complexity: 578 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:27,947 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:27,948 INFO L93 Difference]: Finished difference Result 3143 states and 4595 transitions. [2022-07-14 16:02:27,949 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:02:27,949 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3143 states and 4595 transitions. [2022-07-14 16:02:27,968 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2928 [2022-07-14 16:02:27,986 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3143 states to 3143 states and 4595 transitions. [2022-07-14 16:02:27,987 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3143 [2022-07-14 16:02:27,988 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3143 [2022-07-14 16:02:27,989 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3143 states and 4595 transitions. [2022-07-14 16:02:27,993 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:27,994 INFO L369 hiAutomatonCegarLoop]: Abstraction has 3143 states and 4595 transitions. [2022-07-14 16:02:27,996 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3143 states and 4595 transitions. [2022-07-14 16:02:28,032 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3143 to 2955. [2022-07-14 16:02:28,038 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2955 states, 2955 states have (on average 1.4683587140439933) internal successors, (4339), 2954 states have internal predecessors, (4339), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:28,046 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2955 states to 2955 states and 4339 transitions. [2022-07-14 16:02:28,047 INFO L392 hiAutomatonCegarLoop]: Abstraction has 2955 states and 4339 transitions. [2022-07-14 16:02:28,047 INFO L374 stractBuchiCegarLoop]: Abstraction has 2955 states and 4339 transitions. [2022-07-14 16:02:28,047 INFO L287 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-07-14 16:02:28,047 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2955 states and 4339 transitions. [2022-07-14 16:02:28,059 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2842 [2022-07-14 16:02:28,059 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:28,059 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:28,060 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:28,061 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:28,061 INFO L752 eck$LassoCheckResult]: Stem: 15455#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 15341#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 15270#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15173#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15174#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 14749#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14750#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14594#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14595#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14563#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14564#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14727#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14910#L696 assume !(0 == ~M_E~0); 14911#L696-2 assume !(0 == ~T1_E~0); 15307#L701-1 assume !(0 == ~T2_E~0); 15310#L706-1 assume !(0 == ~T3_E~0); 15044#L711-1 assume !(0 == ~T4_E~0); 14785#L716-1 assume !(0 == ~T5_E~0); 14786#L721-1 assume !(0 == ~T6_E~0); 14987#L726-1 assume !(0 == ~E_M~0); 14988#L731-1 assume !(0 == ~E_1~0); 14950#L736-1 assume !(0 == ~E_2~0); 14951#L741-1 assume !(0 == ~E_3~0); 15057#L746-1 assume !(0 == ~E_4~0); 14823#L751-1 assume !(0 == ~E_5~0); 14824#L756-1 assume !(0 == ~E_6~0); 14782#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14612#L346 assume !(1 == ~m_pc~0); 14613#L346-2 is_master_triggered_~__retres1~0#1 := 0; 14835#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14519#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 14520#L861 assume !(0 != activate_threads_~tmp~1#1); 15248#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14643#L365 assume !(1 == ~t1_pc~0); 14644#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 15269#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15271#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14634#L869 assume !(0 != activate_threads_~tmp___0~0#1); 14635#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15123#L384 assume !(1 == ~t2_pc~0); 15113#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15114#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14724#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14545#L877 assume !(0 != activate_threads_~tmp___1~0#1); 14546#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14928#L403 assume 1 == ~t3_pc~0; 14787#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14788#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14772#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14773#L885 assume !(0 != activate_threads_~tmp___2~0#1); 14918#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14919#L422 assume 1 == ~t4_pc~0; 14540#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14541#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15119#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15120#L893 assume !(0 != activate_threads_~tmp___3~0#1); 15019#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14565#L441 assume !(1 == ~t5_pc~0); 14566#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 15244#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15344#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15345#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15032#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15033#L460 assume 1 == ~t6_pc~0; 14503#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14504#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14573#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15191#L909 assume !(0 != activate_threads_~tmp___5~0#1); 15192#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14998#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 14999#L774-2 assume !(1 == ~T1_E~0); 17278#L779-1 assume !(1 == ~T2_E~0); 17277#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17276#L789-1 assume !(1 == ~T4_E~0); 17275#L794-1 assume !(1 == ~T5_E~0); 17274#L799-1 assume !(1 == ~T6_E~0); 17273#L804-1 assume !(1 == ~E_M~0); 15383#L809-1 assume !(1 == ~E_1~0); 17272#L814-1 assume !(1 == ~E_2~0); 17271#L819-1 assume !(1 == ~E_3~0); 17270#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 17269#L829-1 assume !(1 == ~E_5~0); 17268#L834-1 assume !(1 == ~E_6~0); 17245#L839-1 assume { :end_inline_reset_delta_events } true; 17244#L1065-2 [2022-07-14 16:02:28,061 INFO L754 eck$LassoCheckResult]: Loop: 17244#L1065-2 assume !false; 17239#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17236#L671 assume !false; 17235#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 15166#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 14605#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 15090#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 15091#L582 assume !(0 != eval_~tmp~0#1); 15389#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15390#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17072#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15365#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15366#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15449#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15450#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15308#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15309#L721-3 assume !(0 == ~T6_E~0); 14840#L726-3 assume !(0 == ~E_M~0); 14841#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15284#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15285#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14778#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14779#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15200#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15201#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14686#L346-24 assume !(1 == ~m_pc~0); 14687#L346-26 is_master_triggered_~__retres1~0#1 := 0; 15053#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15054#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15272#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15273#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14720#L365-24 assume !(1 == ~t1_pc~0); 14721#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 15431#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15432#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15153#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15154#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14671#L384-24 assume !(1 == ~t2_pc~0); 14672#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 15422#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15423#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15036#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 15037#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14826#L403-24 assume 1 == ~t3_pc~0; 14827#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14866#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14867#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14978#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14979#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14751#L422-24 assume !(1 == ~t4_pc~0); 14752#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 14706#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14707#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15313#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15314#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14765#L441-24 assume 1 == ~t5_pc~0; 14766#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15008#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15009#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14636#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14637#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15125#L460-24 assume !(1 == ~t6_pc~0); 15126#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 15463#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15464#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15242#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15243#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15418#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15419#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14838#L779-3 assume !(1 == ~T2_E~0); 14839#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15461#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15462#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14645#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14646#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 15005#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15292#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14906#L819-3 assume !(1 == ~E_3~0); 14907#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14776#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14777#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14626#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 14627#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 17261#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 17260#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 17259#L1084 assume !(0 == start_simulation_~tmp~3#1); 15235#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 17254#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 17251#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 17250#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 17249#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17248#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17247#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 17246#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 17244#L1065-2 [2022-07-14 16:02:28,062 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:28,062 INFO L85 PathProgramCache]: Analyzing trace with hash 1143388102, now seen corresponding path program 1 times [2022-07-14 16:02:28,062 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:28,062 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [45996792] [2022-07-14 16:02:28,063 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:28,063 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:28,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:28,091 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:28,091 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:28,091 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [45996792] [2022-07-14 16:02:28,092 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [45996792] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:28,092 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:28,092 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:28,092 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [881451110] [2022-07-14 16:02:28,092 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:28,093 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:28,093 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:28,093 INFO L85 PathProgramCache]: Analyzing trace with hash 2035255744, now seen corresponding path program 1 times [2022-07-14 16:02:28,093 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:28,093 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [589351014] [2022-07-14 16:02:28,094 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:28,094 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:28,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:28,135 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:28,136 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:28,136 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [589351014] [2022-07-14 16:02:28,136 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [589351014] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:28,136 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:28,136 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:28,136 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [590326743] [2022-07-14 16:02:28,137 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:28,137 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:28,137 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:28,137 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:02:28,138 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:02:28,138 INFO L87 Difference]: Start difference. First operand 2955 states and 4339 transitions. cyclomatic complexity: 1388 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:28,367 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:28,367 INFO L93 Difference]: Finished difference Result 8082 states and 11722 transitions. [2022-07-14 16:02:28,368 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:02:28,369 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8082 states and 11722 transitions. [2022-07-14 16:02:28,421 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7720 [2022-07-14 16:02:28,469 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8082 states to 8082 states and 11722 transitions. [2022-07-14 16:02:28,470 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8082 [2022-07-14 16:02:28,480 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8082 [2022-07-14 16:02:28,481 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8082 states and 11722 transitions. [2022-07-14 16:02:28,492 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:28,493 INFO L369 hiAutomatonCegarLoop]: Abstraction has 8082 states and 11722 transitions. [2022-07-14 16:02:28,498 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8082 states and 11722 transitions. [2022-07-14 16:02:28,610 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8082 to 7678. [2022-07-14 16:02:28,624 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7678 states, 7678 states have (on average 1.456629330554832) internal successors, (11184), 7677 states have internal predecessors, (11184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:28,652 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7678 states to 7678 states and 11184 transitions. [2022-07-14 16:02:28,652 INFO L392 hiAutomatonCegarLoop]: Abstraction has 7678 states and 11184 transitions. [2022-07-14 16:02:28,652 INFO L374 stractBuchiCegarLoop]: Abstraction has 7678 states and 11184 transitions. [2022-07-14 16:02:28,652 INFO L287 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-07-14 16:02:28,653 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7678 states and 11184 transitions. [2022-07-14 16:02:28,702 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7546 [2022-07-14 16:02:28,703 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:28,703 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:28,704 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:28,704 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:28,704 INFO L752 eck$LassoCheckResult]: Stem: 26348#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 26283#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 26223#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26150#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26151#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 25785#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25786#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25639#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25640#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25608#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25609#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 25764#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 25926#L696 assume !(0 == ~M_E~0); 25927#L696-2 assume !(0 == ~T1_E~0); 26254#L701-1 assume !(0 == ~T2_E~0); 26257#L706-1 assume !(0 == ~T3_E~0); 26046#L711-1 assume !(0 == ~T4_E~0); 25819#L716-1 assume !(0 == ~T5_E~0); 25820#L721-1 assume !(0 == ~T6_E~0); 25999#L726-1 assume !(0 == ~E_M~0); 26000#L731-1 assume !(0 == ~E_1~0); 25966#L736-1 assume !(0 == ~E_2~0); 25967#L741-1 assume !(0 == ~E_3~0); 26054#L746-1 assume !(0 == ~E_4~0); 25851#L751-1 assume !(0 == ~E_5~0); 25852#L756-1 assume !(0 == ~E_6~0); 25816#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25655#L346 assume !(1 == ~m_pc~0); 25656#L346-2 is_master_triggered_~__retres1~0#1 := 0; 25862#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25566#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 25567#L861 assume !(0 != activate_threads_~tmp~1#1); 26204#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25685#L365 assume !(1 == ~t1_pc~0); 25686#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 26222#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26224#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 25676#L869 assume !(0 != activate_threads_~tmp___0~0#1); 25677#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26110#L384 assume !(1 == ~t2_pc~0); 26100#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 26101#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25761#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 25590#L877 assume !(0 != activate_threads_~tmp___1~0#1); 25591#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25943#L403 assume !(1 == ~t3_pc~0); 25944#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 26145#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25807#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 25808#L885 assume !(0 != activate_threads_~tmp___2~0#1); 25934#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25935#L422 assume 1 == ~t4_pc~0; 25585#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25586#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26106#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26107#L893 assume !(0 != activate_threads_~tmp___3~0#1); 26029#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25610#L441 assume !(1 == ~t5_pc~0); 25611#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 26200#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26285#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26286#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26037#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26038#L460 assume 1 == ~t6_pc~0; 25550#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25551#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25618#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26162#L909 assume !(0 != activate_threads_~tmp___5~0#1); 26163#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26009#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 26010#L774-2 assume !(1 == ~T1_E~0); 32068#L779-1 assume !(1 == ~T2_E~0); 32067#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32066#L789-1 assume !(1 == ~T4_E~0); 32065#L794-1 assume !(1 == ~T5_E~0); 32064#L799-1 assume !(1 == ~T6_E~0); 32063#L804-1 assume !(1 == ~E_M~0); 26308#L809-1 assume !(1 == ~E_1~0); 32062#L814-1 assume !(1 == ~E_2~0); 32061#L819-1 assume !(1 == ~E_3~0); 32060#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 32059#L829-1 assume !(1 == ~E_5~0); 32058#L834-1 assume !(1 == ~E_6~0); 32045#L839-1 assume { :end_inline_reset_delta_events } true; 32038#L1065-2 [2022-07-14 16:02:28,705 INFO L754 eck$LassoCheckResult]: Loop: 32038#L1065-2 assume !false; 32039#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32005#L671 assume !false; 32006#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 31975#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 31968#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 31966#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 31962#L582 assume !(0 != eval_~tmp~0#1); 31964#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33011#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33010#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 33009#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33008#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 33007#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 33006#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33005#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 26058#L721-3 assume !(0 == ~T6_E~0); 25866#L726-3 assume !(0 == ~E_M~0); 25867#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26051#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 32397#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32396#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 32395#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32394#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 32393#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32392#L346-24 assume !(1 == ~m_pc~0); 32391#L346-26 is_master_triggered_~__retres1~0#1 := 0; 32390#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32389#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 26225#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 26177#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25758#L365-24 assume !(1 == ~t1_pc~0); 25759#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 32284#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32283#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 32282#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32281#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32280#L384-24 assume 1 == ~t2_pc~0; 32278#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32275#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32273#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 32271#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 32269#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32267#L403-24 assume !(1 == ~t3_pc~0); 32265#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 32264#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32262#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 32260#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 32258#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32256#L422-24 assume 1 == ~t4_pc~0; 32253#L423-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 32252#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32251#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 32250#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32249#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32248#L441-24 assume 1 == ~t5_pc~0; 32246#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 32245#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32244#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 32243#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 32242#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32240#L460-24 assume !(1 == ~t6_pc~0); 32237#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 32235#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32233#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32231#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 32228#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32226#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 26326#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32221#L779-3 assume !(1 == ~T2_E~0); 32218#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32215#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 32212#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 32208#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 32205#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 26015#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32202#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 32200#L819-3 assume !(1 == ~E_3~0); 32198#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 32196#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32194#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32192#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 32187#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 32180#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 32177#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 32174#L1084 assume !(0 == start_simulation_~tmp~3#1); 26196#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 32172#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 32471#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 32470#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 32469#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 32468#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 32467#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 32466#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 32038#L1065-2 [2022-07-14 16:02:28,705 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:28,705 INFO L85 PathProgramCache]: Analyzing trace with hash 186459719, now seen corresponding path program 1 times [2022-07-14 16:02:28,706 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:28,706 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1415088818] [2022-07-14 16:02:28,706 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:28,706 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:28,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:28,745 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:28,745 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:28,745 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1415088818] [2022-07-14 16:02:28,745 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1415088818] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:28,746 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:28,746 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-14 16:02:28,746 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [620263924] [2022-07-14 16:02:28,746 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:28,747 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:28,747 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:28,748 INFO L85 PathProgramCache]: Analyzing trace with hash 567624895, now seen corresponding path program 1 times [2022-07-14 16:02:28,748 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:28,748 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1079088862] [2022-07-14 16:02:28,748 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:28,748 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:28,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:28,774 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:28,775 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:28,775 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1079088862] [2022-07-14 16:02:28,775 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1079088862] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:28,775 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:28,775 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:28,775 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [705123713] [2022-07-14 16:02:28,776 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:28,776 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:28,776 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:28,777 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:02:28,777 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:02:28,777 INFO L87 Difference]: Start difference. First operand 7678 states and 11184 transitions. cyclomatic complexity: 3514 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:28,883 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:28,884 INFO L93 Difference]: Finished difference Result 14259 states and 20702 transitions. [2022-07-14 16:02:28,884 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:02:28,885 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14259 states and 20702 transitions. [2022-07-14 16:02:29,042 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14062 [2022-07-14 16:02:29,138 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14259 states to 14259 states and 20702 transitions. [2022-07-14 16:02:29,138 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14259 [2022-07-14 16:02:29,154 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14259 [2022-07-14 16:02:29,155 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14259 states and 20702 transitions. [2022-07-14 16:02:29,173 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:29,173 INFO L369 hiAutomatonCegarLoop]: Abstraction has 14259 states and 20702 transitions. [2022-07-14 16:02:29,183 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14259 states and 20702 transitions. [2022-07-14 16:02:29,374 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14259 to 14223. [2022-07-14 16:02:29,408 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14223 states, 14223 states have (on average 1.452998664135555) internal successors, (20666), 14222 states have internal predecessors, (20666), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:29,511 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14223 states to 14223 states and 20666 transitions. [2022-07-14 16:02:29,511 INFO L392 hiAutomatonCegarLoop]: Abstraction has 14223 states and 20666 transitions. [2022-07-14 16:02:29,511 INFO L374 stractBuchiCegarLoop]: Abstraction has 14223 states and 20666 transitions. [2022-07-14 16:02:29,511 INFO L287 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-07-14 16:02:29,511 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14223 states and 20666 transitions. [2022-07-14 16:02:29,615 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14026 [2022-07-14 16:02:29,616 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:29,616 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:29,617 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:29,617 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:29,618 INFO L752 eck$LassoCheckResult]: Stem: 48330#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 48256#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 48204#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 48118#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 48119#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 47729#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 47730#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 47579#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 47580#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47548#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 47549#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 47707#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 47879#L696 assume !(0 == ~M_E~0); 47880#L696-2 assume !(0 == ~T1_E~0); 48228#L701-1 assume !(0 == ~T2_E~0); 48230#L706-1 assume !(0 == ~T3_E~0); 48008#L711-1 assume !(0 == ~T4_E~0); 47761#L716-1 assume !(0 == ~T5_E~0); 47762#L721-1 assume !(0 == ~T6_E~0); 47953#L726-1 assume !(0 == ~E_M~0); 47954#L731-1 assume !(0 == ~E_1~0); 47920#L736-1 assume !(0 == ~E_2~0); 47921#L741-1 assume !(0 == ~E_3~0); 48014#L746-1 assume !(0 == ~E_4~0); 47793#L751-1 assume !(0 == ~E_5~0); 47794#L756-1 assume !(0 == ~E_6~0); 47758#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47595#L346 assume !(1 == ~m_pc~0); 47596#L346-2 is_master_triggered_~__retres1~0#1 := 0; 47805#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47510#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 47511#L861 assume !(0 != activate_threads_~tmp~1#1); 48181#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47625#L365 assume !(1 == ~t1_pc~0); 47626#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 48202#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48205#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 47616#L869 assume !(0 != activate_threads_~tmp___0~0#1); 47617#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 48072#L384 assume !(1 == ~t2_pc~0); 48063#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 48064#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47704#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 47531#L877 assume !(0 != activate_threads_~tmp___1~0#1); 47532#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47897#L403 assume !(1 == ~t3_pc~0); 47898#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 48113#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47749#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 47750#L885 assume !(0 != activate_threads_~tmp___2~0#1); 47888#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47889#L422 assume !(1 == ~t4_pc~0); 48031#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 48032#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48068#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 48069#L893 assume !(0 != activate_threads_~tmp___3~0#1); 47991#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47550#L441 assume !(1 == ~t5_pc~0); 47551#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 48176#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 48258#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 48259#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 48000#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 48001#L460 assume 1 == ~t6_pc~0; 47494#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 47495#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47558#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 48130#L909 assume !(0 != activate_threads_~tmp___5~0#1); 48131#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47969#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 47970#L774-2 assume !(1 == ~T1_E~0); 48150#L779-1 assume !(1 == ~T2_E~0); 47853#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 47854#L789-1 assume !(1 == ~T4_E~0); 47610#L794-1 assume !(1 == ~T5_E~0); 47611#L799-1 assume !(1 == ~T6_E~0); 48320#L804-1 assume !(1 == ~E_M~0); 48286#L809-1 assume !(1 == ~E_1~0); 54248#L814-1 assume !(1 == ~E_2~0); 47512#L819-1 assume !(1 == ~E_3~0); 47513#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 48024#L829-1 assume !(1 == ~E_5~0); 48138#L834-1 assume !(1 == ~E_6~0); 47742#L839-1 assume { :end_inline_reset_delta_events } true; 47733#L1065-2 [2022-07-14 16:02:29,618 INFO L754 eck$LassoCheckResult]: Loop: 47733#L1065-2 assume !false; 47734#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 47783#L671 assume !false; 48193#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 48114#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 47588#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 47597#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 48045#L582 assume !(0 != eval_~tmp~0#1); 48339#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 61610#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 61609#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 61608#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 61607#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 61606#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 48242#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 48229#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 48017#L721-3 assume !(0 == ~T6_E~0); 47811#L726-3 assume !(0 == ~E_M~0); 47812#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 48011#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 48012#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 47755#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 47756#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 47893#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 47636#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47637#L346-24 assume !(1 == ~m_pc~0); 47669#L346-26 is_master_triggered_~__retres1~0#1 := 0; 47748#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48013#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 48206#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 48207#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47701#L365-24 assume !(1 == ~t1_pc~0); 47702#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 48313#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47877#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 47878#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 48101#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47652#L384-24 assume !(1 == ~t2_pc~0); 47653#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 47673#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48210#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 48003#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 47679#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47680#L403-24 assume !(1 == ~t3_pc~0); 47797#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 47835#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47836#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 47943#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 47944#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47731#L422-24 assume !(1 == ~t4_pc~0); 47732#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 61272#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 61271#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 61270#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 61269#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 61268#L441-24 assume 1 == ~t5_pc~0; 61266#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 61265#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 61264#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 61263#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 61262#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 61261#L460-24 assume 1 == ~t6_pc~0; 48274#L461-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 48152#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 61258#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 48175#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 48065#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48066#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 55032#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 61253#L779-3 assume !(1 == ~T2_E~0); 47529#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 47530#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 61249#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 47627#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 47628#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 55019#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 61244#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 47875#L819-3 assume !(1 == ~E_3~0); 47876#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 61240#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 61238#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 61235#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 48161#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 47606#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 47955#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 47956#L1084 assume !(0 == start_simulation_~tmp~3#1); 61185#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 61178#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 61173#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 61171#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 61169#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 61166#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 47634#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 47635#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 47733#L1065-2 [2022-07-14 16:02:29,618 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:29,618 INFO L85 PathProgramCache]: Analyzing trace with hash -1390098040, now seen corresponding path program 1 times [2022-07-14 16:02:29,619 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:29,619 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1863116947] [2022-07-14 16:02:29,619 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:29,619 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:29,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:29,670 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:29,670 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:29,670 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1863116947] [2022-07-14 16:02:29,670 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1863116947] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:29,670 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:29,671 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:02:29,671 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1579105268] [2022-07-14 16:02:29,671 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:29,671 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:29,672 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:29,672 INFO L85 PathProgramCache]: Analyzing trace with hash 1510972288, now seen corresponding path program 1 times [2022-07-14 16:02:29,672 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:29,672 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1186794227] [2022-07-14 16:02:29,672 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:29,672 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:29,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:29,703 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:29,703 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:29,704 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1186794227] [2022-07-14 16:02:29,704 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1186794227] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:29,704 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:29,704 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:29,704 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [72976942] [2022-07-14 16:02:29,704 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:29,704 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:29,705 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:29,705 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-07-14 16:02:29,705 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-07-14 16:02:29,706 INFO L87 Difference]: Start difference. First operand 14223 states and 20666 transitions. cyclomatic complexity: 6459 Second operand has 5 states, 5 states have (on average 16.8) internal successors, (84), 5 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:30,117 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:30,117 INFO L93 Difference]: Finished difference Result 34082 states and 49999 transitions. [2022-07-14 16:02:30,117 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-07-14 16:02:30,118 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34082 states and 49999 transitions. [2022-07-14 16:02:30,288 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 33628 [2022-07-14 16:02:30,528 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34082 states to 34082 states and 49999 transitions. [2022-07-14 16:02:30,528 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 34082 [2022-07-14 16:02:30,562 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 34082 [2022-07-14 16:02:30,563 INFO L73 IsDeterministic]: Start isDeterministic. Operand 34082 states and 49999 transitions. [2022-07-14 16:02:30,596 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:30,596 INFO L369 hiAutomatonCegarLoop]: Abstraction has 34082 states and 49999 transitions. [2022-07-14 16:02:30,617 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34082 states and 49999 transitions. [2022-07-14 16:02:30,924 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34082 to 14832. [2022-07-14 16:02:30,946 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14832 states, 14832 states have (on average 1.434398597626753) internal successors, (21275), 14831 states have internal predecessors, (21275), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:31,067 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14832 states to 14832 states and 21275 transitions. [2022-07-14 16:02:31,069 INFO L392 hiAutomatonCegarLoop]: Abstraction has 14832 states and 21275 transitions. [2022-07-14 16:02:31,070 INFO L374 stractBuchiCegarLoop]: Abstraction has 14832 states and 21275 transitions. [2022-07-14 16:02:31,070 INFO L287 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-07-14 16:02:31,083 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14832 states and 21275 transitions. [2022-07-14 16:02:31,158 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14632 [2022-07-14 16:02:31,183 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:31,183 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:31,184 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:31,185 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:31,185 INFO L752 eck$LassoCheckResult]: Stem: 96625#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 96549#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 96490#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 96410#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 96411#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 96042#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 96043#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 95898#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 95899#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 95865#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 95866#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 96021#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 96183#L696 assume !(0 == ~M_E~0); 96184#L696-2 assume !(0 == ~T1_E~0); 96521#L701-1 assume !(0 == ~T2_E~0); 96522#L706-1 assume !(0 == ~T3_E~0); 96305#L711-1 assume !(0 == ~T4_E~0); 96075#L716-1 assume !(0 == ~T5_E~0); 96076#L721-1 assume !(0 == ~T6_E~0); 96256#L726-1 assume !(0 == ~E_M~0); 96257#L731-1 assume !(0 == ~E_1~0); 96221#L736-1 assume !(0 == ~E_2~0); 96222#L741-1 assume !(0 == ~E_3~0); 96313#L746-1 assume !(0 == ~E_4~0); 96109#L751-1 assume !(0 == ~E_5~0); 96110#L756-1 assume !(0 == ~E_6~0); 96072#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 95912#L346 assume !(1 == ~m_pc~0); 95913#L346-2 is_master_triggered_~__retres1~0#1 := 0; 96122#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 95829#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 95830#L861 assume !(0 != activate_threads_~tmp~1#1); 96471#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 95943#L365 assume !(1 == ~t1_pc~0); 95944#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 96489#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 96494#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 95933#L869 assume !(0 != activate_threads_~tmp___0~0#1); 95934#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 96372#L384 assume !(1 == ~t2_pc~0); 96364#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 96365#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 96020#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 95850#L877 assume !(0 != activate_threads_~tmp___1~0#1); 95851#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 96200#L403 assume !(1 == ~t3_pc~0); 96201#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 96405#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 96067#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 96068#L885 assume !(0 != activate_threads_~tmp___2~0#1); 96192#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 96193#L422 assume !(1 == ~t4_pc~0); 96331#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 96332#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 96370#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 96371#L893 assume !(0 != activate_threads_~tmp___3~0#1); 96287#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 95867#L441 assume !(1 == ~t5_pc~0); 95868#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 96466#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 96597#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 96639#L901 assume !(0 != activate_threads_~tmp___4~0#1); 96297#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 96298#L460 assume 1 == ~t6_pc~0; 95814#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 95815#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 95877#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 96420#L909 assume !(0 != activate_threads_~tmp___5~0#1); 96421#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 96267#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 96268#L774-2 assume !(1 == ~T1_E~0); 96446#L779-1 assume !(1 == ~T2_E~0); 96447#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 96571#L789-1 assume !(1 == ~T4_E~0); 96572#L794-1 assume !(1 == ~T5_E~0); 96616#L799-1 assume !(1 == ~T6_E~0); 96617#L804-1 assume !(1 == ~E_M~0); 96578#L809-1 assume !(1 == ~E_1~0); 96613#L814-1 assume !(1 == ~E_2~0); 95831#L819-1 assume !(1 == ~E_3~0); 95832#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 96610#L829-1 assume !(1 == ~E_5~0); 96611#L834-1 assume !(1 == ~E_6~0); 96058#L839-1 assume { :end_inline_reset_delta_events } true; 96059#L1065-2 [2022-07-14 16:02:31,185 INFO L754 eck$LassoCheckResult]: Loop: 96059#L1065-2 assume !false; 99682#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 99675#L671 assume !false; 99672#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 99666#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 99657#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 99653#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 99645#L582 assume !(0 != eval_~tmp~0#1); 99646#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 108108#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 108107#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 108106#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 108105#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 108104#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 108103#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 108102#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 108101#L721-3 assume !(0 == ~T6_E~0); 108100#L726-3 assume !(0 == ~E_M~0); 108099#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 108098#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 108097#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 108096#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 108095#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 108094#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 108093#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 100206#L346-24 assume !(1 == ~m_pc~0); 100207#L346-26 is_master_triggered_~__retres1~0#1 := 0; 100202#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 100203#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 100198#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 100199#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 100194#L365-24 assume !(1 == ~t1_pc~0); 100195#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 100190#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 100191#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 100186#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 100187#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 100181#L384-24 assume 1 == ~t2_pc~0; 100183#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 100176#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 100177#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 100172#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 100173#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 100168#L403-24 assume !(1 == ~t3_pc~0); 100169#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 100164#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 100165#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 100160#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 100161#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 100156#L422-24 assume !(1 == ~t4_pc~0); 100157#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 100152#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 100153#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 100148#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 100149#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 100143#L441-24 assume !(1 == ~t5_pc~0); 100145#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 100137#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 100138#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 100130#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 100128#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 100125#L460-24 assume !(1 == ~t6_pc~0); 100121#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 100118#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 100115#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 100112#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 100109#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 100106#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 100103#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 100100#L779-3 assume !(1 == ~T2_E~0); 100097#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 100094#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 100091#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 100088#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 100084#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 100080#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 100075#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 100070#L819-3 assume !(1 == ~E_3~0); 100065#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 100060#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 100016#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 100012#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 99958#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 99947#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 99941#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 99935#L1084 assume !(0 == start_simulation_~tmp~3#1); 99929#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 99770#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 99761#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 99756#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 99751#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 99746#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 99739#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 99694#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 96059#L1065-2 [2022-07-14 16:02:31,186 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:31,186 INFO L85 PathProgramCache]: Analyzing trace with hash 1099430922, now seen corresponding path program 1 times [2022-07-14 16:02:31,186 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:31,186 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1800476959] [2022-07-14 16:02:31,186 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:31,186 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:31,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:31,246 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:31,247 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:31,247 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1800476959] [2022-07-14 16:02:31,247 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1800476959] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:31,247 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:31,247 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:31,248 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1520987523] [2022-07-14 16:02:31,248 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:31,248 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:31,248 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:31,248 INFO L85 PathProgramCache]: Analyzing trace with hash -2106786685, now seen corresponding path program 1 times [2022-07-14 16:02:31,249 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:31,249 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [115549990] [2022-07-14 16:02:31,249 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:31,249 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:31,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:31,303 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:31,304 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:31,304 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [115549990] [2022-07-14 16:02:31,304 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [115549990] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:31,304 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:31,304 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:31,304 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1007759505] [2022-07-14 16:02:31,304 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:31,305 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:31,305 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:31,305 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:02:31,305 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:02:31,306 INFO L87 Difference]: Start difference. First operand 14832 states and 21275 transitions. cyclomatic complexity: 6459 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:31,717 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:31,717 INFO L93 Difference]: Finished difference Result 41853 states and 59428 transitions. [2022-07-14 16:02:31,718 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:02:31,719 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41853 states and 59428 transitions. [2022-07-14 16:02:32,091 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 40462 [2022-07-14 16:02:32,298 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41853 states to 41853 states and 59428 transitions. [2022-07-14 16:02:32,299 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41853 [2022-07-14 16:02:32,336 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41853 [2022-07-14 16:02:32,336 INFO L73 IsDeterministic]: Start isDeterministic. Operand 41853 states and 59428 transitions. [2022-07-14 16:02:32,379 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:32,380 INFO L369 hiAutomatonCegarLoop]: Abstraction has 41853 states and 59428 transitions. [2022-07-14 16:02:32,409 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41853 states and 59428 transitions. [2022-07-14 16:02:32,844 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41853 to 40669. [2022-07-14 16:02:32,904 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40669 states, 40669 states have (on average 1.4247215323710936) internal successors, (57942), 40668 states have internal predecessors, (57942), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:33,012 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40669 states to 40669 states and 57942 transitions. [2022-07-14 16:02:33,012 INFO L392 hiAutomatonCegarLoop]: Abstraction has 40669 states and 57942 transitions. [2022-07-14 16:02:33,013 INFO L374 stractBuchiCegarLoop]: Abstraction has 40669 states and 57942 transitions. [2022-07-14 16:02:33,013 INFO L287 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-07-14 16:02:33,013 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40669 states and 57942 transitions. [2022-07-14 16:02:33,302 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 40318 [2022-07-14 16:02:33,302 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:33,303 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:33,304 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:33,304 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:33,304 INFO L752 eck$LassoCheckResult]: Stem: 153361#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 153271#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 153224#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 153139#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 153140#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 152739#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 152740#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 152591#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 152592#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 152559#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 152560#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 152718#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 152892#L696 assume !(0 == ~M_E~0); 152893#L696-2 assume !(0 == ~T1_E~0); 153247#L701-1 assume !(0 == ~T2_E~0); 153248#L706-1 assume !(0 == ~T3_E~0); 153018#L711-1 assume !(0 == ~T4_E~0); 152773#L716-1 assume !(0 == ~T5_E~0); 152774#L721-1 assume !(0 == ~T6_E~0); 152964#L726-1 assume !(0 == ~E_M~0); 152965#L731-1 assume !(0 == ~E_1~0); 152930#L736-1 assume !(0 == ~E_2~0); 152931#L741-1 assume !(0 == ~E_3~0); 153025#L746-1 assume !(0 == ~E_4~0); 152807#L751-1 assume !(0 == ~E_5~0); 152808#L756-1 assume !(0 == ~E_6~0); 152770#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 152605#L346 assume !(1 == ~m_pc~0); 152606#L346-2 is_master_triggered_~__retres1~0#1 := 0; 152821#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 152522#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 152523#L861 assume !(0 != activate_threads_~tmp~1#1); 153203#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 152638#L365 assume !(1 == ~t1_pc~0); 152639#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 153223#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 153228#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 152628#L869 assume !(0 != activate_threads_~tmp___0~0#1); 152629#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 153091#L384 assume !(1 == ~t2_pc~0); 153083#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 153084#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 152717#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 152543#L877 assume !(0 != activate_threads_~tmp___1~0#1); 152544#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 152910#L403 assume !(1 == ~t3_pc~0); 152911#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 153134#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 152765#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 152766#L885 assume !(0 != activate_threads_~tmp___2~0#1); 152898#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 152899#L422 assume !(1 == ~t4_pc~0); 153043#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 153044#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 153089#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 153090#L893 assume !(0 != activate_threads_~tmp___3~0#1); 152999#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 152561#L441 assume !(1 == ~t5_pc~0); 152562#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 153196#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 153273#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 153274#L901 assume !(0 != activate_threads_~tmp___4~0#1); 153009#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 153010#L460 assume !(1 == ~t6_pc~0); 153159#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 152570#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 152571#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 153154#L909 assume !(0 != activate_threads_~tmp___5~0#1); 153155#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 152978#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 152979#L774-2 assume !(1 == ~T1_E~0); 153306#L779-1 assume !(1 == ~T2_E~0); 152868#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 152869#L789-1 assume !(1 == ~T4_E~0); 152620#L794-1 assume !(1 == ~T5_E~0); 152621#L799-1 assume !(1 == ~T6_E~0); 153314#L804-1 assume !(1 == ~E_M~0); 153315#L809-1 assume !(1 == ~E_1~0); 152959#L814-1 assume !(1 == ~E_2~0); 152960#L819-1 assume !(1 == ~E_3~0); 153035#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 153036#L829-1 assume !(1 == ~E_5~0); 153162#L834-1 assume !(1 == ~E_6~0); 153163#L839-1 assume { :end_inline_reset_delta_events } true; 158281#L1065-2 [2022-07-14 16:02:33,305 INFO L754 eck$LassoCheckResult]: Loop: 158281#L1065-2 assume !false; 183488#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 183485#L671 assume !false; 183484#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 183482#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 183476#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 183475#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 183473#L582 assume !(0 != eval_~tmp~0#1); 183474#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 183588#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 183587#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 183586#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 183585#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 183584#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 183583#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 183582#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 183581#L721-3 assume !(0 == ~T6_E~0); 183580#L726-3 assume !(0 == ~E_M~0); 183579#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 183578#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 183577#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 183576#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 183575#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 183574#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 183573#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 183572#L346-24 assume !(1 == ~m_pc~0); 183571#L346-26 is_master_triggered_~__retres1~0#1 := 0; 183570#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 183569#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 183568#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 183567#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 183566#L365-24 assume !(1 == ~t1_pc~0); 183565#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 183564#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 183563#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 183562#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 183561#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 183560#L384-24 assume 1 == ~t2_pc~0; 183558#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 183557#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 183556#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 183555#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 183554#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 183553#L403-24 assume !(1 == ~t3_pc~0); 183552#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 183551#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 183550#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 183549#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 183548#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 183547#L422-24 assume !(1 == ~t4_pc~0); 183546#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 183545#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 183544#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 183543#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 183542#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 183541#L441-24 assume !(1 == ~t5_pc~0); 183538#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 183537#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 183536#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 183535#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 183533#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 183532#L460-24 assume !(1 == ~t6_pc~0); 183531#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 183530#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 183529#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 183528#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 183527#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 183526#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 173459#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 183525#L779-3 assume !(1 == ~T2_E~0); 183524#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 183523#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 183522#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 183521#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 183520#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 173406#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 183519#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 183518#L819-3 assume !(1 == ~E_3~0); 183517#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 183516#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 183515#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 183514#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 183512#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 183506#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 183505#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 183504#L1084 assume !(0 == start_simulation_~tmp~3#1); 183502#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 183497#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 183494#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 183493#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 183492#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 183491#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 183490#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 183489#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 158281#L1065-2 [2022-07-14 16:02:33,305 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:33,306 INFO L85 PathProgramCache]: Analyzing trace with hash 125941963, now seen corresponding path program 1 times [2022-07-14 16:02:33,306 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:33,306 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1088476468] [2022-07-14 16:02:33,306 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:33,306 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:33,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:33,335 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:33,335 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:33,336 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1088476468] [2022-07-14 16:02:33,336 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1088476468] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:33,336 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:33,336 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-14 16:02:33,336 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1582106606] [2022-07-14 16:02:33,336 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:33,337 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:33,338 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:33,338 INFO L85 PathProgramCache]: Analyzing trace with hash -2106786685, now seen corresponding path program 2 times [2022-07-14 16:02:33,338 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:33,338 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [760140685] [2022-07-14 16:02:33,338 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:33,339 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:33,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:33,363 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:33,364 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:33,364 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [760140685] [2022-07-14 16:02:33,364 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [760140685] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:33,364 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:33,364 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:33,364 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1846283121] [2022-07-14 16:02:33,365 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:33,365 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:33,365 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:33,366 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:02:33,366 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:02:33,366 INFO L87 Difference]: Start difference. First operand 40669 states and 57942 transitions. cyclomatic complexity: 17305 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:33,748 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:33,748 INFO L93 Difference]: Finished difference Result 60416 states and 86233 transitions. [2022-07-14 16:02:33,748 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:02:33,750 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 60416 states and 86233 transitions. [2022-07-14 16:02:34,036 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 59948 [2022-07-14 16:02:34,487 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 60416 states to 60416 states and 86233 transitions. [2022-07-14 16:02:34,488 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 60416 [2022-07-14 16:02:34,532 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 60416 [2022-07-14 16:02:34,533 INFO L73 IsDeterministic]: Start isDeterministic. Operand 60416 states and 86233 transitions. [2022-07-14 16:02:34,585 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:34,585 INFO L369 hiAutomatonCegarLoop]: Abstraction has 60416 states and 86233 transitions. [2022-07-14 16:02:34,627 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60416 states and 86233 transitions. [2022-07-14 16:02:35,129 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60416 to 42340. [2022-07-14 16:02:35,323 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42340 states, 42340 states have (on average 1.4298299480396788) internal successors, (60539), 42339 states have internal predecessors, (60539), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:35,449 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42340 states to 42340 states and 60539 transitions. [2022-07-14 16:02:35,450 INFO L392 hiAutomatonCegarLoop]: Abstraction has 42340 states and 60539 transitions. [2022-07-14 16:02:35,451 INFO L374 stractBuchiCegarLoop]: Abstraction has 42340 states and 60539 transitions. [2022-07-14 16:02:35,451 INFO L287 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-07-14 16:02:35,451 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42340 states and 60539 transitions. [2022-07-14 16:02:35,601 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 42003 [2022-07-14 16:02:35,601 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:35,601 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:35,603 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:35,603 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:35,603 INFO L752 eck$LassoCheckResult]: Stem: 254421#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 254349#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 254294#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 254208#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 254209#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 253829#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 253830#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 253682#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 253683#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 253651#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 253652#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 253808#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 253971#L696 assume !(0 == ~M_E~0); 253972#L696-2 assume !(0 == ~T1_E~0); 254324#L701-1 assume !(0 == ~T2_E~0); 254326#L706-1 assume !(0 == ~T3_E~0); 254093#L711-1 assume !(0 == ~T4_E~0); 253863#L716-1 assume !(0 == ~T5_E~0); 253864#L721-1 assume !(0 == ~T6_E~0); 254043#L726-1 assume !(0 == ~E_M~0); 254044#L731-1 assume !(0 == ~E_1~0); 254009#L736-1 assume !(0 == ~E_2~0); 254010#L741-1 assume !(0 == ~E_3~0); 254099#L746-1 assume !(0 == ~E_4~0); 253896#L751-1 assume !(0 == ~E_5~0); 253897#L756-1 assume !(0 == ~E_6~0); 253860#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 253697#L346 assume !(1 == ~m_pc~0); 253698#L346-2 is_master_triggered_~__retres1~0#1 := 0; 253909#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 253612#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 253613#L861 assume !(0 != activate_threads_~tmp~1#1); 254271#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 253727#L365 assume !(1 == ~t1_pc~0); 253728#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 254293#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 254295#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 253718#L869 assume !(0 != activate_threads_~tmp___0~0#1); 253719#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 254159#L384 assume !(1 == ~t2_pc~0); 254149#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 254150#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 253805#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 253633#L877 assume !(0 != activate_threads_~tmp___1~0#1); 253634#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 253988#L403 assume !(1 == ~t3_pc~0); 253989#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 254202#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 253850#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 253851#L885 assume !(0 != activate_threads_~tmp___2~0#1); 253979#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 253980#L422 assume !(1 == ~t4_pc~0); 254114#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 254115#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 254155#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 254156#L893 assume !(0 != activate_threads_~tmp___3~0#1); 254074#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 253653#L441 assume !(1 == ~t5_pc~0); 253654#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 254263#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 254351#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 254352#L901 assume !(0 != activate_threads_~tmp___4~0#1); 254084#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 254085#L460 assume !(1 == ~t6_pc~0); 254228#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 253660#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 253661#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 254223#L909 assume !(0 != activate_threads_~tmp___5~0#1); 254224#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 254055#L774 assume !(1 == ~M_E~0); 254056#L774-2 assume !(1 == ~T1_E~0); 254242#L779-1 assume !(1 == ~T2_E~0); 253952#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 253953#L789-1 assume !(1 == ~T4_E~0); 253712#L794-1 assume !(1 == ~T5_E~0); 253713#L799-1 assume !(1 == ~T6_E~0); 254372#L804-1 assume !(1 == ~E_M~0); 254373#L809-1 assume !(1 == ~E_1~0); 254039#L814-1 assume !(1 == ~E_2~0); 253614#L819-1 assume !(1 == ~E_3~0); 253615#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 254109#L829-1 assume !(1 == ~E_5~0); 254232#L834-1 assume !(1 == ~E_6~0); 253842#L839-1 assume { :end_inline_reset_delta_events } true; 253843#L1065-2 [2022-07-14 16:02:35,604 INFO L754 eck$LassoCheckResult]: Loop: 253843#L1065-2 assume !false; 279684#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 274117#L671 assume !false; 279681#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 279676#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 279669#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 279667#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 279664#L582 assume !(0 != eval_~tmp~0#1); 279665#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 280081#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 280080#L696-3 assume !(0 == ~M_E~0); 280079#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 280078#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 280077#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 280076#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 280075#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 280074#L721-3 assume !(0 == ~T6_E~0); 280073#L726-3 assume !(0 == ~E_M~0); 280072#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 280071#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 280069#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 280067#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 280065#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 280063#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 280061#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 280059#L346-24 assume !(1 == ~m_pc~0); 280057#L346-26 is_master_triggered_~__retres1~0#1 := 0; 280056#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 280054#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 280052#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 280050#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 280048#L365-24 assume !(1 == ~t1_pc~0); 280046#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 280043#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 280041#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 280039#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 280037#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 280035#L384-24 assume 1 == ~t2_pc~0; 280032#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 280030#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 280028#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 280026#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 280024#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 280022#L403-24 assume !(1 == ~t3_pc~0); 280020#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 280018#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 280016#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 280014#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 280012#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 280010#L422-24 assume !(1 == ~t4_pc~0); 261104#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 261103#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 261102#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 261101#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 261100#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 261099#L441-24 assume !(1 == ~t5_pc~0); 261098#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 261096#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 261094#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 261092#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 261090#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 261089#L460-24 assume !(1 == ~t6_pc~0); 261088#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 261087#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 261086#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 261085#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 261084#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 261083#L774-3 assume !(1 == ~M_E~0); 260326#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 261082#L779-3 assume !(1 == ~T2_E~0); 261081#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 261080#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 261079#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 261078#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 261077#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 261076#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 261075#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 261074#L819-3 assume !(1 == ~E_3~0); 261073#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 261072#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 261071#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 261070#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 261068#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 261062#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 261061#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 260416#L1084 assume !(0 == start_simulation_~tmp~3#1); 260417#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 279702#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 279698#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 279696#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 279694#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 279692#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 279690#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 279688#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 253843#L1065-2 [2022-07-14 16:02:35,604 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:35,605 INFO L85 PathProgramCache]: Analyzing trace with hash -1153921715, now seen corresponding path program 1 times [2022-07-14 16:02:35,605 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:35,605 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2069555791] [2022-07-14 16:02:35,605 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:35,605 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:35,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:35,638 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:35,638 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:35,638 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2069555791] [2022-07-14 16:02:35,639 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2069555791] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:35,639 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:35,639 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:35,639 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [292914885] [2022-07-14 16:02:35,639 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:35,641 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:35,642 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:35,642 INFO L85 PathProgramCache]: Analyzing trace with hash -2062689597, now seen corresponding path program 1 times [2022-07-14 16:02:35,642 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:35,642 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1280852218] [2022-07-14 16:02:35,642 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:35,642 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:35,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:35,667 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:35,667 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:35,668 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1280852218] [2022-07-14 16:02:35,668 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1280852218] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:35,668 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:35,668 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:35,668 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [234547898] [2022-07-14 16:02:35,669 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:35,669 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:35,670 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:35,670 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:02:35,670 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:02:35,671 INFO L87 Difference]: Start difference. First operand 42340 states and 60539 transitions. cyclomatic complexity: 18215 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:35,943 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:35,944 INFO L93 Difference]: Finished difference Result 68301 states and 97092 transitions. [2022-07-14 16:02:35,944 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:02:35,945 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 68301 states and 97092 transitions. [2022-07-14 16:02:36,575 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 67767 [2022-07-14 16:02:36,848 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 68301 states to 68301 states and 97092 transitions. [2022-07-14 16:02:36,848 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 68301 [2022-07-14 16:02:36,902 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 68301 [2022-07-14 16:02:36,903 INFO L73 IsDeterministic]: Start isDeterministic. Operand 68301 states and 97092 transitions. [2022-07-14 16:02:36,966 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:36,967 INFO L369 hiAutomatonCegarLoop]: Abstraction has 68301 states and 97092 transitions. [2022-07-14 16:02:37,014 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68301 states and 97092 transitions. [2022-07-14 16:02:37,676 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68301 to 49292. [2022-07-14 16:02:37,727 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49292 states, 49292 states have (on average 1.4246328004544349) internal successors, (70223), 49291 states have internal predecessors, (70223), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:37,833 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49292 states to 49292 states and 70223 transitions. [2022-07-14 16:02:37,834 INFO L392 hiAutomatonCegarLoop]: Abstraction has 49292 states and 70223 transitions. [2022-07-14 16:02:37,834 INFO L374 stractBuchiCegarLoop]: Abstraction has 49292 states and 70223 transitions. [2022-07-14 16:02:37,834 INFO L287 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-07-14 16:02:37,834 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49292 states and 70223 transitions. [2022-07-14 16:02:37,983 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 48893 [2022-07-14 16:02:37,983 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:37,984 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:37,985 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:37,985 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:37,985 INFO L752 eck$LassoCheckResult]: Stem: 365086#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 365006#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 364940#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 364862#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 364863#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 364477#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 364478#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 364331#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 364332#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 364300#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 364301#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 364456#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 364627#L696 assume !(0 == ~M_E~0); 364628#L696-2 assume !(0 == ~T1_E~0); 364973#L701-1 assume !(0 == ~T2_E~0); 364975#L706-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 365005#L711-1 assume !(0 == ~T4_E~0); 364511#L716-1 assume !(0 == ~T5_E~0); 364512#L721-1 assume !(0 == ~T6_E~0); 364698#L726-1 assume !(0 == ~E_M~0); 364699#L731-1 assume !(0 == ~E_1~0); 364667#L736-1 assume !(0 == ~E_2~0); 364668#L741-1 assume !(0 == ~E_3~0); 365053#L746-1 assume !(0 == ~E_4~0); 365054#L751-1 assume !(0 == ~E_5~0); 365138#L756-1 assume !(0 == ~E_6~0); 364508#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 364346#L346 assume !(1 == ~m_pc~0); 364347#L346-2 is_master_triggered_~__retres1~0#1 := 0; 364877#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 364262#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 364263#L861 assume !(0 != activate_threads_~tmp~1#1); 365135#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 364377#L365 assume !(1 == ~t1_pc~0); 364378#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 364939#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 364941#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 364368#L869 assume !(0 != activate_threads_~tmp___0~0#1); 364369#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 365130#L384 assume !(1 == ~t2_pc~0); 364804#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 364805#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 365129#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 364283#L877 assume !(0 != activate_threads_~tmp___1~0#1); 364284#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 364646#L403 assume !(1 == ~t3_pc~0); 364647#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 364856#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 365088#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 365124#L885 assume !(0 != activate_threads_~tmp___2~0#1); 365123#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 365122#L422 assume !(1 == ~t4_pc~0); 364768#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 364769#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 364809#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 364810#L893 assume !(0 != activate_threads_~tmp___3~0#1); 364906#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 365118#L441 assume !(1 == ~t5_pc~0); 365116#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 365114#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 365112#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 365110#L901 assume !(0 != activate_threads_~tmp___4~0#1); 364737#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 364738#L460 assume !(1 == ~t6_pc~0); 364883#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 364968#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 364997#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 364878#L909 assume !(0 != activate_threads_~tmp___5~0#1); 364879#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 364710#L774 assume !(1 == ~M_E~0); 364711#L774-2 assume !(1 == ~T1_E~0); 365106#L779-1 assume !(1 == ~T2_E~0); 365105#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 364607#L789-1 assume !(1 == ~T4_E~0); 364362#L794-1 assume !(1 == ~T5_E~0); 364363#L799-1 assume !(1 == ~T6_E~0); 365040#L804-1 assume !(1 == ~E_M~0); 365041#L809-1 assume !(1 == ~E_1~0); 364694#L814-1 assume !(1 == ~E_2~0); 364264#L819-1 assume !(1 == ~E_3~0); 364265#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 364763#L829-1 assume !(1 == ~E_5~0); 364887#L834-1 assume !(1 == ~E_6~0); 364492#L839-1 assume { :end_inline_reset_delta_events } true; 364493#L1065-2 [2022-07-14 16:02:37,986 INFO L754 eck$LassoCheckResult]: Loop: 364493#L1065-2 assume !false; 397845#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 397842#L671 assume !false; 397841#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 397839#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 397832#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 397830#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 397827#L582 assume !(0 != eval_~tmp~0#1); 397825#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 397823#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 397821#L696-3 assume !(0 == ~M_E~0); 397819#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 397817#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 397814#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 397815#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 397833#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 397831#L721-3 assume !(0 == ~T6_E~0); 397829#L726-3 assume !(0 == ~E_M~0); 397826#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 397824#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 397822#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 397820#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 397818#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 397816#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 397813#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 397811#L346-24 assume !(1 == ~m_pc~0); 397809#L346-26 is_master_triggered_~__retres1~0#1 := 0; 397807#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 397805#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 397803#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 397801#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 397799#L365-24 assume !(1 == ~t1_pc~0); 397797#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 397795#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 397793#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 397791#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 397789#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 397787#L384-24 assume 1 == ~t2_pc~0; 397784#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 397782#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 397780#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 397778#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 397776#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 397774#L403-24 assume !(1 == ~t3_pc~0); 397772#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 397770#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 397768#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 397766#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 397764#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 397761#L422-24 assume !(1 == ~t4_pc~0); 397759#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 397757#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 397755#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 397753#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 397751#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 397749#L441-24 assume 1 == ~t5_pc~0; 397747#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 397748#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 397925#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 397738#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 397736#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 397734#L460-24 assume !(1 == ~t6_pc~0); 397732#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 397730#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 397728#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 397726#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 397722#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 397720#L774-3 assume !(1 == ~M_E~0); 384084#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 397717#L779-3 assume !(1 == ~T2_E~0); 397695#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 397693#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 397691#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 397688#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 397686#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 397684#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 397682#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 397680#L819-3 assume !(1 == ~E_3~0); 397678#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 397677#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 397675#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 397673#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 397668#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 397660#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 397658#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 384015#L1084 assume !(0 == start_simulation_~tmp~3#1); 384016#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 397866#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 397862#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 397860#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 397858#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 397854#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 397852#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 397850#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 364493#L1065-2 [2022-07-14 16:02:37,986 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:37,986 INFO L85 PathProgramCache]: Analyzing trace with hash -661295541, now seen corresponding path program 1 times [2022-07-14 16:02:37,987 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:37,987 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [809480968] [2022-07-14 16:02:37,987 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:37,987 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:37,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:38,008 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:38,008 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:38,008 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [809480968] [2022-07-14 16:02:38,009 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [809480968] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:38,009 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:38,009 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:38,009 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2090448080] [2022-07-14 16:02:38,009 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:38,009 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:38,010 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:38,010 INFO L85 PathProgramCache]: Analyzing trace with hash -261755712, now seen corresponding path program 1 times [2022-07-14 16:02:38,010 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:38,010 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [290304920] [2022-07-14 16:02:38,010 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:38,011 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:38,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:38,032 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:38,032 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:38,032 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [290304920] [2022-07-14 16:02:38,033 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [290304920] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:38,033 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:38,033 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:38,033 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1924383074] [2022-07-14 16:02:38,033 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:38,034 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:38,034 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:38,034 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:02:38,034 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:02:38,034 INFO L87 Difference]: Start difference. First operand 49292 states and 70223 transitions. cyclomatic complexity: 20947 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:38,279 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:38,279 INFO L93 Difference]: Finished difference Result 61338 states and 87007 transitions. [2022-07-14 16:02:38,280 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:02:38,281 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 61338 states and 87007 transitions. [2022-07-14 16:02:38,708 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 60877 [2022-07-14 16:02:38,959 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 61338 states to 61338 states and 87007 transitions. [2022-07-14 16:02:38,959 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 61338 [2022-07-14 16:02:39,008 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 61338 [2022-07-14 16:02:39,008 INFO L73 IsDeterministic]: Start isDeterministic. Operand 61338 states and 87007 transitions. [2022-07-14 16:02:39,074 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:39,074 INFO L369 hiAutomatonCegarLoop]: Abstraction has 61338 states and 87007 transitions. [2022-07-14 16:02:39,121 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61338 states and 87007 transitions. [2022-07-14 16:02:39,628 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61338 to 42340. [2022-07-14 16:02:39,670 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42340 states, 42340 states have (on average 1.4221303731695796) internal successors, (60213), 42339 states have internal predecessors, (60213), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:39,758 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42340 states to 42340 states and 60213 transitions. [2022-07-14 16:02:39,759 INFO L392 hiAutomatonCegarLoop]: Abstraction has 42340 states and 60213 transitions. [2022-07-14 16:02:39,759 INFO L374 stractBuchiCegarLoop]: Abstraction has 42340 states and 60213 transitions. [2022-07-14 16:02:39,759 INFO L287 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-07-14 16:02:39,759 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42340 states and 60213 transitions. [2022-07-14 16:02:39,901 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 42003 [2022-07-14 16:02:39,902 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:39,902 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:39,903 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:39,903 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:39,904 INFO L752 eck$LassoCheckResult]: Stem: 475692#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 475627#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 475575#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 475501#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 475502#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 475119#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 475120#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 474973#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 474974#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 474942#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 474943#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 475098#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 475261#L696 assume !(0 == ~M_E~0); 475262#L696-2 assume !(0 == ~T1_E~0); 475601#L701-1 assume !(0 == ~T2_E~0); 475604#L706-1 assume !(0 == ~T3_E~0); 475382#L711-1 assume !(0 == ~T4_E~0); 475153#L716-1 assume !(0 == ~T5_E~0); 475154#L721-1 assume !(0 == ~T6_E~0); 475332#L726-1 assume !(0 == ~E_M~0); 475333#L731-1 assume !(0 == ~E_1~0); 475299#L736-1 assume !(0 == ~E_2~0); 475300#L741-1 assume !(0 == ~E_3~0); 475389#L746-1 assume !(0 == ~E_4~0); 475186#L751-1 assume !(0 == ~E_5~0); 475187#L756-1 assume !(0 == ~E_6~0); 475150#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 474988#L346 assume !(1 == ~m_pc~0); 474989#L346-2 is_master_triggered_~__retres1~0#1 := 0; 475197#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 474903#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 474904#L861 assume !(0 != activate_threads_~tmp~1#1); 475559#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 475018#L365 assume !(1 == ~t1_pc~0); 475019#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 475574#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 475576#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 475009#L869 assume !(0 != activate_threads_~tmp___0~0#1); 475010#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 475454#L384 assume !(1 == ~t2_pc~0); 475443#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 475444#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 475095#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 474924#L877 assume !(0 != activate_threads_~tmp___1~0#1); 474925#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 475278#L403 assume !(1 == ~t3_pc~0); 475279#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 475496#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 475141#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 475142#L885 assume !(0 != activate_threads_~tmp___2~0#1); 475269#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 475270#L422 assume !(1 == ~t4_pc~0); 475405#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 475406#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 475450#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 475451#L893 assume !(0 != activate_threads_~tmp___3~0#1); 475363#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 474944#L441 assume !(1 == ~t5_pc~0); 474945#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 475556#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 475629#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 475630#L901 assume !(0 != activate_threads_~tmp___4~0#1); 475373#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 475374#L460 assume !(1 == ~t6_pc~0); 475520#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 474951#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 474952#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 475515#L909 assume !(0 != activate_threads_~tmp___5~0#1); 475516#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 475344#L774 assume !(1 == ~M_E~0); 475345#L774-2 assume !(1 == ~T1_E~0); 475534#L779-1 assume !(1 == ~T2_E~0); 475243#L784-1 assume !(1 == ~T3_E~0); 475244#L789-1 assume !(1 == ~T4_E~0); 475003#L794-1 assume !(1 == ~T5_E~0); 475004#L799-1 assume !(1 == ~T6_E~0); 475649#L804-1 assume !(1 == ~E_M~0); 475650#L809-1 assume !(1 == ~E_1~0); 475328#L814-1 assume !(1 == ~E_2~0); 474905#L819-1 assume !(1 == ~E_3~0); 474906#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 475399#L829-1 assume !(1 == ~E_5~0); 475524#L834-1 assume !(1 == ~E_6~0); 475133#L839-1 assume { :end_inline_reset_delta_events } true; 475134#L1065-2 [2022-07-14 16:02:39,904 INFO L754 eck$LassoCheckResult]: Loop: 475134#L1065-2 assume !false; 486158#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 486137#L671 assume !false; 486131#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 486074#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 486064#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 486059#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 486053#L582 assume !(0 != eval_~tmp~0#1); 486052#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 486012#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 486005#L696-3 assume !(0 == ~M_E~0); 485990#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 485983#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 485976#L706-3 assume !(0 == ~T3_E~0); 485969#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 485962#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 485955#L721-3 assume !(0 == ~T6_E~0); 485949#L726-3 assume !(0 == ~E_M~0); 485939#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 485930#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 485922#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 485914#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 485906#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 485898#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 485845#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 485838#L346-24 assume !(1 == ~m_pc~0); 485832#L346-26 is_master_triggered_~__retres1~0#1 := 0; 485824#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 485817#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 485808#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 485799#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 485791#L365-24 assume !(1 == ~t1_pc~0); 485788#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 485315#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 485307#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 485298#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 485289#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 485283#L384-24 assume !(1 == ~t2_pc~0); 485271#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 485267#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 485264#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 485262#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 485260#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 485258#L403-24 assume !(1 == ~t3_pc~0); 485256#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 485254#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 485252#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 485250#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 485247#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 485234#L422-24 assume !(1 == ~t4_pc~0); 485228#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 485224#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 485184#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 485177#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 485171#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 485164#L441-24 assume !(1 == ~t5_pc~0); 485156#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 485151#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 485142#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 485133#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 485124#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 485117#L460-24 assume !(1 == ~t6_pc~0); 485111#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 485104#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 484436#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 484171#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 484164#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 484158#L774-3 assume !(1 == ~M_E~0); 482300#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 484146#L779-3 assume !(1 == ~T2_E~0); 484140#L784-3 assume !(1 == ~T3_E~0); 484133#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 484125#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 484118#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 484110#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 484102#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 484094#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 484088#L819-3 assume !(1 == ~E_3~0); 484081#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 484073#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 484067#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 484061#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 483333#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 483327#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 483326#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 483212#L1084 assume !(0 == start_simulation_~tmp~3#1); 483213#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 486224#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 486216#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 486210#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 486194#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 486183#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 486175#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 486167#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 475134#L1065-2 [2022-07-14 16:02:39,904 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:39,905 INFO L85 PathProgramCache]: Analyzing trace with hash -895756277, now seen corresponding path program 1 times [2022-07-14 16:02:39,905 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:39,905 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1476164144] [2022-07-14 16:02:39,905 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:39,905 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:39,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:39,932 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:39,932 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:39,933 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1476164144] [2022-07-14 16:02:39,933 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1476164144] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:39,933 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:39,933 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:39,933 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2067004355] [2022-07-14 16:02:39,933 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:39,934 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:39,934 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:39,934 INFO L85 PathProgramCache]: Analyzing trace with hash 1280693444, now seen corresponding path program 1 times [2022-07-14 16:02:39,934 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:39,935 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [536932064] [2022-07-14 16:02:39,935 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:39,935 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:39,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:39,956 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:39,957 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:39,957 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [536932064] [2022-07-14 16:02:39,957 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [536932064] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:39,957 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:39,958 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:39,958 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [83878482] [2022-07-14 16:02:39,958 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:39,958 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:39,958 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:39,959 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:02:39,959 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:02:39,959 INFO L87 Difference]: Start difference. First operand 42340 states and 60213 transitions. cyclomatic complexity: 17889 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:40,225 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:40,226 INFO L93 Difference]: Finished difference Result 67784 states and 95514 transitions. [2022-07-14 16:02:40,226 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:02:40,227 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 67784 states and 95514 transitions. [2022-07-14 16:02:40,524 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 67240 [2022-07-14 16:02:40,728 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 67784 states to 67784 states and 95514 transitions. [2022-07-14 16:02:40,728 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 67784 [2022-07-14 16:02:40,775 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 67784 [2022-07-14 16:02:40,775 INFO L73 IsDeterministic]: Start isDeterministic. Operand 67784 states and 95514 transitions. [2022-07-14 16:02:40,840 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:40,841 INFO L369 hiAutomatonCegarLoop]: Abstraction has 67784 states and 95514 transitions. [2022-07-14 16:02:41,289 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67784 states and 95514 transitions. [2022-07-14 16:02:41,746 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67784 to 49292. [2022-07-14 16:02:41,783 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49292 states, 49292 states have (on average 1.4120344072060376) internal successors, (69602), 49291 states have internal predecessors, (69602), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:41,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49292 states to 49292 states and 69602 transitions. [2022-07-14 16:02:41,863 INFO L392 hiAutomatonCegarLoop]: Abstraction has 49292 states and 69602 transitions. [2022-07-14 16:02:41,863 INFO L374 stractBuchiCegarLoop]: Abstraction has 49292 states and 69602 transitions. [2022-07-14 16:02:41,863 INFO L287 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-07-14 16:02:41,863 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49292 states and 69602 transitions. [2022-07-14 16:02:41,994 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 48893 [2022-07-14 16:02:41,994 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:41,995 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:41,996 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:41,996 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:41,996 INFO L752 eck$LassoCheckResult]: Stem: 585858#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 585776#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 585713#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 585636#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 585637#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 585257#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 585258#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 585109#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 585110#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 585076#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 585077#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 585236#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 585402#L696 assume !(0 == ~M_E~0); 585403#L696-2 assume !(0 == ~T1_E~0); 585741#L701-1 assume !(0 == ~T2_E~0); 585742#L706-1 assume !(0 == ~T3_E~0); 585525#L711-1 assume !(0 == ~T4_E~0); 585292#L716-1 assume !(0 == ~T5_E~0); 585293#L721-1 assume !(0 == ~T6_E~0); 585475#L726-1 assume !(0 == ~E_M~0); 585476#L731-1 assume !(0 == ~E_1~0); 585442#L736-1 assume !(0 == ~E_2~0); 585443#L741-1 assume !(0 == ~E_3~0); 585531#L746-1 assume 0 == ~E_4~0;~E_4~0 := 1; 585831#L751-1 assume !(0 == ~E_5~0); 585907#L756-1 assume !(0 == ~E_6~0); 585289#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 585123#L346 assume !(1 == ~m_pc~0); 585124#L346-2 is_master_triggered_~__retres1~0#1 := 0; 585648#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 585039#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 585040#L861 assume !(0 != activate_threads_~tmp~1#1); 585904#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 585154#L365 assume !(1 == ~t1_pc~0); 585155#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 585712#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 585717#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 585144#L869 assume !(0 != activate_threads_~tmp___0~0#1); 585145#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 585899#L384 assume !(1 == ~t2_pc~0); 585585#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 585586#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 585898#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 585060#L877 assume !(0 != activate_threads_~tmp___1~0#1); 585061#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 585420#L403 assume !(1 == ~t3_pc~0); 585421#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 585631#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 585283#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 585284#L885 assume !(0 != activate_threads_~tmp___2~0#1); 585411#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 585412#L422 assume !(1 == ~t4_pc~0); 585734#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 585891#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 585890#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 585889#L893 assume !(0 != activate_threads_~tmp___3~0#1); 585507#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 585078#L441 assume !(1 == ~t5_pc~0); 585079#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 585689#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 585778#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 585779#L901 assume !(0 != activate_threads_~tmp___4~0#1); 585869#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 585882#L460 assume !(1 == ~t6_pc~0); 585881#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 585087#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 585088#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 585880#L909 assume !(0 != activate_threads_~tmp___5~0#1); 585757#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 585758#L774 assume !(1 == ~M_E~0); 585800#L774-2 assume !(1 == ~T1_E~0); 585667#L779-1 assume !(1 == ~T2_E~0); 585380#L784-1 assume !(1 == ~T3_E~0); 585381#L789-1 assume !(1 == ~T4_E~0); 585877#L794-1 assume !(1 == ~T5_E~0); 585876#L799-1 assume !(1 == ~T6_E~0); 585806#L804-1 assume !(1 == ~E_M~0); 585807#L809-1 assume !(1 == ~E_1~0); 585875#L814-1 assume !(1 == ~E_2~0); 585041#L819-1 assume !(1 == ~E_3~0); 585042#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 585543#L829-1 assume !(1 == ~E_5~0); 585657#L834-1 assume !(1 == ~E_6~0); 585274#L839-1 assume { :end_inline_reset_delta_events } true; 585275#L1065-2 [2022-07-14 16:02:41,997 INFO L754 eck$LassoCheckResult]: Loop: 585275#L1065-2 assume !false; 606773#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 606770#L671 assume !false; 606769#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 606767#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 606761#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 606760#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 606758#L582 assume !(0 != eval_~tmp~0#1); 606759#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 611042#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 611040#L696-3 assume !(0 == ~M_E~0); 611037#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 611035#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 611033#L706-3 assume !(0 == ~T3_E~0); 611031#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 611029#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 611027#L721-3 assume !(0 == ~T6_E~0); 611025#L726-3 assume !(0 == ~E_M~0); 611023#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 611021#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 611019#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 611016#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 611017#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 611455#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 611450#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 611445#L346-24 assume !(1 == ~m_pc~0); 611440#L346-26 is_master_triggered_~__retres1~0#1 := 0; 611053#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 611052#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 611051#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 611050#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 611049#L365-24 assume !(1 == ~t1_pc~0); 611047#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 611046#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 611045#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 611044#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 611043#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 611041#L384-24 assume !(1 == ~t2_pc~0); 611039#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 611036#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 611034#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 611032#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 611030#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 611028#L403-24 assume !(1 == ~t3_pc~0); 611026#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 611024#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 611022#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 611020#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 611018#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 611015#L422-24 assume !(1 == ~t4_pc~0); 611013#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 611011#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 611009#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 611007#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 611005#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 611003#L441-24 assume 1 == ~t5_pc~0; 611001#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 611002#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 611048#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 610992#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 610990#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 610988#L460-24 assume !(1 == ~t6_pc~0); 610986#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 610984#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 610982#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 610980#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 610977#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 610975#L774-3 assume !(1 == ~M_E~0); 590425#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 610972#L779-3 assume !(1 == ~T2_E~0); 610970#L784-3 assume !(1 == ~T3_E~0); 610968#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 610966#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 610964#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 610962#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 610960#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 610958#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 610956#L819-3 assume !(1 == ~E_3~0); 610899#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 610896#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 610894#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 610892#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 594182#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 594168#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 594165#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 590651#L1084 assume !(0 == start_simulation_~tmp~3#1); 590653#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 606821#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 606816#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 606813#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 606810#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 606798#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 606790#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 606785#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 585275#L1065-2 [2022-07-14 16:02:41,997 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:41,997 INFO L85 PathProgramCache]: Analyzing trace with hash 1437636361, now seen corresponding path program 1 times [2022-07-14 16:02:41,998 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:41,998 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [386329676] [2022-07-14 16:02:41,998 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:41,998 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:42,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:42,019 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:42,020 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:42,020 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [386329676] [2022-07-14 16:02:42,020 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [386329676] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:42,020 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:42,020 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:42,020 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1965076013] [2022-07-14 16:02:42,020 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:42,021 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:42,021 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:42,021 INFO L85 PathProgramCache]: Analyzing trace with hash -1213339967, now seen corresponding path program 1 times [2022-07-14 16:02:42,021 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:42,022 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [296180253] [2022-07-14 16:02:42,022 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:42,022 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:42,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:42,042 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:42,042 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:42,042 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [296180253] [2022-07-14 16:02:42,042 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [296180253] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:42,043 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:42,043 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:42,043 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [398855407] [2022-07-14 16:02:42,043 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:42,043 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:42,043 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:42,044 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:02:42,044 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:02:42,044 INFO L87 Difference]: Start difference. First operand 49292 states and 69602 transitions. cyclomatic complexity: 20326 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:42,592 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:42,593 INFO L93 Difference]: Finished difference Result 60427 states and 84941 transitions. [2022-07-14 16:02:42,593 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:02:42,596 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 60427 states and 84941 transitions. [2022-07-14 16:02:42,829 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 59948 [2022-07-14 16:02:42,963 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 60427 states to 60427 states and 84941 transitions. [2022-07-14 16:02:42,964 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 60427 [2022-07-14 16:02:42,994 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 60427 [2022-07-14 16:02:42,994 INFO L73 IsDeterministic]: Start isDeterministic. Operand 60427 states and 84941 transitions. [2022-07-14 16:02:43,022 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:43,022 INFO L369 hiAutomatonCegarLoop]: Abstraction has 60427 states and 84941 transitions. [2022-07-14 16:02:43,048 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60427 states and 84941 transitions. [2022-07-14 16:02:43,397 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60427 to 42340. [2022-07-14 16:02:43,429 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42340 states, 42340 states have (on average 1.4074633915918753) internal successors, (59592), 42339 states have internal predecessors, (59592), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:43,487 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42340 states to 42340 states and 59592 transitions. [2022-07-14 16:02:43,488 INFO L392 hiAutomatonCegarLoop]: Abstraction has 42340 states and 59592 transitions. [2022-07-14 16:02:43,488 INFO L374 stractBuchiCegarLoop]: Abstraction has 42340 states and 59592 transitions. [2022-07-14 16:02:43,488 INFO L287 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-07-14 16:02:43,488 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42340 states and 59592 transitions. [2022-07-14 16:02:43,750 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 42003 [2022-07-14 16:02:43,750 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:43,750 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:43,752 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:43,752 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:43,752 INFO L752 eck$LassoCheckResult]: Stem: 695574#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 695509#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 695447#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 695369#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 695370#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 694985#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 694986#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 694837#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 694838#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 694805#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 694806#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 694964#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 695130#L696 assume !(0 == ~M_E~0); 695131#L696-2 assume !(0 == ~T1_E~0); 695477#L701-1 assume !(0 == ~T2_E~0); 695478#L706-1 assume !(0 == ~T3_E~0); 695251#L711-1 assume !(0 == ~T4_E~0); 695020#L716-1 assume !(0 == ~T5_E~0); 695021#L721-1 assume !(0 == ~T6_E~0); 695202#L726-1 assume !(0 == ~E_M~0); 695203#L731-1 assume !(0 == ~E_1~0); 695168#L736-1 assume !(0 == ~E_2~0); 695169#L741-1 assume !(0 == ~E_3~0); 695259#L746-1 assume !(0 == ~E_4~0); 695052#L751-1 assume !(0 == ~E_5~0); 695053#L756-1 assume !(0 == ~E_6~0); 695017#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 694851#L346 assume !(1 == ~m_pc~0); 694852#L346-2 is_master_triggered_~__retres1~0#1 := 0; 695065#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 694768#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 694769#L861 assume !(0 != activate_threads_~tmp~1#1); 695432#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 694882#L365 assume !(1 == ~t1_pc~0); 694883#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 695446#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 695452#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 694872#L869 assume !(0 != activate_threads_~tmp___0~0#1); 694873#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 695323#L384 assume !(1 == ~t2_pc~0); 695315#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 695316#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 694963#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 694789#L877 assume !(0 != activate_threads_~tmp___1~0#1); 694790#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 695148#L403 assume !(1 == ~t3_pc~0); 695149#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 695362#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 695012#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 695013#L885 assume !(0 != activate_threads_~tmp___2~0#1); 695139#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 695140#L422 assume !(1 == ~t4_pc~0); 695278#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 695279#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 695321#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 695322#L893 assume !(0 != activate_threads_~tmp___3~0#1); 695234#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 694807#L441 assume !(1 == ~t5_pc~0); 694808#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 695426#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 695511#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 695512#L901 assume !(0 != activate_threads_~tmp___4~0#1); 695244#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 695245#L460 assume !(1 == ~t6_pc~0); 695391#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 694816#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 694817#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 695386#L909 assume !(0 != activate_threads_~tmp___5~0#1); 695387#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 695213#L774 assume !(1 == ~M_E~0); 695214#L774-2 assume !(1 == ~T1_E~0); 695406#L779-1 assume !(1 == ~T2_E~0); 695109#L784-1 assume !(1 == ~T3_E~0); 695110#L789-1 assume !(1 == ~T4_E~0); 694866#L794-1 assume !(1 == ~T5_E~0); 694867#L799-1 assume !(1 == ~T6_E~0); 695536#L804-1 assume !(1 == ~E_M~0); 695537#L809-1 assume !(1 == ~E_1~0); 695197#L814-1 assume !(1 == ~E_2~0); 694770#L819-1 assume !(1 == ~E_3~0); 694771#L824-1 assume !(1 == ~E_4~0); 695271#L829-1 assume !(1 == ~E_5~0); 695395#L834-1 assume !(1 == ~E_6~0); 695003#L839-1 assume { :end_inline_reset_delta_events } true; 695004#L1065-2 [2022-07-14 16:02:43,752 INFO L754 eck$LassoCheckResult]: Loop: 695004#L1065-2 assume !false; 715534#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 715126#L671 assume !false; 715533#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 715414#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 715398#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 715294#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 715291#L582 assume !(0 != eval_~tmp~0#1); 715292#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 717784#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 717782#L696-3 assume !(0 == ~M_E~0); 717780#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 716813#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 716810#L706-3 assume !(0 == ~T3_E~0); 716808#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 716806#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 716804#L721-3 assume !(0 == ~T6_E~0); 716802#L726-3 assume !(0 == ~E_M~0); 716800#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 716797#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 716795#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 716793#L746-3 assume !(0 == ~E_4~0); 716791#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 716789#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 716787#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 716770#L346-24 assume !(1 == ~m_pc~0); 716768#L346-26 is_master_triggered_~__retres1~0#1 := 0; 716766#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 716764#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 716761#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 716756#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 716752#L365-24 assume !(1 == ~t1_pc~0); 716748#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 716744#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 716740#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 716734#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 716723#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 716718#L384-24 assume !(1 == ~t2_pc~0); 716712#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 716705#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 716699#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 716694#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 716688#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 716683#L403-24 assume !(1 == ~t3_pc~0); 716678#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 716672#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 716666#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 716660#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 716654#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 716648#L422-24 assume !(1 == ~t4_pc~0); 716643#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 716638#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 716632#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 716627#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 716622#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 716617#L441-24 assume 1 == ~t5_pc~0; 716611#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 716604#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 716597#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 716591#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 716585#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 716578#L460-24 assume !(1 == ~t6_pc~0); 716569#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 716560#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 716552#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 716544#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 716536#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 716525#L774-3 assume !(1 == ~M_E~0); 711972#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 716506#L779-3 assume !(1 == ~T2_E~0); 716490#L784-3 assume !(1 == ~T3_E~0); 716475#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 716464#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 716458#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 716387#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 716386#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 716384#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 716382#L819-3 assume !(1 == ~E_3~0); 716380#L824-3 assume !(1 == ~E_4~0); 716304#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 716303#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 716276#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 716225#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 716215#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 716210#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 716168#L1084 assume !(0 == start_simulation_~tmp~3#1); 716005#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 715558#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 715554#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 715550#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 715548#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 715546#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 715541#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 715539#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 695004#L1065-2 [2022-07-14 16:02:43,753 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:43,753 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 1 times [2022-07-14 16:02:43,753 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:43,753 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [307975679] [2022-07-14 16:02:43,754 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:43,754 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:43,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:43,762 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:02:43,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:43,801 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:02:43,801 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:43,801 INFO L85 PathProgramCache]: Analyzing trace with hash 149516417, now seen corresponding path program 1 times [2022-07-14 16:02:43,802 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:43,802 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1581818704] [2022-07-14 16:02:43,802 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:43,802 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:43,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:43,821 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:43,821 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:43,822 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1581818704] [2022-07-14 16:02:43,822 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1581818704] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:43,822 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:43,822 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:43,822 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1599546342] [2022-07-14 16:02:43,822 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:43,823 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:43,823 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:43,824 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:02:43,824 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:02:43,824 INFO L87 Difference]: Start difference. First operand 42340 states and 59592 transitions. cyclomatic complexity: 17268 Second operand has 3 states, 3 states have (on average 31.333333333333332) internal successors, (94), 3 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:43,975 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:43,976 INFO L93 Difference]: Finished difference Result 49292 states and 69112 transitions. [2022-07-14 16:02:43,978 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:02:43,978 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 49292 states and 69112 transitions. [2022-07-14 16:02:44,174 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 48893 [2022-07-14 16:02:44,301 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 49292 states to 49292 states and 69112 transitions. [2022-07-14 16:02:44,301 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 49292 [2022-07-14 16:02:44,336 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 49292 [2022-07-14 16:02:44,336 INFO L73 IsDeterministic]: Start isDeterministic. Operand 49292 states and 69112 transitions. [2022-07-14 16:02:44,368 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:44,369 INFO L369 hiAutomatonCegarLoop]: Abstraction has 49292 states and 69112 transitions. [2022-07-14 16:02:44,397 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49292 states and 69112 transitions. [2022-07-14 16:02:45,069 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49292 to 49292. [2022-07-14 16:02:45,100 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49292 states, 49292 states have (on average 1.4020936460277529) internal successors, (69112), 49291 states have internal predecessors, (69112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:45,187 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49292 states to 49292 states and 69112 transitions. [2022-07-14 16:02:45,188 INFO L392 hiAutomatonCegarLoop]: Abstraction has 49292 states and 69112 transitions. [2022-07-14 16:02:45,188 INFO L374 stractBuchiCegarLoop]: Abstraction has 49292 states and 69112 transitions. [2022-07-14 16:02:45,188 INFO L287 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-07-14 16:02:45,188 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49292 states and 69112 transitions. [2022-07-14 16:02:45,322 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 48893 [2022-07-14 16:02:45,322 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:45,322 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:45,324 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:45,324 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:45,324 INFO L752 eck$LassoCheckResult]: Stem: 787238#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 787163#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 787104#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 787015#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 787016#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 786622#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 786623#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 786474#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 786475#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 786443#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 786444#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 786601#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 786761#L696 assume !(0 == ~M_E~0); 786762#L696-2 assume !(0 == ~T1_E~0); 787130#L701-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 787132#L706-1 assume !(0 == ~T3_E~0); 787162#L711-1 assume !(0 == ~T4_E~0); 786657#L716-1 assume !(0 == ~T5_E~0); 786658#L721-1 assume !(0 == ~T6_E~0); 786836#L726-1 assume !(0 == ~E_M~0); 786837#L731-1 assume !(0 == ~E_1~0); 786803#L736-1 assume !(0 == ~E_2~0); 786804#L741-1 assume !(0 == ~E_3~0); 787207#L746-1 assume !(0 == ~E_4~0); 787208#L751-1 assume !(0 == ~E_5~0); 787289#L756-1 assume !(0 == ~E_6~0); 786654#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 786489#L346 assume !(1 == ~m_pc~0); 786490#L346-2 is_master_triggered_~__retres1~0#1 := 0; 787287#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 786404#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 786405#L861 assume !(0 != activate_threads_~tmp~1#1); 787286#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 786519#L365 assume !(1 == ~t1_pc~0); 786520#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 787102#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 787105#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 786510#L869 assume !(0 != activate_threads_~tmp___0~0#1); 786511#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 786965#L384 assume !(1 == ~t2_pc~0); 786955#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 786956#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 787277#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 786425#L877 assume !(0 != activate_threads_~tmp___1~0#1); 786426#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 786781#L403 assume !(1 == ~t3_pc~0); 786782#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 787008#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 787240#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 787272#L885 assume !(0 != activate_threads_~tmp___2~0#1); 787271#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 787270#L422 assume !(1 == ~t4_pc~0); 786916#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 786917#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 786961#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 786962#L893 assume !(0 != activate_threads_~tmp___3~0#1); 787062#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 787266#L441 assume !(1 == ~t5_pc~0); 787264#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 787263#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 787165#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 787166#L901 assume !(0 != activate_threads_~tmp___4~0#1); 787248#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 787260#L460 assume !(1 == ~t6_pc~0); 787259#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 786452#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 786453#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 787032#L909 assume !(0 != activate_threads_~tmp___5~0#1); 787033#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 786850#L774 assume !(1 == ~M_E~0); 786851#L774-2 assume !(1 == ~T1_E~0); 787052#L779-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 786744#L784-1 assume !(1 == ~T3_E~0); 786745#L789-1 assume !(1 == ~T4_E~0); 786504#L794-1 assume !(1 == ~T5_E~0); 786505#L799-1 assume !(1 == ~T6_E~0); 787192#L804-1 assume !(1 == ~E_M~0); 787193#L809-1 assume !(1 == ~E_1~0); 786831#L814-1 assume !(1 == ~E_2~0); 786406#L819-1 assume !(1 == ~E_3~0); 786407#L824-1 assume !(1 == ~E_4~0); 786908#L829-1 assume !(1 == ~E_5~0); 787041#L834-1 assume !(1 == ~E_6~0); 786637#L839-1 assume { :end_inline_reset_delta_events } true; 786638#L1065-2 [2022-07-14 16:02:45,325 INFO L754 eck$LassoCheckResult]: Loop: 786638#L1065-2 assume !false; 801067#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 800870#L671 assume !false; 801066#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 801064#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 801058#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 801057#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 801056#L582 assume !(0 != eval_~tmp~0#1); 796603#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 796601#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 796599#L696-3 assume !(0 == ~M_E~0); 796597#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 796594#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 796592#L706-3 assume !(0 == ~T3_E~0); 796590#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 796588#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 796586#L721-3 assume !(0 == ~T6_E~0); 796584#L726-3 assume !(0 == ~E_M~0); 796582#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 796580#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 796578#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 796576#L746-3 assume !(0 == ~E_4~0); 796573#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 796571#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 796569#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 796567#L346-24 assume !(1 == ~m_pc~0); 796565#L346-26 is_master_triggered_~__retres1~0#1 := 0; 796563#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 796561#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 796559#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 796557#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 796554#L365-24 assume !(1 == ~t1_pc~0); 796555#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 801150#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 801148#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 801146#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 796543#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 796541#L384-24 assume 1 == ~t2_pc~0; 796538#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 796534#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 796532#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 796530#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 796528#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 796525#L403-24 assume !(1 == ~t3_pc~0); 796523#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 796521#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 796519#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 796517#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 796514#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 796512#L422-24 assume !(1 == ~t4_pc~0); 796510#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 796509#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 796508#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 796506#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 796505#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 796504#L441-24 assume 1 == ~t5_pc~0; 796502#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 796501#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 796499#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 796463#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 796461#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 796459#L460-24 assume !(1 == ~t6_pc~0); 796457#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 796454#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 796452#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 796450#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 796447#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 796448#L774-3 assume !(1 == ~M_E~0); 801107#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 801106#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 801104#L784-3 assume !(1 == ~T3_E~0); 801103#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 801102#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 801101#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 801100#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 801099#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 801098#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 801097#L819-3 assume !(1 == ~E_3~0); 801096#L824-3 assume !(1 == ~E_4~0); 801095#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 801094#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 801093#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 801091#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 801085#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 801084#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 801083#L1084 assume !(0 == start_simulation_~tmp~3#1); 801081#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 801076#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 801073#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 801072#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 801071#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 801070#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 801069#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 801068#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 786638#L1065-2 [2022-07-14 16:02:45,325 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:45,325 INFO L85 PathProgramCache]: Analyzing trace with hash 2077618825, now seen corresponding path program 1 times [2022-07-14 16:02:45,326 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:45,326 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1753670633] [2022-07-14 16:02:45,326 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:45,326 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:45,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:45,347 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:45,347 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:45,347 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1753670633] [2022-07-14 16:02:45,348 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1753670633] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:45,348 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:45,348 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:45,348 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [48527323] [2022-07-14 16:02:45,348 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:45,349 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:45,350 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:45,350 INFO L85 PathProgramCache]: Analyzing trace with hash -231299522, now seen corresponding path program 1 times [2022-07-14 16:02:45,350 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:45,350 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [889096741] [2022-07-14 16:02:45,350 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:45,351 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:45,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:45,377 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:45,378 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:45,378 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [889096741] [2022-07-14 16:02:45,378 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [889096741] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:45,378 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:45,379 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:45,379 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1728470948] [2022-07-14 16:02:45,381 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:45,382 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:45,382 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:45,382 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:02:45,382 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:02:45,383 INFO L87 Difference]: Start difference. First operand 49292 states and 69112 transitions. cyclomatic complexity: 19836 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:45,589 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:45,590 INFO L93 Difference]: Finished difference Result 61350 states and 86002 transitions. [2022-07-14 16:02:45,590 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:02:45,590 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 61350 states and 86002 transitions. [2022-07-14 16:02:45,843 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 60877 [2022-07-14 16:02:46,007 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 61350 states to 61350 states and 86002 transitions. [2022-07-14 16:02:46,007 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 61350 [2022-07-14 16:02:46,052 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 61350 [2022-07-14 16:02:46,052 INFO L73 IsDeterministic]: Start isDeterministic. Operand 61350 states and 86002 transitions. [2022-07-14 16:02:46,093 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:46,093 INFO L369 hiAutomatonCegarLoop]: Abstraction has 61350 states and 86002 transitions. [2022-07-14 16:02:46,127 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61350 states and 86002 transitions. [2022-07-14 16:02:46,924 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61350 to 42340. [2022-07-14 16:02:46,956 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42340 states, 42340 states have (on average 1.4048889938592348) internal successors, (59483), 42339 states have internal predecessors, (59483), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:47,017 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42340 states to 42340 states and 59483 transitions. [2022-07-14 16:02:47,017 INFO L392 hiAutomatonCegarLoop]: Abstraction has 42340 states and 59483 transitions. [2022-07-14 16:02:47,017 INFO L374 stractBuchiCegarLoop]: Abstraction has 42340 states and 59483 transitions. [2022-07-14 16:02:47,017 INFO L287 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-07-14 16:02:47,017 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42340 states and 59483 transitions. [2022-07-14 16:02:47,121 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 42003 [2022-07-14 16:02:47,121 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:47,121 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:47,122 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:47,122 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:47,123 INFO L752 eck$LassoCheckResult]: Stem: 897851#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 897789#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 897732#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 897654#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 897655#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 897272#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 897273#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 897126#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 897127#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 897095#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 897096#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 897251#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 897413#L696 assume !(0 == ~M_E~0); 897414#L696-2 assume !(0 == ~T1_E~0); 897762#L701-1 assume !(0 == ~T2_E~0); 897764#L706-1 assume !(0 == ~T3_E~0); 897536#L711-1 assume !(0 == ~T4_E~0); 897307#L716-1 assume !(0 == ~T5_E~0); 897308#L721-1 assume !(0 == ~T6_E~0); 897488#L726-1 assume !(0 == ~E_M~0); 897489#L731-1 assume !(0 == ~E_1~0); 897453#L736-1 assume !(0 == ~E_2~0); 897454#L741-1 assume !(0 == ~E_3~0); 897544#L746-1 assume !(0 == ~E_4~0); 897339#L751-1 assume !(0 == ~E_5~0); 897340#L756-1 assume !(0 == ~E_6~0); 897304#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 897142#L346 assume !(1 == ~m_pc~0); 897143#L346-2 is_master_triggered_~__retres1~0#1 := 0; 897350#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 897056#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 897057#L861 assume !(0 != activate_threads_~tmp~1#1); 897711#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 897172#L365 assume !(1 == ~t1_pc~0); 897173#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 897731#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 897733#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 897163#L869 assume !(0 != activate_threads_~tmp___0~0#1); 897164#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 897604#L384 assume !(1 == ~t2_pc~0); 897594#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 897595#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 897248#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 897077#L877 assume !(0 != activate_threads_~tmp___1~0#1); 897078#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 897430#L403 assume !(1 == ~t3_pc~0); 897431#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 897648#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 897295#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 897296#L885 assume !(0 != activate_threads_~tmp___2~0#1); 897421#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 897422#L422 assume !(1 == ~t4_pc~0); 897560#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 897561#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 897600#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 897601#L893 assume !(0 != activate_threads_~tmp___3~0#1); 897519#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 897097#L441 assume !(1 == ~t5_pc~0); 897098#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 897706#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 897791#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 897792#L901 assume !(0 != activate_threads_~tmp___4~0#1); 897527#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 897528#L460 assume !(1 == ~t6_pc~0); 897671#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 897104#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 897105#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 897666#L909 assume !(0 != activate_threads_~tmp___5~0#1); 897667#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 897500#L774 assume !(1 == ~M_E~0); 897501#L774-2 assume !(1 == ~T1_E~0); 897687#L779-1 assume !(1 == ~T2_E~0); 897395#L784-1 assume !(1 == ~T3_E~0); 897396#L789-1 assume !(1 == ~T4_E~0); 897157#L794-1 assume !(1 == ~T5_E~0); 897158#L799-1 assume !(1 == ~T6_E~0); 897812#L804-1 assume !(1 == ~E_M~0); 897813#L809-1 assume !(1 == ~E_1~0); 897484#L814-1 assume !(1 == ~E_2~0); 897058#L819-1 assume !(1 == ~E_3~0); 897059#L824-1 assume !(1 == ~E_4~0); 897556#L829-1 assume !(1 == ~E_5~0); 897675#L834-1 assume !(1 == ~E_6~0); 897287#L839-1 assume { :end_inline_reset_delta_events } true; 897288#L1065-2 [2022-07-14 16:02:47,123 INFO L754 eck$LassoCheckResult]: Loop: 897288#L1065-2 assume !false; 909415#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 909343#L671 assume !false; 909248#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 909244#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 909238#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 909235#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 909226#L582 assume !(0 != eval_~tmp~0#1); 909224#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 909222#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 909219#L696-3 assume !(0 == ~M_E~0); 909217#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 909215#L701-3 assume !(0 == ~T2_E~0); 909213#L706-3 assume !(0 == ~T3_E~0); 909211#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 909209#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 909207#L721-3 assume !(0 == ~T6_E~0); 909205#L726-3 assume !(0 == ~E_M~0); 909203#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 909201#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 909199#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 909197#L746-3 assume !(0 == ~E_4~0); 909195#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 909193#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 909191#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 909189#L346-24 assume !(1 == ~m_pc~0); 909187#L346-26 is_master_triggered_~__retres1~0#1 := 0; 909185#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 909183#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 909181#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 909179#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 909177#L365-24 assume !(1 == ~t1_pc~0); 909175#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 909173#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 909170#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 909167#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 909165#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 909163#L384-24 assume !(1 == ~t2_pc~0); 909161#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 909158#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 909156#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 909153#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 909151#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 909149#L403-24 assume !(1 == ~t3_pc~0); 909147#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 909145#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 909143#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 909141#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 909139#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 909137#L422-24 assume !(1 == ~t4_pc~0); 909135#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 909133#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 909131#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 909129#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 909127#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 909125#L441-24 assume !(1 == ~t5_pc~0); 909121#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 909119#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 909115#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 909113#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 909110#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 909108#L460-24 assume !(1 == ~t6_pc~0); 909105#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 909103#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 909101#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 909099#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 909097#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 909095#L774-3 assume !(1 == ~M_E~0); 907162#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 909092#L779-3 assume !(1 == ~T2_E~0); 909090#L784-3 assume !(1 == ~T3_E~0); 909089#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 909087#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 909085#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 909083#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 909081#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 909079#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 909077#L819-3 assume !(1 == ~E_3~0); 909075#L824-3 assume !(1 == ~E_4~0); 909073#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 909007#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 909006#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 908996#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 908990#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 908774#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 907265#L1084 assume !(0 == start_simulation_~tmp~3#1); 907266#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 909462#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 909458#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 909456#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 909454#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 909452#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 909439#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 909431#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 897288#L1065-2 [2022-07-14 16:02:47,123 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:47,124 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 2 times [2022-07-14 16:02:47,124 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:47,124 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1043762050] [2022-07-14 16:02:47,124 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:47,124 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:47,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:47,132 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:02:47,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:47,167 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:02:47,168 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:47,168 INFO L85 PathProgramCache]: Analyzing trace with hash -84659518, now seen corresponding path program 1 times [2022-07-14 16:02:47,168 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:47,169 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1503990219] [2022-07-14 16:02:47,169 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:47,169 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:47,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:47,196 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:47,197 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:47,197 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1503990219] [2022-07-14 16:02:47,197 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1503990219] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:47,197 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:47,197 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:47,198 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [708770926] [2022-07-14 16:02:47,198 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:47,198 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:47,198 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:47,200 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:02:47,200 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:02:47,200 INFO L87 Difference]: Start difference. First operand 42340 states and 59483 transitions. cyclomatic complexity: 17159 Second operand has 3 states, 3 states have (on average 31.333333333333332) internal successors, (94), 3 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:47,439 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:47,439 INFO L93 Difference]: Finished difference Result 66423 states and 92904 transitions. [2022-07-14 16:02:47,440 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:02:47,440 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 66423 states and 92904 transitions. [2022-07-14 16:02:47,703 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 65832 [2022-07-14 16:02:47,873 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 66423 states to 66423 states and 92904 transitions. [2022-07-14 16:02:47,874 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 66423 [2022-07-14 16:02:47,918 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 66423 [2022-07-14 16:02:47,919 INFO L73 IsDeterministic]: Start isDeterministic. Operand 66423 states and 92904 transitions. [2022-07-14 16:02:47,959 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:47,959 INFO L369 hiAutomatonCegarLoop]: Abstraction has 66423 states and 92904 transitions. [2022-07-14 16:02:47,995 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66423 states and 92904 transitions. [2022-07-14 16:02:48,891 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66423 to 66351. [2022-07-14 16:02:48,940 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 66351 states, 66351 states have (on average 1.3991047610435412) internal successors, (92832), 66350 states have internal predecessors, (92832), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:49,046 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66351 states to 66351 states and 92832 transitions. [2022-07-14 16:02:49,046 INFO L392 hiAutomatonCegarLoop]: Abstraction has 66351 states and 92832 transitions. [2022-07-14 16:02:49,046 INFO L374 stractBuchiCegarLoop]: Abstraction has 66351 states and 92832 transitions. [2022-07-14 16:02:49,047 INFO L287 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-07-14 16:02:49,047 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 66351 states and 92832 transitions. [2022-07-14 16:02:49,232 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 65760 [2022-07-14 16:02:49,232 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:49,232 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:49,233 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:49,233 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:49,233 INFO L752 eck$LassoCheckResult]: Stem: 1006663#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1006589#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1006541#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1006440#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1006441#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 1006041#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1006042#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1005895#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1005896#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1005864#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1005865#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1006020#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1006188#L696 assume !(0 == ~M_E~0); 1006189#L696-2 assume !(0 == ~T1_E~0); 1006565#L701-1 assume !(0 == ~T2_E~0); 1006567#L706-1 assume !(0 == ~T3_E~0); 1006319#L711-1 assume !(0 == ~T4_E~0); 1006075#L716-1 assume !(0 == ~T5_E~0); 1006076#L721-1 assume !(0 == ~T6_E~0); 1006266#L726-1 assume !(0 == ~E_M~0); 1006267#L731-1 assume !(0 == ~E_1~0); 1006230#L736-1 assume !(0 == ~E_2~0); 1006231#L741-1 assume 0 == ~E_3~0;~E_3~0 := 1; 1006326#L746-1 assume !(0 == ~E_4~0); 1006108#L751-1 assume !(0 == ~E_5~0); 1006109#L756-1 assume !(0 == ~E_6~0); 1006208#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1006723#L346 assume !(1 == ~m_pc~0); 1006119#L346-2 is_master_triggered_~__retres1~0#1 := 0; 1006120#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1005825#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1005826#L861 assume !(0 != activate_threads_~tmp~1#1); 1006720#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1005941#L365 assume !(1 == ~t1_pc~0); 1005942#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1006540#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1006542#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1005932#L869 assume !(0 != activate_threads_~tmp___0~0#1); 1005933#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1006395#L384 assume !(1 == ~t2_pc~0); 1006385#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1006386#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1006711#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1005846#L877 assume !(0 != activate_threads_~tmp___1~0#1); 1005847#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1006209#L403 assume !(1 == ~t3_pc~0); 1006210#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1006434#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1006063#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1006064#L885 assume !(0 != activate_threads_~tmp___2~0#1); 1006198#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1006199#L422 assume !(1 == ~t4_pc~0); 1006556#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1006702#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1006701#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1006700#L893 assume !(0 != activate_threads_~tmp___3~0#1); 1006301#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1005866#L441 assume !(1 == ~t5_pc~0); 1005867#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1006697#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1006591#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1006592#L901 assume !(0 != activate_threads_~tmp___4~0#1); 1006673#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1006691#L460 assume !(1 == ~t6_pc~0); 1006689#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1006688#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1006687#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1006686#L909 assume !(0 != activate_threads_~tmp___5~0#1); 1006685#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1006684#L774 assume !(1 == ~M_E~0); 1006683#L774-2 assume !(1 == ~T1_E~0); 1006682#L779-1 assume !(1 == ~T2_E~0); 1006681#L784-1 assume !(1 == ~T3_E~0); 1006680#L789-1 assume !(1 == ~T4_E~0); 1006679#L794-1 assume !(1 == ~T5_E~0); 1006678#L799-1 assume !(1 == ~T6_E~0); 1006677#L804-1 assume !(1 == ~E_M~0); 1006676#L809-1 assume !(1 == ~E_1~0); 1006675#L814-1 assume !(1 == ~E_2~0); 1005827#L819-1 assume 1 == ~E_3~0;~E_3~0 := 2; 1005828#L824-1 assume !(1 == ~E_4~0); 1006339#L829-1 assume !(1 == ~E_5~0); 1006466#L834-1 assume !(1 == ~E_6~0); 1006055#L839-1 assume { :end_inline_reset_delta_events } true; 1006056#L1065-2 [2022-07-14 16:02:49,233 INFO L754 eck$LassoCheckResult]: Loop: 1006056#L1065-2 assume !false; 1046721#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1038655#L671 assume !false; 1046718#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1046711#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1046705#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1046701#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1046697#L582 assume !(0 != eval_~tmp~0#1); 1046693#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1046692#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1046691#L696-3 assume !(0 == ~M_E~0); 1046690#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1046688#L701-3 assume !(0 == ~T2_E~0); 1046687#L706-3 assume !(0 == ~T3_E~0); 1046686#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1046684#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1046683#L721-3 assume !(0 == ~T6_E~0); 1046682#L726-3 assume !(0 == ~E_M~0); 1046681#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1046680#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1046679#L741-3 assume !(0 == ~E_3~0); 1046678#L746-3 assume !(0 == ~E_4~0); 1046676#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1046674#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1046672#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1046670#L346-24 assume !(1 == ~m_pc~0); 1046668#L346-26 is_master_triggered_~__retres1~0#1 := 0; 1046666#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1046664#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1046662#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1046660#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1046658#L365-24 assume !(1 == ~t1_pc~0); 1046656#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 1046654#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1046652#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1046650#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1046648#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1046646#L384-24 assume !(1 == ~t2_pc~0); 1046644#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 1046640#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1046638#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1046636#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 1046634#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1046632#L403-24 assume !(1 == ~t3_pc~0); 1046630#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 1046628#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1046626#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1046624#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1046622#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1046620#L422-24 assume !(1 == ~t4_pc~0); 1046618#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 1046616#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1046614#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1046612#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1046610#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1046608#L441-24 assume 1 == ~t5_pc~0; 1046606#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1046607#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1046685#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1046595#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1046592#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1046590#L460-24 assume !(1 == ~t6_pc~0); 1046588#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 1046586#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1046584#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1046582#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1046580#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1046578#L774-3 assume !(1 == ~M_E~0); 1046321#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1046576#L779-3 assume !(1 == ~T2_E~0); 1046574#L784-3 assume !(1 == ~T3_E~0); 1046572#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1046570#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1046568#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1046566#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1046564#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1046562#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1046559#L819-3 assume !(1 == ~E_3~0); 1046558#L824-3 assume !(1 == ~E_4~0); 1046557#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1046556#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1046555#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1046553#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1046546#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1046545#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1046543#L1084 assume !(0 == start_simulation_~tmp~3#1); 1046544#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1046739#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1046735#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1046732#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 1046730#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1046728#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1046726#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1046724#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 1006056#L1065-2 [2022-07-14 16:02:49,234 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:49,234 INFO L85 PathProgramCache]: Analyzing trace with hash -1576815991, now seen corresponding path program 1 times [2022-07-14 16:02:49,234 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:49,234 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [386269978] [2022-07-14 16:02:49,235 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:49,235 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:49,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:49,261 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:49,262 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:49,262 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [386269978] [2022-07-14 16:02:49,262 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [386269978] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:49,262 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:49,262 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:49,262 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1495975331] [2022-07-14 16:02:49,263 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:49,263 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:49,263 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:49,263 INFO L85 PathProgramCache]: Analyzing trace with hash -1691470083, now seen corresponding path program 1 times [2022-07-14 16:02:49,263 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:49,264 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1972412708] [2022-07-14 16:02:49,264 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:49,264 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:49,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:49,298 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:49,298 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:49,298 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1972412708] [2022-07-14 16:02:49,299 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1972412708] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:49,299 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:49,299 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:02:49,299 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [45271485] [2022-07-14 16:02:49,299 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:49,299 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:49,300 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:49,300 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:02:49,300 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:02:49,300 INFO L87 Difference]: Start difference. First operand 66351 states and 92832 transitions. cyclomatic complexity: 26497 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:49,587 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:49,587 INFO L93 Difference]: Finished difference Result 90753 states and 126954 transitions. [2022-07-14 16:02:49,587 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:02:49,588 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 90753 states and 126954 transitions. [2022-07-14 16:02:50,526 INFO L131 ngComponentsAnalysis]: Automaton has 40 accepting balls. 87188 [2022-07-14 16:02:50,747 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 90753 states to 90753 states and 126954 transitions. [2022-07-14 16:02:50,747 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 90753 [2022-07-14 16:02:50,807 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 90753 [2022-07-14 16:02:50,807 INFO L73 IsDeterministic]: Start isDeterministic. Operand 90753 states and 126954 transitions. [2022-07-14 16:02:50,856 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:50,857 INFO L369 hiAutomatonCegarLoop]: Abstraction has 90753 states and 126954 transitions. [2022-07-14 16:02:50,909 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90753 states and 126954 transitions. [2022-07-14 16:02:51,474 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90753 to 64015. [2022-07-14 16:02:51,525 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 64015 states, 64015 states have (on average 1.3985159728188705) internal successors, (89526), 64014 states have internal predecessors, (89526), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:51,628 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64015 states to 64015 states and 89526 transitions. [2022-07-14 16:02:51,628 INFO L392 hiAutomatonCegarLoop]: Abstraction has 64015 states and 89526 transitions. [2022-07-14 16:02:51,628 INFO L374 stractBuchiCegarLoop]: Abstraction has 64015 states and 89526 transitions. [2022-07-14 16:02:51,628 INFO L287 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-07-14 16:02:51,628 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 64015 states and 89526 transitions. [2022-07-14 16:02:52,135 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 63486 [2022-07-14 16:02:52,136 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:52,136 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:52,137 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:52,137 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:52,137 INFO L752 eck$LassoCheckResult]: Stem: 1163755#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1163681#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1163625#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1163543#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1163544#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 1163160#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1163161#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1163011#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1163012#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1162980#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1162981#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1163139#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1163304#L696 assume !(0 == ~M_E~0); 1163305#L696-2 assume !(0 == ~T1_E~0); 1163650#L701-1 assume !(0 == ~T2_E~0); 1163654#L706-1 assume !(0 == ~T3_E~0); 1163424#L711-1 assume !(0 == ~T4_E~0); 1163195#L716-1 assume !(0 == ~T5_E~0); 1163196#L721-1 assume !(0 == ~T6_E~0); 1163378#L726-1 assume !(0 == ~E_M~0); 1163379#L731-1 assume !(0 == ~E_1~0); 1163345#L736-1 assume !(0 == ~E_2~0); 1163346#L741-1 assume !(0 == ~E_3~0); 1163431#L746-1 assume !(0 == ~E_4~0); 1163226#L751-1 assume !(0 == ~E_5~0); 1163227#L756-1 assume !(0 == ~E_6~0); 1163192#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1163027#L346 assume !(1 == ~m_pc~0); 1163028#L346-2 is_master_triggered_~__retres1~0#1 := 0; 1163238#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1162941#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1162942#L861 assume !(0 != activate_threads_~tmp~1#1); 1163604#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1163058#L365 assume !(1 == ~t1_pc~0); 1163059#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1163624#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1163626#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1163049#L869 assume !(0 != activate_threads_~tmp___0~0#1); 1163050#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1163494#L384 assume !(1 == ~t2_pc~0); 1163484#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1163485#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1163136#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1162962#L877 assume !(0 != activate_threads_~tmp___1~0#1); 1162963#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1163323#L403 assume !(1 == ~t3_pc~0); 1163324#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1163538#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1163182#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1163183#L885 assume !(0 != activate_threads_~tmp___2~0#1); 1163314#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1163315#L422 assume !(1 == ~t4_pc~0); 1163444#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1163445#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1163490#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1163491#L893 assume !(0 != activate_threads_~tmp___3~0#1); 1163408#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1162982#L441 assume !(1 == ~t5_pc~0); 1162983#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1163597#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1163683#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1163684#L901 assume !(0 != activate_threads_~tmp___4~0#1); 1163415#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1163416#L460 assume !(1 == ~t6_pc~0); 1163562#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1162989#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1162990#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1163557#L909 assume !(0 != activate_threads_~tmp___5~0#1); 1163558#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1163389#L774 assume !(1 == ~M_E~0); 1163390#L774-2 assume !(1 == ~T1_E~0); 1163575#L779-1 assume !(1 == ~T2_E~0); 1163285#L784-1 assume !(1 == ~T3_E~0); 1163286#L789-1 assume !(1 == ~T4_E~0); 1163042#L794-1 assume !(1 == ~T5_E~0); 1163043#L799-1 assume !(1 == ~T6_E~0); 1163700#L804-1 assume !(1 == ~E_M~0); 1163701#L809-1 assume !(1 == ~E_1~0); 1163373#L814-1 assume !(1 == ~E_2~0); 1162943#L819-1 assume !(1 == ~E_3~0); 1162944#L824-1 assume !(1 == ~E_4~0); 1163441#L829-1 assume !(1 == ~E_5~0); 1163565#L834-1 assume !(1 == ~E_6~0); 1163174#L839-1 assume { :end_inline_reset_delta_events } true; 1163175#L1065-2 [2022-07-14 16:02:52,138 INFO L754 eck$LassoCheckResult]: Loop: 1163175#L1065-2 assume !false; 1187689#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1187671#L671 assume !false; 1187664#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1187652#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1187637#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1187628#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1187620#L582 assume !(0 != eval_~tmp~0#1); 1187613#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1187608#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1187604#L696-3 assume !(0 == ~M_E~0); 1187591#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1187587#L701-3 assume !(0 == ~T2_E~0); 1187005#L706-3 assume !(0 == ~T3_E~0); 1187003#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1187001#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1186999#L721-3 assume !(0 == ~T6_E~0); 1186997#L726-3 assume !(0 == ~E_M~0); 1186995#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1186934#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1186931#L741-3 assume !(0 == ~E_3~0); 1186928#L746-3 assume !(0 == ~E_4~0); 1186925#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1186922#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1186919#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1186916#L346-24 assume !(1 == ~m_pc~0); 1186913#L346-26 is_master_triggered_~__retres1~0#1 := 0; 1186910#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1186907#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1186904#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1186901#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1186898#L365-24 assume !(1 == ~t1_pc~0); 1186895#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 1186890#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1186885#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1186880#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1186875#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1186872#L384-24 assume 1 == ~t2_pc~0; 1186866#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1186861#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1186858#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1186855#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 1186852#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1186849#L403-24 assume !(1 == ~t3_pc~0); 1186846#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 1186845#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1186842#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1186839#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1186836#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1186833#L422-24 assume !(1 == ~t4_pc~0); 1186830#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 1186827#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1186824#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1186821#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1186818#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1186816#L441-24 assume !(1 == ~t5_pc~0); 1186814#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 1186811#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1186808#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1186799#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 1186796#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1186739#L460-24 assume !(1 == ~t6_pc~0); 1186736#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 1186733#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1186730#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1186727#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1186724#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1186721#L774-3 assume !(1 == ~M_E~0); 1186571#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1186716#L779-3 assume !(1 == ~T2_E~0); 1186712#L784-3 assume !(1 == ~T3_E~0); 1186708#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1186704#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1186700#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1186696#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1186692#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1186688#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1186684#L819-3 assume !(1 == ~E_3~0); 1186680#L824-3 assume !(1 == ~E_4~0); 1186677#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1186674#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1186670#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1186665#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1186651#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1186648#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1186588#L1084 assume !(0 == start_simulation_~tmp~3#1); 1174889#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1174751#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1174740#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1174741#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 1187769#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1187754#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1187742#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1187731#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 1163175#L1065-2 [2022-07-14 16:02:52,138 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:52,138 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 3 times [2022-07-14 16:02:52,138 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:52,139 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2114015242] [2022-07-14 16:02:52,139 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:52,139 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:52,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:52,148 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:02:52,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:52,169 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:02:52,170 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:52,170 INFO L85 PathProgramCache]: Analyzing trace with hash 562295999, now seen corresponding path program 1 times [2022-07-14 16:02:52,171 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:52,171 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [781042429] [2022-07-14 16:02:52,171 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:52,171 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:52,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:52,196 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:52,197 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:52,197 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [781042429] [2022-07-14 16:02:52,197 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [781042429] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:52,197 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:52,197 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:02:52,199 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [439427033] [2022-07-14 16:02:52,199 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:52,199 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:52,199 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:52,200 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-07-14 16:02:52,200 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-07-14 16:02:52,200 INFO L87 Difference]: Start difference. First operand 64015 states and 89526 transitions. cyclomatic complexity: 25527 Second operand has 5 states, 5 states have (on average 18.8) internal successors, (94), 5 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:52,601 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:52,601 INFO L93 Difference]: Finished difference Result 113123 states and 156492 transitions. [2022-07-14 16:02:52,602 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-07-14 16:02:52,602 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 113123 states and 156492 transitions. [2022-07-14 16:02:53,124 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 112154 [2022-07-14 16:02:53,462 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 113123 states to 113123 states and 156492 transitions. [2022-07-14 16:02:53,462 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 113123 [2022-07-14 16:02:53,544 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 113123 [2022-07-14 16:02:53,544 INFO L73 IsDeterministic]: Start isDeterministic. Operand 113123 states and 156492 transitions. [2022-07-14 16:02:53,616 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:53,616 INFO L369 hiAutomatonCegarLoop]: Abstraction has 113123 states and 156492 transitions. [2022-07-14 16:02:53,681 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 113123 states and 156492 transitions. [2022-07-14 16:02:54,794 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 113123 to 64555. [2022-07-14 16:02:54,843 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 64555 states, 64555 states have (on average 1.395182402602432) internal successors, (90066), 64554 states have internal predecessors, (90066), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:54,952 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64555 states to 64555 states and 90066 transitions. [2022-07-14 16:02:54,952 INFO L392 hiAutomatonCegarLoop]: Abstraction has 64555 states and 90066 transitions. [2022-07-14 16:02:54,952 INFO L374 stractBuchiCegarLoop]: Abstraction has 64555 states and 90066 transitions. [2022-07-14 16:02:54,952 INFO L287 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-07-14 16:02:54,952 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 64555 states and 90066 transitions. [2022-07-14 16:02:55,130 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 64026 [2022-07-14 16:02:55,130 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:55,130 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:55,131 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:55,131 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:55,132 INFO L752 eck$LassoCheckResult]: Stem: 1340937#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1340861#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1340803#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1340719#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1340720#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 1340311#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1340312#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1340165#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1340166#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1340133#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1340134#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1340290#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1340459#L696 assume !(0 == ~M_E~0); 1340460#L696-2 assume !(0 == ~T1_E~0); 1340831#L701-1 assume !(0 == ~T2_E~0); 1340832#L706-1 assume !(0 == ~T3_E~0); 1340586#L711-1 assume !(0 == ~T4_E~0); 1340344#L716-1 assume !(0 == ~T5_E~0); 1340345#L721-1 assume !(0 == ~T6_E~0); 1340530#L726-1 assume !(0 == ~E_M~0); 1340531#L731-1 assume !(0 == ~E_1~0); 1340496#L736-1 assume !(0 == ~E_2~0); 1340497#L741-1 assume !(0 == ~E_3~0); 1340592#L746-1 assume !(0 == ~E_4~0); 1340376#L751-1 assume !(0 == ~E_5~0); 1340377#L756-1 assume !(0 == ~E_6~0); 1340341#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1340179#L346 assume !(1 == ~m_pc~0); 1340180#L346-2 is_master_triggered_~__retres1~0#1 := 0; 1340388#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1340097#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1340098#L861 assume !(0 != activate_threads_~tmp~1#1); 1340782#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1340212#L365 assume !(1 == ~t1_pc~0); 1340213#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1340801#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1340807#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1340201#L869 assume !(0 != activate_threads_~tmp___0~0#1); 1340202#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1340657#L384 assume !(1 == ~t2_pc~0); 1340650#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1340651#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1340289#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1340118#L877 assume !(0 != activate_threads_~tmp___1~0#1); 1340119#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1340476#L403 assume !(1 == ~t3_pc~0); 1340477#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1340714#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1340336#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1340337#L885 assume !(0 != activate_threads_~tmp___2~0#1); 1340468#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1340469#L422 assume !(1 == ~t4_pc~0); 1340608#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1340609#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1340655#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1340656#L893 assume !(0 != activate_threads_~tmp___3~0#1); 1340564#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1340135#L441 assume !(1 == ~t5_pc~0); 1340136#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1340778#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1340863#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1340864#L901 assume !(0 != activate_threads_~tmp___4~0#1); 1340578#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1340579#L460 assume !(1 == ~t6_pc~0); 1340740#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1340144#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1340145#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1340735#L909 assume !(0 != activate_threads_~tmp___5~0#1); 1340736#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1340543#L774 assume !(1 == ~M_E~0); 1340544#L774-2 assume !(1 == ~T1_E~0); 1340752#L779-1 assume !(1 == ~T2_E~0); 1340435#L784-1 assume !(1 == ~T3_E~0); 1340436#L789-1 assume !(1 == ~T4_E~0); 1340195#L794-1 assume !(1 == ~T5_E~0); 1340196#L799-1 assume !(1 == ~T6_E~0); 1340888#L804-1 assume !(1 == ~E_M~0); 1340889#L809-1 assume !(1 == ~E_1~0); 1340527#L814-1 assume !(1 == ~E_2~0); 1340099#L819-1 assume !(1 == ~E_3~0); 1340100#L824-1 assume !(1 == ~E_4~0); 1340603#L829-1 assume !(1 == ~E_5~0); 1340743#L834-1 assume !(1 == ~E_6~0); 1340327#L839-1 assume { :end_inline_reset_delta_events } true; 1340328#L1065-2 [2022-07-14 16:02:55,132 INFO L754 eck$LassoCheckResult]: Loop: 1340328#L1065-2 assume !false; 1368545#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1368543#L671 assume !false; 1368542#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1368540#L530 assume !(0 == ~m_st~0); 1368541#L534 assume !(0 == ~t1_st~0); 1368536#L538 assume !(0 == ~t2_st~0); 1368537#L542 assume !(0 == ~t3_st~0); 1368539#L546 assume !(0 == ~t4_st~0); 1368534#L550 assume !(0 == ~t5_st~0); 1368535#L554 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 1368538#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1368418#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1368419#L582 assume !(0 != eval_~tmp~0#1); 1368753#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1368751#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1368749#L696-3 assume !(0 == ~M_E~0); 1368747#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1368745#L701-3 assume !(0 == ~T2_E~0); 1368743#L706-3 assume !(0 == ~T3_E~0); 1368741#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1368739#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1368737#L721-3 assume !(0 == ~T6_E~0); 1368735#L726-3 assume !(0 == ~E_M~0); 1368733#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1368731#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1368729#L741-3 assume !(0 == ~E_3~0); 1368727#L746-3 assume !(0 == ~E_4~0); 1368725#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1368723#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1368721#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1368719#L346-24 assume !(1 == ~m_pc~0); 1368717#L346-26 is_master_triggered_~__retres1~0#1 := 0; 1368715#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1368713#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1368711#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1368709#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1368707#L365-24 assume !(1 == ~t1_pc~0); 1368705#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 1368703#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1368701#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1368699#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1368697#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1368695#L384-24 assume 1 == ~t2_pc~0; 1368692#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1368689#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1368687#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1368685#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 1368683#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1368681#L403-24 assume !(1 == ~t3_pc~0); 1368679#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 1368677#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1368675#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1368673#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1368671#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1368669#L422-24 assume !(1 == ~t4_pc~0); 1368667#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 1368665#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1368663#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1368661#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1368659#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1368657#L441-24 assume 1 == ~t5_pc~0; 1368654#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1368650#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1368646#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1368642#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1368639#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1368637#L460-24 assume !(1 == ~t6_pc~0); 1368635#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 1368633#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1368631#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1368629#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1368627#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1368625#L774-3 assume !(1 == ~M_E~0); 1368622#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1368621#L779-3 assume !(1 == ~T2_E~0); 1368620#L784-3 assume !(1 == ~T3_E~0); 1368619#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1368618#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1368617#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1368616#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1368615#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1368614#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1368613#L819-3 assume !(1 == ~E_3~0); 1368612#L824-3 assume !(1 == ~E_4~0); 1368611#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1368610#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1368609#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1368607#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1368598#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1368595#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1368592#L1084 assume !(0 == start_simulation_~tmp~3#1); 1368589#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1368584#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1368579#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1368577#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 1368575#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1368562#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1368555#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1368551#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 1340328#L1065-2 [2022-07-14 16:02:55,132 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:55,133 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 4 times [2022-07-14 16:02:55,133 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:55,133 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1915201013] [2022-07-14 16:02:55,133 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:55,133 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:55,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:55,141 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:02:55,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:55,161 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:02:55,162 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:55,162 INFO L85 PathProgramCache]: Analyzing trace with hash 95138891, now seen corresponding path program 1 times [2022-07-14 16:02:55,162 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:55,162 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1603815095] [2022-07-14 16:02:55,162 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:55,163 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:55,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:55,188 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:55,188 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:55,188 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1603815095] [2022-07-14 16:02:55,189 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1603815095] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:55,189 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:55,189 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:02:55,189 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [262756109] [2022-07-14 16:02:55,189 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:55,189 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:55,190 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:55,190 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-07-14 16:02:55,190 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-07-14 16:02:55,190 INFO L87 Difference]: Start difference. First operand 64555 states and 90066 transitions. cyclomatic complexity: 25527 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:55,628 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:55,628 INFO L93 Difference]: Finished difference Result 126464 states and 174868 transitions. [2022-07-14 16:02:55,628 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-07-14 16:02:55,629 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 126464 states and 174868 transitions. [2022-07-14 16:02:56,776 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 125448 [2022-07-14 16:02:57,092 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 126464 states to 126464 states and 174868 transitions. [2022-07-14 16:02:57,092 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 126464 [2022-07-14 16:02:57,181 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 126464 [2022-07-14 16:02:57,181 INFO L73 IsDeterministic]: Start isDeterministic. Operand 126464 states and 174868 transitions. [2022-07-14 16:02:57,254 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:57,254 INFO L369 hiAutomatonCegarLoop]: Abstraction has 126464 states and 174868 transitions. [2022-07-14 16:02:57,322 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126464 states and 174868 transitions. [2022-07-14 16:02:57,888 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126464 to 67162. [2022-07-14 16:02:58,461 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 67162 states, 67162 states have (on average 1.379842768232036) internal successors, (92673), 67161 states have internal predecessors, (92673), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:58,603 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67162 states to 67162 states and 92673 transitions. [2022-07-14 16:02:58,603 INFO L392 hiAutomatonCegarLoop]: Abstraction has 67162 states and 92673 transitions. [2022-07-14 16:02:58,603 INFO L374 stractBuchiCegarLoop]: Abstraction has 67162 states and 92673 transitions. [2022-07-14 16:02:58,603 INFO L287 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2022-07-14 16:02:58,603 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 67162 states and 92673 transitions. [2022-07-14 16:02:58,784 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 66630 [2022-07-14 16:02:58,785 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:58,785 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:58,786 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:58,786 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:58,786 INFO L752 eck$LassoCheckResult]: Stem: 1532002#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1531909#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1531847#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1531752#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1531753#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 1531350#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1531351#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1531197#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1531198#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1531166#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1531167#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1531327#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1531498#L696 assume !(0 == ~M_E~0); 1531499#L696-2 assume !(0 == ~T1_E~0); 1531872#L701-1 assume !(0 == ~T2_E~0); 1531874#L706-1 assume !(0 == ~T3_E~0); 1531626#L711-1 assume !(0 == ~T4_E~0); 1531384#L716-1 assume !(0 == ~T5_E~0); 1531385#L721-1 assume !(0 == ~T6_E~0); 1531571#L726-1 assume !(0 == ~E_M~0); 1531572#L731-1 assume !(0 == ~E_1~0); 1531538#L736-1 assume !(0 == ~E_2~0); 1531539#L741-1 assume !(0 == ~E_3~0); 1531635#L746-1 assume !(0 == ~E_4~0); 1531417#L751-1 assume !(0 == ~E_5~0); 1531418#L756-1 assume !(0 == ~E_6~0); 1531381#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1531212#L346 assume !(1 == ~m_pc~0); 1531213#L346-2 is_master_triggered_~__retres1~0#1 := 0; 1531428#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1531128#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1531129#L861 assume !(0 != activate_threads_~tmp~1#1); 1531822#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1531242#L365 assume !(1 == ~t1_pc~0); 1531243#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1531846#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1531848#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1531233#L869 assume !(0 != activate_threads_~tmp___0~0#1); 1531234#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1531702#L384 assume !(1 == ~t2_pc~0); 1531692#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1531693#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1531323#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1531324#L877 assume !(0 != activate_threads_~tmp___1~0#1); 1531150#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1531517#L403 assume !(1 == ~t3_pc~0); 1531518#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1531745#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1531371#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1531372#L885 assume !(0 != activate_threads_~tmp___2~0#1); 1531507#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1531508#L422 assume !(1 == ~t4_pc~0); 1531651#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1531652#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1531698#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1531699#L893 assume !(0 != activate_threads_~tmp___3~0#1); 1531608#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1531168#L441 assume !(1 == ~t5_pc~0); 1531169#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1531817#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1531912#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1531913#L901 assume !(0 != activate_threads_~tmp___4~0#1); 1531616#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1531617#L460 assume !(1 == ~t6_pc~0); 1531775#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1531175#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1531176#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1531769#L909 assume !(0 != activate_threads_~tmp___5~0#1); 1531770#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1531587#L774 assume !(1 == ~M_E~0); 1531588#L774-2 assume !(1 == ~T1_E~0); 1531791#L779-1 assume !(1 == ~T2_E~0); 1531476#L784-1 assume !(1 == ~T3_E~0); 1531477#L789-1 assume !(1 == ~T4_E~0); 1531227#L794-1 assume !(1 == ~T5_E~0); 1531228#L799-1 assume !(1 == ~T6_E~0); 1531944#L804-1 assume !(1 == ~E_M~0); 1531945#L809-1 assume !(1 == ~E_1~0); 1531568#L814-1 assume !(1 == ~E_2~0); 1531130#L819-1 assume !(1 == ~E_3~0); 1531131#L824-1 assume !(1 == ~E_4~0); 1531646#L829-1 assume !(1 == ~E_5~0); 1531778#L834-1 assume !(1 == ~E_6~0); 1531363#L839-1 assume { :end_inline_reset_delta_events } true; 1531364#L1065-2 [2022-07-14 16:02:58,786 INFO L754 eck$LassoCheckResult]: Loop: 1531364#L1065-2 assume !false; 1597227#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1568424#L671 assume !false; 1597167#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1596502#L530 assume !(0 == ~m_st~0); 1596503#L534 assume !(0 == ~t1_st~0); 1596499#L538 assume !(0 == ~t2_st~0); 1596500#L542 assume !(0 == ~t3_st~0); 1596501#L546 assume !(0 == ~t4_st~0); 1596496#L550 assume !(0 == ~t5_st~0); 1596498#L554 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 1596495#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1595082#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1595083#L582 assume !(0 != eval_~tmp~0#1); 1598102#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1598100#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1598098#L696-3 assume !(0 == ~M_E~0); 1598096#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1598094#L701-3 assume !(0 == ~T2_E~0); 1598092#L706-3 assume !(0 == ~T3_E~0); 1598090#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1598088#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1598086#L721-3 assume !(0 == ~T6_E~0); 1598084#L726-3 assume !(0 == ~E_M~0); 1598082#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1598080#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1598078#L741-3 assume !(0 == ~E_3~0); 1598076#L746-3 assume !(0 == ~E_4~0); 1598074#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1598072#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1598070#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1598068#L346-24 assume !(1 == ~m_pc~0); 1598066#L346-26 is_master_triggered_~__retres1~0#1 := 0; 1598057#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1598054#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1598051#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1598048#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1598045#L365-24 assume !(1 == ~t1_pc~0); 1598042#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 1598039#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1598036#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1598033#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1598031#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1598030#L384-24 assume !(1 == ~t2_pc~0); 1598028#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 1598026#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1598024#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1598022#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 1598011#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1598009#L403-24 assume !(1 == ~t3_pc~0); 1598007#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 1598005#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1598003#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1598001#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1597998#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1597988#L422-24 assume !(1 == ~t4_pc~0); 1597985#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 1597982#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1597980#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1597977#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1597974#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1597971#L441-24 assume 1 == ~t5_pc~0; 1597967#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1597962#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1597957#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1597952#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1597948#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1597945#L460-24 assume !(1 == ~t6_pc~0); 1597942#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 1597939#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1597936#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1597933#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1597930#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1597926#L774-3 assume !(1 == ~M_E~0); 1597922#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1597653#L779-3 assume !(1 == ~T2_E~0); 1597652#L784-3 assume !(1 == ~T3_E~0); 1597651#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1597648#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1597646#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1597644#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1597642#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1597640#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1597638#L819-3 assume !(1 == ~E_3~0); 1597636#L824-3 assume !(1 == ~E_4~0); 1597634#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1597632#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1597630#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1597573#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1597563#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1597558#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1597554#L1084 assume !(0 == start_simulation_~tmp~3#1); 1597287#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1597267#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1597263#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1597261#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 1597259#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1597257#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1597255#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1597253#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 1531364#L1065-2 [2022-07-14 16:02:58,787 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:58,787 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 5 times [2022-07-14 16:02:58,787 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:58,787 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [376853685] [2022-07-14 16:02:58,787 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:58,788 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:58,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:58,810 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:02:58,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:02:58,838 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:02:58,839 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:58,839 INFO L85 PathProgramCache]: Analyzing trace with hash 335406220, now seen corresponding path program 1 times [2022-07-14 16:02:58,839 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:58,839 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1024445217] [2022-07-14 16:02:58,839 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:58,840 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:58,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:58,900 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:58,900 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:58,901 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1024445217] [2022-07-14 16:02:58,901 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1024445217] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:58,901 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:58,901 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:02:58,901 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [608580348] [2022-07-14 16:02:58,901 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:58,902 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:58,902 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:58,903 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-07-14 16:02:58,903 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-07-14 16:02:58,903 INFO L87 Difference]: Start difference. First operand 67162 states and 92673 transitions. cyclomatic complexity: 25527 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:59,355 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:59,355 INFO L93 Difference]: Finished difference Result 119258 states and 163636 transitions. [2022-07-14 16:02:59,356 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-07-14 16:02:59,356 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 119258 states and 163636 transitions. [2022-07-14 16:02:59,864 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 118598 [2022-07-14 16:03:00,770 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 119258 states to 119258 states and 163636 transitions. [2022-07-14 16:03:00,771 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 119258 [2022-07-14 16:03:00,841 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 119258 [2022-07-14 16:03:00,841 INFO L73 IsDeterministic]: Start isDeterministic. Operand 119258 states and 163636 transitions. [2022-07-14 16:03:00,899 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:00,899 INFO L369 hiAutomatonCegarLoop]: Abstraction has 119258 states and 163636 transitions. [2022-07-14 16:03:00,953 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 119258 states and 163636 transitions. [2022-07-14 16:03:01,634 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 119258 to 68266. [2022-07-14 16:03:01,692 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 68266 states, 68266 states have (on average 1.3663609996191368) internal successors, (93276), 68265 states have internal predecessors, (93276), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:01,809 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68266 states to 68266 states and 93276 transitions. [2022-07-14 16:03:01,809 INFO L392 hiAutomatonCegarLoop]: Abstraction has 68266 states and 93276 transitions. [2022-07-14 16:03:01,809 INFO L374 stractBuchiCegarLoop]: Abstraction has 68266 states and 93276 transitions. [2022-07-14 16:03:01,809 INFO L287 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2022-07-14 16:03:01,810 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 68266 states and 93276 transitions. [2022-07-14 16:03:02,007 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 67734 [2022-07-14 16:03:02,007 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:02,007 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:02,008 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:02,008 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:02,009 INFO L752 eck$LassoCheckResult]: Stem: 1718390#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1718315#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1718264#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1718180#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1718181#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 1717784#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1717785#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1717631#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1717632#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1717600#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1717601#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1717763#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1717932#L696 assume !(0 == ~M_E~0); 1717933#L696-2 assume !(0 == ~T1_E~0); 1718291#L701-1 assume !(0 == ~T2_E~0); 1718294#L706-1 assume !(0 == ~T3_E~0); 1718060#L711-1 assume !(0 == ~T4_E~0); 1717818#L716-1 assume !(0 == ~T5_E~0); 1717819#L721-1 assume !(0 == ~T6_E~0); 1718008#L726-1 assume !(0 == ~E_M~0); 1718009#L731-1 assume !(0 == ~E_1~0); 1717972#L736-1 assume !(0 == ~E_2~0); 1717973#L741-1 assume !(0 == ~E_3~0); 1718067#L746-1 assume !(0 == ~E_4~0); 1717853#L751-1 assume !(0 == ~E_5~0); 1717854#L756-1 assume !(0 == ~E_6~0); 1717815#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1717646#L346 assume !(1 == ~m_pc~0); 1717647#L346-2 is_master_triggered_~__retres1~0#1 := 0; 1717865#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1717561#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1717562#L861 assume !(0 != activate_threads_~tmp~1#1); 1718246#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1717676#L365 assume !(1 == ~t1_pc~0); 1717677#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1718263#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1718265#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1717667#L869 assume !(0 != activate_threads_~tmp___0~0#1); 1717668#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1718131#L384 assume !(1 == ~t2_pc~0); 1718121#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1718122#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1718409#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1718408#L877 assume !(0 != activate_threads_~tmp___1~0#1); 1717583#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1717950#L403 assume !(1 == ~t3_pc~0); 1717951#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1718173#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1717806#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1717807#L885 assume !(0 != activate_threads_~tmp___2~0#1); 1717941#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1717942#L422 assume !(1 == ~t4_pc~0); 1718083#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1718084#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1718127#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1718128#L893 assume !(0 != activate_threads_~tmp___3~0#1); 1718040#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1717602#L441 assume !(1 == ~t5_pc~0); 1717603#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1718240#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1718317#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1718318#L901 assume !(0 != activate_threads_~tmp___4~0#1); 1718050#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1718051#L460 assume !(1 == ~t6_pc~0); 1718199#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1717609#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1717610#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1718194#L909 assume !(0 != activate_threads_~tmp___5~0#1); 1718195#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1718019#L774 assume !(1 == ~M_E~0); 1718020#L774-2 assume !(1 == ~T1_E~0); 1718217#L779-1 assume !(1 == ~T2_E~0); 1717914#L784-1 assume !(1 == ~T3_E~0); 1717915#L789-1 assume !(1 == ~T4_E~0); 1717661#L794-1 assume !(1 == ~T5_E~0); 1717662#L799-1 assume !(1 == ~T6_E~0); 1718340#L804-1 assume !(1 == ~E_M~0); 1718341#L809-1 assume !(1 == ~E_1~0); 1718004#L814-1 assume !(1 == ~E_2~0); 1717563#L819-1 assume !(1 == ~E_3~0); 1717564#L824-1 assume !(1 == ~E_4~0); 1718077#L829-1 assume !(1 == ~E_5~0); 1718202#L834-1 assume !(1 == ~E_6~0); 1717798#L839-1 assume { :end_inline_reset_delta_events } true; 1717799#L1065-2 [2022-07-14 16:03:02,009 INFO L754 eck$LassoCheckResult]: Loop: 1717799#L1065-2 assume !false; 1728754#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1742334#L671 assume !false; 1742333#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1742332#L530 assume !(0 == ~m_st~0); 1742331#L534 assume !(0 == ~t1_st~0); 1742330#L538 assume !(0 == ~t2_st~0); 1742329#L542 assume !(0 == ~t3_st~0); 1742328#L546 assume !(0 == ~t4_st~0); 1742327#L550 assume !(0 == ~t5_st~0); 1742325#L554 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 1742324#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1742323#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1742322#L582 assume !(0 != eval_~tmp~0#1); 1742321#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1742320#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1742319#L696-3 assume !(0 == ~M_E~0); 1742318#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1742317#L701-3 assume !(0 == ~T2_E~0); 1742316#L706-3 assume !(0 == ~T3_E~0); 1742315#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1742314#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1742313#L721-3 assume !(0 == ~T6_E~0); 1742312#L726-3 assume !(0 == ~E_M~0); 1742311#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1742310#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1742309#L741-3 assume !(0 == ~E_3~0); 1742308#L746-3 assume !(0 == ~E_4~0); 1742307#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1742306#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1742305#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1742304#L346-24 assume !(1 == ~m_pc~0); 1742303#L346-26 is_master_triggered_~__retres1~0#1 := 0; 1742302#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1742301#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1742300#L861-24 assume !(0 != activate_threads_~tmp~1#1); 1742299#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1742298#L365-24 assume !(1 == ~t1_pc~0); 1742297#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 1742296#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1742295#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1742294#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1742293#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1742292#L384-24 assume 1 == ~t2_pc~0; 1742290#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1742291#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1734837#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1734838#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1742285#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1742284#L403-24 assume !(1 == ~t3_pc~0); 1742283#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 1742282#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1742281#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1742280#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1742279#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1742278#L422-24 assume !(1 == ~t4_pc~0); 1742277#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 1742276#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1742275#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1742274#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1742273#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1742272#L441-24 assume 1 == ~t5_pc~0; 1742270#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1742271#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1743309#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1742265#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1742264#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1742263#L460-24 assume !(1 == ~t6_pc~0); 1742262#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 1742261#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1742260#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1742259#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1742258#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1742257#L774-3 assume !(1 == ~M_E~0); 1742108#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1742256#L779-3 assume !(1 == ~T2_E~0); 1742255#L784-3 assume !(1 == ~T3_E~0); 1742254#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1742253#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1742252#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1742251#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1742250#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1742249#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1742248#L819-3 assume !(1 == ~E_3~0); 1742247#L824-3 assume !(1 == ~E_4~0); 1742246#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1742245#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1742244#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1742242#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1742236#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1742235#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1742234#L1084 assume !(0 == start_simulation_~tmp~3#1); 1728795#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1734696#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1728779#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1728780#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 1728773#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1728774#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1728764#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1728765#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 1717799#L1065-2 [2022-07-14 16:03:02,010 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:02,010 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 6 times [2022-07-14 16:03:02,010 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:02,010 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [244333966] [2022-07-14 16:03:02,010 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:02,010 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:02,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:02,019 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:03:02,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:02,040 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:03:02,040 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:02,041 INFO L85 PathProgramCache]: Analyzing trace with hash -2034941621, now seen corresponding path program 1 times [2022-07-14 16:03:02,041 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:02,041 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [355798215] [2022-07-14 16:03:02,041 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:02,041 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:02,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:02,062 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:02,062 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:02,063 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [355798215] [2022-07-14 16:03:02,063 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [355798215] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:02,063 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:02,063 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:02,063 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [725326795] [2022-07-14 16:03:02,063 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:02,064 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:02,064 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:02,065 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:02,065 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:02,065 INFO L87 Difference]: Start difference. First operand 68266 states and 93276 transitions. cyclomatic complexity: 25026 Second operand has 3 states, 3 states have (on average 33.333333333333336) internal successors, (100), 3 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:02,913 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:02,913 INFO L93 Difference]: Finished difference Result 104379 states and 140726 transitions. [2022-07-14 16:03:02,913 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:02,914 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 104379 states and 140726 transitions. [2022-07-14 16:03:03,376 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 103853 [2022-07-14 16:03:03,669 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 104379 states to 104379 states and 140726 transitions. [2022-07-14 16:03:03,669 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 104379 [2022-07-14 16:03:03,739 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 104379 [2022-07-14 16:03:03,739 INFO L73 IsDeterministic]: Start isDeterministic. Operand 104379 states and 140726 transitions. [2022-07-14 16:03:03,799 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:03,800 INFO L369 hiAutomatonCegarLoop]: Abstraction has 104379 states and 140726 transitions. [2022-07-14 16:03:03,861 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 104379 states and 140726 transitions. [2022-07-14 16:03:04,979 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 104379 to 101323. [2022-07-14 16:03:05,054 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 101323 states, 101323 states have (on average 1.3503548059177086) internal successors, (136822), 101322 states have internal predecessors, (136822), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:05,233 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101323 states to 101323 states and 136822 transitions. [2022-07-14 16:03:05,233 INFO L392 hiAutomatonCegarLoop]: Abstraction has 101323 states and 136822 transitions. [2022-07-14 16:03:05,233 INFO L374 stractBuchiCegarLoop]: Abstraction has 101323 states and 136822 transitions. [2022-07-14 16:03:05,233 INFO L287 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2022-07-14 16:03:05,233 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 101323 states and 136822 transitions. [2022-07-14 16:03:05,543 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 100797 [2022-07-14 16:03:05,544 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:05,544 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:05,544 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:05,544 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:05,546 INFO L752 eck$LassoCheckResult]: Stem: 1891048#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1890966#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1890917#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1890832#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1890833#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 1890431#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1890432#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1890282#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1890283#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1890249#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1890250#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1890410#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1890587#L696 assume !(0 == ~M_E~0); 1890588#L696-2 assume !(0 == ~T1_E~0); 1890948#L701-1 assume !(0 == ~T2_E~0); 1890949#L706-1 assume !(0 == ~T3_E~0); 1890711#L711-1 assume !(0 == ~T4_E~0); 1890466#L716-1 assume !(0 == ~T5_E~0); 1890467#L721-1 assume !(0 == ~T6_E~0); 1890661#L726-1 assume !(0 == ~E_M~0); 1890662#L731-1 assume !(0 == ~E_1~0); 1890623#L736-1 assume !(0 == ~E_2~0); 1890624#L741-1 assume !(0 == ~E_3~0); 1890717#L746-1 assume !(0 == ~E_4~0); 1890502#L751-1 assume !(0 == ~E_5~0); 1890503#L756-1 assume !(0 == ~E_6~0); 1890463#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1890296#L346 assume !(1 == ~m_pc~0); 1890297#L346-2 is_master_triggered_~__retres1~0#1 := 0; 1890514#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1890213#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1890214#L861 assume !(0 != activate_threads_~tmp~1#1); 1890897#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1890328#L365 assume !(1 == ~t1_pc~0); 1890329#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1890916#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1890922#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1890318#L869 assume !(0 != activate_threads_~tmp___0~0#1); 1890319#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1890785#L384 assume !(1 == ~t2_pc~0); 1890778#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1890779#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1891069#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1891068#L877 assume !(0 != activate_threads_~tmp___1~0#1); 1890235#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1890603#L403 assume !(1 == ~t3_pc~0); 1890604#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1890825#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1890458#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1890459#L885 assume !(0 != activate_threads_~tmp___2~0#1); 1890596#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1890597#L422 assume !(1 == ~t4_pc~0); 1890735#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1890736#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1890783#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1890784#L893 assume !(0 != activate_threads_~tmp___3~0#1); 1890694#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1890251#L441 assume !(1 == ~t5_pc~0); 1890252#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1890891#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1890968#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1890969#L901 assume !(0 != activate_threads_~tmp___4~0#1); 1890703#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1890704#L460 assume !(1 == ~t6_pc~0); 1890851#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1890260#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1890261#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1890846#L909 assume !(0 != activate_threads_~tmp___5~0#1); 1890847#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1890673#L774 assume !(1 == ~M_E~0); 1890674#L774-2 assume !(1 == ~T1_E~0); 1890864#L779-1 assume !(1 == ~T2_E~0); 1890562#L784-1 assume !(1 == ~T3_E~0); 1890563#L789-1 assume !(1 == ~T4_E~0); 1890312#L794-1 assume !(1 == ~T5_E~0); 1890313#L799-1 assume !(1 == ~T6_E~0); 1891002#L804-1 assume !(1 == ~E_M~0); 1891003#L809-1 assume !(1 == ~E_1~0); 1890656#L814-1 assume !(1 == ~E_2~0); 1890215#L819-1 assume !(1 == ~E_3~0); 1890216#L824-1 assume !(1 == ~E_4~0); 1890728#L829-1 assume !(1 == ~E_5~0); 1890854#L834-1 assume !(1 == ~E_6~0); 1890448#L839-1 assume { :end_inline_reset_delta_events } true; 1890449#L1065-2 assume !false; 1902184#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1902166#L671 [2022-07-14 16:03:05,546 INFO L754 eck$LassoCheckResult]: Loop: 1902166#L671 assume !false; 1902154#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1902143#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1902137#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1902131#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1902121#L582 assume 0 != eval_~tmp~0#1; 1902113#L582-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1902088#L590 assume !(0 != eval_~tmp_ndt_1~0#1); 1902089#L587 assume !(0 == ~t1_st~0); 1898836#L601 assume !(0 == ~t2_st~0); 1902250#L615 assume !(0 == ~t3_st~0); 1898086#L629 assume !(0 == ~t4_st~0); 1902189#L643 assume !(0 == ~t5_st~0); 1902182#L657 assume !(0 == ~t6_st~0); 1902166#L671 [2022-07-14 16:03:05,547 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:05,547 INFO L85 PathProgramCache]: Analyzing trace with hash -1771052117, now seen corresponding path program 1 times [2022-07-14 16:03:05,547 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:05,547 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1519561568] [2022-07-14 16:03:05,547 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:05,548 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:05,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:05,556 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:03:05,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:05,575 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:03:05,576 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:05,576 INFO L85 PathProgramCache]: Analyzing trace with hash -919284357, now seen corresponding path program 1 times [2022-07-14 16:03:05,576 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:05,576 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1214935743] [2022-07-14 16:03:05,576 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:05,576 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:05,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:05,580 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-14 16:03:05,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-14 16:03:05,582 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-14 16:03:05,584 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:05,584 INFO L85 PathProgramCache]: Analyzing trace with hash 743442341, now seen corresponding path program 1 times [2022-07-14 16:03:05,584 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:05,584 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [484265703] [2022-07-14 16:03:05,584 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:05,585 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:05,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:05,612 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:05,613 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:05,613 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [484265703] [2022-07-14 16:03:05,613 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [484265703] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:05,613 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:05,613 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:05,613 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1567974414] [2022-07-14 16:03:05,614 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:05,712 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:05,712 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:05,712 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:05,713 INFO L87 Difference]: Start difference. First operand 101323 states and 136822 transitions. cyclomatic complexity: 35529 Second operand has 3 states, 3 states have (on average 33.333333333333336) internal successors, (100), 3 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:06,206 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:06,206 INFO L93 Difference]: Finished difference Result 191882 states and 256741 transitions. [2022-07-14 16:03:06,206 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:06,207 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 191882 states and 256741 transitions. [2022-07-14 16:03:07,555 INFO L131 ngComponentsAnalysis]: Automaton has 54 accepting balls. 185306 [2022-07-14 16:03:07,919 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 191882 states to 191882 states and 256741 transitions. [2022-07-14 16:03:07,919 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 191882 [2022-07-14 16:03:07,992 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 191882 [2022-07-14 16:03:07,992 INFO L73 IsDeterministic]: Start isDeterministic. Operand 191882 states and 256741 transitions. [2022-07-14 16:03:08,065 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:08,066 INFO L369 hiAutomatonCegarLoop]: Abstraction has 191882 states and 256741 transitions. [2022-07-14 16:03:08,142 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 191882 states and 256741 transitions. [2022-07-14 16:03:10,066 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 191882 to 187317. [2022-07-14 16:03:10,215 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 187317 states, 187317 states have (on average 1.3401186224421702) internal successors, (251027), 187316 states have internal predecessors, (251027), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)