./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.11.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version f4b24e32 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.11.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 79f20a4b12634e812af836a5fe92e9d987e7766e2c28337c49504608346f2347 --- Real Ultimate output --- This is Ultimate 0.2.2-?-f4b24e3 [2022-07-14 16:02:55,673 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-07-14 16:02:55,675 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-07-14 16:02:55,703 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-07-14 16:02:55,704 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-07-14 16:02:55,705 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-07-14 16:02:55,707 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-07-14 16:02:55,712 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-07-14 16:02:55,713 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-07-14 16:02:55,717 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-07-14 16:02:55,718 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-07-14 16:02:55,720 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-07-14 16:02:55,720 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-07-14 16:02:55,722 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-07-14 16:02:55,723 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-07-14 16:02:55,724 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-07-14 16:02:55,725 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-07-14 16:02:55,726 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-07-14 16:02:55,728 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-07-14 16:02:55,732 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-07-14 16:02:55,734 INFO L181 SettingsManager]: Resetting HornVerifier preferences to default values [2022-07-14 16:02:55,734 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-07-14 16:02:55,735 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-07-14 16:02:55,735 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-07-14 16:02:55,737 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-07-14 16:02:55,741 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-07-14 16:02:55,742 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-07-14 16:02:55,742 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-07-14 16:02:55,743 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-07-14 16:02:55,744 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-07-14 16:02:55,744 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-07-14 16:02:55,745 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-07-14 16:02:55,746 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-07-14 16:02:55,746 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-07-14 16:02:55,747 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-07-14 16:02:55,747 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-07-14 16:02:55,747 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-07-14 16:02:55,748 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-07-14 16:02:55,748 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-07-14 16:02:55,749 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-07-14 16:02:55,749 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-07-14 16:02:55,751 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-07-14 16:02:55,752 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-07-14 16:02:55,780 INFO L113 SettingsManager]: Loading preferences was successful [2022-07-14 16:02:55,780 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-07-14 16:02:55,781 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-07-14 16:02:55,781 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-07-14 16:02:55,782 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-07-14 16:02:55,782 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-07-14 16:02:55,782 INFO L138 SettingsManager]: * Use SBE=true [2022-07-14 16:02:55,782 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-07-14 16:02:55,782 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-07-14 16:02:55,783 INFO L138 SettingsManager]: * Use old map elimination=false [2022-07-14 16:02:55,783 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-07-14 16:02:55,783 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-07-14 16:02:55,784 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-07-14 16:02:55,784 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-07-14 16:02:55,784 INFO L138 SettingsManager]: * sizeof long=4 [2022-07-14 16:02:55,784 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-07-14 16:02:55,784 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-07-14 16:02:55,785 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-07-14 16:02:55,785 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-07-14 16:02:55,785 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-07-14 16:02:55,786 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-07-14 16:02:55,786 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-07-14 16:02:55,786 INFO L138 SettingsManager]: * sizeof long double=12 [2022-07-14 16:02:55,786 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-07-14 16:02:55,786 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-07-14 16:02:55,786 INFO L138 SettingsManager]: * Use constant arrays=true [2022-07-14 16:02:55,786 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-07-14 16:02:55,787 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-07-14 16:02:55,787 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-07-14 16:02:55,787 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-07-14 16:02:55,792 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-07-14 16:02:55,794 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-07-14 16:02:55,794 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 79f20a4b12634e812af836a5fe92e9d987e7766e2c28337c49504608346f2347 [2022-07-14 16:02:56,007 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-07-14 16:02:56,029 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-07-14 16:02:56,031 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-07-14 16:02:56,032 INFO L271 PluginConnector]: Initializing CDTParser... [2022-07-14 16:02:56,033 INFO L275 PluginConnector]: CDTParser initialized [2022-07-14 16:02:56,034 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.11.cil-1.c [2022-07-14 16:02:56,072 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c3f4523f5/4d6a011e28ef47bdb9a62e1728505187/FLAG5ab247447 [2022-07-14 16:02:56,480 INFO L306 CDTParser]: Found 1 translation units. [2022-07-14 16:02:56,481 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.11.cil-1.c [2022-07-14 16:02:56,497 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c3f4523f5/4d6a011e28ef47bdb9a62e1728505187/FLAG5ab247447 [2022-07-14 16:02:56,508 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c3f4523f5/4d6a011e28ef47bdb9a62e1728505187 [2022-07-14 16:02:56,510 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-07-14 16:02:56,511 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-07-14 16:02:56,513 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-07-14 16:02:56,514 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-07-14 16:02:56,516 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-07-14 16:02:56,516 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.07 04:02:56" (1/1) ... [2022-07-14 16:02:56,517 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5c1a2b87 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:56, skipping insertion in model container [2022-07-14 16:02:56,518 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.07 04:02:56" (1/1) ... [2022-07-14 16:02:56,522 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-07-14 16:02:56,553 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-07-14 16:02:56,633 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.11.cil-1.c[671,684] [2022-07-14 16:02:56,706 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-14 16:02:56,721 INFO L203 MainTranslator]: Completed pre-run [2022-07-14 16:02:56,731 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.11.cil-1.c[671,684] [2022-07-14 16:02:56,846 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-14 16:02:56,861 INFO L208 MainTranslator]: Completed translation [2022-07-14 16:02:56,862 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:56 WrapperNode [2022-07-14 16:02:56,862 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-07-14 16:02:56,863 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-07-14 16:02:56,863 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-07-14 16:02:56,863 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-07-14 16:02:56,869 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:56" (1/1) ... [2022-07-14 16:02:56,880 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:56" (1/1) ... [2022-07-14 16:02:56,955 INFO L137 Inliner]: procedures = 50, calls = 65, calls flagged for inlining = 60, calls inlined = 239, statements flattened = 3657 [2022-07-14 16:02:56,958 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-07-14 16:02:56,959 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-07-14 16:02:56,959 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-07-14 16:02:56,959 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-07-14 16:02:56,965 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:56" (1/1) ... [2022-07-14 16:02:56,965 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:56" (1/1) ... [2022-07-14 16:02:56,988 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:56" (1/1) ... [2022-07-14 16:02:56,996 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:56" (1/1) ... [2022-07-14 16:02:57,028 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:56" (1/1) ... [2022-07-14 16:02:57,065 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:56" (1/1) ... [2022-07-14 16:02:57,074 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:56" (1/1) ... [2022-07-14 16:02:57,098 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-07-14 16:02:57,099 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-07-14 16:02:57,099 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-07-14 16:02:57,099 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-07-14 16:02:57,100 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:56" (1/1) ... [2022-07-14 16:02:57,120 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-14 16:02:57,126 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-14 16:02:57,153 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-14 16:02:57,171 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-07-14 16:02:57,184 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-07-14 16:02:57,185 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-07-14 16:02:57,185 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-07-14 16:02:57,185 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-07-14 16:02:57,256 INFO L234 CfgBuilder]: Building ICFG [2022-07-14 16:02:57,267 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-07-14 16:02:58,666 INFO L275 CfgBuilder]: Performing block encoding [2022-07-14 16:02:58,690 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-07-14 16:02:58,703 INFO L299 CfgBuilder]: Removed 14 assume(true) statements. [2022-07-14 16:02:58,707 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.07 04:02:58 BoogieIcfgContainer [2022-07-14 16:02:58,707 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-07-14 16:02:58,708 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-07-14 16:02:58,708 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-07-14 16:02:58,711 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-07-14 16:02:58,712 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-14 16:02:58,712 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 14.07 04:02:56" (1/3) ... [2022-07-14 16:02:58,713 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@d5a2193 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 14.07 04:02:58, skipping insertion in model container [2022-07-14 16:02:58,713 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-14 16:02:58,713 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.07 04:02:56" (2/3) ... [2022-07-14 16:02:58,714 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@d5a2193 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 14.07 04:02:58, skipping insertion in model container [2022-07-14 16:02:58,714 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-14 16:02:58,714 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.07 04:02:58" (3/3) ... [2022-07-14 16:02:58,715 INFO L354 chiAutomizerObserver]: Analyzing ICFG token_ring.11.cil-1.c [2022-07-14 16:02:58,794 INFO L255 stractBuchiCegarLoop]: Interprodecural is true [2022-07-14 16:02:58,795 INFO L256 stractBuchiCegarLoop]: Hoare is false [2022-07-14 16:02:58,795 INFO L257 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-07-14 16:02:58,795 INFO L258 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-07-14 16:02:58,795 INFO L259 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-07-14 16:02:58,795 INFO L260 stractBuchiCegarLoop]: Difference is false [2022-07-14 16:02:58,795 INFO L261 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-07-14 16:02:58,796 INFO L265 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-07-14 16:02:58,804 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1579 states, 1578 states have (on average 1.503168567807351) internal successors, (2372), 1578 states have internal predecessors, (2372), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:58,874 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1424 [2022-07-14 16:02:58,874 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:58,874 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:58,913 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:58,913 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:58,913 INFO L287 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-07-14 16:02:58,916 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1579 states, 1578 states have (on average 1.503168567807351) internal successors, (2372), 1578 states have internal predecessors, (2372), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:58,930 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1424 [2022-07-14 16:02:58,930 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:58,930 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:58,934 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:58,934 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:58,942 INFO L752 eck$LassoCheckResult]: Stem: 347#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 1497#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 779#L1653true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 967#L785true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 651#L792true assume !(1 == ~m_i~0);~m_st~0 := 2; 999#L792-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 47#L797-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1411#L802-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1302#L807-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 628#L812-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1134#L817-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 928#L822-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1063#L827-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 1355#L832-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 1216#L837-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 1223#L842-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 1001#L847-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 794#L1121true assume !(0 == ~M_E~0); 574#L1121-2true assume !(0 == ~T1_E~0); 177#L1126-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 271#L1131-1true assume !(0 == ~T3_E~0); 326#L1136-1true assume !(0 == ~T4_E~0); 473#L1141-1true assume !(0 == ~T5_E~0); 1260#L1146-1true assume !(0 == ~T6_E~0); 727#L1151-1true assume !(0 == ~T7_E~0); 359#L1156-1true assume !(0 == ~T8_E~0); 40#L1161-1true assume !(0 == ~T9_E~0); 859#L1166-1true assume 0 == ~T10_E~0;~T10_E~0 := 1; 144#L1171-1true assume !(0 == ~T11_E~0); 741#L1176-1true assume !(0 == ~E_M~0); 885#L1181-1true assume !(0 == ~E_1~0); 1329#L1186-1true assume !(0 == ~E_2~0); 945#L1191-1true assume !(0 == ~E_3~0); 158#L1196-1true assume !(0 == ~E_4~0); 1339#L1201-1true assume !(0 == ~E_5~0); 1419#L1206-1true assume 0 == ~E_6~0;~E_6~0 := 1; 1002#L1211-1true assume !(0 == ~E_7~0); 1156#L1216-1true assume !(0 == ~E_8~0); 232#L1221-1true assume !(0 == ~E_9~0); 1085#L1226-1true assume !(0 == ~E_10~0); 86#L1231-1true assume !(0 == ~E_11~0); 1233#L1236-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 742#L556true assume 1 == ~m_pc~0; 756#L557true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 27#L567true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 537#L568true activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1135#L1391true assume !(0 != activate_threads_~tmp~1#1); 918#L1391-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1081#L575true assume !(1 == ~t1_pc~0); 5#L575-2true is_transmit1_triggered_~__retres1~1#1 := 0; 68#L586true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1074#L587true activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 239#L1399true assume !(0 != activate_threads_~tmp___0~0#1); 217#L1399-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 716#L594true assume 1 == ~t2_pc~0; 180#L595true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1520#L605true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 458#L606true activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35#L1407true assume !(0 != activate_threads_~tmp___1~0#1); 63#L1407-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1208#L613true assume !(1 == ~t3_pc~0); 1542#L613-2true is_transmit3_triggered_~__retres1~3#1 := 0; 306#L624true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 84#L625true activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 472#L1415true assume !(0 != activate_threads_~tmp___2~0#1); 1077#L1415-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 293#L632true assume 1 == ~t4_pc~0; 637#L633true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 795#L643true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1341#L644true activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1495#L1423true assume !(0 != activate_threads_~tmp___3~0#1); 748#L1423-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 524#L651true assume 1 == ~t5_pc~0; 969#L652true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 123#L662true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 366#L663true activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 448#L1431true assume !(0 != activate_threads_~tmp___4~0#1); 131#L1431-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1110#L670true assume !(1 == ~t6_pc~0); 976#L670-2true is_transmit6_triggered_~__retres1~6#1 := 0; 320#L681true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1132#L682true activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1304#L1439true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 502#L1439-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1322#L689true assume 1 == ~t7_pc~0; 1515#L690true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 584#L700true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1572#L701true activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 998#L1447true assume !(0 != activate_threads_~tmp___6~0#1); 430#L1447-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1189#L708true assume !(1 == ~t8_pc~0); 175#L708-2true is_transmit8_triggered_~__retres1~8#1 := 0; 1130#L719true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1386#L720true activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1107#L1455true assume !(0 != activate_threads_~tmp___7~0#1); 208#L1455-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 279#L727true assume 1 == ~t9_pc~0; 1225#L728true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1408#L738true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1360#L739true activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1433#L1463true assume !(0 != activate_threads_~tmp___8~0#1); 1305#L1463-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 237#L746true assume !(1 == ~t10_pc~0); 705#L746-2true is_transmit10_triggered_~__retres1~10#1 := 0; 816#L757true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1434#L758true activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1122#L1471true assume !(0 != activate_threads_~tmp___9~0#1); 923#L1471-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 331#L765true assume 1 == ~t11_pc~0; 1363#L766true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1387#L776true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 11#L777true activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 974#L1479true assume !(0 != activate_threads_~tmp___10~0#1); 1165#L1479-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1104#L1249true assume !(1 == ~M_E~0); 641#L1249-2true assume !(1 == ~T1_E~0); 381#L1254-1true assume !(1 == ~T2_E~0); 33#L1259-1true assume !(1 == ~T3_E~0); 24#L1264-1true assume !(1 == ~T4_E~0); 1573#L1269-1true assume !(1 == ~T5_E~0); 1502#L1274-1true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1244#L1279-1true assume !(1 == ~T7_E~0); 118#L1284-1true assume !(1 == ~T8_E~0); 1364#L1289-1true assume !(1 == ~T9_E~0); 413#L1294-1true assume !(1 == ~T10_E~0); 420#L1299-1true assume !(1 == ~T11_E~0); 1429#L1304-1true assume !(1 == ~E_M~0); 1460#L1309-1true assume !(1 == ~E_1~0); 1439#L1314-1true assume 1 == ~E_2~0;~E_2~0 := 2; 95#L1319-1true assume !(1 == ~E_3~0); 838#L1324-1true assume !(1 == ~E_4~0); 156#L1329-1true assume !(1 == ~E_5~0); 1042#L1334-1true assume !(1 == ~E_6~0); 1393#L1339-1true assume !(1 == ~E_7~0); 1169#L1344-1true assume !(1 == ~E_8~0); 1519#L1349-1true assume !(1 == ~E_9~0); 513#L1354-1true assume 1 == ~E_10~0;~E_10~0 := 2; 842#L1359-1true assume !(1 == ~E_11~0); 1368#L1364-1true assume { :end_inline_reset_delta_events } true; 201#L1690-2true [2022-07-14 16:02:58,944 INFO L754 eck$LassoCheckResult]: Loop: 201#L1690-2true assume !false; 870#L1691true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 856#L1096true assume !true; 679#L1111true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1377#L785-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 318#L1121-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1514#L1121-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1312#L1126-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 446#L1131-3true assume !(0 == ~T3_E~0); 1525#L1136-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1507#L1141-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 750#L1146-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 174#L1151-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1161#L1156-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1379#L1161-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 575#L1166-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1254#L1171-3true assume !(0 == ~T11_E~0); 608#L1176-3true assume 0 == ~E_M~0;~E_M~0 := 1; 199#L1181-3true assume 0 == ~E_1~0;~E_1~0 := 1; 1224#L1186-3true assume 0 == ~E_2~0;~E_2~0 := 1; 681#L1191-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1212#L1196-3true assume 0 == ~E_4~0;~E_4~0 := 1; 897#L1201-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1422#L1206-3true assume 0 == ~E_6~0;~E_6~0 := 1; 587#L1211-3true assume !(0 == ~E_7~0); 154#L1216-3true assume 0 == ~E_8~0;~E_8~0 := 1; 388#L1221-3true assume 0 == ~E_9~0;~E_9~0 := 1; 868#L1226-3true assume 0 == ~E_10~0;~E_10~0 := 1; 183#L1231-3true assume 0 == ~E_11~0;~E_11~0 := 1; 310#L1236-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1450#L556-39true assume 1 == ~m_pc~0; 690#L557-13true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 656#L567-13true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 236#L568-13true activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 335#L1391-39true assume !(0 != activate_threads_~tmp~1#1); 1295#L1391-41true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 620#L575-39true assume !(1 == ~t1_pc~0); 1421#L575-41true is_transmit1_triggered_~__retres1~1#1 := 0; 903#L586-13true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 745#L587-13true activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1476#L1399-39true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 599#L1399-41true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 798#L594-39true assume 1 == ~t2_pc~0; 929#L595-13true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 601#L605-13true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1530#L606-13true activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1111#L1407-39true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 272#L1407-41true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1072#L613-39true assume 1 == ~t3_pc~0; 1467#L614-13true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14#L624-13true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 417#L625-13true activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 806#L1415-39true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 60#L1415-41true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1492#L632-39true assume 1 == ~t4_pc~0; 1018#L633-13true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 367#L643-13true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 831#L644-13true activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1080#L1423-39true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1016#L1423-41true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 189#L651-39true assume 1 == ~t5_pc~0; 1556#L652-13true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 995#L662-13true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1179#L663-13true activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1270#L1431-39true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1499#L1431-41true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1366#L670-39true assume !(1 == ~t6_pc~0); 693#L670-41true is_transmit6_triggered_~__retres1~6#1 := 0; 36#L681-13true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 69#L682-13true activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 471#L1439-39true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 386#L1439-41true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 547#L689-39true assume 1 == ~t7_pc~0; 982#L690-13true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 487#L700-13true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 190#L701-13true activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1466#L1447-39true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 125#L1447-41true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 730#L708-39true assume !(1 == ~t8_pc~0); 485#L708-41true is_transmit8_triggered_~__retres1~8#1 := 0; 422#L719-13true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 146#L720-13true activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1176#L1455-39true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 757#L1455-41true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 352#L727-39true assume !(1 == ~t9_pc~0); 361#L727-41true is_transmit9_triggered_~__retres1~9#1 := 0; 224#L738-13true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1045#L739-13true activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1147#L1463-39true assume !(0 != activate_threads_~tmp___8~0#1); 800#L1463-41true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 959#L746-39true assume 1 == ~t10_pc~0; 774#L747-13true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1281#L757-13true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1150#L758-13true activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 533#L1471-39true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 964#L1471-41true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1454#L765-39true assume 1 == ~t11_pc~0; 38#L766-13true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1196#L776-13true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 824#L777-13true activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 200#L1479-39true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 711#L1479-41true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 570#L1249-3true assume 1 == ~M_E~0;~M_E~0 := 2; 106#L1249-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1342#L1254-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1159#L1259-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 673#L1264-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 88#L1269-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1412#L1274-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1240#L1279-3true assume !(1 == ~T7_E~0); 338#L1284-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1283#L1289-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 334#L1294-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1455#L1299-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 510#L1304-3true assume 1 == ~E_M~0;~E_M~0 := 2; 862#L1309-3true assume 1 == ~E_1~0;~E_1~0 := 2; 291#L1314-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1529#L1319-3true assume !(1 == ~E_3~0); 911#L1324-3true assume 1 == ~E_4~0;~E_4~0 := 2; 137#L1329-3true assume 1 == ~E_5~0;~E_5~0 := 2; 1407#L1334-3true assume 1 == ~E_6~0;~E_6~0 := 2; 457#L1339-3true assume 1 == ~E_7~0;~E_7~0 := 2; 665#L1344-3true assume 1 == ~E_8~0;~E_8~0 := 2; 625#L1349-3true assume 1 == ~E_9~0;~E_9~0 := 2; 276#L1354-3true assume 1 == ~E_10~0;~E_10~0 := 2; 636#L1359-3true assume !(1 == ~E_11~0); 1428#L1364-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 70#L860-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 594#L922-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 407#L923-1true start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 836#L1709true assume !(0 == start_simulation_~tmp~3#1); 1293#L1709-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 937#L860-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1523#L922-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 399#L923-2true stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 104#L1664true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 609#L1671true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1238#L1672true start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 1057#L1722true assume !(0 != start_simulation_~tmp___0~1#1); 201#L1690-2true [2022-07-14 16:02:58,950 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:58,950 INFO L85 PathProgramCache]: Analyzing trace with hash 430082112, now seen corresponding path program 1 times [2022-07-14 16:02:58,958 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:58,958 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1920259090] [2022-07-14 16:02:58,958 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:58,959 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:59,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:59,119 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:59,119 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:59,120 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1920259090] [2022-07-14 16:02:59,120 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1920259090] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:59,120 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:59,121 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:59,122 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1589382051] [2022-07-14 16:02:59,122 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:59,126 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:59,127 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:59,127 INFO L85 PathProgramCache]: Analyzing trace with hash -1639843427, now seen corresponding path program 1 times [2022-07-14 16:02:59,127 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:59,127 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [388959256] [2022-07-14 16:02:59,127 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:59,128 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:59,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:59,161 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:59,161 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:59,161 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [388959256] [2022-07-14 16:02:59,162 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [388959256] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:59,162 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:59,162 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-14 16:02:59,162 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [160581544] [2022-07-14 16:02:59,162 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:59,164 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:59,164 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:59,187 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-07-14 16:02:59,188 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-07-14 16:02:59,192 INFO L87 Difference]: Start difference. First operand has 1579 states, 1578 states have (on average 1.503168567807351) internal successors, (2372), 1578 states have internal predecessors, (2372), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 69.5) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:59,227 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:59,227 INFO L93 Difference]: Finished difference Result 1577 states and 2340 transitions. [2022-07-14 16:02:59,228 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-07-14 16:02:59,232 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1577 states and 2340 transitions. [2022-07-14 16:02:59,246 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2022-07-14 16:02:59,262 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1577 states to 1571 states and 2334 transitions. [2022-07-14 16:02:59,263 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2022-07-14 16:02:59,266 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2022-07-14 16:02:59,267 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2334 transitions. [2022-07-14 16:02:59,277 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:59,277 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1571 states and 2334 transitions. [2022-07-14 16:02:59,294 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2334 transitions. [2022-07-14 16:02:59,336 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2022-07-14 16:02:59,339 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.4856779121578612) internal successors, (2334), 1570 states have internal predecessors, (2334), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:59,344 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2334 transitions. [2022-07-14 16:02:59,345 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1571 states and 2334 transitions. [2022-07-14 16:02:59,345 INFO L374 stractBuchiCegarLoop]: Abstraction has 1571 states and 2334 transitions. [2022-07-14 16:02:59,346 INFO L287 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-07-14 16:02:59,346 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2334 transitions. [2022-07-14 16:02:59,353 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2022-07-14 16:02:59,353 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:59,353 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:59,356 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:59,356 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:59,357 INFO L752 eck$LassoCheckResult]: Stem: 3841#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 3842#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 4382#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4383#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4252#L792 assume !(1 == ~m_i~0);~m_st~0 := 2; 4253#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3260#L797-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3261#L802-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4699#L807-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4226#L812-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4227#L817-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4504#L822-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4505#L827-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4588#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4670#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4671#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4552#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4400#L1121 assume !(0 == ~M_E~0); 4155#L1121-2 assume !(0 == ~T1_E~0); 3536#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3537#L1131-1 assume !(0 == ~T3_E~0); 3707#L1136-1 assume !(0 == ~T4_E~0); 3803#L1141-1 assume !(0 == ~T5_E~0); 4023#L1146-1 assume !(0 == ~T6_E~0); 4323#L1151-1 assume !(0 == ~T7_E~0); 3863#L1156-1 assume !(0 == ~T8_E~0); 3246#L1161-1 assume !(0 == ~T9_E~0); 3247#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3472#L1171-1 assume !(0 == ~T11_E~0); 3473#L1176-1 assume !(0 == ~E_M~0); 4337#L1181-1 assume !(0 == ~E_1~0); 4465#L1186-1 assume !(0 == ~E_2~0); 4515#L1191-1 assume !(0 == ~E_3~0); 3499#L1196-1 assume !(0 == ~E_4~0); 3500#L1201-1 assume !(0 == ~E_5~0); 4708#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 4553#L1211-1 assume !(0 == ~E_7~0); 4554#L1216-1 assume !(0 == ~E_8~0); 3642#L1221-1 assume !(0 == ~E_9~0); 3643#L1226-1 assume !(0 == ~E_10~0); 3342#L1231-1 assume !(0 == ~E_11~0); 3343#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4338#L556 assume 1 == ~m_pc~0; 4339#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3220#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3221#L568 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4116#L1391 assume !(0 != activate_threads_~tmp~1#1); 4493#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4494#L575 assume !(1 == ~t1_pc~0); 3171#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3172#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3305#L587 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3655#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 3612#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3613#L594 assume 1 == ~t2_pc~0; 3541#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3542#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4008#L606 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3235#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 3236#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3294#L613 assume !(1 == ~t3_pc~0); 3413#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3412#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3338#L625 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3339#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 4022#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3740#L632 assume 1 == ~t4_pc~0; 3741#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4241#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4401#L644 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4709#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 4347#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4098#L651 assume 1 == ~t5_pc~0; 4099#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3426#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3427#L663 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3875#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 3443#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3444#L670 assume !(1 == ~t6_pc~0); 4535#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3789#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3790#L682 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4631#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4063#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4064#L689 assume 1 == ~t7_pc~0; 4705#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4174#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4175#L701 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4550#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 3966#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3967#L708 assume !(1 == ~t8_pc~0); 3532#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3533#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4630#L720 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4615#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 3597#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3598#L727 assume 1 == ~t9_pc~0; 3720#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3296#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4712#L739 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4713#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 4700#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3651#L746 assume !(1 == ~t10_pc~0); 3652#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4300#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4416#L758 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4624#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 4497#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3812#L765 assume 1 == ~t11_pc~0; 3813#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4018#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3185#L777 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 3186#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 4534#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4612#L1249 assume !(1 == ~M_E~0); 4245#L1249-2 assume !(1 == ~T1_E~0); 3895#L1254-1 assume !(1 == ~T2_E~0); 3231#L1259-1 assume !(1 == ~T3_E~0); 3213#L1264-1 assume !(1 == ~T4_E~0); 3214#L1269-1 assume !(1 == ~T5_E~0); 4731#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4679#L1279-1 assume !(1 == ~T7_E~0); 3414#L1284-1 assume !(1 == ~T8_E~0); 3415#L1289-1 assume !(1 == ~T9_E~0); 3945#L1294-1 assume !(1 == ~T10_E~0); 3946#L1299-1 assume !(1 == ~T11_E~0); 3955#L1304-1 assume !(1 == ~E_M~0); 4725#L1309-1 assume !(1 == ~E_1~0); 4728#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 3361#L1319-1 assume !(1 == ~E_3~0); 3362#L1324-1 assume !(1 == ~E_4~0); 3494#L1329-1 assume !(1 == ~E_5~0); 3495#L1334-1 assume !(1 == ~E_6~0); 4573#L1339-1 assume !(1 == ~E_7~0); 4650#L1344-1 assume !(1 == ~E_8~0); 4651#L1349-1 assume !(1 == ~E_9~0); 4078#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 4079#L1359-1 assume !(1 == ~E_11~0); 4438#L1364-1 assume { :end_inline_reset_delta_events } true; 3583#L1690-2 [2022-07-14 16:02:59,357 INFO L754 eck$LassoCheckResult]: Loop: 3583#L1690-2 assume !false; 3584#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3469#L1096 assume !false; 4447#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 3315#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3316#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 4341#L923 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3810#L937 assume !(0 != eval_~tmp~0#1); 3811#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4281#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3785#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3786#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4701#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3993#L1131-3 assume !(0 == ~T3_E~0); 3994#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4732#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4348#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3530#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3531#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4645#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4156#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4157#L1171-3 assume !(0 == ~T11_E~0); 4202#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3579#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3580#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4283#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4284#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4474#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4475#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4180#L1211-3 assume !(0 == ~E_7~0); 3492#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3493#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3906#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3549#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 3550#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3770#L556-39 assume 1 == ~m_pc~0; 4291#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4258#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3649#L568-13 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3650#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 3822#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4216#L575-39 assume 1 == ~t1_pc~0; 4217#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4482#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4343#L587-13 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4344#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4191#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4192#L594-39 assume !(1 == ~t2_pc~0); 4403#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 4194#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4195#L606-13 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4617#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3708#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3709#L613-39 assume 1 == ~t3_pc~0; 4594#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3191#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3192#L625-13 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3950#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3290#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3291#L632-39 assume 1 == ~t4_pc~0; 4562#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3876#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3877#L644-13 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4430#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4561#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3560#L651-39 assume 1 == ~t5_pc~0; 3561#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3323#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4549#L663-13 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4656#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4694#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4714#L670-39 assume !(1 == ~t6_pc~0); 4293#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 3237#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3238#L682-13 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3306#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3903#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3904#L689-39 assume !(1 == ~t7_pc~0); 4027#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 4028#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3562#L701-13 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3563#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3430#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3431#L708-39 assume 1 == ~t8_pc~0; 3367#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3368#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3476#L720-13 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3477#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4357#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3849#L727-39 assume !(1 == ~t9_pc~0); 3850#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 3627#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3628#L739-13 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4577#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 4406#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4407#L746-39 assume 1 == ~t10_pc~0; 4376#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4377#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4642#L758-13 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4112#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4113#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4525#L765-39 assume 1 == ~t11_pc~0; 3241#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3243#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4425#L777-13 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 3581#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3582#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4149#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3387#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3388#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4644#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4272#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3346#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3347#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4677#L1279-3 assume !(1 == ~T7_E~0); 3825#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3826#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3820#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3821#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4072#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4073#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3737#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3738#L1319-3 assume !(1 == ~E_3~0); 4491#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3456#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3457#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4006#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4007#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4225#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3716#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3717#L1359-3 assume !(1 == ~E_11~0); 4240#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 3307#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3308#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3934#L923-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 3935#L1709 assume !(0 == start_simulation_~tmp~3#1); 3745#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4511#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3421#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3923#L923-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 3384#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3385#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4203#L1672 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 4584#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 3583#L1690-2 [2022-07-14 16:02:59,358 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:59,358 INFO L85 PathProgramCache]: Analyzing trace with hash 430082112, now seen corresponding path program 2 times [2022-07-14 16:02:59,359 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:59,359 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [695558180] [2022-07-14 16:02:59,359 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:59,359 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:59,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:59,436 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:59,436 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:59,436 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [695558180] [2022-07-14 16:02:59,436 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [695558180] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:59,437 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:59,437 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:59,437 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1903980687] [2022-07-14 16:02:59,437 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:59,439 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:59,440 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:59,440 INFO L85 PathProgramCache]: Analyzing trace with hash -1946660288, now seen corresponding path program 1 times [2022-07-14 16:02:59,440 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:59,440 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1070290289] [2022-07-14 16:02:59,442 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:59,442 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:59,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:59,579 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:59,582 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:59,582 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1070290289] [2022-07-14 16:02:59,583 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1070290289] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:59,583 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:59,583 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:59,583 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2046948982] [2022-07-14 16:02:59,584 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:59,584 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:59,584 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:59,585 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:02:59,585 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:02:59,585 INFO L87 Difference]: Start difference. First operand 1571 states and 2334 transitions. cyclomatic complexity: 764 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:59,622 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:59,623 INFO L93 Difference]: Finished difference Result 1571 states and 2333 transitions. [2022-07-14 16:02:59,623 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:02:59,624 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2333 transitions. [2022-07-14 16:02:59,632 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2022-07-14 16:02:59,640 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1571 states and 2333 transitions. [2022-07-14 16:02:59,640 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2022-07-14 16:02:59,642 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2022-07-14 16:02:59,642 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2333 transitions. [2022-07-14 16:02:59,644 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:59,644 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1571 states and 2333 transitions. [2022-07-14 16:02:59,646 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2333 transitions. [2022-07-14 16:02:59,662 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2022-07-14 16:02:59,665 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.4850413749204328) internal successors, (2333), 1570 states have internal predecessors, (2333), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:59,669 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2333 transitions. [2022-07-14 16:02:59,670 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1571 states and 2333 transitions. [2022-07-14 16:02:59,670 INFO L374 stractBuchiCegarLoop]: Abstraction has 1571 states and 2333 transitions. [2022-07-14 16:02:59,670 INFO L287 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-07-14 16:02:59,670 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2333 transitions. [2022-07-14 16:02:59,676 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2022-07-14 16:02:59,676 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:59,677 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:59,682 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:59,683 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:59,684 INFO L752 eck$LassoCheckResult]: Stem: 6990#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 6991#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 7531#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7532#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7401#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 7402#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6409#L797-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 6410#L802-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 7848#L807-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 7375#L812-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7376#L817-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7653#L822-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7654#L827-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7737#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7819#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 7820#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 7701#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7549#L1121 assume !(0 == ~M_E~0); 7304#L1121-2 assume !(0 == ~T1_E~0); 6685#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6686#L1131-1 assume !(0 == ~T3_E~0); 6856#L1136-1 assume !(0 == ~T4_E~0); 6952#L1141-1 assume !(0 == ~T5_E~0); 7172#L1146-1 assume !(0 == ~T6_E~0); 7472#L1151-1 assume !(0 == ~T7_E~0); 7012#L1156-1 assume !(0 == ~T8_E~0); 6395#L1161-1 assume !(0 == ~T9_E~0); 6396#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 6621#L1171-1 assume !(0 == ~T11_E~0); 6622#L1176-1 assume !(0 == ~E_M~0); 7486#L1181-1 assume !(0 == ~E_1~0); 7614#L1186-1 assume !(0 == ~E_2~0); 7664#L1191-1 assume !(0 == ~E_3~0); 6648#L1196-1 assume !(0 == ~E_4~0); 6649#L1201-1 assume !(0 == ~E_5~0); 7857#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 7702#L1211-1 assume !(0 == ~E_7~0); 7703#L1216-1 assume !(0 == ~E_8~0); 6791#L1221-1 assume !(0 == ~E_9~0); 6792#L1226-1 assume !(0 == ~E_10~0); 6491#L1231-1 assume !(0 == ~E_11~0); 6492#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7487#L556 assume 1 == ~m_pc~0; 7488#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6369#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6370#L568 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7265#L1391 assume !(0 != activate_threads_~tmp~1#1); 7642#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7643#L575 assume !(1 == ~t1_pc~0); 6320#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6321#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6454#L587 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6804#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 6761#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6762#L594 assume 1 == ~t2_pc~0; 6690#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6691#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7157#L606 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6384#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 6385#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6443#L613 assume !(1 == ~t3_pc~0); 6562#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6561#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6487#L625 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6488#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 7171#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6889#L632 assume 1 == ~t4_pc~0; 6890#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7390#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7550#L644 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7858#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 7496#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7247#L651 assume 1 == ~t5_pc~0; 7248#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6575#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6576#L663 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7024#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 6592#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6593#L670 assume !(1 == ~t6_pc~0); 7684#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6938#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6939#L682 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7780#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7212#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7213#L689 assume 1 == ~t7_pc~0; 7854#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7323#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7324#L701 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7699#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 7115#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7116#L708 assume !(1 == ~t8_pc~0); 6681#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 6682#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7779#L720 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 7764#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 6746#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6747#L727 assume 1 == ~t9_pc~0; 6869#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 6445#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7861#L739 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7862#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 7849#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6800#L746 assume !(1 == ~t10_pc~0); 6801#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 7449#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7565#L758 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7773#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 7646#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6961#L765 assume 1 == ~t11_pc~0; 6962#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7167#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 6334#L777 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 6335#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 7683#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7761#L1249 assume !(1 == ~M_E~0); 7394#L1249-2 assume !(1 == ~T1_E~0); 7044#L1254-1 assume !(1 == ~T2_E~0); 6380#L1259-1 assume !(1 == ~T3_E~0); 6362#L1264-1 assume !(1 == ~T4_E~0); 6363#L1269-1 assume !(1 == ~T5_E~0); 7880#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7828#L1279-1 assume !(1 == ~T7_E~0); 6563#L1284-1 assume !(1 == ~T8_E~0); 6564#L1289-1 assume !(1 == ~T9_E~0); 7094#L1294-1 assume !(1 == ~T10_E~0); 7095#L1299-1 assume !(1 == ~T11_E~0); 7104#L1304-1 assume !(1 == ~E_M~0); 7874#L1309-1 assume !(1 == ~E_1~0); 7877#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 6510#L1319-1 assume !(1 == ~E_3~0); 6511#L1324-1 assume !(1 == ~E_4~0); 6643#L1329-1 assume !(1 == ~E_5~0); 6644#L1334-1 assume !(1 == ~E_6~0); 7722#L1339-1 assume !(1 == ~E_7~0); 7799#L1344-1 assume !(1 == ~E_8~0); 7800#L1349-1 assume !(1 == ~E_9~0); 7227#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 7228#L1359-1 assume !(1 == ~E_11~0); 7587#L1364-1 assume { :end_inline_reset_delta_events } true; 6732#L1690-2 [2022-07-14 16:02:59,685 INFO L754 eck$LassoCheckResult]: Loop: 6732#L1690-2 assume !false; 6733#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6618#L1096 assume !false; 7596#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 6464#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6465#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 7490#L923 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 6959#L937 assume !(0 != eval_~tmp~0#1); 6960#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7430#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6934#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6935#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7850#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7142#L1131-3 assume !(0 == ~T3_E~0); 7143#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7881#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7497#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6679#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6680#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7794#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7305#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 7306#L1171-3 assume !(0 == ~T11_E~0); 7351#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6728#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6729#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7432#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7433#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7623#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7624#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7329#L1211-3 assume !(0 == ~E_7~0); 6641#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6642#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 7055#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 6698#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 6699#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6919#L556-39 assume 1 == ~m_pc~0; 7440#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7407#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6798#L568-13 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6799#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 6971#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7365#L575-39 assume 1 == ~t1_pc~0; 7366#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7631#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7492#L587-13 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7493#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7340#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7341#L594-39 assume !(1 == ~t2_pc~0); 7552#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 7343#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7344#L606-13 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7766#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6857#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6858#L613-39 assume !(1 == ~t3_pc~0); 7744#L613-41 is_transmit3_triggered_~__retres1~3#1 := 0; 6340#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6341#L625-13 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7099#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6439#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6440#L632-39 assume !(1 == ~t4_pc~0); 7588#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 7025#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7026#L644-13 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7579#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7710#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6709#L651-39 assume 1 == ~t5_pc~0; 6710#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6472#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7698#L663-13 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7805#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7843#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7863#L670-39 assume !(1 == ~t6_pc~0); 7442#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 6386#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6387#L682-13 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6455#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7052#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7053#L689-39 assume !(1 == ~t7_pc~0); 7176#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 7177#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6711#L701-13 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6712#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6579#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6580#L708-39 assume 1 == ~t8_pc~0; 6516#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6517#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6625#L720-13 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6626#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7506#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6998#L727-39 assume !(1 == ~t9_pc~0); 6999#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 6776#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6777#L739-13 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7726#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 7555#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7556#L746-39 assume 1 == ~t10_pc~0; 7525#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 7526#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7791#L758-13 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7261#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 7262#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 7674#L765-39 assume 1 == ~t11_pc~0; 6390#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 6392#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7574#L777-13 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 6730#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 6731#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7298#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6536#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6537#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7793#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7421#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6495#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6496#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7826#L1279-3 assume !(1 == ~T7_E~0); 6974#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6975#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 6969#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 6970#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 7221#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7222#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6886#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6887#L1319-3 assume !(1 == ~E_3~0); 7640#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6605#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6606#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7155#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7156#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7374#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 6865#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 6866#L1359-3 assume !(1 == ~E_11~0); 7389#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 6456#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6457#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 7083#L923-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 7084#L1709 assume !(0 == start_simulation_~tmp~3#1); 6894#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 7660#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6570#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 7072#L923-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 6533#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6534#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7352#L1672 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 7733#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 6732#L1690-2 [2022-07-14 16:02:59,687 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:59,688 INFO L85 PathProgramCache]: Analyzing trace with hash -968871490, now seen corresponding path program 1 times [2022-07-14 16:02:59,688 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:59,688 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1886952832] [2022-07-14 16:02:59,688 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:59,688 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:59,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:59,765 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:59,766 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:59,766 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1886952832] [2022-07-14 16:02:59,766 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1886952832] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:59,766 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:59,766 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:59,766 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1938483801] [2022-07-14 16:02:59,766 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:59,767 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:59,767 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:59,767 INFO L85 PathProgramCache]: Analyzing trace with hash -29726974, now seen corresponding path program 1 times [2022-07-14 16:02:59,767 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:59,767 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [77215397] [2022-07-14 16:02:59,767 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:59,768 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:59,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:59,831 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:59,831 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:59,831 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [77215397] [2022-07-14 16:02:59,831 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [77215397] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:59,831 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:59,831 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:59,832 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [10456250] [2022-07-14 16:02:59,832 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:59,832 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:59,832 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:59,832 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:02:59,832 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:02:59,833 INFO L87 Difference]: Start difference. First operand 1571 states and 2333 transitions. cyclomatic complexity: 763 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:59,877 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:02:59,877 INFO L93 Difference]: Finished difference Result 1571 states and 2332 transitions. [2022-07-14 16:02:59,877 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:02:59,887 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2332 transitions. [2022-07-14 16:02:59,893 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2022-07-14 16:02:59,899 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1571 states and 2332 transitions. [2022-07-14 16:02:59,899 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2022-07-14 16:02:59,900 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2022-07-14 16:02:59,900 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2332 transitions. [2022-07-14 16:02:59,901 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:02:59,901 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1571 states and 2332 transitions. [2022-07-14 16:02:59,919 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2332 transitions. [2022-07-14 16:02:59,932 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2022-07-14 16:02:59,934 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.4844048376830044) internal successors, (2332), 1570 states have internal predecessors, (2332), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:02:59,937 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2332 transitions. [2022-07-14 16:02:59,937 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1571 states and 2332 transitions. [2022-07-14 16:02:59,937 INFO L374 stractBuchiCegarLoop]: Abstraction has 1571 states and 2332 transitions. [2022-07-14 16:02:59,937 INFO L287 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-07-14 16:02:59,938 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2332 transitions. [2022-07-14 16:02:59,942 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2022-07-14 16:02:59,942 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:02:59,942 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:02:59,944 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:59,944 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:02:59,944 INFO L752 eck$LassoCheckResult]: Stem: 10143#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 10144#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 10680#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10681#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10550#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 10551#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9558#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9559#L802-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 10997#L807-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 10524#L812-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 10525#L817-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10802#L822-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10803#L827-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 10886#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 10968#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 10969#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 10850#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10698#L1121 assume !(0 == ~M_E~0); 10453#L1121-2 assume !(0 == ~T1_E~0); 9835#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9836#L1131-1 assume !(0 == ~T3_E~0); 10005#L1136-1 assume !(0 == ~T4_E~0); 10101#L1141-1 assume !(0 == ~T5_E~0); 10326#L1146-1 assume !(0 == ~T6_E~0); 10621#L1151-1 assume !(0 == ~T7_E~0); 10161#L1156-1 assume !(0 == ~T8_E~0); 9544#L1161-1 assume !(0 == ~T9_E~0); 9545#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9770#L1171-1 assume !(0 == ~T11_E~0); 9771#L1176-1 assume !(0 == ~E_M~0); 10635#L1181-1 assume !(0 == ~E_1~0); 10763#L1186-1 assume !(0 == ~E_2~0); 10813#L1191-1 assume !(0 == ~E_3~0); 9797#L1196-1 assume !(0 == ~E_4~0); 9798#L1201-1 assume !(0 == ~E_5~0); 11006#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 10851#L1211-1 assume !(0 == ~E_7~0); 10852#L1216-1 assume !(0 == ~E_8~0); 9943#L1221-1 assume !(0 == ~E_9~0); 9944#L1226-1 assume !(0 == ~E_10~0); 9640#L1231-1 assume !(0 == ~E_11~0); 9641#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10637#L556 assume 1 == ~m_pc~0; 10638#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9518#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9519#L568 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10415#L1391 assume !(0 != activate_threads_~tmp~1#1); 10791#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10792#L575 assume !(1 == ~t1_pc~0); 9469#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9470#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9603#L587 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9953#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 9910#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9911#L594 assume 1 == ~t2_pc~0; 9839#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9840#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10306#L606 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9535#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 9536#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9592#L613 assume !(1 == ~t3_pc~0); 9711#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9710#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9636#L625 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9637#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 10320#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10038#L632 assume 1 == ~t4_pc~0; 10039#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10539#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10699#L644 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11007#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 10645#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10396#L651 assume 1 == ~t5_pc~0; 10397#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9724#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9725#L663 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10173#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 9741#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9742#L670 assume !(1 == ~t6_pc~0); 10834#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 10092#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10093#L682 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10930#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10363#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10364#L689 assume 1 == ~t7_pc~0; 11003#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10472#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10473#L701 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10848#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 10264#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10265#L708 assume !(1 == ~t8_pc~0); 9830#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 9831#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10928#L720 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 10913#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 9895#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9896#L727 assume 1 == ~t9_pc~0; 10018#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9594#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11010#L739 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11011#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 10998#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9950#L746 assume !(1 == ~t10_pc~0); 9951#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 10598#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 10714#L758 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 10922#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 10795#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10113#L765 assume 1 == ~t11_pc~0; 10114#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 10316#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9483#L777 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 9484#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 10832#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10910#L1249 assume !(1 == ~M_E~0); 10544#L1249-2 assume !(1 == ~T1_E~0); 10193#L1254-1 assume !(1 == ~T2_E~0); 9529#L1259-1 assume !(1 == ~T3_E~0); 9511#L1264-1 assume !(1 == ~T4_E~0); 9512#L1269-1 assume !(1 == ~T5_E~0); 11029#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10977#L1279-1 assume !(1 == ~T7_E~0); 9712#L1284-1 assume !(1 == ~T8_E~0); 9713#L1289-1 assume !(1 == ~T9_E~0); 10243#L1294-1 assume !(1 == ~T10_E~0); 10244#L1299-1 assume !(1 == ~T11_E~0); 10253#L1304-1 assume !(1 == ~E_M~0); 11023#L1309-1 assume !(1 == ~E_1~0); 11026#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 9659#L1319-1 assume !(1 == ~E_3~0); 9660#L1324-1 assume !(1 == ~E_4~0); 9792#L1329-1 assume !(1 == ~E_5~0); 9793#L1334-1 assume !(1 == ~E_6~0); 10871#L1339-1 assume !(1 == ~E_7~0); 10948#L1344-1 assume !(1 == ~E_8~0); 10949#L1349-1 assume !(1 == ~E_9~0); 10376#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 10377#L1359-1 assume !(1 == ~E_11~0); 10736#L1364-1 assume { :end_inline_reset_delta_events } true; 9881#L1690-2 [2022-07-14 16:02:59,944 INFO L754 eck$LassoCheckResult]: Loop: 9881#L1690-2 assume !false; 9882#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9767#L1096 assume !false; 10745#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 9613#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9614#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 10640#L923 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 10108#L937 assume !(0 != eval_~tmp~0#1); 10109#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10579#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10085#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10086#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10999#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10291#L1131-3 assume !(0 == ~T3_E~0); 10292#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11030#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10646#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9828#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9829#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 10943#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10454#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 10455#L1171-3 assume !(0 == ~T11_E~0); 10500#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9877#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9878#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10581#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10582#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10772#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10773#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10478#L1211-3 assume !(0 == ~E_7~0); 9790#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9791#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 10204#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 9847#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 9848#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10068#L556-39 assume 1 == ~m_pc~0; 10589#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10556#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9947#L568-13 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9948#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 10120#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10514#L575-39 assume 1 == ~t1_pc~0; 10515#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10780#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10641#L587-13 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10642#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10489#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10490#L594-39 assume !(1 == ~t2_pc~0); 10701#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 10492#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10493#L606-13 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10915#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10006#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10007#L613-39 assume 1 == ~t3_pc~0; 10892#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9489#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9490#L625-13 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10248#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9588#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9589#L632-39 assume !(1 == ~t4_pc~0); 10737#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 10174#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10175#L644-13 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10728#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10859#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9858#L651-39 assume 1 == ~t5_pc~0; 9859#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9621#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10847#L663-13 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10954#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10992#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11012#L670-39 assume 1 == ~t6_pc~0; 11013#L671-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9533#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9534#L682-13 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9604#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10201#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10202#L689-39 assume !(1 == ~t7_pc~0); 10324#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 10325#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9860#L701-13 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9861#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9728#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9729#L708-39 assume 1 == ~t8_pc~0; 9665#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9666#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9772#L720-13 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9773#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 10655#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10147#L727-39 assume !(1 == ~t9_pc~0); 10148#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 9925#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9926#L739-13 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 10875#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 10704#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10705#L746-39 assume 1 == ~t10_pc~0; 10674#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 10675#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 10940#L758-13 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 10410#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 10411#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10823#L765-39 assume 1 == ~t11_pc~0; 9539#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 9541#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10723#L777-13 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 9879#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 9880#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10447#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9685#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9686#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10942#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10570#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9644#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9645#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10975#L1279-3 assume !(1 == ~T7_E~0); 10123#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10124#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 10118#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 10119#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 10370#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10371#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10032#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10033#L1319-3 assume !(1 == ~E_3~0); 10789#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9751#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9752#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10304#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10305#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 10523#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 10014#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 10015#L1359-3 assume !(1 == ~E_11~0); 10538#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 9605#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9606#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 10232#L923-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 10233#L1709 assume !(0 == start_simulation_~tmp~3#1); 10043#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 10809#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9719#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 10221#L923-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 9682#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9683#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10501#L1672 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 10882#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 9881#L1690-2 [2022-07-14 16:02:59,945 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:59,945 INFO L85 PathProgramCache]: Analyzing trace with hash -1332337988, now seen corresponding path program 1 times [2022-07-14 16:02:59,945 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:59,945 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [395336012] [2022-07-14 16:02:59,945 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:59,945 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:59,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:59,965 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:59,965 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:59,966 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [395336012] [2022-07-14 16:02:59,966 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [395336012] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:59,966 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:59,966 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:59,966 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1209062460] [2022-07-14 16:02:59,966 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:59,966 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:02:59,967 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:02:59,967 INFO L85 PathProgramCache]: Analyzing trace with hash -1000867648, now seen corresponding path program 1 times [2022-07-14 16:02:59,967 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:02:59,967 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1234919181] [2022-07-14 16:02:59,967 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:02:59,967 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:02:59,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:02:59,996 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:02:59,996 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:02:59,996 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1234919181] [2022-07-14 16:02:59,996 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1234919181] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:02:59,996 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:02:59,996 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:02:59,997 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [609942690] [2022-07-14 16:02:59,997 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:02:59,997 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:02:59,997 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:02:59,997 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:02:59,997 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:02:59,998 INFO L87 Difference]: Start difference. First operand 1571 states and 2332 transitions. cyclomatic complexity: 762 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:00,018 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:00,018 INFO L93 Difference]: Finished difference Result 1571 states and 2331 transitions. [2022-07-14 16:03:00,019 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:00,019 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2331 transitions. [2022-07-14 16:03:00,027 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2022-07-14 16:03:00,033 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1571 states and 2331 transitions. [2022-07-14 16:03:00,033 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2022-07-14 16:03:00,034 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2022-07-14 16:03:00,034 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2331 transitions. [2022-07-14 16:03:00,036 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:00,036 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1571 states and 2331 transitions. [2022-07-14 16:03:00,038 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2331 transitions. [2022-07-14 16:03:00,050 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2022-07-14 16:03:00,052 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.4837683004455762) internal successors, (2331), 1570 states have internal predecessors, (2331), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:00,055 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2331 transitions. [2022-07-14 16:03:00,055 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1571 states and 2331 transitions. [2022-07-14 16:03:00,055 INFO L374 stractBuchiCegarLoop]: Abstraction has 1571 states and 2331 transitions. [2022-07-14 16:03:00,055 INFO L287 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-07-14 16:03:00,055 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2331 transitions. [2022-07-14 16:03:00,068 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2022-07-14 16:03:00,069 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:00,069 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:00,070 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:00,070 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:00,071 INFO L752 eck$LassoCheckResult]: Stem: 13290#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 13291#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 13829#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13830#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13699#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 13700#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12707#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12708#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14146#L807-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 13673#L812-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13674#L817-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13951#L822-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 13952#L827-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14035#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14117#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 14118#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 13999#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13847#L1121 assume !(0 == ~M_E~0); 13602#L1121-2 assume !(0 == ~T1_E~0); 12984#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12985#L1131-1 assume !(0 == ~T3_E~0); 13154#L1136-1 assume !(0 == ~T4_E~0); 13250#L1141-1 assume !(0 == ~T5_E~0); 13470#L1146-1 assume !(0 == ~T6_E~0); 13770#L1151-1 assume !(0 == ~T7_E~0); 13310#L1156-1 assume !(0 == ~T8_E~0); 12693#L1161-1 assume !(0 == ~T9_E~0); 12694#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12919#L1171-1 assume !(0 == ~T11_E~0); 12920#L1176-1 assume !(0 == ~E_M~0); 13784#L1181-1 assume !(0 == ~E_1~0); 13912#L1186-1 assume !(0 == ~E_2~0); 13962#L1191-1 assume !(0 == ~E_3~0); 12946#L1196-1 assume !(0 == ~E_4~0); 12947#L1201-1 assume !(0 == ~E_5~0); 14155#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 14000#L1211-1 assume !(0 == ~E_7~0); 14001#L1216-1 assume !(0 == ~E_8~0); 13089#L1221-1 assume !(0 == ~E_9~0); 13090#L1226-1 assume !(0 == ~E_10~0); 12789#L1231-1 assume !(0 == ~E_11~0); 12790#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13785#L556 assume 1 == ~m_pc~0; 13786#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12667#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12668#L568 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13564#L1391 assume !(0 != activate_threads_~tmp~1#1); 13940#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13941#L575 assume !(1 == ~t1_pc~0); 12618#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12619#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12752#L587 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13102#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 13059#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13060#L594 assume 1 == ~t2_pc~0; 12988#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12989#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13455#L606 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12682#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 12683#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12741#L613 assume !(1 == ~t3_pc~0); 12860#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12859#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12785#L625 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12786#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 13469#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13187#L632 assume 1 == ~t4_pc~0; 13188#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13688#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13848#L644 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14156#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 13794#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13545#L651 assume 1 == ~t5_pc~0; 13546#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12873#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12874#L663 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13322#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 12890#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12891#L670 assume !(1 == ~t6_pc~0); 13982#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 13236#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13237#L682 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14079#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13510#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13511#L689 assume 1 == ~t7_pc~0; 14152#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13621#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13622#L701 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13997#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 13413#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13414#L708 assume !(1 == ~t8_pc~0); 12979#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 12980#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14077#L720 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14062#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 13044#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13045#L727 assume 1 == ~t9_pc~0; 13167#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12743#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14159#L739 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14160#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 14147#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13098#L746 assume !(1 == ~t10_pc~0); 13099#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 13747#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13863#L758 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 14071#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 13944#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13259#L765 assume 1 == ~t11_pc~0; 13260#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 13465#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12632#L777 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12633#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 13981#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14059#L1249 assume !(1 == ~M_E~0); 13692#L1249-2 assume !(1 == ~T1_E~0); 13342#L1254-1 assume !(1 == ~T2_E~0); 12678#L1259-1 assume !(1 == ~T3_E~0); 12660#L1264-1 assume !(1 == ~T4_E~0); 12661#L1269-1 assume !(1 == ~T5_E~0); 14178#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14126#L1279-1 assume !(1 == ~T7_E~0); 12861#L1284-1 assume !(1 == ~T8_E~0); 12862#L1289-1 assume !(1 == ~T9_E~0); 13392#L1294-1 assume !(1 == ~T10_E~0); 13393#L1299-1 assume !(1 == ~T11_E~0); 13402#L1304-1 assume !(1 == ~E_M~0); 14172#L1309-1 assume !(1 == ~E_1~0); 14175#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 12808#L1319-1 assume !(1 == ~E_3~0); 12809#L1324-1 assume !(1 == ~E_4~0); 12941#L1329-1 assume !(1 == ~E_5~0); 12942#L1334-1 assume !(1 == ~E_6~0); 14020#L1339-1 assume !(1 == ~E_7~0); 14097#L1344-1 assume !(1 == ~E_8~0); 14098#L1349-1 assume !(1 == ~E_9~0); 13525#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 13526#L1359-1 assume !(1 == ~E_11~0); 13885#L1364-1 assume { :end_inline_reset_delta_events } true; 13030#L1690-2 [2022-07-14 16:03:00,071 INFO L754 eck$LassoCheckResult]: Loop: 13030#L1690-2 assume !false; 13031#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12916#L1096 assume !false; 13894#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 12762#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12763#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 13788#L923 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 13257#L937 assume !(0 != eval_~tmp~0#1); 13258#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13728#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13234#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13235#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14148#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13440#L1131-3 assume !(0 == ~T3_E~0); 13441#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14179#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13795#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12977#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12978#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 14092#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13603#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13604#L1171-3 assume !(0 == ~T11_E~0); 13650#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13026#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13027#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13730#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13731#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 13921#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13922#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13627#L1211-3 assume !(0 == ~E_7~0); 12939#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12940#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 13353#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12996#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 12997#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13217#L556-39 assume 1 == ~m_pc~0; 13738#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 13705#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13096#L568-13 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13097#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 13269#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13663#L575-39 assume 1 == ~t1_pc~0; 13664#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13929#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13790#L587-13 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13791#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13638#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13639#L594-39 assume !(1 == ~t2_pc~0); 13850#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 13641#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13642#L606-13 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14064#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13155#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13156#L613-39 assume 1 == ~t3_pc~0; 14041#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12638#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12639#L625-13 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13398#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12737#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12738#L632-39 assume 1 == ~t4_pc~0; 14009#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13323#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13324#L644-13 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13877#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14008#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13007#L651-39 assume 1 == ~t5_pc~0; 13008#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12770#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13996#L663-13 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14104#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14141#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14161#L670-39 assume 1 == ~t6_pc~0; 14162#L671-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12684#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12685#L682-13 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12756#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13350#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13351#L689-39 assume !(1 == ~t7_pc~0); 13474#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 13475#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13009#L701-13 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13010#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12875#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12876#L708-39 assume !(1 == ~t8_pc~0); 12816#L708-41 is_transmit8_triggered_~__retres1~8#1 := 0; 12815#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12921#L720-13 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12922#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 13804#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13295#L727-39 assume !(1 == ~t9_pc~0); 13296#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 13074#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13075#L739-13 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14024#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 13852#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13853#L746-39 assume !(1 == ~t10_pc~0); 13825#L746-41 is_transmit10_triggered_~__retres1~10#1 := 0; 13824#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14089#L758-13 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13559#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 13560#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13972#L765-39 assume 1 == ~t11_pc~0; 12688#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 12690#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 13872#L777-13 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13028#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 13029#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13596#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12833#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12834#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14091#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13719#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12793#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12794#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14124#L1279-3 assume !(1 == ~T7_E~0); 13272#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13273#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 13265#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 13266#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 13519#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 13520#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13180#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13181#L1319-3 assume !(1 == ~E_3~0); 13938#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12897#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12898#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13453#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13454#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 13672#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 13163#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 13164#L1359-3 assume !(1 == ~E_11~0); 13686#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 12753#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12754#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 13381#L923-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 13382#L1709 assume !(0 == start_simulation_~tmp~3#1); 13192#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 13958#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12868#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 13370#L923-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 12831#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12832#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13649#L1672 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 14031#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 13030#L1690-2 [2022-07-14 16:03:00,071 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:00,071 INFO L85 PathProgramCache]: Analyzing trace with hash -1621157378, now seen corresponding path program 1 times [2022-07-14 16:03:00,072 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:00,072 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [509442194] [2022-07-14 16:03:00,072 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:00,072 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:00,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:00,093 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:00,093 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:00,093 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [509442194] [2022-07-14 16:03:00,093 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [509442194] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:00,093 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:00,094 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:00,094 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1757049269] [2022-07-14 16:03:00,094 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:00,094 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:00,094 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:00,095 INFO L85 PathProgramCache]: Analyzing trace with hash -1581912831, now seen corresponding path program 1 times [2022-07-14 16:03:00,095 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:00,095 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1118850613] [2022-07-14 16:03:00,095 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:00,095 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:00,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:00,125 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:00,125 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:00,125 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1118850613] [2022-07-14 16:03:00,125 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1118850613] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:00,125 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:00,125 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:00,125 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [384137283] [2022-07-14 16:03:00,126 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:00,126 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:00,126 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:00,126 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:00,126 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:00,127 INFO L87 Difference]: Start difference. First operand 1571 states and 2331 transitions. cyclomatic complexity: 761 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:00,148 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:00,148 INFO L93 Difference]: Finished difference Result 1571 states and 2330 transitions. [2022-07-14 16:03:00,148 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:00,149 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2330 transitions. [2022-07-14 16:03:00,155 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2022-07-14 16:03:00,161 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1571 states and 2330 transitions. [2022-07-14 16:03:00,161 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2022-07-14 16:03:00,162 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2022-07-14 16:03:00,162 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2330 transitions. [2022-07-14 16:03:00,163 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:00,163 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1571 states and 2330 transitions. [2022-07-14 16:03:00,165 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2330 transitions. [2022-07-14 16:03:00,179 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2022-07-14 16:03:00,181 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.4831317632081478) internal successors, (2330), 1570 states have internal predecessors, (2330), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:00,184 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2330 transitions. [2022-07-14 16:03:00,184 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1571 states and 2330 transitions. [2022-07-14 16:03:00,184 INFO L374 stractBuchiCegarLoop]: Abstraction has 1571 states and 2330 transitions. [2022-07-14 16:03:00,184 INFO L287 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-07-14 16:03:00,184 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2330 transitions. [2022-07-14 16:03:00,189 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2022-07-14 16:03:00,189 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:00,189 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:00,190 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:00,190 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:00,191 INFO L752 eck$LassoCheckResult]: Stem: 16437#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 16438#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 16978#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16979#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16848#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 16849#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15856#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15857#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17295#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16822#L812-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 16823#L817-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17100#L822-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17101#L827-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17184#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 17266#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 17267#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 17148#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16996#L1121 assume !(0 == ~M_E~0); 16751#L1121-2 assume !(0 == ~T1_E~0); 16132#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16133#L1131-1 assume !(0 == ~T3_E~0); 16303#L1136-1 assume !(0 == ~T4_E~0); 16399#L1141-1 assume !(0 == ~T5_E~0); 16619#L1146-1 assume !(0 == ~T6_E~0); 16919#L1151-1 assume !(0 == ~T7_E~0); 16459#L1156-1 assume !(0 == ~T8_E~0); 15842#L1161-1 assume !(0 == ~T9_E~0); 15843#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 16068#L1171-1 assume !(0 == ~T11_E~0); 16069#L1176-1 assume !(0 == ~E_M~0); 16933#L1181-1 assume !(0 == ~E_1~0); 17061#L1186-1 assume !(0 == ~E_2~0); 17111#L1191-1 assume !(0 == ~E_3~0); 16095#L1196-1 assume !(0 == ~E_4~0); 16096#L1201-1 assume !(0 == ~E_5~0); 17304#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 17149#L1211-1 assume !(0 == ~E_7~0); 17150#L1216-1 assume !(0 == ~E_8~0); 16238#L1221-1 assume !(0 == ~E_9~0); 16239#L1226-1 assume !(0 == ~E_10~0); 15938#L1231-1 assume !(0 == ~E_11~0); 15939#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16934#L556 assume 1 == ~m_pc~0; 16935#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 15816#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15817#L568 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16712#L1391 assume !(0 != activate_threads_~tmp~1#1); 17089#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17090#L575 assume !(1 == ~t1_pc~0); 15767#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 15768#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15901#L587 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16251#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 16208#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16209#L594 assume 1 == ~t2_pc~0; 16137#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16138#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16604#L606 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15831#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 15832#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15890#L613 assume !(1 == ~t3_pc~0); 16009#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 16008#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15934#L625 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15935#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 16618#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16336#L632 assume 1 == ~t4_pc~0; 16337#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16837#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16997#L644 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17305#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 16943#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16694#L651 assume 1 == ~t5_pc~0; 16695#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16022#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16023#L663 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16471#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 16039#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16040#L670 assume !(1 == ~t6_pc~0); 17131#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 16385#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16386#L682 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17227#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16659#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16660#L689 assume 1 == ~t7_pc~0; 17301#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16770#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16771#L701 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17146#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 16562#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16563#L708 assume !(1 == ~t8_pc~0); 16128#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 16129#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17226#L720 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17211#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 16193#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16194#L727 assume 1 == ~t9_pc~0; 16316#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15892#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17308#L739 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17309#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 17296#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16247#L746 assume !(1 == ~t10_pc~0); 16248#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 16896#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17012#L758 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17220#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 17093#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16408#L765 assume 1 == ~t11_pc~0; 16409#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 16614#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15781#L777 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 15782#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 17130#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17208#L1249 assume !(1 == ~M_E~0); 16841#L1249-2 assume !(1 == ~T1_E~0); 16491#L1254-1 assume !(1 == ~T2_E~0); 15827#L1259-1 assume !(1 == ~T3_E~0); 15809#L1264-1 assume !(1 == ~T4_E~0); 15810#L1269-1 assume !(1 == ~T5_E~0); 17327#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17275#L1279-1 assume !(1 == ~T7_E~0); 16010#L1284-1 assume !(1 == ~T8_E~0); 16011#L1289-1 assume !(1 == ~T9_E~0); 16541#L1294-1 assume !(1 == ~T10_E~0); 16542#L1299-1 assume !(1 == ~T11_E~0); 16551#L1304-1 assume !(1 == ~E_M~0); 17321#L1309-1 assume !(1 == ~E_1~0); 17324#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 15957#L1319-1 assume !(1 == ~E_3~0); 15958#L1324-1 assume !(1 == ~E_4~0); 16090#L1329-1 assume !(1 == ~E_5~0); 16091#L1334-1 assume !(1 == ~E_6~0); 17169#L1339-1 assume !(1 == ~E_7~0); 17246#L1344-1 assume !(1 == ~E_8~0); 17247#L1349-1 assume !(1 == ~E_9~0); 16674#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 16675#L1359-1 assume !(1 == ~E_11~0); 17034#L1364-1 assume { :end_inline_reset_delta_events } true; 16179#L1690-2 [2022-07-14 16:03:00,191 INFO L754 eck$LassoCheckResult]: Loop: 16179#L1690-2 assume !false; 16180#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16065#L1096 assume !false; 17043#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 15911#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15912#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 16937#L923 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 16406#L937 assume !(0 != eval_~tmp~0#1); 16407#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16877#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16381#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16382#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17297#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16589#L1131-3 assume !(0 == ~T3_E~0); 16590#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17328#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16944#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16126#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16127#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17241#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16752#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 16753#L1171-3 assume !(0 == ~T11_E~0); 16798#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16175#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16176#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16879#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16880#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17070#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17071#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 16776#L1211-3 assume !(0 == ~E_7~0); 16088#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16089#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 16502#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 16145#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16146#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16366#L556-39 assume 1 == ~m_pc~0; 16887#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 16854#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16245#L568-13 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16246#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 16418#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16812#L575-39 assume 1 == ~t1_pc~0; 16813#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17078#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16939#L587-13 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16940#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16787#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16788#L594-39 assume !(1 == ~t2_pc~0); 16999#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 16790#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16791#L606-13 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17213#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16304#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16305#L613-39 assume 1 == ~t3_pc~0; 17190#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15787#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15788#L625-13 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16546#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15886#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15887#L632-39 assume 1 == ~t4_pc~0; 17158#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16472#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16473#L644-13 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17026#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17157#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16156#L651-39 assume 1 == ~t5_pc~0; 16157#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15919#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17145#L663-13 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17252#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17290#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17310#L670-39 assume !(1 == ~t6_pc~0); 16889#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 15833#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15834#L682-13 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15902#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16499#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16500#L689-39 assume 1 == ~t7_pc~0; 16722#L690-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16624#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16158#L701-13 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16159#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16026#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16027#L708-39 assume 1 == ~t8_pc~0; 15963#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15964#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16072#L720-13 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16073#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16953#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16445#L727-39 assume !(1 == ~t9_pc~0); 16446#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 16223#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16224#L739-13 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17173#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 17002#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17003#L746-39 assume 1 == ~t10_pc~0; 16972#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 16973#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17238#L758-13 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16708#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16709#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17121#L765-39 assume 1 == ~t11_pc~0; 15837#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 15839#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17021#L777-13 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 16177#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 16178#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16745#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15983#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15984#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17240#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16868#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15942#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15943#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17273#L1279-3 assume !(1 == ~T7_E~0); 16421#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16422#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16416#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 16417#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 16668#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16669#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16333#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16334#L1319-3 assume !(1 == ~E_3~0); 17087#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16052#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16053#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16602#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16603#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16821#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 16312#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 16313#L1359-3 assume !(1 == ~E_11~0); 16836#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 15903#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15904#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 16530#L923-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 16531#L1709 assume !(0 == start_simulation_~tmp~3#1); 16341#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 17107#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 16017#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 16519#L923-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 15980#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15981#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16799#L1672 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 17180#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 16179#L1690-2 [2022-07-14 16:03:00,191 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:00,191 INFO L85 PathProgramCache]: Analyzing trace with hash -1076284804, now seen corresponding path program 1 times [2022-07-14 16:03:00,192 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:00,192 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2121225461] [2022-07-14 16:03:00,192 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:00,192 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:00,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:00,211 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:00,211 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:00,211 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2121225461] [2022-07-14 16:03:00,211 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2121225461] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:00,211 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:00,211 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:00,212 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1297921383] [2022-07-14 16:03:00,212 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:00,212 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:00,212 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:00,212 INFO L85 PathProgramCache]: Analyzing trace with hash 210812735, now seen corresponding path program 1 times [2022-07-14 16:03:00,213 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:00,213 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [950466479] [2022-07-14 16:03:00,213 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:00,213 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:00,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:00,244 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:00,245 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:00,245 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [950466479] [2022-07-14 16:03:00,245 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [950466479] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:00,245 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:00,245 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:00,246 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1815424725] [2022-07-14 16:03:00,246 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:00,246 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:00,246 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:00,247 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:00,247 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:00,247 INFO L87 Difference]: Start difference. First operand 1571 states and 2330 transitions. cyclomatic complexity: 760 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:00,268 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:00,268 INFO L93 Difference]: Finished difference Result 1571 states and 2329 transitions. [2022-07-14 16:03:00,269 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:00,270 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2329 transitions. [2022-07-14 16:03:00,275 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2022-07-14 16:03:00,281 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1571 states and 2329 transitions. [2022-07-14 16:03:00,281 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2022-07-14 16:03:00,282 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2022-07-14 16:03:00,282 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2329 transitions. [2022-07-14 16:03:00,283 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:00,284 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1571 states and 2329 transitions. [2022-07-14 16:03:00,285 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2329 transitions. [2022-07-14 16:03:00,299 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2022-07-14 16:03:00,301 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.4824952259707194) internal successors, (2329), 1570 states have internal predecessors, (2329), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:00,304 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2329 transitions. [2022-07-14 16:03:00,305 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1571 states and 2329 transitions. [2022-07-14 16:03:00,305 INFO L374 stractBuchiCegarLoop]: Abstraction has 1571 states and 2329 transitions. [2022-07-14 16:03:00,305 INFO L287 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-07-14 16:03:00,305 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2329 transitions. [2022-07-14 16:03:00,309 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2022-07-14 16:03:00,309 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:00,309 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:00,310 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:00,310 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:00,311 INFO L752 eck$LassoCheckResult]: Stem: 19586#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 19587#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 20127#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20128#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19997#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 19998#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19005#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19006#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20444#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19971#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19972#L817-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 20249#L822-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 20250#L827-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 20333#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 20415#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 20416#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 20297#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20145#L1121 assume !(0 == ~M_E~0); 19900#L1121-2 assume !(0 == ~T1_E~0); 19281#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19282#L1131-1 assume !(0 == ~T3_E~0); 19452#L1136-1 assume !(0 == ~T4_E~0); 19548#L1141-1 assume !(0 == ~T5_E~0); 19768#L1146-1 assume !(0 == ~T6_E~0); 20068#L1151-1 assume !(0 == ~T7_E~0); 19608#L1156-1 assume !(0 == ~T8_E~0); 18991#L1161-1 assume !(0 == ~T9_E~0); 18992#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19217#L1171-1 assume !(0 == ~T11_E~0); 19218#L1176-1 assume !(0 == ~E_M~0); 20082#L1181-1 assume !(0 == ~E_1~0); 20210#L1186-1 assume !(0 == ~E_2~0); 20260#L1191-1 assume !(0 == ~E_3~0); 19244#L1196-1 assume !(0 == ~E_4~0); 19245#L1201-1 assume !(0 == ~E_5~0); 20453#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 20298#L1211-1 assume !(0 == ~E_7~0); 20299#L1216-1 assume !(0 == ~E_8~0); 19387#L1221-1 assume !(0 == ~E_9~0); 19388#L1226-1 assume !(0 == ~E_10~0); 19087#L1231-1 assume !(0 == ~E_11~0); 19088#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20083#L556 assume 1 == ~m_pc~0; 20084#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 18965#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18966#L568 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19861#L1391 assume !(0 != activate_threads_~tmp~1#1); 20238#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20239#L575 assume !(1 == ~t1_pc~0); 18916#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 18917#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19050#L587 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19400#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 19357#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19358#L594 assume 1 == ~t2_pc~0; 19286#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19287#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19753#L606 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18980#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 18981#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19039#L613 assume !(1 == ~t3_pc~0); 19158#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 19157#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19083#L625 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19084#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 19767#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19485#L632 assume 1 == ~t4_pc~0; 19486#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19986#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20146#L644 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20454#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 20092#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19843#L651 assume 1 == ~t5_pc~0; 19844#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19171#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19172#L663 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19620#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 19188#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19189#L670 assume !(1 == ~t6_pc~0); 20280#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19534#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19535#L682 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20376#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19808#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19809#L689 assume 1 == ~t7_pc~0; 20450#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19919#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19920#L701 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20295#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 19711#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19712#L708 assume !(1 == ~t8_pc~0); 19277#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19278#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20375#L720 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20360#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 19342#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19343#L727 assume 1 == ~t9_pc~0; 19465#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19041#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20457#L739 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20458#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 20445#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19396#L746 assume !(1 == ~t10_pc~0); 19397#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 20045#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20161#L758 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20369#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 20242#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 19557#L765 assume 1 == ~t11_pc~0; 19558#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 19763#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18930#L777 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 18931#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 20279#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20357#L1249 assume !(1 == ~M_E~0); 19990#L1249-2 assume !(1 == ~T1_E~0); 19640#L1254-1 assume !(1 == ~T2_E~0); 18976#L1259-1 assume !(1 == ~T3_E~0); 18958#L1264-1 assume !(1 == ~T4_E~0); 18959#L1269-1 assume !(1 == ~T5_E~0); 20476#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20424#L1279-1 assume !(1 == ~T7_E~0); 19159#L1284-1 assume !(1 == ~T8_E~0); 19160#L1289-1 assume !(1 == ~T9_E~0); 19690#L1294-1 assume !(1 == ~T10_E~0); 19691#L1299-1 assume !(1 == ~T11_E~0); 19700#L1304-1 assume !(1 == ~E_M~0); 20470#L1309-1 assume !(1 == ~E_1~0); 20473#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 19106#L1319-1 assume !(1 == ~E_3~0); 19107#L1324-1 assume !(1 == ~E_4~0); 19239#L1329-1 assume !(1 == ~E_5~0); 19240#L1334-1 assume !(1 == ~E_6~0); 20318#L1339-1 assume !(1 == ~E_7~0); 20395#L1344-1 assume !(1 == ~E_8~0); 20396#L1349-1 assume !(1 == ~E_9~0); 19823#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 19824#L1359-1 assume !(1 == ~E_11~0); 20183#L1364-1 assume { :end_inline_reset_delta_events } true; 19328#L1690-2 [2022-07-14 16:03:00,311 INFO L754 eck$LassoCheckResult]: Loop: 19328#L1690-2 assume !false; 19329#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19214#L1096 assume !false; 20192#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 19060#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 19061#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 20086#L923 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 19555#L937 assume !(0 != eval_~tmp~0#1); 19556#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20026#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19530#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19531#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20446#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19738#L1131-3 assume !(0 == ~T3_E~0); 19739#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20477#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20093#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19275#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19276#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20390#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19901#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19902#L1171-3 assume !(0 == ~T11_E~0); 19947#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19324#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19325#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20028#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20029#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20219#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20220#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 19925#L1211-3 assume !(0 == ~E_7~0); 19237#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19238#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19651#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 19294#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 19295#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19515#L556-39 assume 1 == ~m_pc~0; 20036#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 20003#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19394#L568-13 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19395#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 19567#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19961#L575-39 assume 1 == ~t1_pc~0; 19962#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20227#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20088#L587-13 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20089#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19936#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19937#L594-39 assume !(1 == ~t2_pc~0); 20148#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 19939#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19940#L606-13 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20362#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19453#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19454#L613-39 assume 1 == ~t3_pc~0; 20339#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18936#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18937#L625-13 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19695#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19035#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19036#L632-39 assume 1 == ~t4_pc~0; 20307#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19621#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19622#L644-13 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20175#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20306#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19305#L651-39 assume 1 == ~t5_pc~0; 19306#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19068#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20294#L663-13 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20401#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20439#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20459#L670-39 assume !(1 == ~t6_pc~0); 20038#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 18982#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18983#L682-13 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19051#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19648#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19649#L689-39 assume !(1 == ~t7_pc~0); 19772#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 19773#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19307#L701-13 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19308#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19175#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19176#L708-39 assume 1 == ~t8_pc~0; 19112#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19113#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19221#L720-13 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19222#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20102#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19594#L727-39 assume !(1 == ~t9_pc~0); 19595#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 19372#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19373#L739-13 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20322#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 20151#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20152#L746-39 assume 1 == ~t10_pc~0; 20121#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 20122#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20387#L758-13 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 19857#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 19858#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20270#L765-39 assume 1 == ~t11_pc~0; 18986#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 18988#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20170#L777-13 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 19326#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 19327#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19894#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19132#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19133#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20389#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20017#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19091#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19092#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20422#L1279-3 assume !(1 == ~T7_E~0); 19570#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19571#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19565#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19566#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 19817#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19818#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19482#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19483#L1319-3 assume !(1 == ~E_3~0); 20236#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19201#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19202#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19751#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19752#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19970#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 19461#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 19462#L1359-3 assume !(1 == ~E_11~0); 19985#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 19052#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 19053#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 19679#L923-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 19680#L1709 assume !(0 == start_simulation_~tmp~3#1); 19490#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 20256#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 19166#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 19668#L923-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 19129#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19130#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19948#L1672 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 20329#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 19328#L1690-2 [2022-07-14 16:03:00,311 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:00,312 INFO L85 PathProgramCache]: Analyzing trace with hash -1751444930, now seen corresponding path program 1 times [2022-07-14 16:03:00,312 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:00,312 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [412719702] [2022-07-14 16:03:00,312 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:00,312 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:00,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:00,332 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:00,332 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:00,332 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [412719702] [2022-07-14 16:03:00,332 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [412719702] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:00,333 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:00,333 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:00,333 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2055736943] [2022-07-14 16:03:00,333 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:00,333 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:00,333 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:00,334 INFO L85 PathProgramCache]: Analyzing trace with hash -1946660288, now seen corresponding path program 2 times [2022-07-14 16:03:00,334 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:00,334 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2130422850] [2022-07-14 16:03:00,334 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:00,334 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:00,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:00,370 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:00,370 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:00,370 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2130422850] [2022-07-14 16:03:00,370 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2130422850] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:00,371 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:00,371 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:00,371 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1492281872] [2022-07-14 16:03:00,371 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:00,371 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:00,371 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:00,372 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:00,372 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:00,372 INFO L87 Difference]: Start difference. First operand 1571 states and 2329 transitions. cyclomatic complexity: 759 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:00,391 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:00,391 INFO L93 Difference]: Finished difference Result 1571 states and 2328 transitions. [2022-07-14 16:03:00,391 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:00,393 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2328 transitions. [2022-07-14 16:03:00,398 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2022-07-14 16:03:00,403 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1571 states and 2328 transitions. [2022-07-14 16:03:00,403 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2022-07-14 16:03:00,404 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2022-07-14 16:03:00,404 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2328 transitions. [2022-07-14 16:03:00,406 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:00,406 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1571 states and 2328 transitions. [2022-07-14 16:03:00,407 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2328 transitions. [2022-07-14 16:03:00,418 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2022-07-14 16:03:00,420 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.481858688733291) internal successors, (2328), 1570 states have internal predecessors, (2328), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:00,423 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2328 transitions. [2022-07-14 16:03:00,423 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1571 states and 2328 transitions. [2022-07-14 16:03:00,423 INFO L374 stractBuchiCegarLoop]: Abstraction has 1571 states and 2328 transitions. [2022-07-14 16:03:00,423 INFO L287 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-07-14 16:03:00,423 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2328 transitions. [2022-07-14 16:03:00,427 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2022-07-14 16:03:00,427 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:00,427 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:00,428 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:00,428 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:00,428 INFO L752 eck$LassoCheckResult]: Stem: 22735#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 22736#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 23276#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23277#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23146#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 23147#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22154#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22155#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23593#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 23120#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23121#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 23398#L822-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 23399#L827-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 23482#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 23564#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 23565#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 23446#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23294#L1121 assume !(0 == ~M_E~0); 23049#L1121-2 assume !(0 == ~T1_E~0); 22430#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22431#L1131-1 assume !(0 == ~T3_E~0); 22601#L1136-1 assume !(0 == ~T4_E~0); 22697#L1141-1 assume !(0 == ~T5_E~0); 22917#L1146-1 assume !(0 == ~T6_E~0); 23217#L1151-1 assume !(0 == ~T7_E~0); 22757#L1156-1 assume !(0 == ~T8_E~0); 22140#L1161-1 assume !(0 == ~T9_E~0); 22141#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 22366#L1171-1 assume !(0 == ~T11_E~0); 22367#L1176-1 assume !(0 == ~E_M~0); 23231#L1181-1 assume !(0 == ~E_1~0); 23359#L1186-1 assume !(0 == ~E_2~0); 23409#L1191-1 assume !(0 == ~E_3~0); 22393#L1196-1 assume !(0 == ~E_4~0); 22394#L1201-1 assume !(0 == ~E_5~0); 23602#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 23447#L1211-1 assume !(0 == ~E_7~0); 23448#L1216-1 assume !(0 == ~E_8~0); 22536#L1221-1 assume !(0 == ~E_9~0); 22537#L1226-1 assume !(0 == ~E_10~0); 22236#L1231-1 assume !(0 == ~E_11~0); 22237#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23232#L556 assume 1 == ~m_pc~0; 23233#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22114#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22115#L568 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23010#L1391 assume !(0 != activate_threads_~tmp~1#1); 23387#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23388#L575 assume !(1 == ~t1_pc~0); 22065#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22066#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22199#L587 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22549#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 22506#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22507#L594 assume 1 == ~t2_pc~0; 22435#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22436#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22902#L606 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22129#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 22130#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22188#L613 assume !(1 == ~t3_pc~0); 22307#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 22306#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22232#L625 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22233#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 22916#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22634#L632 assume 1 == ~t4_pc~0; 22635#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 23135#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23295#L644 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23603#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 23241#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22992#L651 assume 1 == ~t5_pc~0; 22993#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22320#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22321#L663 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22769#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 22337#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22338#L670 assume !(1 == ~t6_pc~0); 23429#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 22683#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22684#L682 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23525#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22957#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22958#L689 assume 1 == ~t7_pc~0; 23599#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23068#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23069#L701 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23444#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 22860#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22861#L708 assume !(1 == ~t8_pc~0); 22426#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22427#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23524#L720 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 23509#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 22491#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22492#L727 assume 1 == ~t9_pc~0; 22614#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22190#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23606#L739 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23607#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 23594#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22545#L746 assume !(1 == ~t10_pc~0); 22546#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 23194#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 23310#L758 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 23518#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 23391#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22706#L765 assume 1 == ~t11_pc~0; 22707#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 22912#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 22079#L777 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 22080#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 23428#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23506#L1249 assume !(1 == ~M_E~0); 23139#L1249-2 assume !(1 == ~T1_E~0); 22789#L1254-1 assume !(1 == ~T2_E~0); 22125#L1259-1 assume !(1 == ~T3_E~0); 22107#L1264-1 assume !(1 == ~T4_E~0); 22108#L1269-1 assume !(1 == ~T5_E~0); 23625#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23573#L1279-1 assume !(1 == ~T7_E~0); 22308#L1284-1 assume !(1 == ~T8_E~0); 22309#L1289-1 assume !(1 == ~T9_E~0); 22839#L1294-1 assume !(1 == ~T10_E~0); 22840#L1299-1 assume !(1 == ~T11_E~0); 22849#L1304-1 assume !(1 == ~E_M~0); 23619#L1309-1 assume !(1 == ~E_1~0); 23622#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 22255#L1319-1 assume !(1 == ~E_3~0); 22256#L1324-1 assume !(1 == ~E_4~0); 22388#L1329-1 assume !(1 == ~E_5~0); 22389#L1334-1 assume !(1 == ~E_6~0); 23467#L1339-1 assume !(1 == ~E_7~0); 23544#L1344-1 assume !(1 == ~E_8~0); 23545#L1349-1 assume !(1 == ~E_9~0); 22972#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 22973#L1359-1 assume !(1 == ~E_11~0); 23332#L1364-1 assume { :end_inline_reset_delta_events } true; 22477#L1690-2 [2022-07-14 16:03:00,429 INFO L754 eck$LassoCheckResult]: Loop: 22477#L1690-2 assume !false; 22478#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22363#L1096 assume !false; 23341#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 22209#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 22210#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 23235#L923 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 22704#L937 assume !(0 != eval_~tmp~0#1); 22705#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 23175#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22679#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22680#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 23595#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22887#L1131-3 assume !(0 == ~T3_E~0); 22888#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 23626#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 23242#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22424#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22425#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 23539#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 23050#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 23051#L1171-3 assume !(0 == ~T11_E~0); 23096#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 22473#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22474#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23177#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23178#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23368#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 23369#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 23074#L1211-3 assume !(0 == ~E_7~0); 22386#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 22387#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 22800#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 22443#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22444#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22664#L556-39 assume 1 == ~m_pc~0; 23185#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 23152#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22543#L568-13 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22544#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 22716#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23110#L575-39 assume 1 == ~t1_pc~0; 23111#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 23376#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23237#L587-13 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23238#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23085#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23086#L594-39 assume !(1 == ~t2_pc~0); 23297#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 23088#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23089#L606-13 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23511#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22602#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22603#L613-39 assume 1 == ~t3_pc~0; 23488#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22085#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22086#L625-13 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22844#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22184#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22185#L632-39 assume 1 == ~t4_pc~0; 23456#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22770#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22771#L644-13 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23324#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23455#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22454#L651-39 assume 1 == ~t5_pc~0; 22455#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22217#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23443#L663-13 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23550#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 23588#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23608#L670-39 assume !(1 == ~t6_pc~0); 23187#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 22131#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22132#L682-13 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22200#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22797#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22798#L689-39 assume !(1 == ~t7_pc~0); 22921#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 22922#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22456#L701-13 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22457#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22324#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22325#L708-39 assume 1 == ~t8_pc~0; 22261#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22262#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22370#L720-13 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22371#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 23251#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22743#L727-39 assume !(1 == ~t9_pc~0); 22744#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 22521#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22522#L739-13 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23471#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 23300#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23301#L746-39 assume 1 == ~t10_pc~0; 23270#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 23271#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 23536#L758-13 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 23006#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 23007#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 23419#L765-39 assume 1 == ~t11_pc~0; 22135#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 22137#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 23319#L777-13 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 22475#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 22476#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23043#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22281#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22282#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23538#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23166#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22240#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22241#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23571#L1279-3 assume !(1 == ~T7_E~0); 22719#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22720#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22714#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22715#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 22966#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22967#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22631#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22632#L1319-3 assume !(1 == ~E_3~0); 23385#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22350#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22351#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22900#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22901#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 23119#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 22610#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 22611#L1359-3 assume !(1 == ~E_11~0); 23134#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 22201#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 22202#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 22828#L923-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 22829#L1709 assume !(0 == start_simulation_~tmp~3#1); 22639#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 23405#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 22315#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 22817#L923-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 22278#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22279#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23097#L1672 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 23478#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 22477#L1690-2 [2022-07-14 16:03:00,429 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:00,429 INFO L85 PathProgramCache]: Analyzing trace with hash -803392964, now seen corresponding path program 1 times [2022-07-14 16:03:00,429 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:00,430 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [697647358] [2022-07-14 16:03:00,430 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:00,431 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:00,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:00,450 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:00,450 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:00,450 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [697647358] [2022-07-14 16:03:00,450 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [697647358] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:00,452 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:00,452 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:00,453 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [887366723] [2022-07-14 16:03:00,454 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:00,454 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:00,454 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:00,454 INFO L85 PathProgramCache]: Analyzing trace with hash -1946660288, now seen corresponding path program 3 times [2022-07-14 16:03:00,455 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:00,455 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [305787924] [2022-07-14 16:03:00,455 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:00,455 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:00,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:00,501 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:00,501 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:00,502 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [305787924] [2022-07-14 16:03:00,503 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [305787924] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:00,503 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:00,503 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:00,503 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1029017222] [2022-07-14 16:03:00,505 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:00,505 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:00,505 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:00,505 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:00,506 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:00,506 INFO L87 Difference]: Start difference. First operand 1571 states and 2328 transitions. cyclomatic complexity: 758 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:00,525 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:00,525 INFO L93 Difference]: Finished difference Result 1571 states and 2327 transitions. [2022-07-14 16:03:00,525 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:00,527 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2327 transitions. [2022-07-14 16:03:00,533 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2022-07-14 16:03:00,538 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1571 states and 2327 transitions. [2022-07-14 16:03:00,538 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2022-07-14 16:03:00,540 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2022-07-14 16:03:00,540 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2327 transitions. [2022-07-14 16:03:00,542 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:00,542 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1571 states and 2327 transitions. [2022-07-14 16:03:00,543 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2327 transitions. [2022-07-14 16:03:00,554 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2022-07-14 16:03:00,555 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.4812221514958626) internal successors, (2327), 1570 states have internal predecessors, (2327), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:00,558 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2327 transitions. [2022-07-14 16:03:00,559 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1571 states and 2327 transitions. [2022-07-14 16:03:00,559 INFO L374 stractBuchiCegarLoop]: Abstraction has 1571 states and 2327 transitions. [2022-07-14 16:03:00,559 INFO L287 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-07-14 16:03:00,559 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2327 transitions. [2022-07-14 16:03:00,562 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2022-07-14 16:03:00,563 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:00,563 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:00,564 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:00,564 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:00,564 INFO L752 eck$LassoCheckResult]: Stem: 25886#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 25887#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 26425#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26426#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26295#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 26296#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25303#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25304#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26742#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26269#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26270#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26547#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26548#L827-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 26631#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 26713#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 26714#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 26595#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26443#L1121 assume !(0 == ~M_E~0); 26198#L1121-2 assume !(0 == ~T1_E~0); 25580#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25581#L1131-1 assume !(0 == ~T3_E~0); 25750#L1136-1 assume !(0 == ~T4_E~0); 25846#L1141-1 assume !(0 == ~T5_E~0); 26071#L1146-1 assume !(0 == ~T6_E~0); 26366#L1151-1 assume !(0 == ~T7_E~0); 25906#L1156-1 assume !(0 == ~T8_E~0); 25289#L1161-1 assume !(0 == ~T9_E~0); 25290#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25515#L1171-1 assume !(0 == ~T11_E~0); 25516#L1176-1 assume !(0 == ~E_M~0); 26380#L1181-1 assume !(0 == ~E_1~0); 26508#L1186-1 assume !(0 == ~E_2~0); 26558#L1191-1 assume !(0 == ~E_3~0); 25542#L1196-1 assume !(0 == ~E_4~0); 25543#L1201-1 assume !(0 == ~E_5~0); 26751#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 26596#L1211-1 assume !(0 == ~E_7~0); 26597#L1216-1 assume !(0 == ~E_8~0); 25685#L1221-1 assume !(0 == ~E_9~0); 25686#L1226-1 assume !(0 == ~E_10~0); 25385#L1231-1 assume !(0 == ~E_11~0); 25386#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26381#L556 assume 1 == ~m_pc~0; 26382#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25263#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25264#L568 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26160#L1391 assume !(0 != activate_threads_~tmp~1#1); 26536#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26537#L575 assume !(1 == ~t1_pc~0); 25214#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25215#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25348#L587 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25698#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 25655#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25656#L594 assume 1 == ~t2_pc~0; 25584#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25585#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26051#L606 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25280#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 25281#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25337#L613 assume !(1 == ~t3_pc~0); 25456#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 25455#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25381#L625 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25382#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 26065#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25783#L632 assume 1 == ~t4_pc~0; 25784#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 26284#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26444#L644 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26752#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 26390#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26141#L651 assume 1 == ~t5_pc~0; 26142#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25469#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25470#L663 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25918#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 25486#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25487#L670 assume !(1 == ~t6_pc~0); 26578#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 25834#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25835#L682 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26675#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26106#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26107#L689 assume 1 == ~t7_pc~0; 26748#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26217#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26218#L701 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26593#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 26009#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26010#L708 assume !(1 == ~t8_pc~0); 25575#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 25576#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26673#L720 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26658#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 25640#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25641#L727 assume 1 == ~t9_pc~0; 25763#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25339#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26755#L739 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26756#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 26743#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25694#L746 assume !(1 == ~t10_pc~0); 25695#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 26343#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26459#L758 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26667#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 26540#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 25855#L765 assume 1 == ~t11_pc~0; 25856#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 26061#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25228#L777 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25229#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 26577#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26655#L1249 assume !(1 == ~M_E~0); 26288#L1249-2 assume !(1 == ~T1_E~0); 25938#L1254-1 assume !(1 == ~T2_E~0); 25274#L1259-1 assume !(1 == ~T3_E~0); 25256#L1264-1 assume !(1 == ~T4_E~0); 25257#L1269-1 assume !(1 == ~T5_E~0); 26774#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26722#L1279-1 assume !(1 == ~T7_E~0); 25457#L1284-1 assume !(1 == ~T8_E~0); 25458#L1289-1 assume !(1 == ~T9_E~0); 25988#L1294-1 assume !(1 == ~T10_E~0); 25989#L1299-1 assume !(1 == ~T11_E~0); 25998#L1304-1 assume !(1 == ~E_M~0); 26768#L1309-1 assume !(1 == ~E_1~0); 26771#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 25404#L1319-1 assume !(1 == ~E_3~0); 25405#L1324-1 assume !(1 == ~E_4~0); 25537#L1329-1 assume !(1 == ~E_5~0); 25538#L1334-1 assume !(1 == ~E_6~0); 26616#L1339-1 assume !(1 == ~E_7~0); 26693#L1344-1 assume !(1 == ~E_8~0); 26694#L1349-1 assume !(1 == ~E_9~0); 26121#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 26122#L1359-1 assume !(1 == ~E_11~0); 26481#L1364-1 assume { :end_inline_reset_delta_events } true; 25626#L1690-2 [2022-07-14 16:03:00,565 INFO L754 eck$LassoCheckResult]: Loop: 25626#L1690-2 assume !false; 25627#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25512#L1096 assume !false; 26490#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 25358#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 25359#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 26384#L923 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 25853#L937 assume !(0 != eval_~tmp~0#1); 25854#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 26324#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25830#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25831#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26744#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26036#L1131-3 assume !(0 == ~T3_E~0); 26037#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26775#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 26391#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25573#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 25574#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 26688#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 26199#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 26200#L1171-3 assume !(0 == ~T11_E~0); 26246#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25622#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25623#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 26326#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26327#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26517#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26518#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 26223#L1211-3 assume !(0 == ~E_7~0); 25535#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 25536#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 25949#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 25592#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 25593#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25813#L556-39 assume 1 == ~m_pc~0; 26334#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 26301#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25692#L568-13 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25693#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 25865#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26259#L575-39 assume 1 == ~t1_pc~0; 26260#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 26525#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26386#L587-13 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26387#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26234#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26235#L594-39 assume !(1 == ~t2_pc~0); 26446#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 26237#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26238#L606-13 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26660#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25751#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25752#L613-39 assume 1 == ~t3_pc~0; 26637#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25234#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25235#L625-13 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25997#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25333#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25334#L632-39 assume !(1 == ~t4_pc~0); 26482#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 25919#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25920#L644-13 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26473#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26604#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25600#L651-39 assume 1 == ~t5_pc~0; 25601#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25364#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26592#L663-13 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26699#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26737#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26757#L670-39 assume !(1 == ~t6_pc~0); 26336#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 25278#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25279#L682-13 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25349#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25946#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25947#L689-39 assume !(1 == ~t7_pc~0); 26069#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 26070#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25605#L701-13 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25606#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25473#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25474#L708-39 assume 1 == ~t8_pc~0; 25410#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 25411#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25517#L720-13 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25518#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 26400#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25892#L727-39 assume !(1 == ~t9_pc~0); 25893#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 25670#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25671#L739-13 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26620#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 26448#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 26449#L746-39 assume 1 == ~t10_pc~0; 26419#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 26420#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26685#L758-13 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26155#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 26156#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26568#L765-39 assume 1 == ~t11_pc~0; 25284#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25286#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 26468#L777-13 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25624#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 25625#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26192#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25430#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25431#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26687#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26315#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25389#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25390#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26720#L1279-3 assume !(1 == ~T7_E~0); 25868#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25869#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25861#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25862#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 26115#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 26116#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25776#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25777#L1319-3 assume !(1 == ~E_3~0); 26534#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25493#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25494#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 26049#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 26050#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 26268#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 25759#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 25760#L1359-3 assume !(1 == ~E_11~0); 26282#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 25350#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 25351#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 25977#L923-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 25978#L1709 assume !(0 == start_simulation_~tmp~3#1); 25788#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 26554#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 25464#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 25966#L923-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 25427#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25428#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26245#L1672 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 26627#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 25626#L1690-2 [2022-07-14 16:03:00,565 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:00,565 INFO L85 PathProgramCache]: Analyzing trace with hash -218621314, now seen corresponding path program 1 times [2022-07-14 16:03:00,566 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:00,566 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1854772703] [2022-07-14 16:03:00,566 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:00,566 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:00,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:00,584 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:00,584 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:00,584 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1854772703] [2022-07-14 16:03:00,584 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1854772703] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:00,584 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:00,584 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:00,585 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1588630807] [2022-07-14 16:03:00,585 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:00,585 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:00,585 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:00,585 INFO L85 PathProgramCache]: Analyzing trace with hash 1131120385, now seen corresponding path program 1 times [2022-07-14 16:03:00,585 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:00,586 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [782109139] [2022-07-14 16:03:00,586 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:00,586 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:00,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:00,610 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:00,610 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:00,610 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [782109139] [2022-07-14 16:03:00,611 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [782109139] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:00,611 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:00,611 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:00,611 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [784308598] [2022-07-14 16:03:00,611 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:00,612 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:00,612 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:00,612 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:00,612 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:00,612 INFO L87 Difference]: Start difference. First operand 1571 states and 2327 transitions. cyclomatic complexity: 757 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:00,631 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:00,632 INFO L93 Difference]: Finished difference Result 1571 states and 2326 transitions. [2022-07-14 16:03:00,632 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:00,632 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2326 transitions. [2022-07-14 16:03:00,637 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2022-07-14 16:03:00,642 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1571 states and 2326 transitions. [2022-07-14 16:03:00,642 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2022-07-14 16:03:00,643 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2022-07-14 16:03:00,643 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2326 transitions. [2022-07-14 16:03:00,645 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:00,645 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1571 states and 2326 transitions. [2022-07-14 16:03:00,646 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2326 transitions. [2022-07-14 16:03:00,657 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2022-07-14 16:03:00,658 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.4805856142584342) internal successors, (2326), 1570 states have internal predecessors, (2326), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:00,661 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2326 transitions. [2022-07-14 16:03:00,662 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1571 states and 2326 transitions. [2022-07-14 16:03:00,662 INFO L374 stractBuchiCegarLoop]: Abstraction has 1571 states and 2326 transitions. [2022-07-14 16:03:00,662 INFO L287 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-07-14 16:03:00,662 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2326 transitions. [2022-07-14 16:03:00,665 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2022-07-14 16:03:00,665 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:00,666 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:00,667 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:00,667 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:00,667 INFO L752 eck$LassoCheckResult]: Stem: 29033#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 29034#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 29574#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29575#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29444#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 29445#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28452#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28453#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29891#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29418#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29419#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29696#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29697#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 29780#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29862#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 29863#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 29744#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29592#L1121 assume !(0 == ~M_E~0); 29347#L1121-2 assume !(0 == ~T1_E~0); 28728#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28729#L1131-1 assume !(0 == ~T3_E~0); 28899#L1136-1 assume !(0 == ~T4_E~0); 28995#L1141-1 assume !(0 == ~T5_E~0); 29215#L1146-1 assume !(0 == ~T6_E~0); 29515#L1151-1 assume !(0 == ~T7_E~0); 29055#L1156-1 assume !(0 == ~T8_E~0); 28438#L1161-1 assume !(0 == ~T9_E~0); 28439#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 28664#L1171-1 assume !(0 == ~T11_E~0); 28665#L1176-1 assume !(0 == ~E_M~0); 29529#L1181-1 assume !(0 == ~E_1~0); 29657#L1186-1 assume !(0 == ~E_2~0); 29707#L1191-1 assume !(0 == ~E_3~0); 28691#L1196-1 assume !(0 == ~E_4~0); 28692#L1201-1 assume !(0 == ~E_5~0); 29900#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 29745#L1211-1 assume !(0 == ~E_7~0); 29746#L1216-1 assume !(0 == ~E_8~0); 28834#L1221-1 assume !(0 == ~E_9~0); 28835#L1226-1 assume !(0 == ~E_10~0); 28534#L1231-1 assume !(0 == ~E_11~0); 28535#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29530#L556 assume 1 == ~m_pc~0; 29531#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 28412#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28413#L568 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29308#L1391 assume !(0 != activate_threads_~tmp~1#1); 29685#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29686#L575 assume !(1 == ~t1_pc~0); 28363#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 28364#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28497#L587 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28847#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 28804#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28805#L594 assume 1 == ~t2_pc~0; 28733#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28734#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29200#L606 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28427#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 28428#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28486#L613 assume !(1 == ~t3_pc~0); 28605#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 28604#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28530#L625 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28531#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 29214#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28932#L632 assume 1 == ~t4_pc~0; 28933#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29433#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29593#L644 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29901#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 29539#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29290#L651 assume 1 == ~t5_pc~0; 29291#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28618#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28619#L663 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29067#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 28635#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28636#L670 assume !(1 == ~t6_pc~0); 29727#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 28981#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28982#L682 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29823#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29255#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29256#L689 assume 1 == ~t7_pc~0; 29897#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29366#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29367#L701 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29742#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 29158#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29159#L708 assume !(1 == ~t8_pc~0); 28724#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 28725#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29822#L720 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29807#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 28789#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28790#L727 assume 1 == ~t9_pc~0; 28912#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28488#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29904#L739 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29905#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 29892#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28843#L746 assume !(1 == ~t10_pc~0); 28844#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 29492#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29608#L758 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29816#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 29689#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29004#L765 assume 1 == ~t11_pc~0; 29005#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29210#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28377#L777 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 28378#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 29726#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29804#L1249 assume !(1 == ~M_E~0); 29437#L1249-2 assume !(1 == ~T1_E~0); 29087#L1254-1 assume !(1 == ~T2_E~0); 28423#L1259-1 assume !(1 == ~T3_E~0); 28405#L1264-1 assume !(1 == ~T4_E~0); 28406#L1269-1 assume !(1 == ~T5_E~0); 29923#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 29871#L1279-1 assume !(1 == ~T7_E~0); 28606#L1284-1 assume !(1 == ~T8_E~0); 28607#L1289-1 assume !(1 == ~T9_E~0); 29137#L1294-1 assume !(1 == ~T10_E~0); 29138#L1299-1 assume !(1 == ~T11_E~0); 29147#L1304-1 assume !(1 == ~E_M~0); 29917#L1309-1 assume !(1 == ~E_1~0); 29920#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 28553#L1319-1 assume !(1 == ~E_3~0); 28554#L1324-1 assume !(1 == ~E_4~0); 28686#L1329-1 assume !(1 == ~E_5~0); 28687#L1334-1 assume !(1 == ~E_6~0); 29765#L1339-1 assume !(1 == ~E_7~0); 29842#L1344-1 assume !(1 == ~E_8~0); 29843#L1349-1 assume !(1 == ~E_9~0); 29270#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 29271#L1359-1 assume !(1 == ~E_11~0); 29630#L1364-1 assume { :end_inline_reset_delta_events } true; 28775#L1690-2 [2022-07-14 16:03:00,667 INFO L754 eck$LassoCheckResult]: Loop: 28775#L1690-2 assume !false; 28776#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28661#L1096 assume !false; 29639#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 28507#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 28508#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 29533#L923 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 29002#L937 assume !(0 != eval_~tmp~0#1); 29003#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29473#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28977#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28978#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29893#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29185#L1131-3 assume !(0 == ~T3_E~0); 29186#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29924#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29540#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 28722#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 28723#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29837#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29348#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 29349#L1171-3 assume !(0 == ~T11_E~0); 29394#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 28771#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 28772#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29475#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29476#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 29666#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 29667#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 29372#L1211-3 assume !(0 == ~E_7~0); 28684#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 28685#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 29098#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 28741#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28742#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28962#L556-39 assume 1 == ~m_pc~0; 29483#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29450#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28841#L568-13 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28842#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 29014#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29408#L575-39 assume 1 == ~t1_pc~0; 29409#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29674#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29535#L587-13 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29536#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29383#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29384#L594-39 assume !(1 == ~t2_pc~0); 29595#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 29386#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29387#L606-13 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29809#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28900#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28901#L613-39 assume 1 == ~t3_pc~0; 29786#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 28383#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28384#L625-13 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29142#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28482#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28483#L632-39 assume 1 == ~t4_pc~0; 29754#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29068#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29069#L644-13 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29622#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29753#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28752#L651-39 assume 1 == ~t5_pc~0; 28753#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28515#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29741#L663-13 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29848#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29886#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29906#L670-39 assume 1 == ~t6_pc~0; 29907#L671-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 28429#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28430#L682-13 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28498#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29095#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29096#L689-39 assume !(1 == ~t7_pc~0); 29219#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 29220#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28754#L701-13 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 28755#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 28622#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28623#L708-39 assume !(1 == ~t8_pc~0); 28561#L708-41 is_transmit8_triggered_~__retres1~8#1 := 0; 28560#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28668#L720-13 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28669#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29549#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29041#L727-39 assume !(1 == ~t9_pc~0); 29042#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 28819#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28820#L739-13 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29769#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 29598#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29599#L746-39 assume 1 == ~t10_pc~0; 29568#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 29569#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29834#L758-13 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29304#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 29305#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29717#L765-39 assume 1 == ~t11_pc~0; 28433#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 28435#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29617#L777-13 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 28773#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 28774#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29341#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 28579#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28580#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29836#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29464#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28538#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 28539#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 29869#L1279-3 assume !(1 == ~T7_E~0); 29017#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 29018#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 29012#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29013#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29264#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 29265#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28929#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 28930#L1319-3 assume !(1 == ~E_3~0); 29683#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 28648#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 28649#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 29198#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 29199#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 29417#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 28908#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 28909#L1359-3 assume !(1 == ~E_11~0); 29432#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 28499#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 28500#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 29126#L923-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 29127#L1709 assume !(0 == start_simulation_~tmp~3#1); 28937#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 29703#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 28613#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 29115#L923-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 28576#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 28577#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 29395#L1672 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 29776#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 28775#L1690-2 [2022-07-14 16:03:00,668 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:00,668 INFO L85 PathProgramCache]: Analyzing trace with hash 215884284, now seen corresponding path program 1 times [2022-07-14 16:03:00,668 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:00,668 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [307885202] [2022-07-14 16:03:00,668 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:00,669 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:00,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:00,685 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:00,685 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:00,685 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [307885202] [2022-07-14 16:03:00,685 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [307885202] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:00,686 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:00,686 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:00,686 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [314155781] [2022-07-14 16:03:00,686 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:00,686 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:00,686 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:00,687 INFO L85 PathProgramCache]: Analyzing trace with hash 1244851136, now seen corresponding path program 1 times [2022-07-14 16:03:00,687 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:00,687 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1184061802] [2022-07-14 16:03:00,687 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:00,687 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:00,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:00,729 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:00,729 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:00,729 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1184061802] [2022-07-14 16:03:00,730 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1184061802] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:00,730 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:00,730 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:00,730 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2134132142] [2022-07-14 16:03:00,730 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:00,730 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:00,731 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:00,732 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:00,732 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:00,732 INFO L87 Difference]: Start difference. First operand 1571 states and 2326 transitions. cyclomatic complexity: 756 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:00,754 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:00,754 INFO L93 Difference]: Finished difference Result 1571 states and 2325 transitions. [2022-07-14 16:03:00,754 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:00,755 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2325 transitions. [2022-07-14 16:03:00,759 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2022-07-14 16:03:00,764 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1571 states and 2325 transitions. [2022-07-14 16:03:00,764 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2022-07-14 16:03:00,765 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2022-07-14 16:03:00,765 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2325 transitions. [2022-07-14 16:03:00,766 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:00,766 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1571 states and 2325 transitions. [2022-07-14 16:03:00,768 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2325 transitions. [2022-07-14 16:03:00,778 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2022-07-14 16:03:00,780 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.4799490770210058) internal successors, (2325), 1570 states have internal predecessors, (2325), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:00,782 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2325 transitions. [2022-07-14 16:03:00,782 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1571 states and 2325 transitions. [2022-07-14 16:03:00,782 INFO L374 stractBuchiCegarLoop]: Abstraction has 1571 states and 2325 transitions. [2022-07-14 16:03:00,782 INFO L287 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-07-14 16:03:00,782 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2325 transitions. [2022-07-14 16:03:00,786 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2022-07-14 16:03:00,786 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:00,786 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:00,787 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:00,787 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:00,787 INFO L752 eck$LassoCheckResult]: Stem: 32182#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 32183#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 32723#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 32724#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 32593#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 32594#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 31601#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31602#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33040#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32567#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 32568#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 32845#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 32846#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 32929#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33011#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 33012#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 32893#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32741#L1121 assume !(0 == ~M_E~0); 32496#L1121-2 assume !(0 == ~T1_E~0); 31877#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31878#L1131-1 assume !(0 == ~T3_E~0); 32048#L1136-1 assume !(0 == ~T4_E~0); 32144#L1141-1 assume !(0 == ~T5_E~0); 32364#L1146-1 assume !(0 == ~T6_E~0); 32664#L1151-1 assume !(0 == ~T7_E~0); 32204#L1156-1 assume !(0 == ~T8_E~0); 31587#L1161-1 assume !(0 == ~T9_E~0); 31588#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 31813#L1171-1 assume !(0 == ~T11_E~0); 31814#L1176-1 assume !(0 == ~E_M~0); 32678#L1181-1 assume !(0 == ~E_1~0); 32806#L1186-1 assume !(0 == ~E_2~0); 32856#L1191-1 assume !(0 == ~E_3~0); 31840#L1196-1 assume !(0 == ~E_4~0); 31841#L1201-1 assume !(0 == ~E_5~0); 33049#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 32894#L1211-1 assume !(0 == ~E_7~0); 32895#L1216-1 assume !(0 == ~E_8~0); 31983#L1221-1 assume !(0 == ~E_9~0); 31984#L1226-1 assume !(0 == ~E_10~0); 31683#L1231-1 assume !(0 == ~E_11~0); 31684#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32679#L556 assume 1 == ~m_pc~0; 32680#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 31561#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31562#L568 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 32457#L1391 assume !(0 != activate_threads_~tmp~1#1); 32834#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32835#L575 assume !(1 == ~t1_pc~0); 31512#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 31513#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31646#L587 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31996#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 31953#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31954#L594 assume 1 == ~t2_pc~0; 31882#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 31883#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32349#L606 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31576#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 31577#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31635#L613 assume !(1 == ~t3_pc~0); 31754#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 31753#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31679#L625 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 31680#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 32363#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32081#L632 assume 1 == ~t4_pc~0; 32082#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 32582#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32742#L644 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33050#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 32688#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32439#L651 assume 1 == ~t5_pc~0; 32440#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31767#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31768#L663 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32216#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 31784#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31785#L670 assume !(1 == ~t6_pc~0); 32876#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 32130#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32131#L682 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32972#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 32404#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32405#L689 assume 1 == ~t7_pc~0; 33046#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 32515#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32516#L701 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32891#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 32307#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32308#L708 assume !(1 == ~t8_pc~0); 31873#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 31874#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32971#L720 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32956#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 31938#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 31939#L727 assume 1 == ~t9_pc~0; 32061#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31637#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33053#L739 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33054#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 33041#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31992#L746 assume !(1 == ~t10_pc~0); 31993#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 32641#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32757#L758 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32965#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 32838#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32153#L765 assume 1 == ~t11_pc~0; 32154#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32359#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 31526#L777 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 31527#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 32875#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32953#L1249 assume !(1 == ~M_E~0); 32586#L1249-2 assume !(1 == ~T1_E~0); 32236#L1254-1 assume !(1 == ~T2_E~0); 31572#L1259-1 assume !(1 == ~T3_E~0); 31554#L1264-1 assume !(1 == ~T4_E~0); 31555#L1269-1 assume !(1 == ~T5_E~0); 33072#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33020#L1279-1 assume !(1 == ~T7_E~0); 31755#L1284-1 assume !(1 == ~T8_E~0); 31756#L1289-1 assume !(1 == ~T9_E~0); 32286#L1294-1 assume !(1 == ~T10_E~0); 32287#L1299-1 assume !(1 == ~T11_E~0); 32296#L1304-1 assume !(1 == ~E_M~0); 33066#L1309-1 assume !(1 == ~E_1~0); 33069#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 31702#L1319-1 assume !(1 == ~E_3~0); 31703#L1324-1 assume !(1 == ~E_4~0); 31835#L1329-1 assume !(1 == ~E_5~0); 31836#L1334-1 assume !(1 == ~E_6~0); 32914#L1339-1 assume !(1 == ~E_7~0); 32991#L1344-1 assume !(1 == ~E_8~0); 32992#L1349-1 assume !(1 == ~E_9~0); 32419#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 32420#L1359-1 assume !(1 == ~E_11~0); 32779#L1364-1 assume { :end_inline_reset_delta_events } true; 31924#L1690-2 [2022-07-14 16:03:00,788 INFO L754 eck$LassoCheckResult]: Loop: 31924#L1690-2 assume !false; 31925#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 31810#L1096 assume !false; 32788#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 31656#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 31657#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 32682#L923 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 32151#L937 assume !(0 != eval_~tmp~0#1); 32152#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 32622#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 32126#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 32127#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33042#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 32334#L1131-3 assume !(0 == ~T3_E~0); 32335#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33073#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 32689#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 31871#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 31872#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32986#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 32497#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 32498#L1171-3 assume !(0 == ~T11_E~0); 32543#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 31920#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 31921#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 32624#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32625#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 32815#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32816#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 32521#L1211-3 assume !(0 == ~E_7~0); 31833#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 31834#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 32247#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 31890#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 31891#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32111#L556-39 assume 1 == ~m_pc~0; 32632#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 32599#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31990#L568-13 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31991#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 32163#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32557#L575-39 assume 1 == ~t1_pc~0; 32558#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 32823#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32684#L587-13 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32685#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32532#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32533#L594-39 assume !(1 == ~t2_pc~0); 32744#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 32535#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32536#L606-13 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32958#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 32049#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32050#L613-39 assume 1 == ~t3_pc~0; 32935#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 31532#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31533#L625-13 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32291#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 31631#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31632#L632-39 assume 1 == ~t4_pc~0; 32903#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 32217#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32218#L644-13 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32771#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32902#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31901#L651-39 assume 1 == ~t5_pc~0; 31902#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31664#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32890#L663-13 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32997#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 33035#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33055#L670-39 assume 1 == ~t6_pc~0; 33056#L671-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 31578#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31579#L682-13 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 31647#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 32244#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32245#L689-39 assume !(1 == ~t7_pc~0); 32368#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 32369#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31903#L701-13 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 31904#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 31771#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31772#L708-39 assume 1 == ~t8_pc~0; 31708#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 31709#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 31817#L720-13 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 31818#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32698#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32190#L727-39 assume 1 == ~t9_pc~0; 32192#L728-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31968#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 31969#L739-13 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32918#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 32747#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32748#L746-39 assume 1 == ~t10_pc~0; 32717#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 32718#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32983#L758-13 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32453#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 32454#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32866#L765-39 assume 1 == ~t11_pc~0; 31582#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 31584#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32766#L777-13 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 31922#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 31923#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32490#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 31728#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 31729#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32985#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32613#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31687#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 31688#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33018#L1279-3 assume !(1 == ~T7_E~0); 32166#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 32167#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 32161#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 32162#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 32413#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 32414#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32078#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 32079#L1319-3 assume !(1 == ~E_3~0); 32832#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31797#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 31798#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32347#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 32348#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 32566#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 32057#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 32058#L1359-3 assume !(1 == ~E_11~0); 32581#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 31648#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 31649#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 32275#L923-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 32276#L1709 assume !(0 == start_simulation_~tmp~3#1); 32086#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 32852#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 31762#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 32264#L923-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 31725#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 31726#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 32544#L1672 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 32925#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 31924#L1690-2 [2022-07-14 16:03:00,788 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:00,788 INFO L85 PathProgramCache]: Analyzing trace with hash 922480890, now seen corresponding path program 1 times [2022-07-14 16:03:00,789 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:00,789 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [158314746] [2022-07-14 16:03:00,789 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:00,789 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:00,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:00,808 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:00,808 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:00,808 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [158314746] [2022-07-14 16:03:00,808 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [158314746] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:00,808 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:00,808 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:00,808 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2054726491] [2022-07-14 16:03:00,809 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:00,809 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:00,809 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:00,809 INFO L85 PathProgramCache]: Analyzing trace with hash 1324447614, now seen corresponding path program 1 times [2022-07-14 16:03:00,809 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:00,809 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [869209371] [2022-07-14 16:03:00,810 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:00,810 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:00,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:00,831 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:00,831 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:00,831 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [869209371] [2022-07-14 16:03:00,831 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [869209371] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:00,831 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:00,831 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:00,831 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [202602876] [2022-07-14 16:03:00,831 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:00,832 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:00,832 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:00,832 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:00,832 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:00,832 INFO L87 Difference]: Start difference. First operand 1571 states and 2325 transitions. cyclomatic complexity: 755 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:00,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:00,849 INFO L93 Difference]: Finished difference Result 1571 states and 2324 transitions. [2022-07-14 16:03:00,850 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:00,850 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2324 transitions. [2022-07-14 16:03:00,854 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2022-07-14 16:03:00,858 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1571 states and 2324 transitions. [2022-07-14 16:03:00,858 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2022-07-14 16:03:00,859 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2022-07-14 16:03:00,859 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2324 transitions. [2022-07-14 16:03:00,861 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:00,861 INFO L369 hiAutomatonCegarLoop]: Abstraction has 1571 states and 2324 transitions. [2022-07-14 16:03:00,862 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2324 transitions. [2022-07-14 16:03:00,873 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2022-07-14 16:03:00,874 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.4793125397835774) internal successors, (2324), 1570 states have internal predecessors, (2324), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:00,877 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2324 transitions. [2022-07-14 16:03:00,877 INFO L392 hiAutomatonCegarLoop]: Abstraction has 1571 states and 2324 transitions. [2022-07-14 16:03:00,877 INFO L374 stractBuchiCegarLoop]: Abstraction has 1571 states and 2324 transitions. [2022-07-14 16:03:00,877 INFO L287 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-07-14 16:03:00,877 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2324 transitions. [2022-07-14 16:03:00,880 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2022-07-14 16:03:00,881 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:00,881 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:00,882 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:00,882 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:00,882 INFO L752 eck$LassoCheckResult]: Stem: 35331#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 35332#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 35872#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 35873#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 35742#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 35743#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 34750#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34751#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36189#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35716#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 35717#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 35994#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35995#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 36078#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 36160#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 36161#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 36042#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 35890#L1121 assume !(0 == ~M_E~0); 35645#L1121-2 assume !(0 == ~T1_E~0); 35026#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35027#L1131-1 assume !(0 == ~T3_E~0); 35197#L1136-1 assume !(0 == ~T4_E~0); 35293#L1141-1 assume !(0 == ~T5_E~0); 35513#L1146-1 assume !(0 == ~T6_E~0); 35813#L1151-1 assume !(0 == ~T7_E~0); 35353#L1156-1 assume !(0 == ~T8_E~0); 34736#L1161-1 assume !(0 == ~T9_E~0); 34737#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 34962#L1171-1 assume !(0 == ~T11_E~0); 34963#L1176-1 assume !(0 == ~E_M~0); 35827#L1181-1 assume !(0 == ~E_1~0); 35955#L1186-1 assume !(0 == ~E_2~0); 36005#L1191-1 assume !(0 == ~E_3~0); 34989#L1196-1 assume !(0 == ~E_4~0); 34990#L1201-1 assume !(0 == ~E_5~0); 36198#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 36043#L1211-1 assume !(0 == ~E_7~0); 36044#L1216-1 assume !(0 == ~E_8~0); 35132#L1221-1 assume !(0 == ~E_9~0); 35133#L1226-1 assume !(0 == ~E_10~0); 34832#L1231-1 assume !(0 == ~E_11~0); 34833#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35828#L556 assume 1 == ~m_pc~0; 35829#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 34710#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34711#L568 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35606#L1391 assume !(0 != activate_threads_~tmp~1#1); 35983#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35984#L575 assume !(1 == ~t1_pc~0); 34661#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 34662#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34795#L587 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35145#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 35102#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35103#L594 assume 1 == ~t2_pc~0; 35031#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35032#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35498#L606 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34725#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 34726#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34784#L613 assume !(1 == ~t3_pc~0); 34903#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 34902#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34828#L625 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34829#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 35512#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35230#L632 assume 1 == ~t4_pc~0; 35231#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 35731#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35891#L644 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36199#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 35837#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35588#L651 assume 1 == ~t5_pc~0; 35589#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 34916#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34917#L663 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 35365#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 34933#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34934#L670 assume !(1 == ~t6_pc~0); 36025#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 35279#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35280#L682 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36121#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35553#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35554#L689 assume 1 == ~t7_pc~0; 36195#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 35664#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35665#L701 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36040#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 35456#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35457#L708 assume !(1 == ~t8_pc~0); 35022#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 35023#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36120#L720 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36105#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 35087#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35088#L727 assume 1 == ~t9_pc~0; 35210#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34786#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36202#L739 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36203#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 36190#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35141#L746 assume !(1 == ~t10_pc~0); 35142#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 35790#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35906#L758 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36114#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 35987#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35302#L765 assume 1 == ~t11_pc~0; 35303#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 35508#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 34675#L777 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 34676#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 36024#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36102#L1249 assume !(1 == ~M_E~0); 35735#L1249-2 assume !(1 == ~T1_E~0); 35385#L1254-1 assume !(1 == ~T2_E~0); 34721#L1259-1 assume !(1 == ~T3_E~0); 34703#L1264-1 assume !(1 == ~T4_E~0); 34704#L1269-1 assume !(1 == ~T5_E~0); 36221#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36169#L1279-1 assume !(1 == ~T7_E~0); 34904#L1284-1 assume !(1 == ~T8_E~0); 34905#L1289-1 assume !(1 == ~T9_E~0); 35435#L1294-1 assume !(1 == ~T10_E~0); 35436#L1299-1 assume !(1 == ~T11_E~0); 35445#L1304-1 assume !(1 == ~E_M~0); 36215#L1309-1 assume !(1 == ~E_1~0); 36218#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 34851#L1319-1 assume !(1 == ~E_3~0); 34852#L1324-1 assume !(1 == ~E_4~0); 34984#L1329-1 assume !(1 == ~E_5~0); 34985#L1334-1 assume !(1 == ~E_6~0); 36063#L1339-1 assume !(1 == ~E_7~0); 36140#L1344-1 assume !(1 == ~E_8~0); 36141#L1349-1 assume !(1 == ~E_9~0); 35568#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 35569#L1359-1 assume !(1 == ~E_11~0); 35928#L1364-1 assume { :end_inline_reset_delta_events } true; 35073#L1690-2 [2022-07-14 16:03:00,882 INFO L754 eck$LassoCheckResult]: Loop: 35073#L1690-2 assume !false; 35074#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 34959#L1096 assume !false; 35937#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 34805#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 34806#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 35831#L923 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 35300#L937 assume !(0 != eval_~tmp~0#1); 35301#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 35771#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35275#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 35276#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36191#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35483#L1131-3 assume !(0 == ~T3_E~0); 35484#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36222#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 35838#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 35020#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 35021#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36135#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 35646#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 35647#L1171-3 assume !(0 == ~T11_E~0); 35692#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 35069#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 35070#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 35773#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 35774#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 35964#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 35965#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 35670#L1211-3 assume !(0 == ~E_7~0); 34982#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 34983#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 35396#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 35039#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 35040#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35260#L556-39 assume 1 == ~m_pc~0; 35781#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 35748#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35139#L568-13 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35140#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 35312#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35706#L575-39 assume 1 == ~t1_pc~0; 35707#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 35972#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35833#L587-13 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35834#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 35681#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35682#L594-39 assume !(1 == ~t2_pc~0); 35893#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 35684#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35685#L606-13 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36107#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 35198#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35199#L613-39 assume 1 == ~t3_pc~0; 36084#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34681#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34682#L625-13 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35440#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 34780#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34781#L632-39 assume 1 == ~t4_pc~0; 36052#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 35366#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35367#L644-13 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35920#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36051#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35050#L651-39 assume 1 == ~t5_pc~0; 35051#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 34813#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36039#L663-13 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36146#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 36184#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36204#L670-39 assume !(1 == ~t6_pc~0); 35783#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 34727#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34728#L682-13 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34796#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35393#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35394#L689-39 assume 1 == ~t7_pc~0; 35616#L690-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 35518#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35052#L701-13 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 35053#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 34920#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 34921#L708-39 assume 1 == ~t8_pc~0; 34857#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 34858#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34966#L720-13 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 34967#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 35847#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35339#L727-39 assume !(1 == ~t9_pc~0); 35340#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 35117#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35118#L739-13 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36067#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 35896#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35897#L746-39 assume 1 == ~t10_pc~0; 35866#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 35867#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36132#L758-13 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35602#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 35603#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 36015#L765-39 assume 1 == ~t11_pc~0; 34731#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 34733#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35915#L777-13 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 35071#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35072#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35639#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 34877#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34878#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36134#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 35762#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 34836#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 34837#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36167#L1279-3 assume !(1 == ~T7_E~0); 35315#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 35316#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 35310#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 35311#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 35562#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 35563#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 35227#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 35228#L1319-3 assume !(1 == ~E_3~0); 35981#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 34946#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 34947#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 35496#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 35497#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 35715#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 35206#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 35207#L1359-3 assume !(1 == ~E_11~0); 35730#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 34797#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 34798#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 35424#L923-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 35425#L1709 assume !(0 == start_simulation_~tmp~3#1); 35235#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 36001#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 34911#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 35413#L923-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 34874#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34875#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 35693#L1672 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 36074#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 35073#L1690-2 [2022-07-14 16:03:00,883 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:00,883 INFO L85 PathProgramCache]: Analyzing trace with hash -24556996, now seen corresponding path program 1 times [2022-07-14 16:03:00,883 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:00,883 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [625715489] [2022-07-14 16:03:00,883 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:00,884 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:00,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:00,906 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:00,907 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:00,907 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [625715489] [2022-07-14 16:03:00,907 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [625715489] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:00,907 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:00,907 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:00,907 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1173148570] [2022-07-14 16:03:00,907 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:00,908 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:00,908 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:00,908 INFO L85 PathProgramCache]: Analyzing trace with hash 210812735, now seen corresponding path program 2 times [2022-07-14 16:03:00,908 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:00,908 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [755314944] [2022-07-14 16:03:00,908 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:00,909 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:00,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:00,929 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:00,929 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:00,929 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [755314944] [2022-07-14 16:03:00,929 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [755314944] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:00,930 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:00,930 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:00,930 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [795645242] [2022-07-14 16:03:00,930 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:00,930 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:00,930 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:00,931 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:03:00,931 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:03:00,931 INFO L87 Difference]: Start difference. First operand 1571 states and 2324 transitions. cyclomatic complexity: 754 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:01,003 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:01,004 INFO L93 Difference]: Finished difference Result 2905 states and 4283 transitions. [2022-07-14 16:03:01,004 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:03:01,004 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2905 states and 4283 transitions. [2022-07-14 16:03:01,012 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2730 [2022-07-14 16:03:01,019 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2905 states to 2905 states and 4283 transitions. [2022-07-14 16:03:01,020 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2905 [2022-07-14 16:03:01,021 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2905 [2022-07-14 16:03:01,021 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2905 states and 4283 transitions. [2022-07-14 16:03:01,024 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:01,024 INFO L369 hiAutomatonCegarLoop]: Abstraction has 2905 states and 4283 transitions. [2022-07-14 16:03:01,026 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2905 states and 4283 transitions. [2022-07-14 16:03:01,080 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2905 to 2905. [2022-07-14 16:03:01,084 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2905 states, 2905 states have (on average 1.474354561101549) internal successors, (4283), 2904 states have internal predecessors, (4283), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:01,089 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2905 states to 2905 states and 4283 transitions. [2022-07-14 16:03:01,089 INFO L392 hiAutomatonCegarLoop]: Abstraction has 2905 states and 4283 transitions. [2022-07-14 16:03:01,089 INFO L374 stractBuchiCegarLoop]: Abstraction has 2905 states and 4283 transitions. [2022-07-14 16:03:01,089 INFO L287 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-07-14 16:03:01,090 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2905 states and 4283 transitions. [2022-07-14 16:03:01,095 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2730 [2022-07-14 16:03:01,096 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:01,096 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:01,097 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:01,097 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:01,097 INFO L752 eck$LassoCheckResult]: Stem: 39823#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 39824#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 40376#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 40377#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 40239#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 40240#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39236#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 39237#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 40718#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 40213#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 40214#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 40509#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 40510#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 40593#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 40683#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 40684#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 40557#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40395#L1121 assume !(0 == ~M_E~0); 40140#L1121-2 assume !(0 == ~T1_E~0); 39513#L1126-1 assume !(0 == ~T2_E~0); 39514#L1131-1 assume !(0 == ~T3_E~0); 39683#L1136-1 assume !(0 == ~T4_E~0); 39780#L1141-1 assume !(0 == ~T5_E~0); 40009#L1146-1 assume !(0 == ~T6_E~0); 40314#L1151-1 assume !(0 == ~T7_E~0); 39841#L1156-1 assume !(0 == ~T8_E~0); 39222#L1161-1 assume !(0 == ~T9_E~0); 39223#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 39448#L1171-1 assume !(0 == ~T11_E~0); 39449#L1176-1 assume !(0 == ~E_M~0); 40328#L1181-1 assume !(0 == ~E_1~0); 40467#L1186-1 assume !(0 == ~E_2~0); 40520#L1191-1 assume !(0 == ~E_3~0); 39475#L1196-1 assume !(0 == ~E_4~0); 39476#L1201-1 assume !(0 == ~E_5~0); 40731#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 40558#L1211-1 assume !(0 == ~E_7~0); 40559#L1216-1 assume !(0 == ~E_8~0); 39621#L1221-1 assume !(0 == ~E_9~0); 39622#L1226-1 assume !(0 == ~E_10~0); 39318#L1231-1 assume !(0 == ~E_11~0); 39319#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40330#L556 assume 1 == ~m_pc~0; 40331#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 39196#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39197#L568 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 40099#L1391 assume !(0 != activate_threads_~tmp~1#1); 40498#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40499#L575 assume !(1 == ~t1_pc~0); 39147#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 39148#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39281#L587 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 39631#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 39588#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39589#L594 assume 1 == ~t2_pc~0; 39517#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 39518#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39989#L606 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 39213#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 39214#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39270#L613 assume !(1 == ~t3_pc~0); 39389#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 39388#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39314#L625 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39315#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 40003#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 39716#L632 assume 1 == ~t4_pc~0; 39717#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 40228#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40396#L644 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40732#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 40339#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40080#L651 assume 1 == ~t5_pc~0; 40081#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39402#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39403#L663 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39853#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 39419#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39420#L670 assume !(1 == ~t6_pc~0); 40541#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 39771#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39772#L682 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40642#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 40046#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40047#L689 assume 1 == ~t7_pc~0; 40728#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 40159#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40160#L701 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40555#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 39946#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39947#L708 assume !(1 == ~t8_pc~0); 39508#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 39509#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40640#L720 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 40625#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 39573#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 39574#L727 assume 1 == ~t9_pc~0; 39696#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 39272#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40736#L739 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 40737#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 40719#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39628#L746 assume !(1 == ~t10_pc~0); 39629#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 40290#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40411#L758 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 40634#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 40502#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39793#L765 assume 1 == ~t11_pc~0; 39794#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 39999#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39161#L777 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 39162#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 40539#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40619#L1249 assume 1 == ~M_E~0;~M_E~0 := 2; 40233#L1249-2 assume !(1 == ~T1_E~0); 39873#L1254-1 assume !(1 == ~T2_E~0); 39207#L1259-1 assume !(1 == ~T3_E~0); 39189#L1264-1 assume !(1 == ~T4_E~0); 39190#L1269-1 assume !(1 == ~T5_E~0); 40761#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 40693#L1279-1 assume !(1 == ~T7_E~0); 39390#L1284-1 assume !(1 == ~T8_E~0); 39391#L1289-1 assume !(1 == ~T9_E~0); 39925#L1294-1 assume !(1 == ~T10_E~0); 39926#L1299-1 assume !(1 == ~T11_E~0); 39935#L1304-1 assume !(1 == ~E_M~0); 40754#L1309-1 assume !(1 == ~E_1~0); 40757#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 39337#L1319-1 assume !(1 == ~E_3~0); 39338#L1324-1 assume !(1 == ~E_4~0); 39470#L1329-1 assume !(1 == ~E_5~0); 39471#L1334-1 assume !(1 == ~E_6~0); 40578#L1339-1 assume !(1 == ~E_7~0); 40660#L1344-1 assume !(1 == ~E_8~0); 40661#L1349-1 assume !(1 == ~E_9~0); 40059#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 40060#L1359-1 assume !(1 == ~E_11~0); 40436#L1364-1 assume { :end_inline_reset_delta_events } true; 39559#L1690-2 [2022-07-14 16:03:01,098 INFO L754 eck$LassoCheckResult]: Loop: 39559#L1690-2 assume !false; 39560#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 39445#L1096 assume !false; 40449#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 40760#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 40333#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 40334#L923 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 40768#L937 assume !(0 != eval_~tmp~0#1); 40268#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 40269#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 40743#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 40769#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41680#L1126-3 assume !(0 == ~T2_E~0); 41679#L1131-3 assume !(0 == ~T3_E~0); 41678#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 41677#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 41676#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 41675#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 41674#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 41673#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 41672#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 41671#L1171-3 assume !(0 == ~T11_E~0); 41670#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 41669#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 41668#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 41667#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 41666#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 41665#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 41664#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 41663#L1211-3 assume !(0 == ~E_7~0); 41662#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 41661#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 41660#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 41659#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 41658#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41657#L556-39 assume 1 == ~m_pc~0; 41655#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 41654#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41653#L568-13 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 41652#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 41651#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41650#L575-39 assume 1 == ~t1_pc~0; 41648#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 41647#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41646#L587-13 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41645#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 41644#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41643#L594-39 assume 1 == ~t2_pc~0; 41641#L595-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 41640#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41639#L606-13 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41638#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 41637#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41636#L613-39 assume 1 == ~t3_pc~0; 41634#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 41633#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41632#L625-13 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41631#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41630#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41629#L632-39 assume !(1 == ~t4_pc~0); 41627#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 41626#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41625#L644-13 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41624#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 41623#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41622#L651-39 assume 1 == ~t5_pc~0; 41620#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 41619#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41618#L663-13 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41617#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 41616#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41615#L670-39 assume !(1 == ~t6_pc~0); 41613#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 41612#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41611#L682-13 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41610#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 41609#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41608#L689-39 assume 1 == ~t7_pc~0; 41606#L690-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41605#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41604#L701-13 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 41603#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 41602#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41601#L708-39 assume 1 == ~t8_pc~0; 41600#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 41598#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41597#L720-13 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41596#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 41595#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41594#L727-39 assume 1 == ~t9_pc~0; 41592#L728-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41591#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41590#L739-13 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 41589#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 41588#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41587#L746-39 assume 1 == ~t10_pc~0; 41585#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 41584#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41583#L758-13 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41582#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41581#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41580#L765-39 assume !(1 == ~t11_pc~0); 41578#L765-41 is_transmit11_triggered_~__retres1~11#1 := 0; 41577#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41576#L777-13 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41575#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 41574#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41573#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 40134#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 41572#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40733#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41571#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41570#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 41569#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 41568#L1279-3 assume !(1 == ~T7_E~0); 41567#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 41566#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 41565#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 41564#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 41563#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41562#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 41561#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 41560#L1319-3 assume !(1 == ~E_3~0); 41559#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 41558#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 41557#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 41556#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 41555#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 41554#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 41553#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 41552#L1359-3 assume !(1 == ~E_11~0); 41551#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 41541#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 41538#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 41537#L923-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 41536#L1709 assume !(0 == start_simulation_~tmp~3#1); 39721#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 40516#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 39397#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 39901#L923-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 39360#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 39361#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 40188#L1672 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 40589#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 39559#L1690-2 [2022-07-14 16:03:01,098 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:01,098 INFO L85 PathProgramCache]: Analyzing trace with hash -1257740808, now seen corresponding path program 1 times [2022-07-14 16:03:01,098 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:01,099 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [282257177] [2022-07-14 16:03:01,099 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:01,099 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:01,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:01,118 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:01,119 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:01,119 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [282257177] [2022-07-14 16:03:01,119 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [282257177] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:01,119 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:01,119 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:01,119 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [583054166] [2022-07-14 16:03:01,119 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:01,120 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:01,120 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:01,120 INFO L85 PathProgramCache]: Analyzing trace with hash -144450819, now seen corresponding path program 1 times [2022-07-14 16:03:01,120 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:01,120 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1107168299] [2022-07-14 16:03:01,120 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:01,120 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:01,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:01,140 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:01,140 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:01,140 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1107168299] [2022-07-14 16:03:01,141 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1107168299] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:01,141 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:01,141 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:01,141 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [611889017] [2022-07-14 16:03:01,141 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:01,141 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:01,141 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:01,142 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:03:01,142 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:03:01,142 INFO L87 Difference]: Start difference. First operand 2905 states and 4283 transitions. cyclomatic complexity: 1380 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:01,214 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:01,215 INFO L93 Difference]: Finished difference Result 5561 states and 8178 transitions. [2022-07-14 16:03:01,215 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:03:01,215 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5561 states and 8178 transitions. [2022-07-14 16:03:01,230 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5350 [2022-07-14 16:03:01,241 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5561 states to 5561 states and 8178 transitions. [2022-07-14 16:03:01,241 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5561 [2022-07-14 16:03:01,244 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5561 [2022-07-14 16:03:01,244 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5561 states and 8178 transitions. [2022-07-14 16:03:01,249 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:01,249 INFO L369 hiAutomatonCegarLoop]: Abstraction has 5561 states and 8178 transitions. [2022-07-14 16:03:01,251 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5561 states and 8178 transitions. [2022-07-14 16:03:01,294 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5561 to 5561. [2022-07-14 16:03:01,300 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5561 states, 5561 states have (on average 1.4705988131631003) internal successors, (8178), 5560 states have internal predecessors, (8178), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:01,307 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5561 states to 5561 states and 8178 transitions. [2022-07-14 16:03:01,307 INFO L392 hiAutomatonCegarLoop]: Abstraction has 5561 states and 8178 transitions. [2022-07-14 16:03:01,307 INFO L374 stractBuchiCegarLoop]: Abstraction has 5561 states and 8178 transitions. [2022-07-14 16:03:01,307 INFO L287 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-07-14 16:03:01,307 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5561 states and 8178 transitions. [2022-07-14 16:03:01,318 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5350 [2022-07-14 16:03:01,318 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:01,318 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:01,320 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:01,320 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:01,320 INFO L752 eck$LassoCheckResult]: Stem: 48296#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 48297#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 48846#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 48847#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 48713#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 48714#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 47712#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 47713#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49174#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 48686#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 48687#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 48970#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 48971#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49056#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 49141#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 49142#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 49019#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 48864#L1121 assume !(0 == ~M_E~0); 48615#L1121-2 assume !(0 == ~T1_E~0); 47988#L1126-1 assume !(0 == ~T2_E~0); 47989#L1131-1 assume !(0 == ~T3_E~0); 48160#L1136-1 assume !(0 == ~T4_E~0); 48257#L1141-1 assume !(0 == ~T5_E~0); 48481#L1146-1 assume !(0 == ~T6_E~0); 48785#L1151-1 assume !(0 == ~T7_E~0); 48318#L1156-1 assume !(0 == ~T8_E~0); 47698#L1161-1 assume !(0 == ~T9_E~0); 47699#L1166-1 assume !(0 == ~T10_E~0); 47924#L1171-1 assume !(0 == ~T11_E~0); 47925#L1176-1 assume !(0 == ~E_M~0); 48801#L1181-1 assume !(0 == ~E_1~0); 48931#L1186-1 assume !(0 == ~E_2~0); 48981#L1191-1 assume !(0 == ~E_3~0); 47951#L1196-1 assume !(0 == ~E_4~0); 47952#L1201-1 assume !(0 == ~E_5~0); 49184#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 49020#L1211-1 assume !(0 == ~E_7~0); 49021#L1216-1 assume !(0 == ~E_8~0); 48094#L1221-1 assume !(0 == ~E_9~0); 48095#L1226-1 assume !(0 == ~E_10~0); 47794#L1231-1 assume !(0 == ~E_11~0); 47795#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48802#L556 assume 1 == ~m_pc~0; 48803#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 47672#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47673#L568 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 48574#L1391 assume !(0 != activate_threads_~tmp~1#1); 48959#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48960#L575 assume !(1 == ~t1_pc~0); 47623#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 47624#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47757#L587 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 48108#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 48064#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 48065#L594 assume 1 == ~t2_pc~0; 47993#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 47994#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48466#L606 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47687#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 47688#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47746#L613 assume !(1 == ~t3_pc~0); 47865#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 47864#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47790#L625 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47791#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 48480#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48193#L632 assume 1 == ~t4_pc~0; 48194#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 48701#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48865#L644 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49185#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 48811#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 48556#L651 assume 1 == ~t5_pc~0; 48557#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47878#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47879#L663 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 48331#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 47895#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47896#L670 assume !(1 == ~t6_pc~0); 49002#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 48243#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 48244#L682 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49101#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 48521#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 48522#L689 assume 1 == ~t7_pc~0; 49181#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 48634#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48635#L701 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49017#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 48424#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 48425#L708 assume !(1 == ~t8_pc~0); 47984#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 47985#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49100#L720 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49085#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 48049#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48050#L727 assume 1 == ~t9_pc~0; 48173#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 47748#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49189#L739 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 49190#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 49175#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 48104#L746 assume !(1 == ~t10_pc~0); 48105#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 48761#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 48880#L758 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 49094#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 48963#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48266#L765 assume 1 == ~t11_pc~0; 48267#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 48476#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 47637#L777 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 47638#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 49001#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49081#L1249 assume 1 == ~M_E~0;~M_E~0 := 2; 48705#L1249-2 assume !(1 == ~T1_E~0); 48351#L1254-1 assume !(1 == ~T2_E~0); 48352#L1259-1 assume !(1 == ~T3_E~0); 50017#L1264-1 assume !(1 == ~T4_E~0); 50011#L1269-1 assume !(1 == ~T5_E~0); 49217#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 49151#L1279-1 assume !(1 == ~T7_E~0); 47866#L1284-1 assume !(1 == ~T8_E~0); 47867#L1289-1 assume !(1 == ~T9_E~0); 49191#L1294-1 assume !(1 == ~T10_E~0); 49431#L1299-1 assume !(1 == ~T11_E~0); 49430#L1304-1 assume !(1 == ~E_M~0); 49429#L1309-1 assume !(1 == ~E_1~0); 49426#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 49383#L1319-1 assume !(1 == ~E_3~0); 49350#L1324-1 assume !(1 == ~E_4~0); 49331#L1329-1 assume !(1 == ~E_5~0); 49329#L1334-1 assume !(1 == ~E_6~0); 49314#L1339-1 assume !(1 == ~E_7~0); 49313#L1344-1 assume !(1 == ~E_8~0); 49312#L1349-1 assume !(1 == ~E_9~0); 49288#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 49271#L1359-1 assume !(1 == ~E_11~0); 49262#L1364-1 assume { :end_inline_reset_delta_events } true; 49254#L1690-2 [2022-07-14 16:03:01,320 INFO L754 eck$LassoCheckResult]: Loop: 49254#L1690-2 assume !false; 49247#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49244#L1096 assume !false; 49243#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 49233#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 49230#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 49229#L923 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 49227#L937 assume !(0 != eval_~tmp~0#1); 49226#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 49225#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 49224#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 49219#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 49176#L1126-3 assume !(0 == ~T2_E~0); 48451#L1131-3 assume !(0 == ~T3_E~0); 48452#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 49218#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 48812#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 47982#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 47983#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 49116#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 49196#L1166-3 assume !(0 == ~T10_E~0); 51576#L1171-3 assume !(0 == ~T11_E~0); 51574#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 51572#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 51570#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 51568#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 51566#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 51565#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 51564#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 51563#L1211-3 assume !(0 == ~E_7~0); 51562#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 51561#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 51560#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 51559#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 51558#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51557#L556-39 assume 1 == ~m_pc~0; 48752#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 48719#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48102#L568-13 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 48103#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 48277#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48676#L575-39 assume 1 == ~t1_pc~0; 48677#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49037#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50682#L587-13 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50679#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50676#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50672#L594-39 assume 1 == ~t2_pc~0; 50668#L595-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50664#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50661#L606-13 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50659#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50656#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49062#L613-39 assume 1 == ~t3_pc~0; 49063#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 47643#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47644#L625-13 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 48408#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 47742#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47743#L632-39 assume 1 == ~t4_pc~0; 49029#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 48332#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48333#L644-13 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 48894#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 49028#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 48012#L651-39 assume 1 == ~t5_pc~0; 48013#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47775#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49016#L663-13 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49127#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 49167#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49192#L670-39 assume !(1 == ~t6_pc~0); 48754#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 47689#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47690#L682-13 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47758#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 48360#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 48361#L689-39 assume !(1 == ~t7_pc~0); 48485#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 48486#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48014#L701-13 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 48015#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 47882#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47883#L708-39 assume 1 == ~t8_pc~0; 48787#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 50450#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50442#L720-13 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50432#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 50423#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 50406#L727-39 assume 1 == ~t9_pc~0; 49216#L728-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 48079#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 48080#L739-13 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 49045#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 48870#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 48871#L746-39 assume 1 == ~t10_pc~0; 50340#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 50331#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50323#L758-13 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 50314#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 50305#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 50298#L765-39 assume !(1 == ~t11_pc~0); 50284#L765-41 is_transmit11_triggered_~__retres1~11#1 := 0; 50274#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 50265#L777-13 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50257#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 50246#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50236#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 48609#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 50219#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50211#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50204#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50196#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50187#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 50179#L1279-3 assume !(1 == ~T7_E~0); 50171#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 49170#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 49171#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 50156#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 50154#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 50146#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 50138#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50131#L1319-3 assume !(1 == ~E_3~0); 50128#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 50126#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 50115#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 49472#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 49470#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 49468#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 49466#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 49465#L1359-3 assume !(1 == ~E_11~0); 49425#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 49392#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 49389#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 49388#L923-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 49387#L1709 assume !(0 == start_simulation_~tmp~3#1); 48198#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 49363#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 49352#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 49333#L923-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 49311#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 49287#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 49270#L1672 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 49261#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 49254#L1690-2 [2022-07-14 16:03:01,321 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:01,321 INFO L85 PathProgramCache]: Analyzing trace with hash -786384458, now seen corresponding path program 1 times [2022-07-14 16:03:01,321 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:01,321 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [268458607] [2022-07-14 16:03:01,321 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:01,322 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:01,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:01,341 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:01,342 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:01,342 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [268458607] [2022-07-14 16:03:01,342 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [268458607] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:01,342 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:01,342 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:01,342 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1544343079] [2022-07-14 16:03:01,342 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:01,343 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:01,343 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:01,343 INFO L85 PathProgramCache]: Analyzing trace with hash -137699333, now seen corresponding path program 1 times [2022-07-14 16:03:01,343 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:01,343 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1623730365] [2022-07-14 16:03:01,343 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:01,343 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:01,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:01,396 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:01,396 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:01,396 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1623730365] [2022-07-14 16:03:01,397 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1623730365] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:01,397 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:01,397 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:01,397 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1991029641] [2022-07-14 16:03:01,397 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:01,398 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:01,398 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:01,398 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:03:01,398 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:03:01,398 INFO L87 Difference]: Start difference. First operand 5561 states and 8178 transitions. cyclomatic complexity: 2621 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:01,536 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:01,536 INFO L93 Difference]: Finished difference Result 10493 states and 15401 transitions. [2022-07-14 16:03:01,537 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:03:01,537 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10493 states and 15401 transitions. [2022-07-14 16:03:01,578 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10246 [2022-07-14 16:03:01,604 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10493 states to 10493 states and 15401 transitions. [2022-07-14 16:03:01,604 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10493 [2022-07-14 16:03:01,611 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10493 [2022-07-14 16:03:01,612 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10493 states and 15401 transitions. [2022-07-14 16:03:01,623 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:01,623 INFO L369 hiAutomatonCegarLoop]: Abstraction has 10493 states and 15401 transitions. [2022-07-14 16:03:01,629 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10493 states and 15401 transitions. [2022-07-14 16:03:01,726 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10493 to 10489. [2022-07-14 16:03:01,740 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10489 states, 10489 states have (on average 1.4679187720469062) internal successors, (15397), 10488 states have internal predecessors, (15397), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:01,759 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10489 states to 10489 states and 15397 transitions. [2022-07-14 16:03:01,759 INFO L392 hiAutomatonCegarLoop]: Abstraction has 10489 states and 15397 transitions. [2022-07-14 16:03:01,759 INFO L374 stractBuchiCegarLoop]: Abstraction has 10489 states and 15397 transitions. [2022-07-14 16:03:01,759 INFO L287 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-07-14 16:03:01,760 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10489 states and 15397 transitions. [2022-07-14 16:03:01,787 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10246 [2022-07-14 16:03:01,788 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:01,788 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:01,789 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:01,789 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:01,790 INFO L752 eck$LassoCheckResult]: Stem: 64358#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 64359#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 64921#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 64922#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 64784#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 64785#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 63776#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 63777#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 65270#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 64755#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 64756#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 65049#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 65050#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 65140#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 65233#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 65234#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 65101#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 64939#L1121 assume !(0 == ~M_E~0); 64683#L1121-2 assume !(0 == ~T1_E~0); 64052#L1126-1 assume !(0 == ~T2_E~0); 64053#L1131-1 assume !(0 == ~T3_E~0); 64223#L1136-1 assume !(0 == ~T4_E~0); 64319#L1141-1 assume !(0 == ~T5_E~0); 64547#L1146-1 assume !(0 == ~T6_E~0); 64860#L1151-1 assume !(0 == ~T7_E~0); 64381#L1156-1 assume !(0 == ~T8_E~0); 63762#L1161-1 assume !(0 == ~T9_E~0); 63763#L1166-1 assume !(0 == ~T10_E~0); 63988#L1171-1 assume !(0 == ~T11_E~0); 63989#L1176-1 assume !(0 == ~E_M~0); 64874#L1181-1 assume !(0 == ~E_1~0); 65009#L1186-1 assume !(0 == ~E_2~0); 65061#L1191-1 assume !(0 == ~E_3~0); 64015#L1196-1 assume !(0 == ~E_4~0); 64016#L1201-1 assume !(0 == ~E_5~0); 65281#L1206-1 assume !(0 == ~E_6~0); 65102#L1211-1 assume !(0 == ~E_7~0); 65103#L1216-1 assume !(0 == ~E_8~0); 64158#L1221-1 assume !(0 == ~E_9~0); 64159#L1226-1 assume !(0 == ~E_10~0); 63858#L1231-1 assume !(0 == ~E_11~0); 63859#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 64875#L556 assume 1 == ~m_pc~0; 64876#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 63736#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 63737#L568 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 64643#L1391 assume !(0 != activate_threads_~tmp~1#1); 65038#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65039#L575 assume !(1 == ~t1_pc~0); 63687#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 63688#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 63821#L587 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 64171#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 64128#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 64129#L594 assume 1 == ~t2_pc~0; 64057#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 64058#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 64531#L606 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 63751#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 63752#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 63810#L613 assume !(1 == ~t3_pc~0); 63929#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 63928#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 63854#L625 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 63855#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 64546#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 64256#L632 assume 1 == ~t4_pc~0; 64257#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 64772#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64940#L644 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 65282#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 64884#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 64624#L651 assume 1 == ~t5_pc~0; 64625#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 63942#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 63943#L663 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 64393#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 63959#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 63960#L670 assume !(1 == ~t6_pc~0); 65084#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 64305#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 64306#L682 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 65186#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 64588#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 64589#L689 assume 1 == ~t7_pc~0; 65276#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 64702#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 64703#L701 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 65099#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 64489#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 64490#L708 assume !(1 == ~t8_pc~0); 64048#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 64049#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 65185#L720 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 65168#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 64113#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 64114#L727 assume 1 == ~t9_pc~0; 64236#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 63812#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 65287#L739 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 65288#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 65271#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 64167#L746 assume !(1 == ~t10_pc~0); 64168#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 64833#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 64957#L758 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 65178#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 65042#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 64329#L765 assume 1 == ~t11_pc~0; 64330#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 64541#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 63701#L777 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 63702#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 65083#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 65164#L1249 assume 1 == ~M_E~0;~M_E~0 := 2; 65165#L1249-2 assume !(1 == ~T1_E~0); 64413#L1254-1 assume !(1 == ~T2_E~0); 64414#L1259-1 assume !(1 == ~T3_E~0); 65814#L1264-1 assume !(1 == ~T4_E~0); 65324#L1269-1 assume !(1 == ~T5_E~0); 65314#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 65246#L1279-1 assume !(1 == ~T7_E~0); 65247#L1284-1 assume !(1 == ~T8_E~0); 65758#L1289-1 assume !(1 == ~T9_E~0); 65756#L1294-1 assume !(1 == ~T10_E~0); 65753#L1299-1 assume !(1 == ~T11_E~0); 65751#L1304-1 assume !(1 == ~E_M~0); 65749#L1309-1 assume !(1 == ~E_1~0); 65528#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 65525#L1319-1 assume !(1 == ~E_3~0); 65482#L1324-1 assume !(1 == ~E_4~0); 65450#L1329-1 assume !(1 == ~E_5~0); 65447#L1334-1 assume !(1 == ~E_6~0); 65425#L1339-1 assume !(1 == ~E_7~0); 65423#L1344-1 assume !(1 == ~E_8~0); 65405#L1349-1 assume !(1 == ~E_9~0); 65388#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 65374#L1359-1 assume !(1 == ~E_11~0); 65365#L1364-1 assume { :end_inline_reset_delta_events } true; 65357#L1690-2 [2022-07-14 16:03:01,790 INFO L754 eck$LassoCheckResult]: Loop: 65357#L1690-2 assume !false; 65350#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 65347#L1096 assume !false; 65346#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 65336#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 65333#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 65332#L923 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 65330#L937 assume !(0 != eval_~tmp~0#1); 65329#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 65328#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 65326#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 65327#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 69340#L1126-3 assume !(0 == ~T2_E~0); 69338#L1131-3 assume !(0 == ~T3_E~0); 69336#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 69333#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 69331#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 69329#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 69327#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 69325#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 69323#L1166-3 assume !(0 == ~T10_E~0); 69320#L1171-3 assume !(0 == ~T11_E~0); 69318#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 69316#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 69314#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 69312#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 69310#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 69307#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 69305#L1206-3 assume !(0 == ~E_6~0); 69303#L1211-3 assume !(0 == ~E_7~0); 69301#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 69299#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 69297#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 69294#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 69293#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 69292#L556-39 assume 1 == ~m_pc~0; 69289#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 69286#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69284#L568-13 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 69282#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 69280#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69278#L575-39 assume 1 == ~t1_pc~0; 69275#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 69272#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 69270#L587-13 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 69268#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 69266#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 69264#L594-39 assume 1 == ~t2_pc~0; 69261#L595-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 69258#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 69256#L606-13 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 69254#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 66630#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 66628#L613-39 assume 1 == ~t3_pc~0; 66573#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 66571#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 66510#L625-13 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 66473#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 66471#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 66469#L632-39 assume !(1 == ~t4_pc~0); 66465#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 66422#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66420#L644-13 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 66418#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 66416#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 66360#L651-39 assume !(1 == ~t5_pc~0); 66357#L651-41 is_transmit5_triggered_~__retres1~5#1 := 0; 66354#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 66351#L663-13 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 66349#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 66347#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 66345#L670-39 assume 1 == ~t6_pc~0; 66343#L671-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 66340#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 66337#L682-13 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 66335#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 66333#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 66331#L689-39 assume !(1 == ~t7_pc~0); 66329#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 66327#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 66326#L701-13 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 66325#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 66324#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 66323#L708-39 assume 1 == ~t8_pc~0; 66259#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 66256#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 66254#L720-13 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 66252#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 66250#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 66247#L727-39 assume !(1 == ~t9_pc~0); 66245#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 66242#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 66240#L739-13 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 66238#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 66236#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 65069#L746-39 assume 1 == ~t10_pc~0; 65070#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 66228#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 66226#L758-13 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 66224#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 66166#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 66118#L765-39 assume !(1 == ~t11_pc~0); 66057#L765-41 is_transmit11_triggered_~__retres1~11#1 := 0; 66054#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 66052#L777-13 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 66050#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 66048#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 66014#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 64677#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 66010#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 65283#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 65942#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 65940#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 65938#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 65894#L1279-3 assume !(1 == ~T7_E~0); 65868#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 65841#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 65839#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 65817#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 65815#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 65795#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 65794#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 65792#L1319-3 assume !(1 == ~E_3~0); 65790#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 65789#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 65787#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 65784#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 65783#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 65782#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 65781#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 65779#L1359-3 assume !(1 == ~E_11~0); 65548#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 65513#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 65510#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 65508#L923-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 65506#L1709 assume !(0 == start_simulation_~tmp~3#1); 64261#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 65477#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 65443#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 65422#L923-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 65404#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 65387#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 65373#L1672 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 65364#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 65357#L1690-2 [2022-07-14 16:03:01,790 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:01,791 INFO L85 PathProgramCache]: Analyzing trace with hash 602909556, now seen corresponding path program 1 times [2022-07-14 16:03:01,791 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:01,791 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2086977780] [2022-07-14 16:03:01,791 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:01,791 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:01,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:01,811 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:01,811 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:01,811 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2086977780] [2022-07-14 16:03:01,812 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2086977780] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:01,812 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:01,812 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-14 16:03:01,812 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [416295667] [2022-07-14 16:03:01,812 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:01,812 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:01,813 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:01,813 INFO L85 PathProgramCache]: Analyzing trace with hash -1569705669, now seen corresponding path program 1 times [2022-07-14 16:03:01,813 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:01,813 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1746156953] [2022-07-14 16:03:01,813 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:01,813 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:01,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:01,871 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:01,871 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:01,871 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1746156953] [2022-07-14 16:03:01,872 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1746156953] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:01,872 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:01,872 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:01,872 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [429348512] [2022-07-14 16:03:01,872 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:01,872 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:01,872 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:01,873 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:01,873 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:01,873 INFO L87 Difference]: Start difference. First operand 10489 states and 15397 transitions. cyclomatic complexity: 4916 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:01,997 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:01,997 INFO L93 Difference]: Finished difference Result 20569 states and 29966 transitions. [2022-07-14 16:03:01,998 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:01,998 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20569 states and 29966 transitions. [2022-07-14 16:03:02,067 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 20319 [2022-07-14 16:03:02,107 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20569 states to 20569 states and 29966 transitions. [2022-07-14 16:03:02,108 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20569 [2022-07-14 16:03:02,120 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20569 [2022-07-14 16:03:02,120 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20569 states and 29966 transitions. [2022-07-14 16:03:02,137 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:02,138 INFO L369 hiAutomatonCegarLoop]: Abstraction has 20569 states and 29966 transitions. [2022-07-14 16:03:02,148 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20569 states and 29966 transitions. [2022-07-14 16:03:02,400 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20569 to 19905. [2022-07-14 16:03:02,420 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19905 states, 19905 states have (on average 1.458427530771163) internal successors, (29030), 19904 states have internal predecessors, (29030), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:02,453 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19905 states to 19905 states and 29030 transitions. [2022-07-14 16:03:02,454 INFO L392 hiAutomatonCegarLoop]: Abstraction has 19905 states and 29030 transitions. [2022-07-14 16:03:02,454 INFO L374 stractBuchiCegarLoop]: Abstraction has 19905 states and 29030 transitions. [2022-07-14 16:03:02,454 INFO L287 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-07-14 16:03:02,454 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19905 states and 29030 transitions. [2022-07-14 16:03:02,494 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 19655 [2022-07-14 16:03:02,495 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:02,495 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:02,496 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:02,496 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:02,497 INFO L752 eck$LassoCheckResult]: Stem: 95421#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 95422#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 96006#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 96007#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 95858#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 95859#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 94840#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 94841#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 96449#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 95831#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 95832#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 96158#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 96159#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 96276#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 96385#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 96386#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 96220#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 96026#L1121 assume !(0 == ~M_E~0); 95752#L1121-2 assume !(0 == ~T1_E~0); 95113#L1126-1 assume !(0 == ~T2_E~0); 95114#L1131-1 assume !(0 == ~T3_E~0); 95286#L1136-1 assume !(0 == ~T4_E~0); 95383#L1141-1 assume !(0 == ~T5_E~0); 95609#L1146-1 assume !(0 == ~T6_E~0); 95944#L1151-1 assume !(0 == ~T7_E~0); 95443#L1156-1 assume !(0 == ~T8_E~0); 94826#L1161-1 assume !(0 == ~T9_E~0); 94827#L1166-1 assume !(0 == ~T10_E~0); 95049#L1171-1 assume !(0 == ~T11_E~0); 95050#L1176-1 assume !(0 == ~E_M~0); 95959#L1181-1 assume !(0 == ~E_1~0); 96108#L1186-1 assume !(0 == ~E_2~0); 96173#L1191-1 assume !(0 == ~E_3~0); 95076#L1196-1 assume !(0 == ~E_4~0); 95077#L1201-1 assume !(0 == ~E_5~0); 96472#L1206-1 assume !(0 == ~E_6~0); 96221#L1211-1 assume !(0 == ~E_7~0); 96222#L1216-1 assume !(0 == ~E_8~0); 95219#L1221-1 assume !(0 == ~E_9~0); 95220#L1226-1 assume !(0 == ~E_10~0); 94922#L1231-1 assume !(0 == ~E_11~0); 94923#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 95960#L556 assume !(1 == ~m_pc~0); 95961#L556-2 is_master_triggered_~__retres1~0#1 := 0; 94800#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 94801#L568 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 95706#L1391 assume !(0 != activate_threads_~tmp~1#1); 96147#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 96148#L575 assume !(1 == ~t1_pc~0); 94752#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 94753#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 94885#L587 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 95232#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 95189#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 95190#L594 assume 1 == ~t2_pc~0; 95118#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 95119#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 95592#L606 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 94815#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 94816#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 94874#L613 assume !(1 == ~t3_pc~0); 94993#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 94992#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 94918#L625 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 94919#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 95608#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 95320#L632 assume 1 == ~t4_pc~0; 95321#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 95846#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 96027#L644 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 96475#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 95969#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 95686#L651 assume 1 == ~t5_pc~0; 95687#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 95005#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 95006#L663 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 95455#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 95021#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 95022#L670 assume !(1 == ~t6_pc~0); 96200#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 95369#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 95370#L682 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 96330#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 95651#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 95652#L689 assume 1 == ~t7_pc~0; 96461#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 95771#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 95772#L701 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 96218#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 95549#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 95550#L708 assume !(1 == ~t8_pc~0); 95109#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 95110#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 96329#L720 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 96311#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 95174#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 95175#L727 assume 1 == ~t9_pc~0; 95299#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 94876#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 96489#L739 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 96490#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 96450#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 95228#L746 assume !(1 == ~t10_pc~0); 95229#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 95919#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 96045#L758 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 96322#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 96151#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 95392#L765 assume 1 == ~t11_pc~0; 95393#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 95603#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 94765#L777 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 94766#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 96199#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 96307#L1249 assume 1 == ~M_E~0;~M_E~0 := 2; 95850#L1249-2 assume !(1 == ~T1_E~0); 95475#L1254-1 assume !(1 == ~T2_E~0); 94811#L1259-1 assume !(1 == ~T3_E~0); 94793#L1264-1 assume !(1 == ~T4_E~0); 94794#L1269-1 assume !(1 == ~T5_E~0); 96543#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 96403#L1279-1 assume !(1 == ~T7_E~0); 94994#L1284-1 assume !(1 == ~T8_E~0); 94995#L1289-1 assume !(1 == ~T9_E~0); 95527#L1294-1 assume !(1 == ~T10_E~0); 95528#L1299-1 assume !(1 == ~T11_E~0); 107053#L1304-1 assume !(1 == ~E_M~0); 107051#L1309-1 assume !(1 == ~E_1~0); 107050#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 107049#L1319-1 assume !(1 == ~E_3~0); 107047#L1324-1 assume !(1 == ~E_4~0); 107045#L1329-1 assume !(1 == ~E_5~0); 107005#L1334-1 assume !(1 == ~E_6~0); 106990#L1339-1 assume !(1 == ~E_7~0); 106988#L1344-1 assume !(1 == ~E_8~0); 106986#L1349-1 assume !(1 == ~E_9~0); 106963#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 106947#L1359-1 assume !(1 == ~E_11~0); 106937#L1364-1 assume { :end_inline_reset_delta_events } true; 106928#L1690-2 [2022-07-14 16:03:02,497 INFO L754 eck$LassoCheckResult]: Loop: 106928#L1690-2 assume !false; 106920#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 106916#L1096 assume !false; 106915#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 106904#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 106899#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 106897#L923 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 106894#L937 assume !(0 != eval_~tmp~0#1); 106895#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 109559#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 109558#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 109555#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 109553#L1126-3 assume !(0 == ~T2_E~0); 109551#L1131-3 assume !(0 == ~T3_E~0); 109549#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 109547#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 109545#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 109542#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 109540#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 109538#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 109536#L1166-3 assume !(0 == ~T10_E~0); 109534#L1171-3 assume !(0 == ~T11_E~0); 109532#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 109529#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 109527#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 108326#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 108325#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 108323#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 108321#L1206-3 assume !(0 == ~E_6~0); 108319#L1211-3 assume !(0 == ~E_7~0); 108317#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 108315#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 108312#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 108310#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 108308#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 108306#L556-39 assume !(1 == ~m_pc~0); 108304#L556-41 is_master_triggered_~__retres1~0#1 := 0; 108303#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 108302#L568-13 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 108299#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 108297#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 108295#L575-39 assume !(1 == ~t1_pc~0); 108293#L575-41 is_transmit1_triggered_~__retres1~1#1 := 0; 108290#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 108288#L587-13 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 108287#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 108286#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 108284#L594-39 assume 1 == ~t2_pc~0; 108281#L595-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 108279#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 108277#L606-13 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 108275#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 108274#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 108272#L613-39 assume 1 == ~t3_pc~0; 108269#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 108267#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 108265#L625-13 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 108262#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 108260#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 108258#L632-39 assume 1 == ~t4_pc~0; 108256#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 108253#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 108251#L644-13 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 108250#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 108249#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 108248#L651-39 assume !(1 == ~t5_pc~0); 108247#L651-41 is_transmit5_triggered_~__retres1~5#1 := 0; 108244#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 108140#L663-13 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 108036#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 108034#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 108031#L670-39 assume 1 == ~t6_pc~0; 108029#L671-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 108026#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 108024#L682-13 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 108022#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 108020#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 108019#L689-39 assume 1 == ~t7_pc~0; 108017#L690-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 108016#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 108015#L701-13 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 108014#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 107901#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 107898#L708-39 assume 1 == ~t8_pc~0; 107895#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 107892#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 107890#L720-13 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 107888#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 107886#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 107838#L727-39 assume !(1 == ~t9_pc~0); 107835#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 107832#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 107830#L739-13 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 107828#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 107758#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 107756#L746-39 assume 1 == ~t10_pc~0; 107751#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 107749#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 107747#L758-13 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 107745#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 107743#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 107624#L765-39 assume !(1 == ~t11_pc~0); 107621#L765-41 is_transmit11_triggered_~__retres1~11#1 := 0; 107553#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 107550#L777-13 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 107548#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 107546#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 107544#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 95746#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 107541#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 107537#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 107536#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 107486#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 107484#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 107482#L1279-3 assume !(1 == ~T7_E~0); 107480#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 107441#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 107438#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 107413#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 107410#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 107408#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 107377#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 107336#L1319-3 assume !(1 == ~E_3~0); 107294#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 107267#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 107238#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 107213#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 107211#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 107186#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 107184#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 107154#L1359-3 assume !(1 == ~E_11~0); 107119#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 107083#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 107079#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 107077#L923-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 107075#L1709 assume !(0 == start_simulation_~tmp~3#1); 95325#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 107000#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 106989#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 106987#L923-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 106985#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 106962#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 106946#L1672 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 106936#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 106928#L1690-2 [2022-07-14 16:03:02,497 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:02,498 INFO L85 PathProgramCache]: Analyzing trace with hash -1258502475, now seen corresponding path program 1 times [2022-07-14 16:03:02,498 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:02,498 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [259616224] [2022-07-14 16:03:02,498 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:02,498 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:02,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:02,520 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:02,520 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:02,520 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [259616224] [2022-07-14 16:03:02,520 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [259616224] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:02,520 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:02,521 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:02,521 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1256682076] [2022-07-14 16:03:02,521 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:02,521 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:02,521 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:02,521 INFO L85 PathProgramCache]: Analyzing trace with hash -1139240517, now seen corresponding path program 1 times [2022-07-14 16:03:02,522 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:02,522 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1767493357] [2022-07-14 16:03:02,522 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:02,522 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:02,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:02,542 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:02,542 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:02,542 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1767493357] [2022-07-14 16:03:02,542 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1767493357] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:02,542 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:02,542 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:02,543 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1557689077] [2022-07-14 16:03:02,543 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:02,543 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:02,543 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:02,543 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:03:02,543 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:03:02,544 INFO L87 Difference]: Start difference. First operand 19905 states and 29030 transitions. cyclomatic complexity: 9141 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:02,893 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:02,894 INFO L93 Difference]: Finished difference Result 48409 states and 70033 transitions. [2022-07-14 16:03:02,894 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:03:02,894 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 48409 states and 70033 transitions. [2022-07-14 16:03:03,195 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 47432 [2022-07-14 16:03:03,316 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 48409 states to 48409 states and 70033 transitions. [2022-07-14 16:03:03,317 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 48409 [2022-07-14 16:03:03,351 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 48409 [2022-07-14 16:03:03,352 INFO L73 IsDeterministic]: Start isDeterministic. Operand 48409 states and 70033 transitions. [2022-07-14 16:03:03,477 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:03,478 INFO L369 hiAutomatonCegarLoop]: Abstraction has 48409 states and 70033 transitions. [2022-07-14 16:03:03,494 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48409 states and 70033 transitions. [2022-07-14 16:03:03,879 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48409 to 37973. [2022-07-14 16:03:03,917 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37973 states, 37973 states have (on average 1.4516630237273853) internal successors, (55124), 37972 states have internal predecessors, (55124), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:04,109 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37973 states to 37973 states and 55124 transitions. [2022-07-14 16:03:04,110 INFO L392 hiAutomatonCegarLoop]: Abstraction has 37973 states and 55124 transitions. [2022-07-14 16:03:04,110 INFO L374 stractBuchiCegarLoop]: Abstraction has 37973 states and 55124 transitions. [2022-07-14 16:03:04,110 INFO L287 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-07-14 16:03:04,110 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37973 states and 55124 transitions. [2022-07-14 16:03:04,187 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 37716 [2022-07-14 16:03:04,187 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:04,188 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:04,189 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:04,189 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:04,190 INFO L752 eck$LassoCheckResult]: Stem: 163744#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 163745#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 164319#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 164320#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 164171#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 164172#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 163165#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 163166#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 164684#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 164144#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 164145#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 164460#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 164461#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 164552#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 164647#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 164648#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 164512#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 164338#L1121 assume !(0 == ~M_E~0); 164064#L1121-2 assume !(0 == ~T1_E~0); 163437#L1126-1 assume !(0 == ~T2_E~0); 163438#L1131-1 assume !(0 == ~T3_E~0); 163605#L1136-1 assume !(0 == ~T4_E~0); 163702#L1141-1 assume !(0 == ~T5_E~0); 163931#L1146-1 assume !(0 == ~T6_E~0); 164262#L1151-1 assume !(0 == ~T7_E~0); 163762#L1156-1 assume !(0 == ~T8_E~0); 163150#L1161-1 assume !(0 == ~T9_E~0); 163151#L1166-1 assume !(0 == ~T10_E~0); 163371#L1171-1 assume !(0 == ~T11_E~0); 163372#L1176-1 assume !(0 == ~E_M~0); 164275#L1181-1 assume !(0 == ~E_1~0); 164415#L1186-1 assume !(0 == ~E_2~0); 164475#L1191-1 assume !(0 == ~E_3~0); 163399#L1196-1 assume !(0 == ~E_4~0); 163400#L1201-1 assume !(0 == ~E_5~0); 164700#L1206-1 assume !(0 == ~E_6~0); 164513#L1211-1 assume !(0 == ~E_7~0); 164514#L1216-1 assume !(0 == ~E_8~0); 163542#L1221-1 assume !(0 == ~E_9~0); 163543#L1226-1 assume !(0 == ~E_10~0); 163247#L1231-1 assume !(0 == ~E_11~0); 163248#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 164278#L556 assume !(1 == ~m_pc~0); 164279#L556-2 is_master_triggered_~__retres1~0#1 := 0; 163124#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 163125#L568 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 164023#L1391 assume !(0 != activate_threads_~tmp~1#1); 164450#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 164451#L575 assume !(1 == ~t1_pc~0); 163076#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 163077#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 163210#L587 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 163552#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 163509#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 163510#L594 assume !(1 == ~t2_pc~0); 164247#L594-2 is_transmit2_triggered_~__retres1~2#1 := 0; 164352#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 163910#L606 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 163141#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 163142#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 163199#L613 assume !(1 == ~t3_pc~0); 163316#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 163315#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 163243#L625 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 163244#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 163925#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 163639#L632 assume 1 == ~t4_pc~0; 163640#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 164160#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 164339#L644 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 164701#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 164284#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 164005#L651 assume 1 == ~t5_pc~0; 164006#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 163328#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 163329#L663 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 163774#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 163344#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 163345#L670 assume !(1 == ~t6_pc~0); 164496#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 163693#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 163694#L682 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 164603#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 163968#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 163969#L689 assume 1 == ~t7_pc~0; 164697#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 164084#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 164085#L701 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 164510#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 163868#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 163869#L708 assume !(1 == ~t8_pc~0); 163432#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 163433#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 164601#L720 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 164586#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 163494#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 163495#L727 assume 1 == ~t9_pc~0; 163619#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 163201#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 164707#L739 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 164708#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 164689#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 163549#L746 assume !(1 == ~t10_pc~0); 163550#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 164229#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 164357#L758 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 164595#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 164453#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 163714#L765 assume 1 == ~t11_pc~0; 163715#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 163920#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 163089#L777 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 163090#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 164494#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 164582#L1249 assume 1 == ~M_E~0;~M_E~0 := 2; 164165#L1249-2 assume !(1 == ~T1_E~0); 163795#L1254-1 assume !(1 == ~T2_E~0); 163135#L1259-1 assume !(1 == ~T3_E~0); 163117#L1264-1 assume !(1 == ~T4_E~0); 163118#L1269-1 assume !(1 == ~T5_E~0); 164742#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 164657#L1279-1 assume !(1 == ~T7_E~0); 163317#L1284-1 assume !(1 == ~T8_E~0); 163318#L1289-1 assume !(1 == ~T9_E~0); 163847#L1294-1 assume !(1 == ~T10_E~0); 163848#L1299-1 assume !(1 == ~T11_E~0); 163857#L1304-1 assume !(1 == ~E_M~0); 164738#L1309-1 assume !(1 == ~E_1~0); 164739#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 163266#L1319-1 assume !(1 == ~E_3~0); 163267#L1324-1 assume !(1 == ~E_4~0); 163394#L1329-1 assume !(1 == ~E_5~0); 163395#L1334-1 assume !(1 == ~E_6~0); 164536#L1339-1 assume !(1 == ~E_7~0); 164718#L1344-1 assume !(1 == ~E_8~0); 164749#L1349-1 assume !(1 == ~E_9~0); 164750#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 164386#L1359-1 assume !(1 == ~E_11~0); 164387#L1364-1 assume { :end_inline_reset_delta_events } true; 199282#L1690-2 [2022-07-14 16:03:04,190 INFO L754 eck$LassoCheckResult]: Loop: 199282#L1690-2 assume !false; 199275#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 199272#L1096 assume !false; 199271#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 199261#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 199258#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 199257#L923 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 199255#L937 assume !(0 != eval_~tmp~0#1); 199256#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 200347#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 200345#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 200342#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 200340#L1126-3 assume !(0 == ~T2_E~0); 200338#L1131-3 assume !(0 == ~T3_E~0); 200336#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 200334#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 200332#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 200329#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 200327#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 200325#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 200323#L1166-3 assume !(0 == ~T10_E~0); 200321#L1171-3 assume !(0 == ~T11_E~0); 200319#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 200316#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 200314#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 200312#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 200310#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 200308#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 200306#L1206-3 assume !(0 == ~E_6~0); 200303#L1211-3 assume !(0 == ~E_7~0); 200301#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 200299#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 200297#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 200295#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 200293#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 200290#L556-39 assume !(1 == ~m_pc~0); 200288#L556-41 is_master_triggered_~__retres1~0#1 := 0; 200286#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 200284#L568-13 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 200282#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 200280#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 200277#L575-39 assume !(1 == ~t1_pc~0); 200275#L575-41 is_transmit1_triggered_~__retres1~1#1 := 0; 200272#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 200270#L587-13 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 200268#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 200266#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 200263#L594-39 assume !(1 == ~t2_pc~0); 199194#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 200260#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 200258#L606-13 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 200256#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 200254#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 200251#L613-39 assume !(1 == ~t3_pc~0); 200249#L613-41 is_transmit3_triggered_~__retres1~3#1 := 0; 200246#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 200244#L625-13 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 200242#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 200241#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 200240#L632-39 assume 1 == ~t4_pc~0; 200237#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 200235#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 200234#L644-13 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 200233#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 200232#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 200231#L651-39 assume !(1 == ~t5_pc~0); 200230#L651-41 is_transmit5_triggered_~__retres1~5#1 := 0; 200228#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 200227#L663-13 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 200226#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 200225#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 200224#L670-39 assume 1 == ~t6_pc~0; 200223#L671-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 200221#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 200220#L682-13 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 200219#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 200218#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 200217#L689-39 assume !(1 == ~t7_pc~0); 200215#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 200213#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 200210#L701-13 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 200208#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 200206#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 200204#L708-39 assume 1 == ~t8_pc~0; 200202#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 200199#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 200196#L720-13 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 200194#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 200192#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 200190#L727-39 assume 1 == ~t9_pc~0; 200187#L728-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 200185#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 200182#L739-13 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 200180#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 200178#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 200176#L746-39 assume !(1 == ~t10_pc~0); 200174#L746-41 is_transmit10_triggered_~__retres1~10#1 := 0; 200171#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 200168#L758-13 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 200166#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 200164#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 200162#L765-39 assume 1 == ~t11_pc~0; 200160#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 200157#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 200154#L777-13 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 200152#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 200150#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 200148#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 164058#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 200145#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 194187#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 200141#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 200139#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 200137#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 200135#L1279-3 assume !(1 == ~T7_E~0); 200133#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 200130#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 200128#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 197870#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 200125#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 200123#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 200121#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 200118#L1319-3 assume !(1 == ~E_3~0); 200116#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 200114#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 200112#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 164724#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 200109#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 200106#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 200104#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 200102#L1359-3 assume !(1 == ~E_11~0); 200100#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 200079#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 200076#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 200075#L923-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 200074#L1709 assume !(0 == start_simulation_~tmp~3#1); 163644#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 199379#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 199323#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 199322#L923-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 199321#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 199307#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 199296#L1672 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 199289#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 199282#L1690-2 [2022-07-14 16:03:04,190 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:04,191 INFO L85 PathProgramCache]: Analyzing trace with hash 1819278198, now seen corresponding path program 1 times [2022-07-14 16:03:04,191 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:04,191 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1103779561] [2022-07-14 16:03:04,191 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:04,191 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:04,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:04,221 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:04,221 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:04,221 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1103779561] [2022-07-14 16:03:04,221 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1103779561] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:04,221 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:04,222 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-14 16:03:04,222 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1737239426] [2022-07-14 16:03:04,222 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:04,222 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:04,222 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:04,223 INFO L85 PathProgramCache]: Analyzing trace with hash -1346203971, now seen corresponding path program 1 times [2022-07-14 16:03:04,223 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:04,223 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1314363907] [2022-07-14 16:03:04,223 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:04,223 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:04,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:04,247 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:04,247 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:04,247 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1314363907] [2022-07-14 16:03:04,247 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1314363907] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:04,247 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:04,247 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:04,248 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1071643157] [2022-07-14 16:03:04,248 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:04,248 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:04,248 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:04,248 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:04,249 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:04,249 INFO L87 Difference]: Start difference. First operand 37973 states and 55124 transitions. cyclomatic complexity: 17167 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:04,609 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:04,609 INFO L93 Difference]: Finished difference Result 72612 states and 104949 transitions. [2022-07-14 16:03:04,610 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:04,610 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 72612 states and 104949 transitions. [2022-07-14 16:03:05,025 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 72276 [2022-07-14 16:03:05,220 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 72612 states to 72612 states and 104949 transitions. [2022-07-14 16:03:05,221 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 72612 [2022-07-14 16:03:05,265 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 72612 [2022-07-14 16:03:05,266 INFO L73 IsDeterministic]: Start isDeterministic. Operand 72612 states and 104949 transitions. [2022-07-14 16:03:05,312 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:05,312 INFO L369 hiAutomatonCegarLoop]: Abstraction has 72612 states and 104949 transitions. [2022-07-14 16:03:05,352 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72612 states and 104949 transitions. [2022-07-14 16:03:05,876 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72612 to 72548. [2022-07-14 16:03:05,977 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 72548 states, 72548 states have (on average 1.4457324805645917) internal successors, (104885), 72547 states have internal predecessors, (104885), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:06,264 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72548 states to 72548 states and 104885 transitions. [2022-07-14 16:03:06,265 INFO L392 hiAutomatonCegarLoop]: Abstraction has 72548 states and 104885 transitions. [2022-07-14 16:03:06,265 INFO L374 stractBuchiCegarLoop]: Abstraction has 72548 states and 104885 transitions. [2022-07-14 16:03:06,265 INFO L287 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-07-14 16:03:06,265 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 72548 states and 104885 transitions. [2022-07-14 16:03:06,422 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 72212 [2022-07-14 16:03:06,423 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:06,423 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:06,426 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:06,426 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:06,426 INFO L752 eck$LassoCheckResult]: Stem: 274334#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 274335#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 274943#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 274944#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 274785#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 274786#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 273756#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 273757#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 275390#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 274759#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 274760#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 275102#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 275103#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 275218#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 275340#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 275341#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 275167#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 274962#L1121 assume !(0 == ~M_E~0); 274679#L1121-2 assume !(0 == ~T1_E~0); 274028#L1126-1 assume !(0 == ~T2_E~0); 274029#L1131-1 assume !(0 == ~T3_E~0); 274197#L1136-1 assume !(0 == ~T4_E~0); 274294#L1141-1 assume !(0 == ~T5_E~0); 274535#L1146-1 assume !(0 == ~T6_E~0); 274880#L1151-1 assume !(0 == ~T7_E~0); 274353#L1156-1 assume !(0 == ~T8_E~0); 273742#L1161-1 assume !(0 == ~T9_E~0); 273743#L1166-1 assume !(0 == ~T10_E~0); 273962#L1171-1 assume !(0 == ~T11_E~0); 273963#L1176-1 assume !(0 == ~E_M~0); 274895#L1181-1 assume !(0 == ~E_1~0); 275055#L1186-1 assume !(0 == ~E_2~0); 275118#L1191-1 assume !(0 == ~E_3~0); 273990#L1196-1 assume !(0 == ~E_4~0); 273991#L1201-1 assume !(0 == ~E_5~0); 275414#L1206-1 assume !(0 == ~E_6~0); 275168#L1211-1 assume !(0 == ~E_7~0); 275169#L1216-1 assume !(0 == ~E_8~0); 274132#L1221-1 assume !(0 == ~E_9~0); 274133#L1226-1 assume !(0 == ~E_10~0); 273837#L1231-1 assume !(0 == ~E_11~0); 273838#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 274896#L556 assume !(1 == ~m_pc~0); 274897#L556-2 is_master_triggered_~__retres1~0#1 := 0; 273716#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 273717#L568 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 274634#L1391 assume !(0 != activate_threads_~tmp~1#1); 275089#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 275090#L575 assume !(1 == ~t1_pc~0); 273668#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 273669#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 273801#L587 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 274145#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 274102#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 274103#L594 assume !(1 == ~t2_pc~0); 274864#L594-2 is_transmit2_triggered_~__retres1~2#1 := 0; 274979#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 274516#L606 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 273733#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 273734#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 273791#L613 assume !(1 == ~t3_pc~0); 273906#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 273905#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 273833#L625 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 273834#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 274532#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 274234#L632 assume !(1 == ~t4_pc~0); 274235#L632-2 is_transmit4_triggered_~__retres1~4#1 := 0; 274963#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 274964#L644 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 275415#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 274905#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 274613#L651 assume 1 == ~t5_pc~0; 274614#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 273918#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 273919#L663 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 274367#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 273935#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 273936#L670 assume !(1 == ~t6_pc~0); 275143#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 274283#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 274284#L682 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 275280#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 274576#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 274577#L689 assume 1 == ~t7_pc~0; 275405#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 274699#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 274700#L701 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 275164#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 274470#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 274471#L708 assume !(1 == ~t8_pc~0); 274023#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 274024#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 275277#L720 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 275255#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 274086#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 274087#L727 assume 1 == ~t9_pc~0; 274212#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 273793#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 275424#L739 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 275425#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 275391#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 274141#L746 assume !(1 == ~t10_pc~0); 274142#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 274848#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 274989#L758 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 275268#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 275093#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 274303#L765 assume 1 == ~t11_pc~0; 274304#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 274526#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 273681#L777 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 273682#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 275142#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 275250#L1249 assume 1 == ~M_E~0;~M_E~0 := 2; 275251#L1249-2 assume !(1 == ~T1_E~0); 304603#L1254-1 assume !(1 == ~T2_E~0); 304602#L1259-1 assume !(1 == ~T3_E~0); 304601#L1264-1 assume !(1 == ~T4_E~0); 304600#L1269-1 assume !(1 == ~T5_E~0); 304599#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 304598#L1279-1 assume !(1 == ~T7_E~0); 304597#L1284-1 assume !(1 == ~T8_E~0); 304596#L1289-1 assume !(1 == ~T9_E~0); 304595#L1294-1 assume !(1 == ~T10_E~0); 304594#L1299-1 assume !(1 == ~T11_E~0); 304590#L1304-1 assume !(1 == ~E_M~0); 304588#L1309-1 assume !(1 == ~E_1~0); 304586#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 304581#L1319-1 assume !(1 == ~E_3~0); 304579#L1324-1 assume !(1 == ~E_4~0); 304576#L1329-1 assume !(1 == ~E_5~0); 304574#L1334-1 assume !(1 == ~E_6~0); 304568#L1339-1 assume !(1 == ~E_7~0); 304567#L1344-1 assume !(1 == ~E_8~0); 304565#L1349-1 assume !(1 == ~E_9~0); 304563#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 304561#L1359-1 assume !(1 == ~E_11~0); 304559#L1364-1 assume { :end_inline_reset_delta_events } true; 304556#L1690-2 [2022-07-14 16:03:06,427 INFO L754 eck$LassoCheckResult]: Loop: 304556#L1690-2 assume !false; 304410#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 304406#L1096 assume !false; 304404#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 304378#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 304374#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 304372#L923 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 304370#L937 assume !(0 != eval_~tmp~0#1); 304371#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 343312#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 343309#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 343307#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 343305#L1126-3 assume !(0 == ~T2_E~0); 343303#L1131-3 assume !(0 == ~T3_E~0); 343301#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 343299#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 343296#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 343294#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 343292#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 343290#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 343288#L1166-3 assume !(0 == ~T10_E~0); 343286#L1171-3 assume !(0 == ~T11_E~0); 343283#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 343281#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 343279#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 343277#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 343275#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 343271#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 343269#L1206-3 assume !(0 == ~E_6~0); 343268#L1211-3 assume !(0 == ~E_7~0); 343267#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 343266#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 343265#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 343264#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 343263#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 343262#L556-39 assume !(1 == ~m_pc~0); 343260#L556-41 is_master_triggered_~__retres1~0#1 := 0; 343257#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 343255#L568-13 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 343253#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 343251#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 343249#L575-39 assume 1 == ~t1_pc~0; 343245#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 343246#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 345203#L587-13 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 345201#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 343235#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 319417#L594-39 assume !(1 == ~t2_pc~0); 305322#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 305319#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 305317#L606-13 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 305315#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 305313#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 305311#L613-39 assume !(1 == ~t3_pc~0); 305308#L613-41 is_transmit3_triggered_~__retres1~3#1 := 0; 305304#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 305302#L625-13 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 305300#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 305298#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 305296#L632-39 assume !(1 == ~t4_pc~0); 305294#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 305293#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 305290#L644-13 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 305288#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 305286#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 305284#L651-39 assume 1 == ~t5_pc~0; 305281#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 305279#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 305277#L663-13 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 305275#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 305273#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 305271#L670-39 assume !(1 == ~t6_pc~0); 305268#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 305266#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 305265#L682-13 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 305262#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 305260#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 305258#L689-39 assume 1 == ~t7_pc~0; 305255#L690-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 305253#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 305252#L701-13 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 305249#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 305247#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 305245#L708-39 assume !(1 == ~t8_pc~0); 305242#L708-41 is_transmit8_triggered_~__retres1~8#1 := 0; 305240#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 305237#L720-13 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 305235#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 305233#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 305231#L727-39 assume 1 == ~t9_pc~0; 305228#L728-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 305226#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 305224#L739-13 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 305221#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 305219#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 305217#L746-39 assume 1 == ~t10_pc~0; 305214#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 305212#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 305210#L758-13 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 305208#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 305206#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 305204#L765-39 assume !(1 == ~t11_pc~0); 305201#L765-41 is_transmit11_triggered_~__retres1~11#1 := 0; 305199#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 305197#L777-13 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 305194#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 305192#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 305190#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 305187#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 305185#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 305182#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 305179#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 305177#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 305175#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 305173#L1279-3 assume !(1 == ~T7_E~0); 305171#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 305169#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 305166#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 305162#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 305160#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 305158#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 305156#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 305154#L1319-3 assume !(1 == ~E_3~0); 305151#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 305149#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 305147#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 305143#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 305141#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 305139#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 305136#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 305134#L1359-3 assume !(1 == ~E_11~0); 305132#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 305107#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 305103#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 305101#L923-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 305054#L1709 assume !(0 == start_simulation_~tmp~3#1); 305052#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 305043#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 305032#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 305030#L923-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 305028#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 305026#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 305024#L1672 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 304558#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 304556#L1690-2 [2022-07-14 16:03:06,427 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:06,427 INFO L85 PathProgramCache]: Analyzing trace with hash -343701065, now seen corresponding path program 1 times [2022-07-14 16:03:06,427 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:06,428 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1196345764] [2022-07-14 16:03:06,428 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:06,428 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:06,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:06,456 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:06,456 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:06,456 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1196345764] [2022-07-14 16:03:06,456 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1196345764] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:06,456 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:06,457 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-14 16:03:06,457 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1679841993] [2022-07-14 16:03:06,457 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:06,457 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:06,457 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:06,458 INFO L85 PathProgramCache]: Analyzing trace with hash 1806576445, now seen corresponding path program 1 times [2022-07-14 16:03:06,458 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:06,458 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1062006045] [2022-07-14 16:03:06,458 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:06,458 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:06,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:06,481 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:06,481 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:06,481 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1062006045] [2022-07-14 16:03:06,481 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1062006045] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:06,482 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:06,482 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:06,482 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [330885681] [2022-07-14 16:03:06,482 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:06,483 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:06,483 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:06,483 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-14 16:03:06,483 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-14 16:03:06,484 INFO L87 Difference]: Start difference. First operand 72548 states and 104885 transitions. cyclomatic complexity: 32369 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:07,139 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:07,139 INFO L93 Difference]: Finished difference Result 141407 states and 203438 transitions. [2022-07-14 16:03:07,139 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-14 16:03:07,140 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 141407 states and 203438 transitions. [2022-07-14 16:03:07,828 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 140848 [2022-07-14 16:03:08,206 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 141407 states to 141407 states and 203438 transitions. [2022-07-14 16:03:08,206 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 141407 [2022-07-14 16:03:08,275 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 141407 [2022-07-14 16:03:08,275 INFO L73 IsDeterministic]: Start isDeterministic. Operand 141407 states and 203438 transitions. [2022-07-14 16:03:08,377 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:08,378 INFO L369 hiAutomatonCegarLoop]: Abstraction has 141407 states and 203438 transitions. [2022-07-14 16:03:08,447 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 141407 states and 203438 transitions. [2022-07-14 16:03:09,802 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 141407 to 141279. [2022-07-14 16:03:09,955 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 141279 states, 141279 states have (on average 1.4390673773172233) internal successors, (203310), 141278 states have internal predecessors, (203310), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:10,224 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141279 states to 141279 states and 203310 transitions. [2022-07-14 16:03:10,224 INFO L392 hiAutomatonCegarLoop]: Abstraction has 141279 states and 203310 transitions. [2022-07-14 16:03:10,224 INFO L374 stractBuchiCegarLoop]: Abstraction has 141279 states and 203310 transitions. [2022-07-14 16:03:10,224 INFO L287 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-07-14 16:03:10,224 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 141279 states and 203310 transitions. [2022-07-14 16:03:10,885 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 140720 [2022-07-14 16:03:10,885 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:10,885 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:10,887 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:10,887 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:10,888 INFO L752 eck$LassoCheckResult]: Stem: 488292#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 488293#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 488880#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 488881#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 488726#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 488727#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 487719#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 487720#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 489314#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 488701#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 488702#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 489033#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 489034#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 489146#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 489258#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 489259#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 489099#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 488899#L1121 assume !(0 == ~M_E~0); 488624#L1121-2 assume !(0 == ~T1_E~0); 487991#L1126-1 assume !(0 == ~T2_E~0); 487992#L1131-1 assume !(0 == ~T3_E~0); 488160#L1136-1 assume !(0 == ~T4_E~0); 488254#L1141-1 assume !(0 == ~T5_E~0); 488483#L1146-1 assume !(0 == ~T6_E~0); 488818#L1151-1 assume !(0 == ~T7_E~0); 488314#L1156-1 assume !(0 == ~T8_E~0); 487705#L1161-1 assume !(0 == ~T9_E~0); 487706#L1166-1 assume !(0 == ~T10_E~0); 487927#L1171-1 assume !(0 == ~T11_E~0); 487928#L1176-1 assume !(0 == ~E_M~0); 488833#L1181-1 assume !(0 == ~E_1~0); 488983#L1186-1 assume !(0 == ~E_2~0); 489051#L1191-1 assume !(0 == ~E_3~0); 487954#L1196-1 assume !(0 == ~E_4~0); 487955#L1201-1 assume !(0 == ~E_5~0); 489331#L1206-1 assume !(0 == ~E_6~0); 489100#L1211-1 assume !(0 == ~E_7~0); 489101#L1216-1 assume !(0 == ~E_8~0); 488094#L1221-1 assume !(0 == ~E_9~0); 488095#L1226-1 assume !(0 == ~E_10~0); 487801#L1231-1 assume !(0 == ~E_11~0); 487802#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 488834#L556 assume !(1 == ~m_pc~0); 488835#L556-2 is_master_triggered_~__retres1~0#1 := 0; 487679#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 487680#L568 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 488579#L1391 assume !(0 != activate_threads_~tmp~1#1); 489016#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 489017#L575 assume !(1 == ~t1_pc~0); 487630#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 487631#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 487764#L587 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 488107#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 488064#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 488065#L594 assume !(1 == ~t2_pc~0); 488799#L594-2 is_transmit2_triggered_~__retres1~2#1 := 0; 488914#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 488467#L606 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 487694#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 487695#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 487753#L613 assume !(1 == ~t3_pc~0); 487870#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 487869#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 487797#L625 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 487798#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 488482#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 488193#L632 assume !(1 == ~t4_pc~0); 488194#L632-2 is_transmit4_triggered_~__retres1~4#1 := 0; 488900#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 488901#L644 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 489334#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 488842#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 488561#L651 assume !(1 == ~t5_pc~0); 488562#L651-2 is_transmit5_triggered_~__retres1~5#1 := 0; 487882#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 487883#L663 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 488326#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 487899#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 487900#L670 assume !(1 == ~t6_pc~0); 489076#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 488240#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 488241#L682 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 489198#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 488526#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 488527#L689 assume 1 == ~t7_pc~0; 489322#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 488644#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 488645#L701 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 489097#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 488424#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 488425#L708 assume !(1 == ~t8_pc~0); 487987#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 487988#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 489197#L720 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 489179#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 488049#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 488050#L727 assume 1 == ~t9_pc~0; 488173#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 487755#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 489344#L739 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 489345#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 489315#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 488103#L746 assume !(1 == ~t10_pc~0); 488104#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 488786#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 488922#L758 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 489191#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 489023#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 488263#L765 assume 1 == ~t11_pc~0; 488264#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 488478#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 487644#L777 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 487645#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 489075#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 489175#L1249 assume 1 == ~M_E~0;~M_E~0 := 2; 488719#L1249-2 assume !(1 == ~T1_E~0); 488346#L1254-1 assume !(1 == ~T2_E~0); 487690#L1259-1 assume !(1 == ~T3_E~0); 487672#L1264-1 assume !(1 == ~T4_E~0); 487673#L1269-1 assume !(1 == ~T5_E~0); 489394#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 489275#L1279-1 assume !(1 == ~T7_E~0); 487871#L1284-1 assume !(1 == ~T8_E~0); 487872#L1289-1 assume !(1 == ~T9_E~0); 488402#L1294-1 assume !(1 == ~T10_E~0); 488403#L1299-1 assume !(1 == ~T11_E~0); 502017#L1304-1 assume !(1 == ~E_M~0); 502015#L1309-1 assume !(1 == ~E_1~0); 502013#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 502011#L1319-1 assume !(1 == ~E_3~0); 502009#L1324-1 assume !(1 == ~E_4~0); 502007#L1329-1 assume !(1 == ~E_5~0); 502005#L1334-1 assume !(1 == ~E_6~0); 502001#L1339-1 assume !(1 == ~E_7~0); 501999#L1344-1 assume !(1 == ~E_8~0); 501997#L1349-1 assume !(1 == ~E_9~0); 501995#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 501992#L1359-1 assume !(1 == ~E_11~0); 501990#L1364-1 assume { :end_inline_reset_delta_events } true; 501987#L1690-2 [2022-07-14 16:03:10,888 INFO L754 eck$LassoCheckResult]: Loop: 501987#L1690-2 assume !false; 501912#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 501908#L1096 assume !false; 501906#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 496744#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 496740#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 496738#L923 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 496733#L937 assume !(0 != eval_~tmp~0#1); 496734#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 519580#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 519578#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 519576#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 519574#L1126-3 assume !(0 == ~T2_E~0); 519572#L1131-3 assume !(0 == ~T3_E~0); 519570#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 519568#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 519565#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 519563#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 519561#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 519559#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 519557#L1166-3 assume !(0 == ~T10_E~0); 519554#L1171-3 assume !(0 == ~T11_E~0); 519553#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 519550#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 519548#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 519546#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 519544#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 519542#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 519540#L1206-3 assume !(0 == ~E_6~0); 519537#L1211-3 assume !(0 == ~E_7~0); 519535#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 519533#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 519532#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 519531#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 519530#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 519529#L556-39 assume !(1 == ~m_pc~0); 519528#L556-41 is_master_triggered_~__retres1~0#1 := 0; 519527#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 519526#L568-13 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 519525#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 519524#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 519523#L575-39 assume !(1 == ~t1_pc~0); 519522#L575-41 is_transmit1_triggered_~__retres1~1#1 := 0; 519519#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 519517#L587-13 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 519515#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 519513#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 519511#L594-39 assume !(1 == ~t2_pc~0); 507968#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 519508#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 519505#L606-13 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 519503#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 519501#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 519499#L613-39 assume !(1 == ~t3_pc~0); 519497#L613-41 is_transmit3_triggered_~__retres1~3#1 := 0; 519494#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 519491#L625-13 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 519489#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 519487#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 519485#L632-39 assume !(1 == ~t4_pc~0); 519483#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 519481#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 519478#L644-13 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 519476#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 519474#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 519472#L651-39 assume !(1 == ~t5_pc~0); 519470#L651-41 is_transmit5_triggered_~__retres1~5#1 := 0; 519468#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 519466#L663-13 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 519464#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 519462#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 519460#L670-39 assume 1 == ~t6_pc~0; 515199#L671-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 502306#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 502303#L682-13 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 502301#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 502299#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 502297#L689-39 assume !(1 == ~t7_pc~0); 502295#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 502292#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 502289#L701-13 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 502287#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 502285#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 502283#L708-39 assume !(1 == ~t8_pc~0); 502279#L708-41 is_transmit8_triggered_~__retres1~8#1 := 0; 502276#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 502274#L720-13 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 502272#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 502270#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 502268#L727-39 assume !(1 == ~t9_pc~0); 502266#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 502264#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 502261#L739-13 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 502259#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 502257#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 502255#L746-39 assume !(1 == ~t10_pc~0); 502252#L746-41 is_transmit10_triggered_~__retres1~10#1 := 0; 502249#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 502247#L758-13 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 502245#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 502243#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 502241#L765-39 assume 1 == ~t11_pc~0; 502238#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 502235#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 502233#L777-13 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 502231#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 502229#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 502227#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 502222#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 502220#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 502216#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 502214#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 502212#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 502210#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 502207#L1279-3 assume !(1 == ~T7_E~0); 502205#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 502203#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 502201#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 502197#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 502195#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 502192#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 502190#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 502188#L1319-3 assume !(1 == ~E_3~0); 502186#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 502184#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 502182#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 502177#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 502175#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 502173#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 502171#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 502169#L1359-3 assume !(1 == ~E_11~0); 502167#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 502140#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 502136#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 502133#L923-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 502071#L1709 assume !(0 == start_simulation_~tmp~3#1); 502069#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 502059#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 502048#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 502043#L923-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 502042#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 502040#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 502038#L1672 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 501989#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 501987#L1690-2 [2022-07-14 16:03:10,889 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:10,889 INFO L85 PathProgramCache]: Analyzing trace with hash 1793793208, now seen corresponding path program 1 times [2022-07-14 16:03:10,889 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:10,889 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [284022839] [2022-07-14 16:03:10,889 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:10,889 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:10,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:10,919 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:10,920 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:10,920 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [284022839] [2022-07-14 16:03:10,920 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [284022839] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:10,920 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:10,920 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-07-14 16:03:10,920 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [895249943] [2022-07-14 16:03:10,920 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:10,921 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:10,921 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:10,921 INFO L85 PathProgramCache]: Analyzing trace with hash 1651980224, now seen corresponding path program 1 times [2022-07-14 16:03:10,921 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:10,921 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1863141739] [2022-07-14 16:03:10,921 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:10,922 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:10,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:10,940 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:10,941 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:10,941 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1863141739] [2022-07-14 16:03:10,941 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1863141739] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:10,941 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:10,941 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:10,941 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1140435028] [2022-07-14 16:03:10,941 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:10,942 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:10,942 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:10,942 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-07-14 16:03:10,942 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-07-14 16:03:10,942 INFO L87 Difference]: Start difference. First operand 141279 states and 203310 transitions. cyclomatic complexity: 62095 Second operand has 5 states, 5 states have (on average 27.8) internal successors, (139), 5 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:12,253 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:12,253 INFO L93 Difference]: Finished difference Result 355284 states and 513243 transitions. [2022-07-14 16:03:12,253 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-07-14 16:03:12,254 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 355284 states and 513243 transitions. [2022-07-14 16:03:13,972 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 353776 [2022-07-14 16:03:15,094 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 355284 states to 355284 states and 513243 transitions. [2022-07-14 16:03:15,095 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 355284 [2022-07-14 16:03:15,252 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 355284 [2022-07-14 16:03:15,253 INFO L73 IsDeterministic]: Start isDeterministic. Operand 355284 states and 513243 transitions. [2022-07-14 16:03:15,438 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:15,439 INFO L369 hiAutomatonCegarLoop]: Abstraction has 355284 states and 513243 transitions. [2022-07-14 16:03:15,596 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 355284 states and 513243 transitions. [2022-07-14 16:03:17,291 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 355284 to 145458. [2022-07-14 16:03:17,395 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 145458 states, 145458 states have (on average 1.4264529967413273) internal successors, (207489), 145457 states have internal predecessors, (207489), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:18,039 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 145458 states to 145458 states and 207489 transitions. [2022-07-14 16:03:18,040 INFO L392 hiAutomatonCegarLoop]: Abstraction has 145458 states and 207489 transitions. [2022-07-14 16:03:18,040 INFO L374 stractBuchiCegarLoop]: Abstraction has 145458 states and 207489 transitions. [2022-07-14 16:03:18,040 INFO L287 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-07-14 16:03:18,040 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 145458 states and 207489 transitions. [2022-07-14 16:03:18,353 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 144896 [2022-07-14 16:03:18,354 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:18,354 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:18,355 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:18,355 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:18,355 INFO L752 eck$LassoCheckResult]: Stem: 984878#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 984879#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 985465#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 985466#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 985312#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 985313#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 984296#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 984297#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 985885#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 985283#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 985284#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 985607#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 985608#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 985727#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 985831#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 985832#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 985673#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 985483#L1121 assume !(0 == ~M_E~0); 985206#L1121-2 assume !(0 == ~T1_E~0); 984569#L1126-1 assume !(0 == ~T2_E~0); 984570#L1131-1 assume !(0 == ~T3_E~0); 984742#L1136-1 assume !(0 == ~T4_E~0); 984838#L1141-1 assume !(0 == ~T5_E~0); 985068#L1146-1 assume !(0 == ~T6_E~0); 985402#L1151-1 assume !(0 == ~T7_E~0); 984900#L1156-1 assume !(0 == ~T8_E~0); 984282#L1161-1 assume !(0 == ~T9_E~0); 984283#L1166-1 assume !(0 == ~T10_E~0); 984505#L1171-1 assume !(0 == ~T11_E~0); 984506#L1176-1 assume !(0 == ~E_M~0); 985416#L1181-1 assume !(0 == ~E_1~0); 985560#L1186-1 assume !(0 == ~E_2~0); 985626#L1191-1 assume !(0 == ~E_3~0); 984532#L1196-1 assume !(0 == ~E_4~0); 984533#L1201-1 assume !(0 == ~E_5~0); 985903#L1206-1 assume !(0 == ~E_6~0); 985674#L1211-1 assume !(0 == ~E_7~0); 985675#L1216-1 assume !(0 == ~E_8~0); 984673#L1221-1 assume !(0 == ~E_9~0); 984674#L1226-1 assume !(0 == ~E_10~0); 984379#L1231-1 assume !(0 == ~E_11~0); 984380#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 985417#L556 assume !(1 == ~m_pc~0); 985418#L556-2 is_master_triggered_~__retres1~0#1 := 0; 984255#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 984256#L568 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 985161#L1391 assume !(0 != activate_threads_~tmp~1#1); 985596#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 985597#L575 assume !(1 == ~t1_pc~0); 984206#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 984207#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 984341#L587 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 984689#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 984642#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 984643#L594 assume !(1 == ~t2_pc~0); 985386#L594-2 is_transmit2_triggered_~__retres1~2#1 := 0; 985498#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 985052#L606 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 984271#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 984272#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 984330#L613 assume !(1 == ~t3_pc~0); 984448#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 984447#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 984375#L625 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 984376#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 985067#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 984776#L632 assume !(1 == ~t4_pc~0); 984777#L632-2 is_transmit4_triggered_~__retres1~4#1 := 0; 985484#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 985485#L644 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 985904#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 985425#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 985144#L651 assume !(1 == ~t5_pc~0); 985145#L651-2 is_transmit5_triggered_~__retres1~5#1 := 0; 984460#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 984461#L663 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 984912#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 984477#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 984478#L670 assume !(1 == ~t6_pc~0); 985650#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 984824#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 984825#L682 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 985886#L1439 assume !(0 != activate_threads_~tmp___5~0#1); 985108#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 985109#L689 assume 1 == ~t7_pc~0; 985892#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 985226#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 985227#L701 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 985671#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 985010#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 985011#L708 assume !(1 == ~t8_pc~0); 984565#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 984566#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 985779#L720 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 985762#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 984627#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 984628#L727 assume 1 == ~t9_pc~0; 984755#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 984332#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 985909#L739 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 985910#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 985887#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 984684#L746 assume !(1 == ~t10_pc~0); 984685#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 985373#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 985507#L758 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 985773#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 985600#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 984848#L765 assume 1 == ~t11_pc~0; 984849#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 985063#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 984220#L777 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 984221#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 985649#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 985758#L1249 assume 1 == ~M_E~0;~M_E~0 := 2; 985302#L1249-2 assume !(1 == ~T1_E~0); 984933#L1254-1 assume !(1 == ~T2_E~0); 984934#L1259-1 assume !(1 == ~T3_E~0); 984248#L1264-1 assume !(1 == ~T4_E~0); 984249#L1269-1 assume !(1 == ~T5_E~0); 985974#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 990507#L1279-1 assume !(1 == ~T7_E~0); 990505#L1284-1 assume !(1 == ~T8_E~0); 990503#L1289-1 assume !(1 == ~T9_E~0); 990501#L1294-1 assume !(1 == ~T10_E~0); 990499#L1299-1 assume !(1 == ~T11_E~0); 990497#L1304-1 assume !(1 == ~E_M~0); 990493#L1309-1 assume !(1 == ~E_1~0); 990491#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 990489#L1319-1 assume !(1 == ~E_3~0); 990487#L1324-1 assume !(1 == ~E_4~0); 990485#L1329-1 assume !(1 == ~E_5~0); 990483#L1334-1 assume !(1 == ~E_6~0); 990479#L1339-1 assume !(1 == ~E_7~0); 990477#L1344-1 assume !(1 == ~E_8~0); 990473#L1349-1 assume !(1 == ~E_9~0); 990471#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 990469#L1359-1 assume !(1 == ~E_11~0); 990467#L1364-1 assume { :end_inline_reset_delta_events } true; 990464#L1690-2 [2022-07-14 16:03:18,356 INFO L754 eck$LassoCheckResult]: Loop: 990464#L1690-2 assume !false; 990068#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 990064#L1096 assume !false; 990062#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 989193#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 989189#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 989187#L923 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 989183#L937 assume !(0 != eval_~tmp~0#1); 989184#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1011790#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1011788#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1011786#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1011784#L1126-3 assume !(0 == ~T2_E~0); 1011781#L1131-3 assume !(0 == ~T3_E~0); 1011779#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1011777#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1011775#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1011773#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1011769#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1011767#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1011765#L1166-3 assume !(0 == ~T10_E~0); 1011764#L1171-3 assume !(0 == ~T11_E~0); 1011763#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1011762#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1011761#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1011760#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1011759#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1011758#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1011757#L1206-3 assume !(0 == ~E_6~0); 1011756#L1211-3 assume !(0 == ~E_7~0); 1011755#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1011754#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1011753#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1011752#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1011751#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1011750#L556-39 assume !(1 == ~m_pc~0); 1011749#L556-41 is_master_triggered_~__retres1~0#1 := 0; 1011748#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1011747#L568-13 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1011746#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 1011745#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1011744#L575-39 assume !(1 == ~t1_pc~0); 1011743#L575-41 is_transmit1_triggered_~__retres1~1#1 := 0; 1011741#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1011740#L587-13 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1011739#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1011738#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1011737#L594-39 assume !(1 == ~t2_pc~0); 992829#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 1011736#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1011735#L606-13 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1011734#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1011733#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1011732#L613-39 assume !(1 == ~t3_pc~0); 1011731#L613-41 is_transmit3_triggered_~__retres1~3#1 := 0; 1011729#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1011728#L625-13 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1011727#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1011726#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1011725#L632-39 assume !(1 == ~t4_pc~0); 1011724#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 1011723#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1011722#L644-13 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1011721#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1011720#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1011719#L651-39 assume !(1 == ~t5_pc~0); 1011718#L651-41 is_transmit5_triggered_~__retres1~5#1 := 0; 1011717#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1011716#L663-13 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1011715#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1011714#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1011713#L670-39 assume 1 == ~t6_pc~0; 1011711#L671-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1011709#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1011707#L682-13 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1011705#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1011704#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1011703#L689-39 assume !(1 == ~t7_pc~0); 1011702#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 1010089#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1010087#L701-13 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1010086#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1010085#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1010084#L708-39 assume 1 == ~t8_pc~0; 1010083#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1010081#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1010080#L720-13 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1010079#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1010078#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1010077#L727-39 assume !(1 == ~t9_pc~0); 1010075#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 1010024#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1010022#L739-13 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1010020#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 1010017#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1010015#L746-39 assume !(1 == ~t10_pc~0); 1010013#L746-41 is_transmit10_triggered_~__retres1~10#1 := 0; 1010010#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1010008#L758-13 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1010006#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1010003#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1010001#L765-39 assume 1 == ~t11_pc~0; 1009999#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1009996#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1009994#L777-13 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1009992#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1009989#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1009987#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 995789#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1009982#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1009978#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1009976#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1009973#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1009971#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1009969#L1279-3 assume !(1 == ~T7_E~0); 1009967#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1009965#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1009963#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1009958#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1009956#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1009954#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1009952#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1009950#L1319-3 assume !(1 == ~E_3~0); 995695#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 995693#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 995691#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 995686#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 995684#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 995682#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 995680#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 995678#L1359-3 assume !(1 == ~E_11~0); 995676#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 995650#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 995646#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 995644#L923-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 993315#L1709 assume !(0 == start_simulation_~tmp~3#1); 993312#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 993305#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 993295#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 993294#L923-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 993293#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 993292#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 990838#L1672 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 990466#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 990464#L1690-2 [2022-07-14 16:03:18,356 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:18,356 INFO L85 PathProgramCache]: Analyzing trace with hash -1240256838, now seen corresponding path program 1 times [2022-07-14 16:03:18,356 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:18,356 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [66169842] [2022-07-14 16:03:18,357 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:18,357 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:18,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:18,379 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:18,379 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:18,379 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [66169842] [2022-07-14 16:03:18,379 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [66169842] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:18,379 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:18,379 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:18,379 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [648074115] [2022-07-14 16:03:18,380 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:18,380 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:18,380 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:18,380 INFO L85 PathProgramCache]: Analyzing trace with hash 623448063, now seen corresponding path program 1 times [2022-07-14 16:03:18,380 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:18,380 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [500968711] [2022-07-14 16:03:18,380 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:18,381 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:18,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:18,400 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:18,401 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:18,401 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [500968711] [2022-07-14 16:03:18,401 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [500968711] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:18,401 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:18,401 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:18,401 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [418268981] [2022-07-14 16:03:18,401 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:18,402 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:18,402 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:18,402 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:03:18,402 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:03:18,402 INFO L87 Difference]: Start difference. First operand 145458 states and 207489 transitions. cyclomatic complexity: 62095 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:19,772 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:19,773 INFO L93 Difference]: Finished difference Result 350925 states and 497370 transitions. [2022-07-14 16:03:19,773 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:03:19,778 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 350925 states and 497370 transitions. [2022-07-14 16:03:21,350 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 344060 [2022-07-14 16:03:22,004 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 350925 states to 350925 states and 497370 transitions. [2022-07-14 16:03:22,004 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 350925 [2022-07-14 16:03:22,150 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 350925 [2022-07-14 16:03:22,150 INFO L73 IsDeterministic]: Start isDeterministic. Operand 350925 states and 497370 transitions. [2022-07-14 16:03:22,313 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:22,314 INFO L369 hiAutomatonCegarLoop]: Abstraction has 350925 states and 497370 transitions. [2022-07-14 16:03:22,475 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 350925 states and 497370 transitions. [2022-07-14 16:03:24,760 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 350925 to 277889. [2022-07-14 16:03:24,963 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 277889 states, 277889 states have (on average 1.4215676043312258) internal successors, (395038), 277888 states have internal predecessors, (395038), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:26,117 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 277889 states to 277889 states and 395038 transitions. [2022-07-14 16:03:26,117 INFO L392 hiAutomatonCegarLoop]: Abstraction has 277889 states and 395038 transitions. [2022-07-14 16:03:26,117 INFO L374 stractBuchiCegarLoop]: Abstraction has 277889 states and 395038 transitions. [2022-07-14 16:03:26,117 INFO L287 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-07-14 16:03:26,117 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 277889 states and 395038 transitions. [2022-07-14 16:03:26,768 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 277008 [2022-07-14 16:03:26,769 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-14 16:03:26,769 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-14 16:03:26,770 INFO L179 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:26,771 INFO L180 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-14 16:03:26,771 INFO L752 eck$LassoCheckResult]: Stem: 1481273#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 1481274#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1481879#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1481880#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1481720#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 1481721#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1480688#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1480689#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1482299#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1481687#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1481688#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1482028#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1482029#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1482138#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1482247#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1482248#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1482095#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1481898#L1121 assume !(0 == ~M_E~0); 1481611#L1121-2 assume !(0 == ~T1_E~0); 1480961#L1126-1 assume !(0 == ~T2_E~0); 1480962#L1131-1 assume !(0 == ~T3_E~0); 1481133#L1136-1 assume !(0 == ~T4_E~0); 1481232#L1141-1 assume !(0 == ~T5_E~0); 1481471#L1146-1 assume !(0 == ~T6_E~0); 1481812#L1151-1 assume !(0 == ~T7_E~0); 1481295#L1156-1 assume !(0 == ~T8_E~0); 1480675#L1161-1 assume !(0 == ~T9_E~0); 1480676#L1166-1 assume !(0 == ~T10_E~0); 1480896#L1171-1 assume !(0 == ~T11_E~0); 1480897#L1176-1 assume !(0 == ~E_M~0); 1481829#L1181-1 assume !(0 == ~E_1~0); 1481984#L1186-1 assume !(0 == ~E_2~0); 1482043#L1191-1 assume !(0 == ~E_3~0); 1480924#L1196-1 assume !(0 == ~E_4~0); 1480925#L1201-1 assume !(0 == ~E_5~0); 1482310#L1206-1 assume !(0 == ~E_6~0); 1482096#L1211-1 assume !(0 == ~E_7~0); 1482097#L1216-1 assume !(0 == ~E_8~0); 1481065#L1221-1 assume !(0 == ~E_9~0); 1481066#L1226-1 assume !(0 == ~E_10~0); 1480770#L1231-1 assume !(0 == ~E_11~0); 1480771#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1481830#L556 assume !(1 == ~m_pc~0); 1481831#L556-2 is_master_triggered_~__retres1~0#1 := 0; 1480648#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1480649#L568 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1481563#L1391 assume !(0 != activate_threads_~tmp~1#1); 1482016#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1482017#L575 assume !(1 == ~t1_pc~0); 1480599#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1480600#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1480733#L587 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1481078#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 1481034#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1481035#L594 assume !(1 == ~t2_pc~0); 1481797#L594-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1481911#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1481456#L606 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1480664#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 1480665#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1480722#L613 assume !(1 == ~t3_pc~0); 1480838#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1480837#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1480766#L625 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1480767#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 1481470#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1481171#L632 assume !(1 == ~t4_pc~0); 1481172#L632-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1481899#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1481900#L644 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1482311#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 1481838#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1481547#L651 assume !(1 == ~t5_pc~0); 1481548#L651-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1480850#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1480851#L663 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1481307#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 1480867#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1480868#L670 assume !(1 == ~t6_pc~0); 1482070#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1481218#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1481219#L682 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1482300#L1439 assume !(0 != activate_threads_~tmp___5~0#1); 1481511#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1481512#L689 assume !(1 == ~t7_pc~0); 1481765#L689-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1481631#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1481632#L701 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1482092#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 1481405#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1481406#L708 assume !(1 == ~t8_pc~0); 1480957#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1480958#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1482191#L720 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1482173#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 1481018#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1481019#L727 assume 1 == ~t9_pc~0; 1481148#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1480724#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1482317#L739 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1482318#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 1482301#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1481074#L746 assume !(1 == ~t10_pc~0); 1481075#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1481783#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1481919#L758 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1482185#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 1482021#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1481242#L765 assume 1 == ~t11_pc~0; 1481243#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1481466#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1480613#L777 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1480614#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 1482068#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1482169#L1249 assume 1 == ~M_E~0;~M_E~0 := 2; 1482170#L1249-2 assume !(1 == ~T1_E~0); 1481328#L1254-1 assume !(1 == ~T2_E~0); 1481329#L1259-1 assume !(1 == ~T3_E~0); 1480641#L1264-1 assume !(1 == ~T4_E~0); 1480642#L1269-1 assume !(1 == ~T5_E~0); 1482392#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1482393#L1279-1 assume !(1 == ~T7_E~0); 1480839#L1284-1 assume !(1 == ~T8_E~0); 1480840#L1289-1 assume !(1 == ~T9_E~0); 1481384#L1294-1 assume !(1 == ~T10_E~0); 1481385#L1299-1 assume !(1 == ~T11_E~0); 1481394#L1304-1 assume !(1 == ~E_M~0); 1482381#L1309-1 assume !(1 == ~E_1~0); 1482382#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1480789#L1319-1 assume !(1 == ~E_3~0); 1480790#L1324-1 assume !(1 == ~E_4~0); 1480919#L1329-1 assume !(1 == ~E_5~0); 1480920#L1334-1 assume !(1 == ~E_6~0); 1482119#L1339-1 assume !(1 == ~E_7~0); 1482340#L1344-1 assume !(1 == ~E_8~0); 1482401#L1349-1 assume !(1 == ~E_9~0); 1482402#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 1481950#L1359-1 assume !(1 == ~E_11~0); 1481951#L1364-1 assume { :end_inline_reset_delta_events } true; 1537732#L1690-2 [2022-07-14 16:03:26,771 INFO L754 eck$LassoCheckResult]: Loop: 1537732#L1690-2 assume !false; 1537721#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1537716#L1096 assume !false; 1537714#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1537460#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1537456#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1537454#L923 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1537451#L937 assume !(0 != eval_~tmp~0#1); 1537452#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1541427#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1541424#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1541422#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1541420#L1126-3 assume !(0 == ~T2_E~0); 1541418#L1131-3 assume !(0 == ~T3_E~0); 1541416#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1541395#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1541387#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1541380#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1541372#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1541365#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1541358#L1166-3 assume !(0 == ~T10_E~0); 1541351#L1171-3 assume !(0 == ~T11_E~0); 1541342#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1541332#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1541323#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1541314#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1541306#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1541296#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1541288#L1206-3 assume !(0 == ~E_6~0); 1541278#L1211-3 assume !(0 == ~E_7~0); 1541275#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1541273#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1541271#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1541269#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1541267#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1541265#L556-39 assume !(1 == ~m_pc~0); 1541255#L556-41 is_master_triggered_~__retres1~0#1 := 0; 1541246#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1541237#L568-13 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1541227#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 1541218#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1541209#L575-39 assume !(1 == ~t1_pc~0); 1541201#L575-41 is_transmit1_triggered_~__retres1~1#1 := 0; 1541191#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1541184#L587-13 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1541183#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1541012#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1539105#L594-39 assume !(1 == ~t2_pc~0); 1539104#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 1539103#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1539102#L606-13 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1539101#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1539099#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1539097#L613-39 assume !(1 == ~t3_pc~0); 1539095#L613-41 is_transmit3_triggered_~__retres1~3#1 := 0; 1539092#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1539090#L625-13 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1539088#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1539086#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1539083#L632-39 assume !(1 == ~t4_pc~0); 1539081#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 1539079#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1539077#L644-13 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1539076#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1539075#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1539074#L651-39 assume !(1 == ~t5_pc~0); 1539073#L651-41 is_transmit5_triggered_~__retres1~5#1 := 0; 1539072#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1539071#L663-13 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1539070#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1539069#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1539068#L670-39 assume !(1 == ~t6_pc~0); 1539066#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 1540075#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1540067#L682-13 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1539061#L1439-39 assume !(0 != activate_threads_~tmp___5~0#1); 1539058#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1539056#L689-39 assume !(1 == ~t7_pc~0); 1489502#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 1539053#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1539051#L701-13 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1539049#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1539047#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1539045#L708-39 assume 1 == ~t8_pc~0; 1539043#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1539040#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1539038#L720-13 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1539036#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1539034#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1539030#L727-39 assume !(1 == ~t9_pc~0); 1539027#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 1539024#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1539021#L739-13 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1539019#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 1539017#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1539016#L746-39 assume !(1 == ~t10_pc~0); 1539014#L746-41 is_transmit10_triggered_~__retres1~10#1 := 0; 1539011#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1539009#L758-13 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1539007#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1539005#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1538189#L765-39 assume 1 == ~t11_pc~0; 1538186#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1538183#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1538181#L777-13 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1538179#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1538177#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1538175#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1514161#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1538172#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1514157#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1538169#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1538167#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1538165#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1538163#L1279-3 assume !(1 == ~T7_E~0); 1538136#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1538130#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1538124#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1516841#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1538114#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1538108#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1538101#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1538094#L1319-3 assume !(1 == ~E_3~0); 1538088#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1538080#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1537980#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1537976#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1537974#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1537972#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1537970#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1537966#L1359-3 assume !(1 == ~E_11~0); 1537964#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1537880#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1537870#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1537862#L923-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 1537855#L1709 assume !(0 == start_simulation_~tmp~3#1); 1537849#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1537814#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1537803#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1537802#L923-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 1537798#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1537752#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1537743#L1672 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 1537742#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 1537732#L1690-2 [2022-07-14 16:03:26,772 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:26,772 INFO L85 PathProgramCache]: Analyzing trace with hash 1946581819, now seen corresponding path program 1 times [2022-07-14 16:03:26,772 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:26,772 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1686755546] [2022-07-14 16:03:26,772 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:26,772 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:26,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:26,794 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:26,794 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:26,794 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1686755546] [2022-07-14 16:03:26,794 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1686755546] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:26,795 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:26,795 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:26,795 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [329452875] [2022-07-14 16:03:26,795 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:26,795 INFO L757 eck$LassoCheckResult]: stem already infeasible [2022-07-14 16:03:26,795 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-14 16:03:26,795 INFO L85 PathProgramCache]: Analyzing trace with hash -2032157374, now seen corresponding path program 1 times [2022-07-14 16:03:26,796 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-14 16:03:26,796 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [623635553] [2022-07-14 16:03:26,796 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-14 16:03:26,796 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-14 16:03:26,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-14 16:03:26,813 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-14 16:03:26,813 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-14 16:03:26,814 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [623635553] [2022-07-14 16:03:26,814 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [623635553] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-14 16:03:26,814 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-14 16:03:26,814 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-14 16:03:26,814 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [660187734] [2022-07-14 16:03:26,814 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-14 16:03:26,814 INFO L769 eck$LassoCheckResult]: loop already infeasible [2022-07-14 16:03:26,814 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-14 16:03:26,815 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-14 16:03:26,815 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-14 16:03:26,815 INFO L87 Difference]: Start difference. First operand 277889 states and 395038 transitions. cyclomatic complexity: 117213 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-14 16:03:30,286 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-14 16:03:30,286 INFO L93 Difference]: Finished difference Result 666448 states and 941531 transitions. [2022-07-14 16:03:30,287 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-07-14 16:03:30,287 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 666448 states and 941531 transitions. [2022-07-14 16:03:33,184 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 653024 [2022-07-14 16:03:34,859 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 666448 states to 666448 states and 941531 transitions. [2022-07-14 16:03:34,859 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 666448 [2022-07-14 16:03:35,171 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 666448 [2022-07-14 16:03:35,171 INFO L73 IsDeterministic]: Start isDeterministic. Operand 666448 states and 941531 transitions. [2022-07-14 16:03:35,466 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-14 16:03:35,467 INFO L369 hiAutomatonCegarLoop]: Abstraction has 666448 states and 941531 transitions. [2022-07-14 16:03:36,160 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 666448 states and 941531 transitions.